S29NS-P_技术文档

S29NS-P MirrorBit^TMFlash Family

S29NS512P S29NS256P S29NS128P

512/256/128 Mb (32/16/8 M x 16 bit), 1.8 V Burst Simultaneous

Read/Write, Multiplexed MirrorBit Flash Memory

S29NS-P MirrorBit^TMFlash Family Cover Sheet

Data Sheet (Advance Information)

Notice to Readers: This document states the current technical specifications regarding the Spansion

product(s) described herein. Each product described herein may be designated as Advance Information,

Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.

Publication Number S29NS-P_00

Revision A

Amendment 1

Issue Date February 20, 2007

D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )

Notice On Data Sheet Designations

Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of

product information or intended specifications throughout the product life cycle, including development,

qualification, initial production, and full production. In all cases, however, readers are encouraged to verify

that they have the latest information before finalizing their design. The following descriptions of Spansion data

sheet designations are presented here to highlight their presence and definitions.

Advance Information

The Advance Information designation indicates that Spansion Inc. is developing one or more specific

products, but has not committed any design to production. Information presented in a document with this

designation is likely to change, and in some cases, development on the product may discontinue. Spansion

Inc. therefore places the following conditions upon Advance Information content:

“This document contains information on one or more products under development at Spansion Inc.

The information is intended to help you evaluate this product. Do not design in this product without

contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed

product without notice.”

Preliminary

The Preliminary designation indicates that the product development has progressed such that a commitment

to production has taken place. This designation covers several aspects of the product life cycle, including

product qualification, initial production, and the subsequent phases in the manufacturing process that occur

before full production is achieved. Changes to the technical specifications presented in a Preliminary

document should be expected while keeping these aspects of production under consideration. Spansion

places the following conditions upon Preliminary content:

“This document states the current technical specifications regarding the Spansion product(s)

described herein. The Preliminary status of this document indicates that product qualification has been

completed, and that initial production has begun. Due to the phases of the manufacturing process that

require maintaining efficiency and quality, this document may be revised by subsequent versions or

modifications due to changes in technical specifications.”

Combination

Some data sheets contain a combination of products with different designations (Advance Information,

Preliminary, or Full Production). This type of document distinguishes these products and their designations

wherever necessary, typically on the first page, the ordering information page, and pages with the DC

Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first

page refers the reader to the notice on this page.

Full Production (No Designation on Document)

When a product has been in production for a period of time such that no changes or only nominal changes

are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include

those affecting the number of ordering part numbers available, such as the addition or deletion of a speed

option, temperature range, package type, or V_IOrange. Changes may also include those needed to clarify a

description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following

conditions to documents in this category:

“This document states the current technical specifications regarding the Spansion product(s)

described herein. Spansion Inc. deems the products to have been in sufficient production volume such

that subsequent versions of this document are not expected to change. However, typographical or

specification corrections, or modifications to the valid combinations offered may occur.”

Questions regarding these document designations may be directed to your local sales office.

2

S29NS-P MirrorBit^TMFlash Family

S29NS-P_00_A1 February 20, 2007

S29NS-P MirrorBit^TMFlash Family

S29NS512P S29NS256P S29NS128P

512/256/128 Mb (32/16/8 M x 16 bit), 1.8 V Burst Simultaneous

Read/Write, Multiplexed MirrorBit Flash Memory

Data Sheet (Advance Information)

Features

Single 1.8 V read/program/erase (1.70–1.95 V)

90 nm MirrorBit Technology

Hardware (WP#) protection of highest two sectors

Top Boot sector configuration (NS256/128P)

Handshaking by monitoring RDY

Multiplexed Data and Address for reduced I/O count

Simultaneous Read/Write operation

Full/Half drive output slew rate control

32-word Write Buffer

Offered Packages

– NS512P: 64-ball FBGA (8 mm x 9.2 mm)

– NS256P/NS128P: 44-ball FBGA (6.2 mm x 7.7 mm)

Low V_CCwrite inhibit

Sixteen-bank architecture consisting of

Persistent and Password methods of Advanced Sector

64/32/16 MB for NS512/256/128P, respectively

Protection

Four 32 KB sectors at the top of memory array (NS256/128P)

Write operation status bits indicate program and erase

512 128KB sectors (NS512P), 255/127 128KB sectors (NS256/

operation completion

128P)

Suspend and Resume commands for Program and Erase

Programmable linear (8/16/32) with or without wrap around

operations

and continuous burst read modes

Unlock Bypass program command to reduce programming

Secured Silicon Sector region consisting of 128 words each

time

for factory and customer

Synchronous or Asynchronous program operation,

20-year data retention (typical)

independent of burst control register settings

Cycling Endurance: 100,000 cycles per sector (typical)

RDY output indicates data available to system

Command set compatible with JEDEC (42.4) standard

V_PPinput pin to reduce factory programming time

Support for Common Flash Interface (CFI)

Performance Characteristics

Read Access Times

Current Consumption (typical values)

Speed Option (MHz)

108

80

Continuous Burst Read @ 108 MHz

Simultaneous Operation 108 MHz

Program

42 mA

60 mA

30 mA

20 µA

Max. Synch. Latency, ns (t

)

IACC

Max. Synch. Burst Access, ns (t

)

7.0

80

BACC

Max. Asynch. Access Time, ns (t

)

Standby Mode

ACC

Max OE# Access Time, ns (t

)

7.0

OE

Typical Program & Erase Times

Single Word Programming

Effective Write Buffer Programming (V ) Per Word

30 µs

6 µs

CC

Effective Write Buffer Programming (V ) Per Word

PP

4 µs

Sector Erase (16 Kword Sector)

Sector Erase (64 Kword Sector)

350 ms

600 ms

General Description

The Spansion S29NS512/256/128P are MirrorBit Flash products fabricated on 90 nm process technology. These burst mode

Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate banks using

multiplexed data and address pins. These products can operate up to 108 MHz and use a single V_CCof 1.7 V to 1.95 V that

makes them ideal for the demanding wireless applications of today that require higher density, better performance, and lowered

power consumption.

Publication Number S29NS-P_00

Revision A

Amendment 1

Issue Date February 20, 2007

This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in

this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.

D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )

Table of Contents

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.

2.

3.

4.

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Input/Output Descriptions & Logic Symbol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Physical Dimensions/Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.1

4.2

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Special Handling Instructions for FBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.

6.

Product Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.1

6.2

6.3

6.4

6.5

6.6

6.7

6.8

6.9

Device Operation Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Asynchronous Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Synchronous (Burst) Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Program/Erase Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Simultaneous Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Hardware Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.10 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.11 Programmable Output Slew Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7.

Advanced Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

7.1

7.2

7.3

7.4

7.5

7.6

7.7

Lock Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Persistent Protection Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Dynamic Protection Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Persistent Protection Bit Lock Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Password Protection Method. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Advanced Sector Protection Software Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Hardware Data Protection Methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

8.

9.

Power Conservation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

8.1

8.2

8.3

8.4

Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Automatic Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Hardware RESET# Input Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Output Disable (OE#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Secured Silicon Sector Flash Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

9.1

9.2

9.3

Factory Secured Silicon Sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Customer Secured Silicon Sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Secured Silicon Sector Entry and Exit Command Sequences. . . . . . . . . . . . . . . . . . . . . . . . 62

10. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

10.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

10.2 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

10.3 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

10.4 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

10.5 Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

10.6 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

10.7 CLK Characterization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

10.8 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

10.9 Erase and Programming Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

11. Appendix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

11.1 Common Flash Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

12. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

4

S29NS-P MirrorBit^TMFlash Family

S29NS-P_00_A1 February 20, 2007

D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )

Figures

Figure 3.1

Simultaneous Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

64-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS512P Top View, Balls Facing Down . . 10

44-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS256P Top View, Balls Facing Down . . 11

44-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS128P Top View, Balls Facing Down . . 11

VDD064—64-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS512P. . . . . . . . . . . . . . . . . . 12

VDE044—44-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS128/256P . . . . . . . . . . . . . . 13

Synchronous Read Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Single Word Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Write Buffer Programming Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Sector Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Write Operation Status Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Advanced Sector Protection/Unprotection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

PPB Program/Erase Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Lock Register Program Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 4.1

Figure 4.2

Figure 4.3

Figure 4.4

Figure 4.5

Figure 6.1

Figure 6.2

Figure 6.3

Figure 6.4

Figure 6.5

Figure 7.1

Figure 7.2

Figure 7.3

Figure 10.1 Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 10.2 Maximum Positive Overshoot Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 10.3 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 10.4 Input Waveforms and Measurement Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 10.5

V_CCPower-Up Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 10.6 CLK Characterization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 10.7 8-Word Linear Synchronous Single Data Rate Burst with Wrap Around. . . . . . . . . . . . . . . . 68

Figure 10.8 8-Word Linear Single Data Read Synchronous Burst without Wrap Around. . . . . . . . . . . . . 69

Figure 10.9 Asynchronous Mode Read with Latched Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 10.10 Asynchronous Mode Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 10.11 Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 10.12 Asynchronous Program Operation Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 10.13 Chip/Sector Erase Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 10.14 Accelerated Unlock Bypass Programming Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 10.15 Data# Polling Timings (During Embedded Algorithm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 10.16 Toggle Bit Timings (During Embedded Algorithm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 10.17 Synchronous Data Polling Timings/Toggle Bit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 10.18 DQ2 vs. DQ6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 10.19 Latency with Boundary Crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 10.20 Wait State Configuration Register Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 10.21 Back-to-Back Read/Write Cycle Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

February 20, 2007 S29NS-P_00_A1

S29NS-P MirrorBit^TMFlash Family

5

D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )

Tables

Table 2.1

Table 5.1

Table 5.2

Table 5.3

Table 6.1

Table 6.2

Table 6.3

Table 6.4

Table 6.5

Table 6.6

Table 6.7

Table 6.8

Table 6.9

Table 6.10

Table 6.11

Table 6.12

Table 6.13

Table 6.14

Table 6.15

Table 6.16

Table 6.17

Table 6.18

Table 6.19

Table 6.20

Table 6.21

Table 6.22

Table 6.23

Table 6.24

Table 6.25

Table 6.26

Table 6.27

Table 6.28

Table 6.29

Table 7.1

Table 9.1

Table 9.2

Table 9.3

Table 9.4

Table 10.1

Table 10.2

Table 10.3

Table 10.4

Table 10.5

Table 10.6

Table 10.7

Table 10.8

Table 10.9

Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

S29NS512P Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

S29NS256P Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

S29NS128P Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Address Latency for 9 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Address Latency for 8 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Address Latency for 7 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Address Latency for 6 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Address Latency for 5 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Address Latency for 4 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Address Latency for 3 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Address Latency for 2 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Burst Address Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Autoselect Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Autoselect Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Autoselect Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Single Word Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Write Buffer Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Chip Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Program Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Program Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Unlock Bypass Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Unlock Bypass Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Unlock Bypass Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

DQ6 and DQ2 Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Programmable Output Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Sector Protection Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Secured Silicon SectorSecure Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Secured Silicon Sector Entry (LLD Function = lld_SecSiSectorEntryCmd) . . . . . . . . . . . . . .62

Secured Silicon Sector Program (LLD Function = lld_ProgramCmd) . . . . . . . . . . . . . . . . . . .62

Secured Silicon Sector Exit (LLD Function = lld_SecSiSectorExitCmd) . . . . . . . . . . . . . . . . .63

DC Characteristics—CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

V

_CCPower-Up with No Ramp Rate Restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

CLK Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Synchronous/Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Synchronous Wait State Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Asynchronous Mode Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Warm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Erase/Program Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Table 10.10 Example of Programmable Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Table 10.11 Erase and Programming Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Table 11.1

Table 11.2

Table 11.3

Table 11.4

Table 11.5

Table 11.6

Memory Array Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Sector Protection Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

System Interface String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

6

S29NS-P MirrorBit^TMFlash Family

S29NS-P_00_A1 February 20, 2007

D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )

1. Ordering Information

The ordering part number is formed by a valid combination of the following:

S29NS

512

P

xx

BJ

W

00

0

Packing Type

0

3

= Tray (standard; (Note 1))

= 13-inch Tape and Reel

Model Number

00 = Standard

Temperature Range

W = Wireless (–25°C to +85°C)

Package Type & Material Set

BJ = Very Thin Fine-Pitch BGA,Lead (Pb)-free LF35 Package

Speed Option (Burst Frequency)

0P = 66 MHz

0S = 83 MHz

AB = 108 MHz

Process Technology

P

= 90 nm MirrorBit™ Technology

Flash Density

512 =512 Mb

256 =256 Mb

128 =128 Mb

Product Family

S29NS = 1.8 Volt-only Simultaneous Read/Write, Burst Mode Multiplexed Flash

Memory

Valid Combinations

Package Type

Speed

Option

Base Ordering

Part Number

Package Type, Material,

& Temperature Range

Packing

Type

Model

Number

S29NS512P

S29NS256P

S29NS128P

8.0 mm x 9.2 mm, 64-ball

6.2 mm x 7.7 mm, 44-ball

0P, 0S, AB

BJW (Lead (Pb)-free, LF35)

0, 3 (1)

00

Notes

1. Type 0 is standard. Specify other options as required.

2. BGA package marking omits leading S29 and packing type designator from ordering part number.

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult your local

sales office to confirm availability of specific valid combinations and to check on newly released

combinations.

February 20, 2007 S29NS-P_00_A1

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D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )

2. Input/Output Descriptions & Logic Symbol

Table 2.1 identifies the input and output package connections provided on the device.

Table 2.1 Input/Output Descriptions

Symbol

A24 – A16

Type

Input

I/O

Description

Address inputs, S29NS512P

Address inputs, S29NS256P

Address inputs, S29NS128P

Multiplexed Address/Data input/output

A23 – A16

A22 – A16

A/DQ15 – A/DQ0

CE#

Input

Supply

I/O

Chip Enable. Asynchronous relative to CLK for the Burst mode.

OE#

Output Enable. Asynchronous relative to CLK for the Burst mode

WE#

Write Enable

V

Device Power Supply

CC

Input/Output Power Supply (must be ramped simultaneously with V

)

CCQ

SS

CC

Ground

I/O

Input/Output Ground

SSQ

NC

No Connect No Connected internally

RDY

Output

Ready. Indicates when valid burst data is ready to be read

The first rising edge of CLK in conjunction with AVD# low latches address input and activates burst

mode operation. After the initial word is output, subsequent rising edges of CLK increment the

internal address counter. CLK should remain low during asynchronous access

CLK

Input

Address Valid input. Indicates to device that the valid address is present on the address inputs

(address bits A15 – A0 are multiplexed, address bits Amax – A16 are address only).

AVD#

Input

V = for asynchronous mode, indicates valid address; for burst mode, cause staring address to be

IL

latched on rising edge of CLK.

= device ignores address inputs

V

IH

RESET#

WP#

Input

Hardware Reset. Low = device resets and returns to reading array data.

Write Protect. At V , disables program and erase functions in the four top sectors. Should be at V

IL

for all other conditions.

IH

Accelerated input.

At V , accelerates programming; automatically places device in unlock bypass mode.

HH

V

Input

PP

At V ,disables all program and erase functions.

IL

Should be at V for all other conditions.

IH

RFU

Reserved

Reserved for future use

8

S29NS-P MirrorBit^TMFlash Family

S29NS-P_00_A1 February 20, 2007

D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )

3. Block Diagrams

Figure 3.1 Simultaneous Operation Circuit

V

CC

V

SS

Bank Address

DQ15–DQ0

V

CCQ

Bank 0

V

SSQ

Amax–A0

X-Decoder

OE#

Bank Address

DQ15–DQ0

Bank 1

WP#

V_PP

X-Decoder

?Amax–A0

STATE

CONTROL

&

COMMAND

REGISTER

RESET#

WE#

DQ15–DQ0

Status

CE#

AVD#

RDY

Control

?Amax–A16

A/DQ15–A/DQ0

X-Decoder

Bank (n-1)

DQ15–DQ0

Bank Address

?Amax–A16

X-Decoder

Bank (n)

Bank Address

DQ15–DQ0

Notes

1. Amax = A24 for NS512P, A23 for NS256P, A22 for NS128P.

2. Bank (n) = 15 for NS512P/ NS256P/ NS128P.

February 20, 2007 S29NS-P_00_A1

S29NS-P MirrorBit^TMFlash Family

9

D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )

4. Physical Dimensions/Connection Diagrams

This section shows the I/O designations and package specifications for the OPN.

4.1

4.2

Read Next Data

RD = DQ[15:0]

Delay X Clocks

Crossing

Boundary?

No

End of Data?

Yes

Completed

6.3.2

Continuous Burst Read Mode

In the continuous burst read mode, the device outputs sequential burst data from the starting address given

and then wraps around to address 000000h when it reaches the highest addressable memory location. The

burst read mode continues until the system drives CE# high, or RESET= V_IL. Continuous burst mode can

also be aborted by asserting AVD# low and providing a new address to the device.

If the address being read crosses a 128-word line boundary within the same bank, but not into a program or

erase suspended sector, as mentioned above, additional latency cycles are required as reflected by the

configuration register table (Table 6.11) and Tables 6.2 – 6.9 .

If the address crosses a bank boundary while the subsequent bank is programming or erasing, the device

provides read status information and the clock is ignored. Upon completion of status read or program or erase

operation, the host can restart a burst read operation using a new address and AVD# pulse.

February 20, 2007 S29NS-P_00_A1

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D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )

6.3.3

8-Word, 16-Word, and 32-Word Linear Burst Read with Wrap Around

In a linear burst read operation, a fixed number of words (8, 16, or 32 words) are read from consecutive

addresses that are determined by the group within which the starting address falls. The groups are sized

according to the number of words read in a single burst sequence for a given mode (see Table 6.10).

For example, if the starting address in the 8-word mode is 3Ch, the address range to be read is 38-3Fh, and

the burst sequence is 3C-3D-3E-3F-38-39-3A-3Bh. Thus, the device outputs all words in that burst address

group until all word are read, regardless of where the starting address occurs in the address group, and then

terminates the burst read.

In a similar fashion, the 16-word and 32-word Linear Wrap modes begin their burst sequence on the starting

address provided to the device, then wrap back to the first address in the selected address group.

Note that in this mode the address pointer does not cross the boundary that occurs every 128 words; thus, no

additional wait states are inserted due to boundary crossing.

Table 6.10 Burst Address Groups

Mode

8-word

16-word

32-word

Group Size

8 words

Group Address Ranges

0 – 7h, 8 – Fh, 10 – 17h,...

0 – Fh, 10 – 1Fh, 20 – 2Fh,...

00 – 1Fh, 20 – 3Fh, 40 – 5Fh,...

16 words

32 words

6.3.4

6.3.5

8-Word, 16-Word, and 32-Word Linear Burst without Wrap Around

If wrap around is not enabled for linear burst read operations, the 8-word, 16-word, or 32-word burst executes

up to the maximum memory address of the selected number of words. The burst stops after 8, 16, or 32

addresses and does not wrap around to the first address of the selected group.

For example, if the starting address in the 8-word mode is 3Ch, the address range to be read is 3C-43h, and

the burst sequence is 3C-3D-3E-3F-40-41-42-43h if wrap around is not enabled. The next address to be read

requires a new address and AVD# pulse. Note that in this burst read mode, the address pointer may cross the

boundary that occurs every 128 words, which incurs the additional boundary crossing wait state.

Configuration Registers

This device uses two 16-bit configuration registers to set various operational parameters. Upon power-up or

hardware reset, the device is capable of the asynchronous read mode and synchronous read, and the

configuration register settings are in their default state. The host system should determine the proper settings

for the entire configuration register, and then execute the Set Configuration Register command sequence

before attempting burst operations. The Configuration Register can also be read using a command sequence

(see Table 11.1). The following list describes the register settings.

Table 6.11 Configuration Register

CR Bit

Function

Settings (Binary)

0 = Reserved (Default)

1 = Reserved

Reserved

(Not used)

CR0.15

0 = Reserved (Default)

1 = Reserved

Reserved

(Not used)

CR0.14

32

S29NS-P MirrorBit^TMFlash Family

S29NS-P_00_A1 February 20, 2007

D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )

Table 6.11 Configuration Register

CR Bit

Function

Settings (Binary)

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

2nd

3rd

4th

5th

6th

7th

CR1.0

initial data is

valid on the

rising

CLK edge

AVD# transition

to V

CR0.13

CR0.12

=

IH

Programmable

Wait State

(Note 1)

=

Reserved

8th

9th

initial data is

valid on the

rising

CLK edge

AVD# transition

to V

IH

CR0.11

initial data is

valid on the

rising

CLK edge

AVD# transition

to V (Default)

1101

=

13th

IH

1110

1111

Reserved

0 = RDY signal is active low

1 = RDY signal is active high (Default)

RDY

Polarity

CR0.10

CR0.9

CR0.8

CR0.7

CR0.6

CR0.5

CR1.4

CR0.4

CR0.3

0 = Reserved

1 = Reserved (Default)

Reserved

(Not used)

0 = RDY active one clock cycle before data

1 = RDY active with data (Default)

RDY

0 = Reserved

1 = Reserved (Default)

Reserved

(Not used)

0 = Reserved

1 = Reserved (Default)

Reserved

(Not used)

Reserved

(Not used)

0 = Reserved (Default)

1 = Reserved

0 = Full Drive= Current Driver Strength (Default)

1 = Half Drive

Output Drive

Strength

0 = RDY (Default)

1 = Reserved

RDY Function

0 = No Wrap Around Burst

1 = Wrap Around Burst (Default)

Burst Wrap

Around

000 = Continuous (Default)

010 = 8-Word Linear Burst

011 = 16-Word Linear Burst

100 = 32-Word Linear Burst

(All other bit settings are reserved)

CR0.2

Burst

Length

CR0.1

CR0.0

Notes

1. The addresses are latched by rising edge of CLK.

2. CR1.0 to CR1.3 and CR1.5 to CR1.15 = 1 (Default).

3. A software reset command is required after read command.

4. CR0.3 is ignored if in continuous read mode (no wrap around).

6.4

Autoselect

The Autoselect is used for manufacturer ID, Device identification, and sector protection information. This

mode is primarily intended for programming equipment to automatically match a device with its corresponding

programming algorithm. The Autoselect codes can also be accessed in the system. When verifying sector

protection, the sector address must appear on the appropriate highest order address bits (see Table 6.12).

The remaining address bits are don't care. The most significant four bits of the address during the third write

cycle select the bank from which the Autoselect codes are read by the host. All other banks can be accessed

normally for data read without exiting the Autoselect mode.

February 20, 2007 S29NS-P_00_A1

S29NS-P MirrorBit^TMFlash Family

33

D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )

To access the Autoselect codes, the host system must issue the Autoselect command.

The Autoselect command sequence may be written to an address within a bank that is either in the read or

erase-suspend-read mode.

The Autoselect command may not be written while the device is actively programming or erasing.

Autoselect does not support simultaneous operations or burst mode.

The system must write the reset command to return to the read mode (or erase-suspend-read mode if the

bank was previously in Erase Suspend).

See Table 11.1 for command sequence details.

Table 6.12 Autoselect Addresses

Description

Address

Read Data

Manufacturer ID

Byte 00

(BA) + 00h

0001h

307Eh(NS512P)

317Eh(NS256P)

327Eh(NS128P)

Device ID,

Byte 01

(BA) + 01h

(SA) + 02h

Sector Lock/Unlock

Byte 02

0001h = Locked,

0000h = Unlocked

DQ15 – DQ8 = reserved

DQ7 – Factory Lock Bit;

1 = Locked, 0 = Not Locked

DQ6 – Customer Lock Bit;

1 = Locked, 0 = Not Locked

Indicator Bits

Byte 07

(BA) + 07h

DQ5 – Handshake Bit;

1 = Reserved,

0 = Standard Handshake

DQ4 and DQ3 – WP# Protection Boot Code;

01 = WP# Protects Top Boot Sectors,

DQ2 – DQ0 = reserved

303Fh (NS512P)

3141h (NS256P)

3243h (NS128P)

Device ID,

Byte 0E

(BA) + 0Eh

(BA) + 0Fh

3000h (NS512P)

3100h (NS256P)

3200h (NS128P)

Device ID,

Byte 0F

Software Functions and Sample Code

Table 6.13 Autoselect Entry

(LLD Function = lld_AutoselectEntryCmd)

Cycle

Operation

Write

Byte Address

BA+AAAh

BA+555h

Word Address

BA+555h

Data

Unlock Cycle 1

Unlock Cycle 2

Autoselect Command

0x00AAh

0x0055h

0x0090h

Write

BA+2AAh

Write

BA+AAAh

BA+555h

Table 6.14 Autoselect Exit

(LLD Function = lld_AutoselectExitCmd)

Cycle

Operation

Write

Byte Address

Word Address

base + xxxxh

Data

Unlock Cycle 1

base + xxxxh

0x00F0h

Notes

1. Any offset within the device works.

2. BA = Bank Address. The bank address is required.

3. base = base address.

The following is a C source code example of using the autoselect function to read the manufacturer ID. Refer

to the Spansion Low Level Driver User’s Guide (available on www.spansion.com) for general information on

Spansion Flash memory software development guidelines.

34

S29NS-P MirrorBit^TMFlash Family

S29NS-P_00_A1 February 20, 2007

D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )

/* Here is an example of Autoselect mode (getting manufacturer ID) */

/* Define UINT16 example: typedef unsigned short UINT16; */

UINT16 manuf_id;

/* Auto Select Entry */

*( (UINT16 *)bank_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */

*( (UINT16 *)bank_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */

*( (UINT16 *)bank_addr + 0x555 ) = 0x0090; /* write autoselect command */

/* multiple reads can be performed after entry */

manuf_id = *( (UINT16 *)bank_addr + 0x000 ); /* read manuf. id */

/*

Autoselect exit */

*( (UINT16 *)base_addr + 0x000 ) = 0x00F0; /* exit autoselect (write reset command) */

6.5

Program/Erase Operations

These devices are capable of several modes of programming and or erase operations which are described in

detail in the following sections. However, prior to any programming and or erase operation, devices can be

setup appropriately as outlined in the configuration register (Table 6.11).

For any program and or erase operations, including writing command sequences, the system must drive

AVD# and CE# to V_IL, and OE# to V_IHwhen providing an address to the device, and drive WE# and CE# to

V_IL, and OE# to V_IHwhen writing commands or programming data.

All addresses are latched on the rising edge of AVD# or falling edge of WE#, and all data is latched on the

first rising edge of WE#.

Note the following:

When the Embedded Program/Erase algorithm is complete, the device returns to the read mode.

The system can determine the status of the Program/Erase operation. Refer to the Write Operation Status

section for further information.

While 1 can be programmed to 0, a 0 cannot be programmed to a 1. Any such attempt is ignored as only

an erase operation can covert a 0 to a 1.

Any commands written to the device during the Embedded Program/Erase Algorithm are ignored except

the Program/Erase Suspend command.

Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a program operation is in

progress.

A hardware reset or power removal immediately terminates the Program/Erase operation and the Program/

Erase command sequence should be reinitiated once the device has returned to the read mode, to ensure

data integrity.

Programming is allowed in any sequence and across sector boundaries only for single word programming

operation. See Write Buffer Programming when using the write buffer.

Note: The system may also lock or unlock any sector while the erase operation is suspended.

6.5.1

Single Word Programming

Single word programming mode is the simplest method of programming. In this mode, four Flash command

write cycles are used to program an individual Flash address. While the single word programming method is

supported by all Spansion devices, in general it is not recommended for devices that support Write Buffer

Programming. See Table 11.1 for the required bus cycles and Figure 6.2 for the flowchart.

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When the Embedded Program algorithm is complete, the device then returns to the read mode and

addresses are no longer latched. The system can determine the status of the program operation by using

DQ7 or DQ6. Refer to the Write Operation Status section for information on these status bits.

Figure 6.2 Single Word Program

Write Unlock Cycles:

Address 555h, Data AAh

Address 2AAh, Data 55h

Unlock Cycle 1

Unlock Cycle 2

Write Program Command:

Address 555h, Data A0h

Setup Command

Program Address (PA),

Program Data (PD)

Program Data to Address:

PA, PD

Perform Polling Algorithm

(see Write Operation Status

flowchart)

Yes

Polling Status

= Busy?

No

Yes

Polling Status

= Complete?

Error condition

No

(Exceeded Timing Limits)

Operation successfully completed

Operation failed

Software Functions and Sample Code

Table 6.15 Single Word Program

(LLD Function = lld_ProgramCmd)

Cycle

Operation

Write

Byte Address

Word Address

Data

Unlock Cycle 1

Unlock Cycle 2

Program Setup

Program

Base + AAAh

Base + 554h

Base + AAAh

Word Address

Base + 555h

Base + 2AAh

Base + 555h

Word Address

00AAh

0055h

Write

00A0h

Write

Data Word

Note

Base = Base Address.

The following is a C source code example of using the single word program function. Refer to the Spansion

Low Level Driver User’s Guide (available on www.spansion.com) for general information on Spansion Flash

memory software development guidelines.

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/* Example: Program Command

*/

*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;

*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;

*( (UINT16 *)base_addr + 0x555 ) = 0x00A0;

/* write unlock cycle 1

*/

/* write unlock cycle 2

/* write program setup command

/* write data to be programmed

*( (UINT16 *)pa )

= data;

/* Poll for program completion */

6.5.2

Write Buffer Programming

Write Buffer Programming allows the system to write a maximum of 32 words in one programming operation.

This results in a faster effective word programming time than the standard word programming algorithms. The

Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed

by a third write cycle containing the Write Buffer Load command written at the Sector Address in which

programming occurs. At this point, the system writes the number of word locations minus 1 that is loaded into

the page buffer at the Sector Address in which programming occurs. This tells the device how many write

buffer addresses will be loaded with data and therefore when to expect the Program Buffer to Flash confirm

command. The number of locations to program cannot exceed the size of the write buffer or the operation

aborts. (Note: the size of the write buffer is dependent upon which data are being loaded. Also note that the

number loaded = the number of locations to program minus 1. For example, if the system programs 6 address

locations, then 05h should be written to the device.)

The system then writes the starting address/data combination. This starting address is the first address/data

pair to be programmed, and selects the write-buffer-page address. All subsequent address/data pairs must

be in sequential order.

The write-buffer addresses must be in the same sector for all address/data pairs loaded into the write buffer.

It is to be noted that Write Buffer Programming cannot be performed across multiple sectors. If the system

attempts to load programming data outside of the selected write-buffer addresses, the operation aborts after

the Write to Buffer command is executed. Also, the starting address must be the least significant address and

must be incremental and that the write buffer data cannot be in different sectors.

After writing the Starting Address/Data pair, the system then writes the remaining address/data pairs into the

write buffer. Write buffer locations must be loaded in sequential order starting with the lowest address in the

page. Note that if the number of address/data pairs do not match the word count, the program buffer to flash

command is ignored.

Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter

decrements for every data load operation. Also, the last data loaded at a location before the Program Buffer

to Flash confirm command is programmed into the device. It is the software’s responsibility to comprehend

ramifications of loading a write-buffer location more than once. The counter decrements for each data load

operation, NOT for each unique write-buffer-address location.

Once the specified number of write buffer locations have been loaded, the system must then write the

Program Buffer to Flash command at the Sector Address. Any other address/data write combinations abort

the Write Buffer Programming operation. The device then goes busy. The Data Bar polling techniques should

be used while monitoring the last address location loaded into the write buffer. This eliminates the need to

store an address in memory because the system can load the last address location, issue the program

confirm command at the last loaded address location, and then data bar poll at that same address. DQ7,

DQ6, DQ5, DQ2, and DQ1 should be monitored to determine the device status during Write Buffer

Programming.

The write-buffer embedded programming operation can be suspended using the standard suspend/resume

commands. Upon successful completion of the Write Buffer Programming operation, the device returns to

READ mode.

The Write Buffer Programming Sequence is ABORTED in the following ways:

Load a value that is greater than the buffer size during the Number of Locations to Program step (DQ7 is

not valid in this condition).

Write to an address in a sector different than the one specified during the Write-Buffer-Load command.

Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting Address

during the write buffer data loading stage of the operation.

Write data other than the Confirm Command after the specified number of data load cycles.

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Software Functions and Sample Code

Table 6.16 Write Buffer Program

(LLD Functions Used = lld_WriteToBufferCmd, lld_ProgramBufferToFlashCmd)

Cycle

Description

Unlock

Operation

Write

Byte Address

Base + AAAh

Base + 554h

Word Address

Base + 555h

Base + 2AAh

Data

00AAh

1

2

3

4

Unlock

Write

0055h

Write Buffer Load Command

Write Word Count

Write

Program Address

0025h

Write

Word Count (N–1)h

Number of words (N) loaded into the write buffer can be from 1 to 32 words.

5 to 36

Last

Load Buffer Word N

Write Buffer to Flash

Write

Program Address, Word N

Sector Address

Word N

0029h

Notes

1. Base = Base Address.

2. Last = Last cycle of write buffer program operation; depending on number of words written, the total number of cycles may be from 6 to

37.

3. For maximum efficiency, it is recommended that the write buffer be loaded with the highest number of words (N words) possible.

The following is a C source code example of using the write buffer program function. Refer to the Spansion

Low Level Driver User’s Guide (www.spansion.com) for general information on Spansion Flash memory

software development guidelines.

/* Example: Write Buffer Programming Command */

/* NOTES: Write buffer programming limited to 16 words. */

/* All addresses to be written to the flash in */

/* one operation must be within the same write buffer. */

/* A write buffer begins at addresses evenly divisible */

/* by 0x20.

UINT16 i; */

UINT16 *src = source_of_data; /* address of source data */

UINT16 *dst = destination_of_data; /* flash destination address */

UINT16 wc = words_to_program -1; /* word count (minus 1) */

*( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */

*( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */

*( (UINT16 *)dst ) = 0x0025; /* write write buffer load command */

*( (UINT16 *)dst ) = wc; /* write word count (minus 1) */

for (i=0;i<=wc;i++)

{

*dst++ = *src++; /* ALL dst MUST BE in same Write Buffer */

}

*( (UINT16 *)sector_address ) = 0x0029; /* write confirm command */

/* poll for completion */

/* Example: Write Buffer Abort Reset */

*( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */

*( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */

*( (UINT16 *)base_addr + 0x555 ) = 0x00F0; /* write buffer abort reset */

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Figure 6.3 Write Buffer Programming Operation

Write Unlock Cycles:

Address 555h, Data AAh

Address 2AAh, Data 55h

Unlock Cycle 1

Unlock Cycle 2

Issue

Write Buffer Load Command:

Program Address Data 25h

Load Word Count to Program

Program Data to Address:

SA = wc

wc = number of words – 1

Yes

Confirm command:

wc = 0?

No

SA 29h

Write Next Word,

Decrement wc:

PA data , wc = wc – 1

Perform Polling Algorithm

(see Write Operation Status

flowchart)

Yes

Polling Status

= Done?

No

Error?

Yes

No

Yes

Write Buffer

Abort?

No

RESET. Issue Write Buffer

Abort Reset Command

PASS. Device is in

read mode.

FAIL. Issue reset command

to return to read array mode.

6.5.3

Sector Erase

The sector erase function erases one or more sectors in the memory array. (See Table 11.1 and Figure 6.4.)

The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm

automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase.

After a successful sector erase, all locations within the erased sector contain FFFFh. The system is not

required to provide any controls or timings during these operations.

After the command sequence is written, a sector erase time-out of no less than t_SEAoccurs. During the time-

out period, additional sector addresses and sector erase commands may be written. Loading the sector erase

buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The

time between these additional cycles must be less than t_SEA. Any sector erase address and command

following the exceeded time-out (t_SEA) may or may not be accepted. Any command other than Sector Erase

or Erase Suspend during the time-out period resets that bank to the read mode. The system can monitor DQ3

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to determine if the sector erase timer has timed out (See the section, DQ3: Sector Erase Timeout State

Indicator.) The time-out begins from the rising edge of the final WE# pulse in the command sequence.

When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are

no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data

from the non-erasing banks. The system can determine the status of the erase operation by reading DQ7 or

DQ6/DQ2 in the erasing bank. Refer to Write Operation Status for information on these status bits.

Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands

are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs,

the sector erase command sequence should be reinitiated once that bank has returned to reading array data,

to ensure data integrity.

Figure 6.4 illustrates the algorithm for the erase operation. Refer to Program/Erase Operations for

parameters and timing diagrams.

Software Functions and Sample Code

Table 6.17 Sector Erase

(LLD Function = lld_SectorEraseCmd)

Cycle

Description

Unlock

Operation

Write

Byte Address

Base + AAAh

Base + 554h

Base + AAAh

Base + 554h

Sector Address

Word Address

Base + 555h

Base + 2AAh

Base + 555h

Base + 2AAh

Sector Address

Data

00AAh

0055h

0080h

00AAh

0055h

0030h

1

2

3

4

5

6

Unlock

Write

Setup Command

Unlock

Write

Unlock

Write

Sector Erase Command

Write

Unlimited additional sectors may be selected for erase; command(s) must be written within t

.

SEA

The following is a C source code example of using the sector erase function. Refer to the Spansion Low Level

Driver User’s Guide (available on www.spansion.com) for general information on Spansion Flash memory

software development guidelines.

/* Example: Sector Erase Command */

*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;

*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;

*( (UINT16 *)base_addr + 0x555 ) = 0x0080;

*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;

*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;

/* write unlock cycle 1

/* write unlock cycle 2

/* write setup command

*/

/* write additional unlock cycle 1 */

/* write additional unlock cycle 2 */

*( (UINT16 *)sector_address )

= 0x0030;

/* write sector erase command

*/

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Figure 6.4 Sector Erase Operation

Write Unlock Cycles:

Address 555h, Data AAh

Address 2AAh, Data 55h

Unlock Cycle 1

Unlock Cycle 2

Write Sector Erase Cycles:

Address 555h, Data 80h

Address 555h, Data AAh

Address 2AAh, Data 55h

Command Cycle 1

Command Cycle 2

Command Cycle 3

Specify first sector for erasure

Sector Address, Data 30h

Select

Additional

Sectors?

No

Yes

Write Additional

Sector Addresses

• Each additional cycle must be written within t_SEAtimeout

• Timeout resets after each additional cycle is written

• The host system may monitor DQ3 or wait t_SEAto ensure

acceptance of erase commands

Yes

Last Sector

Selected?

No

• No limit on number of sectors

Poll DQ3.

DQ3 = 1?

• Commands other than Erase Suspend or selecting

additional sectors for erasure during timeout reset device

to reading array data

No

Yes

Perform Write Operation

Status Algorithm

Status may be obtained by reading DQ7, DQ6 and/or DQ2.

Yes

Done?

No

DQ5 = 1?

Yes

Error condition (Exceeded Timing Limits)

PASS. Device returns

to reading array.

FAIL. Write reset command

to return to reading array.

Notes

1. See Table 11.1 for erase command sequence.

2. See DQ3: Sector Erase Timeout State Indicator for information on the sector erase timeout.

6.5.4

Chip Erase Command Sequence

Chip erase is a six-bus cycle operation as indicated by Table 11.1. These commands invoke the Embedded

Erase algorithm, which does not require the system to preprogram prior to erase. The Embedded Erase

algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to

electrical erase. After a successful chip erase, all locations of the chip contain FFFFh. The system is not

required to provide any controls or timings during these operations. Table 11.1 shows the address and data

requirements for the chip erase command sequence.

When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no

longer latched. The system can determine the status of the erase operation by using DQ7 or DQ6/DQ2. Refer

to the Write Operation Status section for information on these status bits.

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Any commands written during the chip erase operation are ignored. However, note that a hardware reset

immediately terminates the erase operation. If that occurs, the chip erase command sequence should be

reinitiated once that bank has returned to reading array data, to ensure data integrity.

Software Functions and Sample Code

Table 6.18 Chip Erase

(LLD Function = lld_ChipEraseCmd)

Cycle

Description

Unlock

Operation

Write

Byte Address

Base + AAAh

Base + 554h

Base + AAAh

Base + 554h

Base + AAAh

Word Address

Base + 555h

Base + 2AAh

Base + 555h

Base + 2AAh

Base + 555h

Data

00AAh

0055h

0080h

00AAh

0055h

0010h

1

2

3

4

5

6

Unlock

Write

Setup Command

Unlock

Write

Unlock

Write

Chip Erase Command

Write

The following is a C source code example of using the chip erase function. Refer to the Spansion Low Level

Driver User’s Guide (www.spansion.comm) for general information on Spansion Flash memory software

development guidelines.

/* Example: Chip Erase Command */

/* Note: Cannot be suspended

*/

*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;

*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;

*( (UINT16 *)base_addr + 0x555 ) = 0x0080;

*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;

*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;

*( (UINT16 *)base_addr + 0x000 ) = 0x0010;

/* write unlock cycle 1

/* write unlock cycle 2

/* write setup command

*/

/* write additional unlock cycle 1 */

/* write additional unlock cycle 2 */

/* write chip erase command

*/

6.5.5

Erase Suspend/Erase Resume Commands

When the Erase Suspend command is written during the sector erase time-out, the device immediately

terminates the time-out period and suspends the erase operation. The Erase Suspend command allows the

system to interrupt a sector erase operation and then read data from, or program data to, any sector not

selected for erasure. The bank address is required when writing this command. This command is valid only

during the sector erase operation, including the minimum t_SEAtime-out period during the sector erase

command sequence. The Erase Suspend command is ignored if written during the chip erase operation.

When the Erase Suspend command is written after the t_SEAtime-out period has expired and during the sector

erase operation, the device requires a maximum of t_ESL(erase suspend latency) to suspend the erase

operation.

After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system

can read data from or program data to any sector not selected for erasure. (The device erase suspends all

sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status

information on DQ7-DQ0. The system can use DQ7, or DQ6, and DQ2 together, to determine if a sector is

actively erasing or is erase-suspended. Refer to Table 6.27 for information on these status bits.

After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode.

The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in

the standard program operation.

In the erase-suspend-read mode, the system can also issue the Autoselect command sequence. Refer to the

Write Buffer Programming section and the Autoselect section for details.

To resume the sector erase operation, the system must write the Erase Resume command. The bank

address of the erase-suspended bank is required when writing this command. Further writes of the Resume

command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing.

Note: While an erase operation can be suspended and resumed multiple times, a minimum delay of t_ERS

(Erase Resume to Suspend) is required from resume to the next suspend.

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Software Functions and Sample Code

Table 6.19 Erase Suspend

(LLD Function = lld_EraseSuspendCmd)

Cycle

Operation

Byte Address

Word Address

Data

1

Write

Bank Address

00B0h

The following is a C source code example of using the erase suspend function. Refer to the Spansion Low

Level Driver User’s Guide (www.spansion.com) for general information on Spansion Flash memory software

development guidelines.

/* Example: Erase suspend command */

*( (UINT16 *)bank_addr + 0x000 ) = 0x00B0;

/* write suspend command

*/

Table 6.20 Erase Resume

(LLD Function = lld_EraseResumeCmd)

Cycle

Operation

Byte Address

Word Address

Bank Address

Data

1

Write

Bank Address

0030h

The following is a C source code example of using the erase resume function. Refer to the Spansion Low

Level Driver User’s Guide (www.spansion.com) for general information on Spansion Flash memory software

development guidelines.

/* Example: Erase resume command */

*( (UINT16 *)bank_addr + 0x000 ) = 0x0030;

/* write resume command

*/

/* The flash needs adequate time in the resume state */

6.5.6

Program Suspend/Program Resume Commands

The Program Suspend command allows the system to interrupt an embedded programming operation or a

Write to Buffer programming operation so that data can read from any non-suspended sector. When the

Program Suspend command is written during a programming process, the device halts the programming

operation within t_PSL(program suspend latency) and updates the status bits. Addresses are don't-cares when

writing the Program Suspend command.

After the programming operation has been suspended, the system can read array data from any non-

suspended sector. The Program Suspend command may also be issued during a programming operation

while an erase is suspended. In this case, data may be read from any addresses not in Erase Suspend or

Program Suspend. If a read is needed from the Secured Silicon Sector area, then user must use the proper

command sequences to enter and exit this region.

The system may also write the Autoselect command sequence when the device is in Program Suspend

mode. The device allows reading Autoselect codes in the suspended sectors, since the codes are not stored

in the memory array. When the device exits the Autoselect mode, the device reverts to Program Suspend

mode, and is ready for another valid operation. See the Autoselect section for more information.

After the Program Resume command is written, the device reverts to programming. The system can

determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard

program operation. See the Write Operation Status section for more information.

The system must write the Program Resume command (address bits are don't care) to exit the Program

Suspend mode and continue the programming operation. Further writes of the Program Resume command

are ignored. Another Program Suspend command can be written after the device has resumed programming.

Note: While a program operation can be suspended and resumed multiple times, a minimum delay of t_PRS

(Program Resume to Suspend) is required from resume to the next suspend.

Software Functions and Sample Code

Table 6.21 Program Suspend

(LLD Function = lld_ProgramSuspendCmd)

Cycle

Operation

Byte Address

Word Address

Data

1

Write

Bank Address

00B0h

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The following is a C source code example of using the program suspend function. Refer to the Spansion Low

Level Driver User’s Guide (www.spansion.com) for general information on Spansion Flash memory software

development guidelines.

/* Example: Program suspend command */

*( (UINT16 *)base_addr + 0x000 ) = 0x00B0;

/* write suspend command

*/

Table 6.22 Program Resume

(LLD Function = lld_ProgramResumeCmd)

Cycle

Operation

Byte Address

Word Address

Bank Address

Data

1

Write

Bank Address

0030h

The following is a C source code example of using the program resume function. Refer to the Spansion Low

Level Driver User’s Guide (www.spansion.com) for general information on Spansion Flash memory software

development guidelines.

/* Example: Program resume command */

*( (UINT16 *)base_addr + 0x000 ) = 0x0030;

/* write resume command

*/

6.5.7

Accelerated Program/Sector Erase

Accelerated single word programming, write buffer programming and sector erase, operations are enabled

through the V_PPfunction. This method is faster than the standard chip program and erase command

sequences.

The accelerated chip program and erase functions must not be used more than 100 times per sector.

In addition, accelerated chip program and erase should be performed at room temperature

(30°C ±10°C).

If the system asserts V_HHon this input, the device automatically enters the accelerated mode and uses the

higher voltage on the input to reduce the time required for program and erase operations. The system can

then use the Write Buffer Load command sequence provided by the Unlock Bypass mode. Note that if a

Write-to-Buffer-Abort Reset is required while in Unlock Bypass mode, the full 3-cycle RESET command

sequence must be used to reset the device. Removing V_HHfrom the V_PPinput, upon completion of the

embedded program or erase operation, returns the device to normal operation.

Sectors must be unlocked prior to raising V_PPto V_HH

.

The V_PPpin must not be at V_HHfor operations other than accelerated programming and accelerated sector

erase, or device damage may result.

The V_PPpin must not be left floating or unconnected; inconsistent behavior of the device may result.

V_PPlocks all sector if set to V_IL; V_PPshould be set to V_IHfor all other conditions.

6.5.8

Unlock Bypass

The unlock bypass feature allows the system to primarily program to a bank faster than using the standard

program command sequence. The unlock bypass command sequence is initiated by first writing two unlock

cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then

enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is

required to program in this mode. The first cycle in this sequence contains the unlock bypass program

command, A0h; the second cycle contains the program address and data. Additional data is programmed in

the same manner. This mode dispenses with the initial two unlock cycles required in the standard program

command sequence, resulting in faster total programming time. The host system may also initiate the chip

erase and sector erase sequences in the unlock bypass mode. The erase command sequences are four

cycles in length instead of six cycles. Table 11.1 shows the requirements for the unlock bypass command

sequences.

During the unlock bypass mode, only the Read, Unlock Bypass Program, Unlock Bypass Sector Erase,

Unlock Bypass Chip Erase, and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode,

the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain

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the bank address and the data 90h. The second cycle need only contain the data 00h. The bank then returns

to the read mode.

The device offers accelerated program operations through the V_PPinput. When the system asserts V_HHon

this input, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle

Unlock Bypass program command sequence. The device uses the higher voltage on the V_PPinput to

accelerate the operation.

Refer to the Erase/Program Timing section for parameters, and Figures 10.12 and 10.13 for timing diagrams

Software Functions and Sample Code

The following are C source code examples of using the unlock bypass entry, program, and exit functions.

Refer to the Spansion Low Level Driver User’s Guide (www.spansion.com) for general information on

Spansion Flash memory software development guidelines.

Table 6.23 Unlock Bypass Entry

(LLD Function = lld_UnlockBypassEntryCmd)

Cycle

Description

Unlock

Operation

Write

Byte Address

Base + AAAh

Base + 554h

Base + AAAh

Word Address

Base + 555h

Base + 2AAh

Base + 555h

Data

00AAh

0055h

0020h

1

2

3

Unlock

Write

Entry Command

Write

/* Example: Unlock Bypass Entry Command

*/

*( (UINT16 *)bank_addr + 0x555 ) = 0x00AA;

*( (UINT16 *)bank_addr + 0x2AA ) = 0x0055;

*( (UINT16 *)bank_addr + 0x555 ) = 0x0020;

/* write unlock cycle 1

*/

/* write unlock cycle 2

*/

/* write unlock bypass command

/* At this point, programming only takes two write cycles.

/* Once you enter Unlock Bypass Mode, do a series of like

/* operations (programming or sector erase) and then exit

/* Unlock Bypass Mode before beginning a different type of

/* operations.

*/

Table 6.24 Unlock Bypass Program

(LLD Function = lld_UnlockBypassProgramCmd)

Cycle

Description

Operation

Write

Byte Address

Base + xxxh

Word Address

Base +xxxh

Data

1

2

Program Setup Command

Program Command

00A0h

Write

Program Address

Program Data

/* Example: Unlock Bypass Program Command */

/* Do while in Unlock Bypass Entry Mode! */

*( (UINT16 *)bank_addr + 0x555 ) = 0x00A0;

/* write program setup command

/* write data to be programmed

*/

*( (UINT16 *)pa )

= data;

*/

/* Poll until done or error.

/* If done and more to program, */

/* do above two cycles again. */

Table 6.25 Unlock Bypass Reset

(LLD Function = lld_UnlockBypassResetCmd)

Cycle

Description

Reset Cycle 1

Reset Cycle 2

Operation

Write

Byte Address

Base + xxxh

Word Address

Base +xxxh

Data

0090h

0000h

1

2

Write

/* Example: Unlock Bypass Exit Command */

*( (UINT16 *)base_addr + 0x000 ) = 0x0090;

*( (UINT16 *)base_addr + 0x000 ) = 0x0000;

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D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )

6.5.9

Write Operation Status

The device provides several bits to determine the status of a program or erase operation. The following

subsections describe the function of DQ1, DQ2, DQ3, DQ5, DQ6, and DQ7.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm

is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising

edge of the final WE# pulse in the command sequence. Note that the Data# Polling is valid only for the last

word being programmed in the write-buffer-page during Write Buffer Programming. Reading Data# Polling

status on any word other than the last word to be programmed in the write-buffer-page returns false status

information. Similarly, attempting to program 1 over a 0 does not return valid Date# information.

During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum

programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. The system must

provide the program address to read valid status information on DQ7. If a program address falls within a

protected sector, Data# polling on DQ7 is active for approximately t_PSP, then that bank returns to the read

mode.

During the Embedded Erase Algorithm, Data# polling produces a 0 on DQ7. When the Embedded Erase

algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a 1 on DQ7.

The system must provide an address within any of the sectors selected for erasure to read valid status

information on DQ7.

After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling

on DQ7 is active for approximately t_ASP, then the bank returns to the read mode. If not all selected sectors are

protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors

that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may

not be valid.

Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously

with DQ6-DQ1 while Output Enable (OE#) is asserted low. That is, the device may change from providing

status information to valid data on DQ7. Even if the device has completed the program or erase operation and

DQ7 has valid data, the data outputs on DQ6-DQ1 may be still invalid. Valid data on DQ7-D01 appears on

successive read cycles.

See the following for more information: Table 6.27, Write Operation Status, shows the outputs for Data#

Polling on DQ7. Table 6.5, Write Operation Status Flowchart, shows the Data# Polling algorithm; and

Figure 10.15, Data# Polling Timings (During Embedded Algorithm), shows the Data# Polling timing diagram.

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Figure 6.5 Write Operation Status Flowchart

START

(Note 6)

YES

Erase

Operation

Complete

DQ7=valid

data?

NO

YES

DQ5=1?

Read3= valid

data?

NO

Program

Operation

Failed

YES

Write Buffer

Programming?

YES

NO

Programming

Operation?

NO

Device BUSY,

Re-Poll

(Note 3)

(Note 5)

(Note 1)

YES

(Note 1)

(Note 2)

YES

DQ6

toggling?

DQ6

DEVICE

ERROR

TIMEOUT

toggling?

NO

(Note 4)

NO

YES

DQ1=1?

YES

NO

Device BUSY,

Re-Poll

DQ2

toggling?

NO

Device BUSY,

Re-Poll

Erase

Device in

Erase/Suspend

Mode

Operation

Complete

Read3 DQ1=1 YES

AND DQ7 ?

Valid Data?

Write Buffer

Operation Failed

NO

Notes:

1) DQ6 is toggling if Read2 DQ6 does not equal Read3 DQ6.

2) DQ2 is toggling if Read2 DQ2 does not equal Read3 DQ2.

3) May be due to an attempt to program a 0 to 1. Use the RESET command to exit operation.

4) Write buffer error if DQ1 of last read =1.

Device BUSY,

Re-Poll

5) Invalid state, use RESET command to exit operation.

6) Valid data is the data that is intended to be programmed or all 1's for an erase operation.

7) Data polling algorithm valid for all operations except advanced sector protection.

8) It can fail if one tries to program DQ7 from '0' to '1'

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete,

or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address in the

same bank, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the

program or erase operation), and during the sector erase time-out.

During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause

DQ6 to toggle. When the operation is complete, DQ6 stops toggling.

After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for

approximately t_ASP[all sectors protected toggle time], then returns to reading array data. If not all selected

sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the

selected sectors that are protected.

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The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-

suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6

toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must

also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use

DQ7 (see the subsection on DQ7: Data# Polling).

If a program address falls within a protected sector, DQ6 toggles for approximately t_PSPafter the program

command sequence is written, then returns to reading array data.

DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program

Algorithm is complete.

See the following for additional information: Figure 6.5, Write Operation Status Flowchart; Figure 10.16,

Toggle Bit Timings (During Embedded Algorithm), and Tables 6.26 and 6.27.

Toggle Bit I on DQ6 requires either OE# or CE# to be de-asserted and reasserted to show the change in state

DQ2: Toggle Bit II

The Toggle Bit II on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that

is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is

valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system

reads at addresses within those sectors that have been selected for erasure. But DQ2 cannot distinguish

whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the

device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for

erasure. Thus, both status bits are required for sector and mode information. Refer to Table 6.26 to compare

outputs for DQ2 and DQ6. See the following for additional information: Figure 6.5, the DQ6: Toggle Bit I

section, and Figures 10.15 – 10.18.

Table 6.26 DQ6 and DQ2 Indications

If device is

and the system reads

then DQ6

toggles,

and DQ2

does not toggle.

also toggles.

programming,

any address at the bank being programmed

at an address within a sector selected for erasure,

actively erasing,

at an address within sectors not selected for

toggles,

does not toggle.

toggles.

erasure,

at an address within a sector selected for erasure, does not toggle,

erase suspended,

at an address within sectors not selected for

returns array

data,

returns array data. The system can read

from any sector not selected for erasure.

erasure,

programming in

erase suspend

any address at the bank being programmed

toggles,

is not applicable.

Reading Toggle Bits DQ6/DQ2

Whenever the system initially begins reading toggle bit status, it must read DQ7 – DQ0 at least twice in a row

to determine whether a toggle bit is toggling. Typically, the system notes and stores the value of the toggle bit

after the first read. After the second read, the system compares the new value of the toggle bit with the first. If

the toggle bit is not toggling, the device has completed the program or erases operation. The system can read

array data on DQ7 – DQ0 on the following read cycle. However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high

(see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling,

since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling,

the device has successfully completed the program or erases operation. If it is still toggling, the device did not

complete the operation successfully, and the system must write the reset command to return to reading array

data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has

not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles,

determining the status as described in the previous paragraph. Alternatively, it may choose to perform other

system tasks. In this case, the system must start at the beginning of the algorithm when it returns to

determine the status of the operation. Refer to Figure 6.5 for more details.

Note: When verifying the status of a write operation (embedded program/erase) of a memory bank, DQ6 and

DQ2 toggle between high and low states in a series of consecutive and contiguous status read cycles. In

order for this toggling behavior to be properly observed, the consecutive status bit reads must not be

interleaved with read accesses to other memory banks. If it is not possible to temporarily prevent reads to

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other memory banks, then it is recommended to use the DQ7 status bit as the alternative method of

determining the active or inactive status of the write operation.

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a 1, indicating that the program or erase cycle was not successfully

completed. The device may output a 1 on DQ5 if the system tries to program a 1 to a location that was

previously programmed to 0. Only an erase operation can change a 0 back to a 1. Under this condition, the

device halts the operation, and when the timing limit has been exceeded, DQ5 produces a 1. Under both

these conditions, the system must write the reset command to return to the read mode (or to the erase-

suspend-read mode if a bank was previously in the erase-suspend-program mode).

DQ3: Sector Erase Timeout State Indicator

After writing a sector erase command sequence, the system may read DQ3 to determine whether or not

erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors

are selected for erasure, the entire time-out also applies after each additional sector erase command. When

the time-out period is complete, DQ3 switches from a 0 to a 1. If the time between additional sector erase

commands from the system can be assumed to be less than t_SEA, the system need not monitor DQ3. See the

Sector Erase Command Sequence, for more details.

After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6

(Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is

1, the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until

the erase operation is complete. If DQ3 is 0, the device accepts additional sector erase commands. To

ensure the command has been accepted, the system software should check the status of DQ3 prior to and

following each sub-sequent sector erase command. If DQ3 is high on the second status check, the last

command might not have been accepted. Table 6.27 shows the status of DQ3 relative to the other status bits.

DQ1: Write to Buffer Abort

DQ1 indicates whether a Write to Buffer operation was aborted. Under these conditions DQ1 produces a 1.

The system must issue the Write to Buffer Abort Reset command sequence to return the device to reading

array data. See Write Buffer Programming Operation for more details.

Table 6.27 Write Operation Status

Status

DQ7 (2)

DQ6

DQ5 (1)

DQ3

DQ2 (2)

DQ1 (4)

Embedded Program

Algorithm

DQ7#

Toggle

0

N/A

No toggle

0

Standard

Mode

Embedded Erase

Algorithm

0

Toggle

0

1

Toggle

N/A

INVALID

Reading within Program

Suspended Sector

Program

Suspend

Mode

(Not

Allowed)

(Not

Allowed)

(Not

Allowed)

(Not

Allowed)

(Not

Allowed)

(Not

Allowed)

Reading within Non-Program

Suspended Sector

(3)

Data

1

Data

0

Data

N/A

Data

N/A

Erase

Suspended

No toggle

Toggle

Sector

Erase-Suspend-

Read

Erase

Suspend

Mode

Non-Erase

Suspended

Sector

Data

Erase-Suspend-Program

BUSY State

DQ7#

Toggle

0

1

0

N/A

0

Write to

Buffer

(5)

Exceeded Timing Limits

ABORT State

0

1

Notes

1. DQ5 switches to 1 when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the

section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

3. Data are invalid for addresses in a Program Suspended sector.

4. DQ1 indicates the Write to Buffer ABORT status during Write Buffer Programming operations.

5. The data-bar polling algorithm should be used for Write Buffer Programming operations. Note that DQ7# during Write Buffer

Programming indicates the data-bar for DQ7 data for the LAST LOADED WRITE-BUFFER ADDRESS location.

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D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )

6.6

6.7

Simultaneous Read/Write

The simultaneous read/write feature allows the host system to read data from one bank of memory while

programming or erasing another bank of memory. An erase operation may also be suspended to read from or

program another location within the same bank (except the sector being erased). Figure 10.21, Back-to-Back

Read/Write Cycle Timings, shows how read and write cycles may be initiated for simultaneous operation with

zero latency. Refer to the DC Characteristics table for read-while-program and read-while-erase current

specification.

Writing Commands/Command Sequences

When the device is in Asynchronous read, only Asynchronous write operations are allowed. During an

asynchronous write operation, the system must drive CE# and WE# to V_ILand OE# to V_IHwhen providing an

address, command, and data. Addresses are latched on the rising edge of AVD#, while data is latched on the

rising edge of WE#. An erase operation can erase one sector, multiple sectors, or the entire device. Table 5.1

– Table 5.3 indicate the address space that each sector occupies. The device address space is divided into

sixteen banks: for NS512P, all 16 banks contain 64-Kword sectors while for NS256P and NS128P, Banks 0

through 14 contain only 64 Kword sectors, Bank 15 contains 16-Kword boot sectors in addition to 64 Kword

sectors. A bank address is the set of address bits required to uniquely select a bank. Similarly, a sector

address is the address bits required to uniquely select a sector. I_CC2in the DC Characteristics section

represents the active current specification for the write mode. AC Characteristics-Synchronous and AC

Characteristics-Asynchronous contain timing specification tables and timing diagrams for write operations.

6.8

6.9

Handshaking

The handshaking feature allows the host system to detect when data is ready to be read by simply monitoring

the RDY pin which is a dedicated output and is controlled by CE#.

Hardware Reset

The RESET# input provides a hardware method of resetting the device to reading array data. When RESET#

is driven low for at least a period of t_RP, the device immediately terminates any operation in progress, tristates

all outputs, resets the configuration register, and ignores all read/write commands for the duration of the

RESET# pulse. The device also resets the internal state machine to reading array data.

To ensure data integrity the operation that was interrupted should be reinitiated once the device is ready to

accept another command sequence.

When RESET# is held at V_SS, the device draws CMOS standby current (I_CC4). If RESET# is held at V_IL, but

not at V_SS, the standby current is greater.

RESET# may be tied to the system reset circuitry which enables the system to read the boot-up firmware

from the Flash memory upon a system reset.

See Figures 10.5 and 10.11 for timing diagrams.

6.10 Software Reset

Software reset is part of the command set (see Table 11.1) that also returns the device to array read mode

and must be used for the following conditions:

1. to exit Autoselect mode

2. when DQ5 goes high during write status operation that indicates program or erase cycle was not

successfully completed

3. exit sector lock/unlock operation.

4. to return to erase-suspend-read mode if the device was previously in Erase Suspend mode.

5. after any aborted operations

6. exiting read configuration registration Mode

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Software Functions and Sample Code

Table 6.28 Reset

(LLD Function = lld_ResetCmd)

Cycle

Operation

Byte Address

Word Address

Data

Reset Command

Write

Base + xxxh

00F0h

Note

Base = Base Address.

The following is a C source code example of using the reset function. Refer to the Spansion Low Level Driver

User’s Guide (www.spansion.com) for general information on Spansion Flash memory software development

guidelines.

/* Example: Reset (software reset of Flash state machine) */

*( (UINT16 *)base_addr + 0x000 ) = 0x00F0;

The following are additional points to consider when using the reset command:

This command resets the banks to the read and address bits are ignored.

Reset commands are ignored once erasure has begun until the operation is complete.

Once programming begins, the device ignores reset commands until the operation is complete

The reset command may be written between the cycles in a program command sequence before

programming begins (prior to the third cycle). This resets the bank to which the system was writing to the

read mode.

If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset

command returns that bank to the erase-suspend-read mode.

The reset command may be also written during an Autoselect command sequence.

If a bank has entered the Autoselect mode while in the Erase Suspend mode, writing the reset command

returns that bank to the erase-suspend-read mode.

If DQ1 goes high during a Write Buffer Programming operation, the system must write the Write to Buffer

Abort Reset command sequence to RESET the device to reading array data. The standard RESET

command does not work during this condition.

To exit the unlock bypass mode, the system must issue a two-cycle unlock bypass reset command

sequence [see command table for details].

6.11 Programmable Output Slew Rate Control

This feature allows the user to change the output slew rate during a read operation by setting the

configuration register bit CR1.4. It allows 2 programmable slew rates. This feature is for users who do not

want to run the part at its maximum speed and could live with a slower output slew rate thereby reducing

noise variations at the output.

Table 6.29 Programmable Output Slew Rate

Mode

Description

Full Drive (Default)

Half Drive

I

& I

OL OH

1

2

100 µA

50 µA

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7. Advanced Sector Protection/Unprotection

The Advanced Sector Protection/Unprotection feature disables or enables programming or erase operations

in any or all sectors and can be implemented through software and/or hardware methods, which are

independent of each other. This section describes the various methods of protecting data stored in the

memory array. An overview of these methods in shown in Figure 7.1.

Figure 7.1 Advanced Sector Protection/Unprotection

Hardware Methods

Software Methods

Lock Register

(One Time Programmable)

V

= V

IL

PP

All sectors locked)

Persistent Method

Password Method

(

(DQ1)

(DQ2)

WP# = V

IL

(All boot

sectors locked)

64-bit Password

(One Time Protect)

1. Bit is volatile, and defaults to 1 on

reset.

PPB Lock Bit^1,2,3

2. Programming to 0 locks all PPBs to

their current state.

0 = PPBs Locked

1 = PPBs Unlocked

3. Once programmed to 0, requires

hardware reset to unlock.

Persistent

Protection Bit

(PPB)^4,5

Dynamic

Protection Bit

(DYB)^6,7,8

Memory Array

Sector 0

Sector 1

Sector 2

PPB 0

PPB 1

PPB 2

DYB 0

DYB 1

DYB 2

Sector N-2

Sector N-1

PPB N-2

PPB N-1

PPB N

DYB N-2

DYB N-1

DYB N

Sector N³

3. N = Highest Address Sector.

4. 0 = Sector Protected,

1 = Sector Unprotected.

6. 0 = Sector Protected,

1 = Sector Unprotected.

5. PPBs programmed individually,

but cleared collectively

7. Protect effective only if PPB Lock Bit

is unlocked and corresponding PPB

is 1 (unprotected).

8. Volatile Bits: defaults to protected

after power up.

7.1

Lock Register

The Lock Register consists of 5 bits. The Secured Silicon Sector Protection Bit is DQ0, Persistent Protection

Mode Lock Bit is DQ1, Password Protection Mode Lock Bit is DQ2, Persistent Sector Protection OTP bit is

DQ3 and Volatile Sector Protection Boot bit is DQ4. If DQ0 is 0, it means that the Customer Secured Silicon

area is locked and if DQ0 is 1, it means that it is unlocked. When DQ2 is set to 1 and DQ1 is set to 0, the

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device can only be used in the Persistent Protection Mode. When the device is set to Password Protection

Mode, DQ1 is required to be set to 1 and DQ2 is required to be set to 0. DQ3 is programmed in the Spansion

factory. When the device is programmed to disable all PPB erase command, DQ3 outputs a 0, when the lock

register bits are read. Similarly, if the device is programmed to enable all PPB erase command, DQ3 outputs

a 1 when the lock register bits are read. Likewise the DQ4 bit is also programmed in the Spansion Factory.

DQ4 is the bit which indicates whether Volatile Sector Protection Bit (DYB) is protected or not after boot up.

When the device is programmed to set all Volatile Sector Protection Bit protected after power up, DQ4

outputs a 0 when the lock register bits are read. Similarly, when the device is programmed to set all Volatile

Sector Protection Bit unprotected after power up, DQ4 outputs a 1. Each of these bits in the lock register are

non-volatile. DQ15 – DQ5 are reserved and are 1s.

Lock Register

DQ15-5

DQ4

DQ3

DQ2

DQ1

DQ0

PPB One Time

Programmable Bit

DYB Lock Boot Bit

0 = DYB bits power up

protected (Default)

Password

Protection

Mode Lock Bit

Persistent

Protection

Mode Lock Bit

Secured

Silicon Sector

Protection Bit

0 = All PPB Erase

Command disabled

1s

1 = DYB bits power up

unprotected

1 = All PPB Erase

Command enabled

For programming lock register bits refer to Table 11.2.

Notes

1. If the password mode is chosen, the password must be programmed and verified before setting the

corresponding lock register bit.

2. It is recommended that a sector protection method to be chosen by programming DQ1 or DQ2

prior to shipment

3. After the Lock Register Bits Command Set Entry command sequence is written, reads and writes

for Bank 0 are disabled, while reads from other banks are allowed until exiting this mode.

4. If both lock bits are selected to be programmed (to zeros) at the same time, the operation aborts.

5. Once the Password Mode Lock Bit is programmed, the Persistent Mode Lock Bit is permanently

disabled, and no changes to the protection scheme are allowed. Similarly, if the Persistent Mode

Lock Bit is programmed, the Password Mode is permanently disabled.

6. During erase/program suspend, ASP entry commands are not allowed.

7. Data Polling can be done immediately after the lock register programming command sequence (no

delay required). Note that status polling can be done only in bank 0.

8. Reads from other banks (simultaneous operation) are not allowed during lock register

programming. This restriction applies to both synchronous and asynchronous read operations.

After selecting a sector protection method, each sector can operate in any of the following three states:

1. Constantly locked. The selected sectors are protected and can not be reprogrammed unless PPB

lock bit is cleared via a password, hardware reset, or power cycle.

2. Dynamically locked. The selected sectors are protected and can be altered via software

commands.

3. Unlocked. The sectors are unprotected and can be erased and/or programmed.

These states are controlled by the bit types described in Sections 7.2 – 7.6.

7.2

Persistent Protection Bits

The Persistent Protection Bits are unique and nonvolatile for each sector and have the same endurances as

the Flash memory. Preprogramming and verification prior to erasure are handled by the device, and therefore

do not require system monitoring.

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Notes

1. Each PPB is individually programmed and all are erased in parallel.

2. While programming PPB for a sector, array data can be read from any other bank, except Bank 0

(used for Data# Polling) and the bank in which sector PPB is being programmed.

3. Entry command disables reads and writes for the bank selected.

4. Reads within that bank return the PPB status for that sector.

5. Reads from other banks are allowed while writes are not allowed.

6. All Reads must be performed using the Asynchronous mode.

7. The specific sector address (Amax – A14) are written at the same time as the program command.

8. If the PPB Lock Bit is set, the PPB Program or erase command does not execute and time out

without programming or erasing the PPB.

9. There are no means for individually erasing a specific PPB and no specific sector address is

required for this operation.

10.PPB exit command must be issued after the execution which resets the device to read mode and

re-enables reads and writes for Bank 0

11.The programming state of the PPB for a given sector can be verified by writing a PPB Status Read

Command to the device as described by the flow chart shown in Figure 7.2.

12.During PPB program/erase data polling can be done synchronously.

13.If customers attempt to program or erase a protected sector, the device ignores the command and

returns to read mode.

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Figure 7.2 PPB Program/Erase Algorithm

Enter PPB

Command Set.

Addr = BA

Program PPB Bit.

Addr = SA

Read Byte Twice

Addr = SA0

No

DQ6 =

Toggle?

Yes

No

DQ5 = 1?

Wait 500 µs

Yes

Read Byte Twice

Addr = SA0

No

Read Byte.

Addr = SA

DQ6 =

Toggle?

Yes

DQ0 =

No

'1' (Erase)

'0' (Pgm.)?

FAIL

Yes

PASS

Exit PPB

Command Set

7.3

Dynamic Protection Bits

Dynamic Protection Bits are volatile and unique for each sector and can be individually modified. DYBs only

control the protection scheme for unprotected sectors that have their PPBs cleared (erased to 1). By issuing

the DYB Set or Clear command sequences, the DYBs are set (programmed to 0) or cleared (erased to 1),

thus placing each sector in the protected or unprotected state respectively. This feature allows software to

easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when

changes are needed.

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Notes

1. The DYBs can be set (programmed to 0) or cleared (erased to 1) as often as needed.

2. When the parts are first shipped, the DYBs are set and programmed to 0 upon power up or reset.

3. The default state of DYB is protected after power up and all sectors can be modified depending on

the status of PPB bit for that sector, (erased to 1). Then the sectors can be modified depending

upon the PPB state of that sector (see Table 7.1).

4. It is possible to have sectors that are persistently locked with sectors that are left in the dynamic

state.

5. The DYB Set or Clear commands for the dynamic sectors signify protected or unprotectedstate of

the sectors respectively. However, if there is a need to change the status of the persistently locked

sectors, a few more steps are required. First, the PPB Lock Bit must be cleared by either putting

the device through a power cycle, or hardware reset. The PPBs can then be changed to reflect the

desired settings. Setting the PPB Lock Bit once again locks the PPBs, and the device operates

normally again.

6. To achieve the best protection, it is recommended to execute the PPB Lock Bit Set command early

in the boot code and protect the boot code by holding WP# = V_IL.

7. Data polling is not available for DYB program/erase.

8. DYB read data can be done synchronously.

9. If customers attempt to program or erase a protected sector, the device ignores the command and

returns to read mode.

7.4

Persistent Protection Bit Lock Bit

The Persistent Protection Bit Lock Bit is a global volatile bit for all sectors. When set (programmed to 0), it

locks all PPBs and when cleared (programmed to 1), allows the PPBs to be changed. There is only one PPB

Lock Bit per device.

Notes

1. If the password mode is chosen, then the password must be programmed and verified before

setting the corresponding lock register bit.

2. No software command sequence unlocks this bit unless the device is in the password protection

mode; only a hardware reset or a power up clears this bit.

3. The PPB Lock Bit must be set (programmed to 0) only after all PPBs are configured to the desired

settings.

7.5

Password Protection Method

The Password Protection Method allows an even higher level of security than the Persistent Sector Protection

Mode by requiring a 64 bit password for unlocking the device PPB Lock Bit. In addition to this password

requirement, after power up and reset, the PPB Lock Bit is set 0 to maintain the password mode of operation.

Successful execution of the Password Unlock command by entering the entire password clears the PPB Lock

Bit, allowing for sector PPBs modifications.

Notes

1. There is no special addressing order required for programming the password. Once the Password

is written and verified, the Password Mode Locking Bit must be set in order to prevent access.

2. The Password Program Command is only capable of programming 0s. Programming a 1 after a

cell is programmed as a 0 results in a time out with the cell as a 0.

3. The password is all 1s when shipped from the factory.

4. All 64-bit password combinations are valid as a password.

5. There is no means to verify what the password is after it is set.

6. The Password Mode Lock Bit, once set, prevents reading the 64-bit password on the data bus and

further password programming.

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7. The Password Mode Lock Bit is not erasable.

8. The lower two address bits (A1 – A0) are valid during the Password Read, Password Program, and

Password Unlock.

9. The exact password must be entered in order for the unlocking function to occur.

10.The Password Unlock command cannot be issued any faster than 1 µs at a time to prevent a

hacker from running through all the 64-bit combinations in an attempt to correctly match a

password.

11.Approximately 1 µs is required for unlocking the device after the valid 64-bit password is given to

the device.

12.Password verification is only allowed during the password programming operation.

13.All further commands to the password region are disabled and all operations are ignored.

14.If the password is lost after setting the Password Mode Lock Bit, there is no way to clear the PPB

Lock Bit.

15.Entry command sequence must be issued prior to any of any operation and it disables reads and

writes for Bank 0. Reads and writes for other banks excluding Bank 0 are allowed.

16.If the user attempts to program or erase a protected sector, the device ignores the command and

returns to read mode.

17.A program or erase command to a protected sector enables status polling and returns to read

mode without having modified the contents of the protected sector.

18.The programming of the DYB, PPB, and PPB Lock for a given sector can be verified by writing

individual status read commands DYB Status, PPB Status, and PPB Lock Status to the device.

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Figure 7.3 Lock Register Program Algorithm

Write Unlock Cycles:

Address 555h, Data AAh

Address 2AAh, Data 55h

Unlock Cycle 1

Unlock Cycle 2

Write

Enter Lock Register Command:

Address 555h, Data 40h

XXXh = Address don’t care

Program Lock Register Data

Address XXXh, Data A0h

Address 77h*, Data PD

* Not on future devices

Program Data (PD): See text for Lock Register

definitions

Caution: Lock register can only be progammed

once.

Wait 4 μs (recommended)

Perform Polling Algorithm

(see Write Operation Status

flowchart)

Yes

Done?

No

DQ5 = 1?

Yes

Error condition (Exceeded Timing Limits)

PASS. Write Lock Register

Exit Command:

FAIL. Write rest command

to return to reading array.

Address XXXh, Data 90h

Address XXXh, Data 00h

Device returns to reading array.

7.6

Advanced Sector Protection Software Examples

Table 7.1 Sector Protection Schemes

Unique Device PPB Lock Bit

0 = locked

Sector PPB

0 = protected

1 = unprotected

Sector DYB

0 = protected

1 = unprotected

Sector Protection Status

1 = unlocked

Any Sector

0

1

0

1

0

1

x

1

0

x

0

1

Protected through PPB

Unprotected

Protected through DYB

Protected through PPB

Protected through DYB

Unprotected

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Table 7.1 contains all possible combinations of the DYB, PPB, and PPB Lock Bit relating to the status of the

sector.

7.7

Hardware Data Protection Methods

The device offers two main types of data protection at the sector level via hardware control:

When WP# is at V_IL, the highest two sectors are locked (device specific).

When V_PPis at V_IL, all sectors are locked.

There are additional methods by which intended or accidental erasure of any sectors can be prevented via

hardware means. The following subsections describes these methods:

WP# Method

The Write Protect feature provides a hardware method of protecting the highest two sectors (NS256P and

NS128P). This function is provided by the WP# pin and overrides the previously discussed Sector Protection/

Unprotection method.

If the system asserts V_ILon the WP# pin, the device disables program and erase functions in the highest two

sectors (NS256P and NS128P) as well as Secured Silicon Area.

If the system asserts V_IHon the WP# pin, the device reverts to whether the boot sectors were last set to be

protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether

they were last protected or unprotected.

Note that the WP# pin must not be left floating or unconnected as inconsistent behavior of the device may

result.

The WP# pin must be held stable during a command sequence execution

V

Method

PP

This method is similar to above, except it protects all sectors (including the Secured Silicon Area). Once V_PP

input is set to V_IL, all program and erase functions are disabled and hence all sectors are protected.

Low V Write Inhibit

CC

When V_CCis less than V_LKO, the device does not accept any write cycles. This protects data during V_CC

power up and power down.

The command register and all internal program/erase circuits are disabled, and the device resets to reading

array data. Subsequent writes are ignored until V_CCis greater than V_LKO. The system must provide the

proper signals to the control inputs to prevent unintentional writes when V_CCis greater than V_LKO

.

Write Pulse Glitch Protection

Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

Power-Up Write Inhibit

If WE# = CE# = RESET# = V_ILand OE# = V_IHduring power up, the device does not accept commands on the

rising edge of WE#. The internal state machine is automatically reset to the read mode on power up.

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8. Power Conservation Modes

8.1

8.2

8.3

Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby mode. In this

mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state,

independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET#

inputs are both held at V_CC0.2 V. The device requires standard access time (t_CE) for read access, before it

is ready to read data. If the device is deselected during erasure or programming, the device draws active

current until the operation is completed. I_CC3in the DC Characteristics section represents the standby current

specification

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption while in asynchronous mode. the

device automatically enables this mode when addresses remain stable for t_ACC+ 20 ns. The automatic sleep

mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide

new data when addresses are changed. While in sleep mode, output data is latched and always available to

the system. While in synchronous mode, the automatic sleep mode is disabled. Note that a new burst

operation is required to provide new data. I_CC6in the DC Characteristics section represents the automatic

sleep mode current specification.

Hardware RESET# Input Operation

The RESET# input provides a hardware method of resetting the device to reading array data. When RESET#

is driven low for at least a period of t_RP, the device immediately terminates any operation in progress, tristates

all outputs, resets the configuration register, and ignores all read/write commands for the duration of the

RESET# pulse. The device also resets the internal state machine to reading array data. The operation that

was interrupted should be reinitiated once the device is ready to accept another command sequence to

ensure data integrity.

When RESET# is held at V_SS0.2 V, the device draws CMOS standby current (I_CC4). If RESET# is held at

V_ILbut not within V_SS0.2 V, the standby current is greater.

RESET# may be tied to the system reset circuitry and thus, a system reset also resets the Flash memory,

enabling the system to read the boot-up firmware from the Flash memory.

8.4

Output Disable (OE#)

When the OE# input is at V_IH, output from the device is disabled. The outputs are placed in the high

impedance state.

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9. Secured Silicon Sector Flash Memory Region

The Secured Silicon Sector provides an extra Flash memory region that enables permanent part identification

through an Electronic Serial Number (ESN). The Secured Silicon Sector is 256 words in length that consists

of 128 words for factory data and 128 words for customer-secured areas. All Secured Silicon reads outside of

the 256-word address range returns invalid data. The Factory Indicator Bit, DQ7, (at Autoselect address 03h)

is used to indicate whether or not the Factory Secured Silicon Sector is locked when shipped from the factory.

The Customer Indicator Bit (DQ6) is used to indicate whether or not the Customer Secured Silicon Sector is

locked when shipped from the factory.

Please note the following general conditions:

While Secured Silicon Sector access is enabled, simultaneous operations are allowed except for Bank 0.

On power-up, or following a hardware reset, the device reverts to sending commands to the normal

address space.

Reads can be performed in the Asynchronous or Synchronous mode.

Burst mode reads within Secured Silicon Sector wrap from address FFh back to address 00h.

Reads outside of sector 0 return memory array data.

Continuous burst read past the maximum address is undefined.

Sector 0 is remapped from memory array to Secured Silicon Sector array.

Once the Secured Silicon Sector Entry Command is issued, the Secured Silicon Sector Exit command

must be issued to exit Secured Silicon Sector Mode.

The Secured Silicon Sector is not accessible when the device is executing an Embedded Program or

Embedded Erase algorithm.

Table 9.1 Secured Silicon SectorSecure Sector Addresses

Sector

Customer

Factory

Sector Size

128 words

Address Range

000080h-0000FFh

000000h-00007Fh

9.1

Factory Secured Silicon Sector

The Factory Secured Silicon Sector is always protected when shipped from the factory and has the Factory

Indicator Bit (DQ7) permanently set to a 1. This prevents cloning of a factory locked part and ensures the

security of the ESN and customer code once the product is shipped to the field.

These devices are available pre programmed with one of the following:

A random, 8 Word secure ESN only within the Factory Secured Silicon Sector

Customer code within the Customer Secured Silicon Sector through the Spansion^TMprogramming service.

Both a random, secure ESN and customer code through the Spansion programming service.

Customers may opt to have their code programmed through the Spansion programming services. Spansion

programs the customer's code, with or without the random ESN. The devices are then shipped from the

Spansion factory with the Factory Secured Silicon Sector and Customer Secured Silicon Sector permanently

locked. Contact your local representative for details on using Spansion programming services.

9.2

Customer Secured Silicon Sector

The Customer Secured Silicon Sector is typically shipped unprotected (DQ6 set to 0), allowing customers to

utilize that sector in any manner they choose. If the security feature is not required, the Customer Secured

Silicon Sector can be treated as an additional Flash memory space.

Please note the following:

Once the Customer Secured Silicon Sector area is protected, the Customer Indicator Bit is permanently

set to 1.

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The Customer Secured Silicon Sector can be read any number of times, but can be programmed and

locked only once. The Customer Secured Silicon Sector lock must be used with caution as once locked,

there is no procedure available for unlocking the Customer Secured Silicon Sector area and none of the

bits in the Customer Secured Silicon Sector memory space can be modified in any way.

The accelerated programming (V_PP) and unlock bypass functions are not available when programming the

Customer Secured Silicon Sector, but reading in Banks 1 through 15 is available.

Once the Customer Secured Silicon Sector is locked and verified, the system must write the Exit Secured

Silicon Sector Region command sequence which return the device to the memory array at sector 0.

9.3

Secured Silicon Sector Entry and Exit Command Sequences

The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon

Sector command sequence. The device continues to access the Secured Silicon Sector region until the

system issues the four-cycle Exit Secured Silicon Sector command sequence.

See Command Definition Table [Secured Silicon Sector Command Table, Appendix

Table 11.1 for address and data requirements for both command sequences.

The Secured Silicon Sector Entry Command allows the following commands to be executed

Read customer and factory Secured Silicon areas

Program the customer Secured Silicon Sector

After the system has written the Enter Secured Silicon Sector command sequence, it may read the Secured

Silicon Sector by using the addresses normally occupied by sector SA0 within the memory array. This mode

of operation continues until the system issues the Exit Secured Silicon Sector command sequence, or until

power is removed from the device.

Software Functions and Sample Code

The following are C functions and source code examples of using the Secured Silicon Sector Entry, Program,

and exit commands. Refer to the Spansion Low Level Driver User’s Guide (www.spansion.com) for general

information on Spansion Flash memory software development guidelines.

Table 9.2 Secured Silicon Sector Entry (LLD Function = lld_SecSiSectorEntryCmd)

Cycle

Operation

Write

Byte Address

Base + AAAh

Base + 554h

Base + AAAh

Word Address

Base + 555h

Base + 2AAh

Base + 555h

Data

00AAh

0055h

0088h

Unlock Cycle 1

Unlock Cycle 2

Entry Cycle

Write

Note

Base = Base Address.

/* Example: Secured Silicon Sector Entry Command */

*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;

*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;

*( (UINT16 *)base_addr + 0x555 ) = 0x0088;

/* write unlock cycle 1

/* write unlock cycle 2

*/

/* write Secured Silicon Sector Entry

Cmd

*/

Table 9.3 Secured Silicon Sector Program (LLD Function = lld_ProgramCmd)

Cycle

Operation

Write

Byte Address

Base + AAAh

Base + 554h

Base + AAAh

Word Address

Base + 555h

Base + 2AAh

Base + 555h

Word Address

Data

00AAh

Unlock Cycle 1

Unlock Cycle 2

Program Setup

Program

Write

0055h

Write

00A0h

Write

Data Word

Note

Base = Base Address.

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/* Once in the Secured Silicon Sector mode, you program */

/* words using the programming algorithm.

*/

Table 9.4 Secured Silicon Sector Exit (LLD Function = lld_SecSiSectorExitCmd)

Cycle

Operation

Write

Byte Address

Base + AAAh

Base + 554h

Base + AAAh

Any address

Word Address

Base + 555h

Base + 2AAh

Base + 555h

Any address

Data

00AAh

0055h

0090h

0000h

Unlock Cycle 1

Unlock Cycle 2

Exit Cycle 3

Exit Cycle 4

Write

Note

Base = Base Address.

/* Example: Secured Silicon Sector Exit Command */

*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;

*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;

*( (UINT16 *)base_addr + 0x555 ) = 0x0090;

cycle 3 */

/* write unlock cycle 1

/* write unlock cycle 2

*/

/* write Secured Silicon Sector Exit

*( (UINT16 *)base_addr + 0x000 ) = 0x0000;

cycle 4 */

/* write Secured Silicon Sector Exit

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10. Electrical Specifications

10.1 Absolute Maximum Ratings

Storage Temperature Plastic Packages

Ambient Temperature with Power Applied

–65°C to +150°C

–65°C to +125°C

–0.5 V to + 2.5 V

Voltage with Respect to Ground: All Inputs and I/Os except as noted below (1)

(1)

V

–0.5 V to +2.5 V

–0.5 V to +9.5 V

100 mA

CC

V

(2)

PP

Output Short Circuit Current (3)

Notes

1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs or I/Os may undershoot V to –2.0 V for periods of up

SS

to 20 ns. See Figure 10.1. Maximum DC voltage on input or I/Os is V + 0.5 V. During voltage transitions outputs may overshoot to V

CC

+ 2.0 V for periods up to 20 ns. See Figure 10.2.

2. Minimum DC input voltage on pin V is –0.5V. During voltage transitions, V may overshoot V to –2.0 V for periods of up to 20 ns.

PP

SS

See Figure 10.1. Maximum DC voltage on pin V is +9.5 V, which may overshoot to 10.5 V for periods up to 20 ns.

PP

3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.

4. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;

functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not

implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.

Figure 10.1 Maximum Negative Overshoot Waveform

20 ns

+0.8 V

–0.5 V

–2.0 V

20 ns

Figure 10.2 Maximum Positive Overshoot Waveform

20 ns

V

+2.0 V

CC

V

+0.5 V

CC

1.0 V

20 ns

10.2 Operating Ranges

Wireless (I) Devices

Ambient Temperature (T )

–25°C to +85°C

A

Supply Voltages

V

Supply Voltages

+1.70 V to +1.95 V

CC

Note

Operating ranges define those limits between which the functionality of the device is guaranteed.

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10.3 DC Characteristics

10.3.1 CMOS Compatible

Table 10.1 DC Characteristics—CMOS Compatible

Parameter

Description

Test Conditions (1)

Min

Typ

Max

1

Unit

µA

I

Input Load Current

V

= V to V , V = V max

SS CC CC CC

LI

IN

I

Output Leakage Current

= V to V , V = V max

1

µA

LO

OUT

SS

CC CC

CC

108 Mhz

83 Mhz

66 Mhz

108 Mhz

83 Mhz

66 Mhz

108 Mhz

83 Mhz

66 Mhz

108 Mhz

83 Mhz

66 Mhz

10 MHz

5 MHz

33

26

24

30

26

24

25

28

26

32

30

28

40

20

10

1

44

36

33

40

38

35

33

40

37

44

42

39

80

40

20

5

mA

µA

CE# = V , OE# = V

,

IH

IL

WE# = V , burst length =

IH

8

CE# = V , OE# = V

,

IH

IL

WE# = V , burst length =

IH

16

I

V

Active burst Read Current

CC

CCB

CE# = V , OE# = V

,

IH

IL

WE# = V , burst length =

IH

32

CE# = V , OE# = V

,

IH

IL

WE# = V , burst length =

IH

Continuous

V

Active Asynchronous Read

CE# = V , OE# = V

,

CC

IL

IH

I

CC1

Current (2)

WE# = V

IH

1 MHz

V

PP

CC

CE# = V , OE# = V

IL

I

V

Active Write Current (3)

Standby Current (4)

CC2

CC

V

= VI

PP

H

V

<20

1

<40

5

mA

µA

V

CE# = RESET# =

0.2 V

PP

CC3

V

CC

V

20

150

70

250

µA

CC

I

V

Reset Current

Active Current

RESET# = V CLK = V

IL

µA

CC4

CC5

CC6

CC

IL,

CE# = V , OE# = V , V = V , (7)

50

60

mA

IL

IH

PP

IH

(Read While Write)

V

Sleep Current

CE# = V , OE# = V

5

40

µA

mA

V

CC

IL

IH

V

<7

<10

<20

0.4

PP

Accelerated Program Current

(5)

CE# = V , OE# = V

IL IH,

I

PPW

V

= 9.5 V

PP

V

<15

CC

V

Input Low Voltage

–0.2

IL

V

0.4

–

V

0.4

+

CC

V

Input High Voltage

IH

V

Output Low Voltage

I

= 100 µA, V = V

= V

CC

0.1

V

OL

OH

OL

CC

CC min

V

0.1

–

CC

V

Output High Voltage

Voltage for Accelerated Program

= –100 µA, V = V

OH CC CC min

V

8.5

9.5

1.4

V

HH

V

Low V Lock-out Voltage

CC

LKO

Notes

1. Maximum I specifications are tested with V = V max.

CC

2. The I current listed is typically less than 2 mA/MHz, with OE# at V

.

CC

IH

3.

I

active while Embedded Erase or Embedded Program is in progress.

CC

4. Device enters automatic sleep mode when addresses are stable for t

+ 20 ns. Typical sleep mode current is equal to I

.

ACC

CC3

5. Total current during accelerated programming is the sum of V and V currents.

PP

CC

6.

7. Clock frequency 66 Mhz and in Continuous Mode.

8. For I , when V = V , V = V

V

= V during all ICC measurements.

CCQ CC

.

SS

CC6

IH

IO IL

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10.4 Test Conditions

Figure 10.3 Test Setup

Device

Under

Test

C

L

Table 10.2 Test Specifications

Test Condition

Output Load Capacitance, C (including jig capacitance)

All Speed Options

Unit

pF

ns

V

30

L,

Input Rise and Fall Times

Input Pulse Levels

1.0 – 1.50

0.0 – V

CC

Input timing measurement reference levels

Output timing measurement reference levels

V

/2

V

CC

V

/2

V

CCQ

10.5 Key to Switching Waveforms

Waveform

Inputs

Outputs

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

10.6 Switching Waveforms

Figure 10.4 Input Waveforms and Measurement Levels

V_CC

All Inputs and Outputs

V_CC/2

V_CCQ/2

Input

Measurement Level

Output

0.0 V

Table 10.3 V_CCPower-Up with No Ramp Rate Restriction

Parameter

Description

Setup Time

CC

Test Setup

Min

Time

Unit

µs

t

V

30

VCS

t

Time between RESET# (high) and CE# (low)

Min

200

ns

RH

Note

and V

V

must be ramped simultaneously for proper power-up.

CCQ

CC

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Figure 10.5 V_CCPower-Up Diagram

t_VCS

V_{CC min}

V_CC

V_IH

RESET#

t_RH

CE#

10.7 CLK Characterization

Table 10.4 CLK Characterization

Parameter

Description

66 MHz

83 MHz

83

108 MHz

Unit

Max

Min

66

108

MHz

60 KHz in 8 word Burst,

120 KHz in 16 word Burst,

250 KHz in 32 word Burst,

1 MHz in Continuous Mode

f

CLK Frequency

CLK

t

CLK Period

Min

Max

15.1

3.0

12.5

9.26

ns

CLK

0.40 t

0.60 t

CLK

t

/t

CLK Low/High Time

CL CH

t

CLK Rise Time

CLK Fall Time

CR

Max

2.5

1.5

ns

t

CF

Figure 10.6 CLK Characterization

t_CLK

t_CH

t_CL

CLK

t_CF

t_CR

10.8 AC Characteristics

10.8.1 Synchronous/Burst Read

Table 10.5 Synchronous/Burst Read

Parameter

JEDEC Standard

Description

66 MHz

83 MHz 108 MHz

Unit

t

Synchronous Access Time

Max

Min

Max

80

ns

IACC

t

Burst Access Time Valid Clock to Output Delay

Address Setup Time to CLK (1)

Address Hold Time from CLK (1)

Data Hold Time

11.2

9

4

7.6

BACC

t

ACS

ACH

BDH

t

6

3

5

2

t

3

t

Chip Enable to RDY Active

10

RDY

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Table 10.5 Synchronous/Burst Read

Parameter

JEDEC Standard

Description

Output Enable to RDY Low

66 MHz

83 MHz 108 MHz

Unit

t

Max

Min

Max

Min

9

10

4

9

ns

OE

t

Chip Enable to High Z

Output Enable to High Z

CE# Setup Time to CLK

Ready Access Time from CLK

CE# Setup Time to AVD#

AVD# Low to CLK Setup Time

AVD# Hold Time to CLK

AVD# High to OE# Low

AVD# Pulse

10

CEZ

OEZ

CES

t

11.2

9

7.5

RACC

t

0

CAS

AVDS

AVDH

t

5

t

3

t

0

AVD0

t

6

AVD

Notes

1. Addresses are latched on the rising edge of CLK

2. Synchronous Access Time is calculated using the formula (#of WS – 1)*(clock period) + (t

or Clock to Out)

BACC

3. Not 100% tested for t

, t

.

CEZ OEZ

Table 10.6 Synchronous Wait State Requirements

Max Frequency

Wait State Requirement

Frequency ≤ 14 MHz

2

3

4

5

6

7

8

9

14 < Frequency ≤ 27MHz

27 MHz < Frequency ≤ 40 MHz

40 MHz < Frequency ≤ 54 MHz

54 MHz < Frequency ≤ 66 MHz

66 MHz < Frequency ≤ 80 MHz

80 MHz < Frequency ≤ 95 MHz

95 MHz < Frequency ≤ 108 MHz

Figure 10.7 8-Word Linear Synchronous Single Data Rate Burst with Wrap Around

t_CES

7 cycles for initial access is shown as an illustration.

CE#

CLK

1

2

3

4

5

6

7

t_AVDS

AVD#

t_AVD

t_ACS

AC

Amax

–

A16

t_ACH

t_BACC

DC

AC

A/DQ15

–

A/DQ0

DD

DE

DB

t_IACC

t_BDH

OE#

t_RDY

t_RACC

t_OE

Hi-Z

RDY

Notes

1. Figure shows for illustration the total number of wait states set to seven cycles.

2. The device is configured synchronous single data rate mode and RDY active with data.

3. CE# (High) drives the RDY to Hi-Z while OE# (High) drives the A/DQ15 – A/DQ0 pins to Hi-Z

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Figure 10.8 8-Word Linear Single Data Read Synchronous Burst without Wrap Around

7

cycles for initial access shown.

t_CES

CE#

CLK

1

2

3

4

5

6

7

t_AVDS

AVD#

t_AVD

t_ACS

AC

Amax–

A16

t_ACH

AC

t_BACC

A/DQ15–

A/DQ0

DC

DD

DE

DF

D13

t_IACC

D10

t_BDH

OE#

t_CR

t_RACC

t_OE

Hi-Z

RDY

t_RDYS

Notes

1. Figure shows for illustration the total number of wait states set to seven cycles.

2. The device is configured synchronous single data rate mode and RDY active with data.

3. CE# (High) drives the RDY to Hi-Z while OE# (High) drives the A/DQ15 – A/DQ0 pins to HI-Z

10.8.2

Asynchronous Mode Read

Table 10.7 Asynchronous Mode Read

Parameter

Description

66 MHz

83 MHz 108 MHz Unit

JEDEC Standard

t

Access Time from CE# Low

Typ

Max

Min

Max

Min

Max

Min

83

80

7.5

5

ns

CE

t

Asynchronous Access Time

ACC

t

AVD# Low Time

AVDP

AAVDS

AAVDH

t

Address Setup Time to Rising Edge of AVD#

Address Hold Time from Rising Edge of AVD#

Output Enable to Output Valid

t

3.5

9

t

9

OE

Read

0

t

Output Enable Hold Time

OEH

Toggle and Data# Polling

10

0

10

t

Output Enable to High Z

CE# Setup Time to AVD#

OEZ

CAS

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Figure 10.9 Asynchronous Mode Read with Latched Addresses

CE#

OE#

WE

t_OE

t_OEH

t_CE

t_OEZ

A/DQ15–

A/DQ0

RA

Valid RD

t_ACC

Amax–

A16

t_{AAVDH =0ns}

t_CAS

AVD#

t_AVDP

t_AAVDS

Note

RA = Read Address, RD = Read Data.

Figure 10.10 Asynchronous Mode Read

CE#

OE#

WE#

t_OE

t_OEH

t_CE

t_OEZ

A/DQ15–

A/DQ0

RA

t_ACC

Valid RD

RA

Amax–A16

AVD#

t_AAVDH

t_AVDP

t_AAVDS

Note

RA = Read Address, RD = Read Data.

10.8.3

Hardware Reset (RESET#)

Table 10.8 Warm Reset

Parameter

All Speed Options

Unit

Description

JEDEC

Std

t

RESET# Pulse Width

Min

50

200

10

ns

µs

RP

RH

t

Reset High Time Before Read

RESET# Low to CE# Low

t

RPH

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Figure 10.11 Reset Timings

t_RPH

CE#, OE#

t_RH

RESET#

t_RP

10.8.4

Erase/Program Timing

Table 10.9 Erase/Program Timing

Parameter

66

MHz

83

MHz

108

MHz

Description

Unit

JEDEC

Standard

t

Write Cycle Time (1)

Min

60

4

ns

AVAV

WC

Synchronous

Asynchronous

Synchronous

Asynchronous

t

Address Setup Time (2)

AVWL

AS

4

3.5

6

ns

t

Address Hold Time (2)

Min

WLAX

AH

t

AVD# Low Time

Min

Typ

Min

ns

µs

ns

µs

AVDP

t

Data Setup Time

20

0

DVWH

DS

DH

t

Data Hold Time

WHDX

t

Read Recovery Time Before Write

CE# Setup Time to AVD#

CE# Hold Time

0

GHWL

t

0

CAS

t

0

WHEH

WLWH

WHWL

CH

t

Write Pulse Width

25

20

0

WP

t

Write Pulse Width High

Latency Between Read and Write Operations

WPH

t

SR/W

t

V

Rise and Fall Time

500

1

VID

PP

t

Setup Time (During Accelerated Programming)

VIDS

t

CE# Setup Time to WE#

4

ELWL

CS

t

AVD# Setup Time to WE#

6

AVSW

AVHW

t

AVD# Hold Time to WE#

4

t

Sector Erase Accept Time out

50

20

280

1

SEA

t

Erase Suspend Latency

ESL

PSL

ASP

PSP

ERS

PRS

Program Suspend Latency

t

Toggle Time During Erase within a Protected Sector

Toggle Time During Programming Within a Protected Sector

Erase Resume to Erase Suspend

Program Resume to Program Suspend

t

30

Notes

1. Not 100% tested.

2. In asynchronous operation timing, addresses are latched on the rising edge of AVD#.

3. See the Erase and Programming Performance section for more information. Does not include the preprogramming time.

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Figure 10.12 Asynchronous Program Operation Timings

Program Command Sequence (last two cycles)

Read Status Data

V

IH

CLK

AVD

V

IL

t_AVSW

t_AVHW

t_AVDP

t_AH

t_AS

Amax–

A16

PA

VA

555h

In

Progress

A/DQ15–

A/DQ0

Complete

A0h

PD

t_DS

t_D

t_CAS

CE#

t_CH

OE#

WE

t_W

t_CS

t_WPH

t_WC

t_VCS

V_CC

Notes

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.

2. In progress and complete refer to status of program operation.

3. CLK can be either V or V

IL

.

IH

Figure 10.13 Chip/Sector Erase Command Sequence

Read Status Data

Erase Command Sequence (last two cycles)

t_AVDP

V

CLK IH

V

IL

AVD

t_AH

t_AS

Amax–

2AAh

A16

SA

VA

555h for

chip erase

10h for

chip erase

In

A/DQ15–

2AAh

A/DQ0

55h

SA

30h

Complete

VA

Progress

t_DS

t_DH

CE#

t_CH

OE#

t_WP

WE

t_WPH

t_WHWH2

t_CS

t_WC

t_VCS

V_CC

Note

SA is the sector address for Sector Erase.

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Figure 10.14 Accelerated Unlock Bypass Programming Timing

CE#

AVD#

WE#

Amax–

A16

PA

A/DQ15–

A/DQ0

Don't Care

t_VIDS

A0h

PD

Don't Care

OE#

V_PP

1 µs

V

HH

or V

IL

IH

Note

Use setup and hold times from conventional program operation.

Figure 10.15 Data# Polling Timings (During Embedded Algorithm)

AVD#

CE#

t_CEZ

t_CE

t_OEZ

t_CH

t_OE

OE

t_OEH

WE#

t_ACC

High Z

Amax–

A16

VA

High Z

A/DQ15–

A/DQ0

Status Data

VA

Notes

1. Status reads in figure are shown as asynchronous.

2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, and Data#

Polling outputs true data.

Figure 10.16 Toggle Bit Timings (During Embedded Algorithm)

AVD#

t_CEZ

t_CE

CE#

t_OEZ

t_CH

t_OE

OE

t_OEH

WE#

t_ACC

High Z

Amax–

A16

VA

High Z

A/DQ15–

A/DQ0

Status Data

Notes

1. Status reads in figure are shown as asynchronous.

2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle

bits stop toggling.

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Figure 10.17 Synchronous Data Polling Timings/Toggle Bit Timings

CE#

CLK

AVD#

Amax–

A16

VA

OE#

t_IACC

A/DQ15–

A/DQ0

Status Data

VA

Status Data

RDY

Notes

1. The timings are similar to synchronous read timings.

2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle

bits stop toggling.

3. RDY is active with data (D8 = 0 in the Configuration Register). When D8 = 1 in the Configuration Register, RDY is active one clock cycle

before data.

Figure 10.18 DQ2 vs. DQ6

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

DQ6

Erase

Erase Suspend

Read

DQ2

Note

DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6.

Figure 10.19 Latency with Boundary Crossing

Address boundary occurs every 128 words, beginning at address

00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.

Address

7C

7D

7E

7F

80

81

82

83

(hex)

CLK

(stays high)

AVD#

t_RACC

latency

t_RACC

RDY

(Note 1)

t_RACC

RDY

(Note 2)

latency

D127

Data

D124

D125

D126

D128

D129

D130

Invalid

OE#,

CE#

(stays low)

Notes

1. RDY active with data (CR0.8 = 0 in the Configuration Register).

2. RDY active one clock cycle before data (CR0.8 = 1 in the Configuration Register).

3. Figure shows the device not crossing a bank in the process of performing an erase or program.

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Figure 10.20 Wait State Configuration Register Setup

Data

D0

D1

Rising edge of next

clock cycle following

last wait state triggers

next burst data

AVD#

OE#

total number of clock cycles

following addresses being latched

1

2

3

4

5

6

7

CLK

1

2

4

5

7

0

3

6

Total number of clock edges following addresses being latched

Table 10.10 Example of Programmable Wait States

Programmable

Wait State

CR1.0

0000

2nd

(See Note)

CR0.13

CR0.12

0001

0010

0011

0100

0101

0110

0111

1000

1001

3rd

4th

5th

6th

7th

initial data is

valid on the

rising

CLK edge

after addresses are

latched

=

Reserved

8th

9th

initial data is

valid on the

rising

CLK edge

after addresses are

latched

CR0.11

initial data is

valid on the

rising

CLK edge

AVD# transition to V

(Default)

IH

1101

=

13th

1110

1111

Reserved

Note

The addresses are latched by rising edge of CLK.

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Figure 10.21 Back-to-Back Read/Write Cycle Timings

Last Cycle in Program or

Sector Erase Command

Sequence

Read status (at least two cycles)

In same bank and/or array data

from other bank

Begin another

write or program

command sequence

t_WC

t_RC

CE#

OE#

t_OE

t_GHWL

t_OEH

WE#

t_OEZ

t_WP

t_DS

t_ACC

t_OEH

t_DH

RA

A/DQ15–

A/DQ0

PA/SA

555h

PD/30h

RD

RA

RD

AAh

t_SR/W

RA

Amax–

A16

PA/SA

t_AS

555h

AVD#

t_AH

Note

Breakpoints in waveforms indicate that system may alternately read array data from the non-busy bank while checking the status of the

program or erase operation in the busy bank. The system should read status twice to ensure valid information.

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10.9 Erase and Programming Performance

Table 10.11 Erase and Programming Performance

Parameter

64 Kword

Typ (1)

0.8

Max (2)

3.5

Unit

Comments

V

CC

Excludes 00h

programming prior to

erasure (3)

16 Kword

64 Kword

16 Kword

64 Kword

16 Kword

64 Kword

16 Kword

0.15

0.8

2.0

CC

Sector Erase Time

V

3.5

PP

CC

0.15

0.90

0.45

0.70

0.35

2.0

s

V

5.00

1.85

3.75

1.40

Includes 00h

programming prior to

erasure (3)

V

PP

77 (NS128P)

154 (NS256P)

306 (NS512P)

154 (NS128P)

308 (NS256P)

612 (NS512P)

Chip Erase Time

V

s

CC

V

40

24

400

240

94

CC

Excludes system level

overhead (4)

Word Programming Time

µs

V

PP

V

9.4

6

CC

Effective Word Programming Time

utilizing Program Write Buffer

V

60

PP

µs

V

300

192

3000

1920

CC

Total 32-Word Buffer Programming

Time

V

PP

78.6 (NS128P)

157.3 (NS256P)

314.6 (NS512P)

157.3 (NS128P)

314.6 (NS256P)

629.2 (NS512P)

V

CC

Chip Programming Time (using 32

word buffer)

Excludes system level

overhead (4)

s

51 (NS128P)

101 (NS256P)

202 (NS512P)

102 (NS128P)

202 (NS256P)

404 (NS512P)

V

PP

Erase Suspend/Erase Resume

Program Suspend/Program Resume

Notes

Min

20

µs

^{1. Typical program and erase times assume the following conditions: 25}°C, 1.8 V V , 10,000 cycles using checkerboard patterns.

CC

2. Under worst case conditions of 90°C, V = 1.70 V, 100,000 cycles.

CC

3. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure.

4. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 11.1,

Memory Array Commands on page 78 and Table 11.2, Sector Protection Commands on page 80for further information on command

definitions.

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11. Appendix

This section contains information relating to software control or interfacing with the Flash device. For

additional information and assistance regarding software, see www.spansion.com.

Table 11.1 Memory Array Commands

Bus Cycles (1, 2, 3, 4, 5, 6)

Command Sequence

(Notes)

First

Data

Second

Third

Fourth

Fifth

Data

Sixth

Data

Addr

(19)

RD

F0

(19)

Asynchronous Read (7)

1

RA

Reset (8)

XXX

(BA)

555

(BA)

X00

Manufacturer ID

Device ID (10)

Indicator Bits

4

6

4

555

AA

2AA

55

90

0001

3x7E

(12)

(BA)

555

(BA)

X01

(BA)X

0E

(BA)

X0F

(10)

(BA)

555

(BA)

X07

Autoselect (9)

(SA)

555

(SA)

X02

0000/

0001

Sector Unlock/Lock Verify

(11)

(BA)

555

(BA)

X03

Revision ID

Single Word Program

4

6

1

3

6

1

5

555

SA

AA

29

2AA

55

555

SA

A0

25

PA

SA

Data

WC

Write to Buffer (17)

PA

PD

WBL

PD

Write Buffer to Flash

Write to Buffer Abort Reset (10)

Chip Erase

555

BA

AA

B0

30

2AA

55

555

F0

80

555

AA

2AA

55

555

SA

10

30

Sector Erase

Program/Erase Suspend (15)

Program/Erase Resume (16)

Set Configuration Register (21, 22, 24)

BA

555

AA

2AA

55

555

D0

C6

X00

CR0

X01

CR1

X0

(0 or

1)

CR

(0 or

1)

Read Configuration Register

4

555

AA

(BA)

55

CFI Query (17)

1

3

2

98

AA

A0

Unlock Bypass Entry (18)

555

XX

2AA

PA

55

555

20

Unlock Bypass Program

(13), (14)

PD

Unlock Bypass Sector Erase

(13), (14)

2

XX

80

SA

30

10

Unlock Bypass

Mode (23)

Unlock Bypass Erase (13),

(14)

XXX

Unlock Bypass CFI (13),

(14)

1

2

XX

98

90

Unlock Bypass Reset

XXX

00

Legend

X = Don’t care.

RA = Read Address.

RD = Read Data.

PA = Program Address. Addresses latch on the rising edge of the AVD# pulse or active edge of CLK, whichever occurs first.

PD = Program Data. Data latches on the rising edge of WE# or CE# pulse, whichever occurs first.

SA = Sector Address. NS128P = A22 – A14; NS256P = A23 – A14.

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BA = Bank Address. NS128P = A22 – A20, and A19; NS064P = A21, A20 – A18; NS256P = A23 – A20.CR = Configuration Register data

bits D15 – D0.

WBL = Write Buffer Location. Address must be within the same write buffer page as PA.

WC = Word Count. Number of write buffer locations to load minus 1.

Notes

1. See Table 6.1 for description of bus operations.

2. All values are in hexadecimal.

3. Except for the following, all bus cycles are write cycle: read cycle, fourth through sixth cycles of the Autoselect commands, fourth cycle of

the configuration register verify and password verify commands, and any cycle reading at RD(0) and RD(1).

4. Data bits DQ15 – DQ8 are don’t care in command sequences, except for RD, PD, WD, PWD, and PWD3 – PWD0.

5. Unless otherwise noted, address bits Amax – A14 are don’t cares.

6. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The

system must write the reset command to return the device to reading array data.

7. No unlock or command cycles required when bank is reading array data.

8. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when

a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information) or performing sector lock/unlock.

9. The fourth cycle of the autoselect address is a read cycle. The system must provide the bank address.

10. (BA) + 0Eh ----> For NS128 = 43h, NS256 = 41h, NS512 = 3Fh (BA) + 0Fh ----> For NS128/256/512 = 00h

11. The data is 0000h for an unlocked sector and 0001h for a locked sector

12. See Table 6.12, Autoselect Addresses on page 34.

13. The Unlock Bypass command sequence is required prior to this command sequence.

14. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode.

15. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The

Program/Erase Suspend command is valid only during a program/ erase operation, and requires the bank address.

16. The Program/Erase Resume command is valid only during the Program/Erase Suspend mode, and requires the bank address.

17. The total number of cycles in the command sequence is determined by the number of words written to the write buffer. The maximum

number of cycles in the command sequence is 37.

18. Write Buffer Programming can be initiated after Unlock Bypass Entry.

19. Data is always output at the rising edge of clock.

20. Do not enter wrong address or data cycles.

21. Do not use 0x30 for CR data (otherwise in the erase suspend --> CR read or set sequence, the device will go into erase resume instead

of CR read or set).

22. Software reset is needed after CR read (otherwise the device is still in CR read mode).

23. When device is in Unlock Bypass mode, do not enter another command before Unlock Bypass reset command is issued).

24. Configuration Registers can not be programmed out of order. CR0 must be programmed prior to CR01 otherwise the configuration

registers retain their previous settings.

February 20, 2007 S29NS-P_00_A1

S29NS-P MirrorBit^TMFlash Family

79

D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )

Table 11.2 Sector Protection Commands

Bus Cycles 1, 2, 3, 4, 5, 6

Command Sequence

(Notes)

First

Second

Third

Fourth

Fifth

Sixth

Seventh

Data

(10)

Data

(10)

Data

(10)

Data

Addr

(10)

PD

00

(10)

Entry (5)

Program

Read

3

4

1

4

555

00

AA

2AA

55

555

88

AA

55

A0

PA

XX

data

AA

Exit (7)

555

2AA

00

55

555

90

40

Register Command Set Entry

(5)

3

555

AA

Register Bits Program (6)

Register Bits Read

2

1

2

3

XX

00

A0

data

90

data

Register Command Set Exit (7)

Protection Command Set Entry

XX

555

XX

00

55

AA

2AA

555

60

00/

01/

02/03

PWD0/

1/

2/3/

Program (9)

2

4

XX

00

A0

PWD

0

PWD

2

PWD

3

Read Password (10)

01

PWD1

02

00

03

01

PWD

0

PWD

1

PWD

2

PWD

3

Unlock (9)

7

2

3

00

XX

25

90

00

XX

03

00

55

02

03

00

29

Protection Command Set Exit

Non-Volatile Sector Protection

Command Set Entry (5)

(BA)

555

AA

2AA

C0

(BA)

SA

Program

2

1

XX

A0

80

00

30

All Erase (8)

Status Read

SA0

XX

(BA)

SA

RD(0)

Non-Volatile Sector Protection

Command Set Exit (7)

2

3

XX

90

00

Global Volatile Sector

Protection Freeze Command

Set Entry (5)

555

AA

2AA

XX

55

00

555

50

Set

2

1

XX

A0

Status Read

RD(0)

Global Volatile Sector

Protection Freeze Command

Set Exit (7)

2

XX

90

XX

00

Volatile Sector Protection

Command Set Entry (5)

(BA)

555

3

2

1

2

555

XX

AA

A0

2AA

55

00

01

E0

(BA)

SA

Set

(BA)

SA

Clear

A0

(BA)

SA

Status Read

RD(0)

90

Volatile Sector Protection

Command Set Exit (7)

XX

00

Program

2

1

4

1

555

RA

SA

A0

80

PA

SA

Data

30

Sector Erase

Asynchronous Read

Write to Buffer

RD

25

SA

WC

PA

PD

WBL

PD

Program Buffer to Flash

SA

29

Legend

X = Don’t care

80

S29NS-P MirrorBit^TMFlash Family

S29NS-P_00_A1 February 20, 2007

D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )

RA = Read Address.

RD = Read Data.

PA = Program Address. Addresses latch on the rising edge of the AVD# pulse or active edge of CLK, whichever occurs first.

PD = Program Data. Data latches on the rising edge of WE# or CE# pulse, whichever occurs first.

SA = Sector Address. NS128P = A22 – A14, NS256P = A23 – A14.

BA = Bank Address. NS128P = A22 – A20, and A19; NS256P = A23 – A20.

CR = Configuration Register data bits D15 – D0.

PWD3 – PWD0 = Password Data. PD3 – PD0 present four 16 bit combinations that represent the 64-bit Password

PWA = Password Address. Address bits A1 and A0 are used to select each 16-bit portion of the 64-bit entity.

PWD = Password Data.

RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 0, if unprotected, DQ0 = 1.

WBL = Write Buffer Location. Address must be within the same write buffer page as PA.

WC = Word Count. Number of write buffer locations to load minus 1.

Notes

1. See Table 6.1 for description of bus operations.

2. All values are in hexadecimal.

3. Except for the following, all bus cycles are write cycle: read cycle, fourth through sixth cycles of the Autoselect commands, fourth cycle of

the configuration register verify and password verify commands, and any cycle reading at RD(0) and RD(1).

4. Data bits DQ15 – DQ8 are don’t care in command sequences, except for RD, PD, WD, PWD, and PWD3 – PWD0.

5. Unless otherwise noted, address bits Amax – A14 are don’t cares.

6. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The

system must write the reset command to return the device to reading array data.

7. No unlock or command cycles required when bank is reading array data.

8. The data is 0000h for an unlocked sector and 0001h for a locked sector.

9. The Exit command must be issued to reset the device into read mode, otherwise the device hangs.

10. Data is always output at the rising edge of clock.

11.1 Common Flash Memory Interface

The Common Flash Interface (CFI) specification outlines device and host system software interrogation

handshake, which allows specific vendor-specified soft-ware algorithms to be used for entire families of

devices. Software support can then be device-independent, JEDEC ID-independent, and forward-compatible

and backward-compatible for the specified flash device families. Flash vendors can standardize their existing

interfaces for long-term compatibility.

This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address

(BA)55h any time the device is ready to read array data. The system can read CFI information at the

addresses given in Tables 11.3 – 11.6) within that bank. All reads outside of the CFI address range, within the

bank, returns non-valid data. Reads from other banks are allowed, writes are not. To terminate reading CFI

data, the system must write the reset command.

The following is a C source code example of using the CFI Entry and Exit functions. Refer to the Spansion

Low Level Driver User’s Guide (www.spansion.com) for general information on Spansion Flash memory

software development guidelines.

/* Example: CFI Entry command */

*( (UINT16 *)bank_addr + 0x0055 = 0x0098;

/* write CFI entry command

/* write cfi exit command

*/

/* Example: CFI Exit command */

*( (UINT16 *)bank_addr + 0x000 ) = 0x00F0;

*/

For further information, please refer to the CFI Specification (see JEDEC publications JEP137-A and

JESD68.01and CFI Publication 100). Please contact your sales office for copies of these documents.

February 20, 2007 S29NS-P_00_A1

S29NS-P MirrorBit^TMFlash Family

81

D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )

Table 11.3 CFI Query Identification String

Addresses

Data

Description

10h

11h

12h

0051h

0052h

0059h

Query Unique ASCII string QRY

13h

14h

0002h

0000h

Primary OEM Command Set

15h

16h

0040h

0000h

Address for Primary Extended Table

17h

18h

0000h

Alternate OEM Command Set (00h = none exists)

19h

1Ah

0000h

Address for Alternate OEM Extended Table (00h = none exists)

Table 11.4 System Interface String

Addresses

Data

Description

V

Min. (write/erase)

CC

1Bh

0017h

D7 – D4: volt, D3 – D0: 100 millivolt

V

Max. (write/erase)

CC

1Ch

0019h

D7 – D4: volt, D3 – D0: 100 millivolt

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

0000h

0005h

0009h

000Ah

0000h

0003h

0002h

0000h

V

Min. voltage (00h = no V pin present)

PP

Max. voltage (00h = no V pin present)

PP

Typical Program Time per single word write 2^Nµs (for example, 30 µs)

Typical Program Time using buffer 2^Nµs (for example, 300us) (00h = not supported)

Typical time for sector erase 2^Nms

Typical time for full chip erase 2^Nms (00h = not supported)

Max. Program Time per single word [2^Ntimes typical value]

Max. Program Time using buffer [2^Ntimes typical value]

Max. time for sector erase [2^Ntimes typical value]

Max. time for full chip erase [2^Ntimes typical value] (00h = not supported)

Table 11.5 Device Geometry Definition (Sheet 1 of 2)

Addresses

Data

Description

0018h (NS128P)

0019h (NS256P)

001Ah (NS512P)

27h

Device Size = 2^Nbyte

28h

29h

0001h

0000h

Flash Device Interface 0h=x8; 1h=x16; 2h=x8/x16; 3h=x32 [lower byte]

[upper byte] (00h = not supported)

2Ah

2Bh

0006h

0000h

Max. number of bytes in multi-byte buffer write = 2^N[lower byte]

[upper byte] (00h = not supported)

0002h (NS128P)

0002h (NS256P)

0001h (NS512P)

Number of Erase Block Regions within device

01h = Uniform Sector; 02h = Boot + Uniform; 03h = Boot + Uniform + Boot

2Ch

2Dh

007Eh (NS128P)

00FEh (NS256P)

01FFh (NS512P)

Erase Block Region 1 Information (Large Sector Section)

[lower byte] – Number of sectors. 00h=1 sector; 01h=2 sectors... 03h=4 sectors

[upper byte]

2Eh

2Fh

30h

0000h

0002h

[lower byte] – Equation =>(n = Density in Bytes of any 1 sector/256)h

[upper byte]

0003h (NS128P)

0003h (NS256P)

0000h (NS512P)

Erase Block Region 2 Information (Small Sector Section)

[lower byte] – Number of sectors.

31h

32h

33h

34h

0000h

0080h (NS128P)

0080h (NS256P)

0000h (NS512P)

[upper byte]

[lower byte] – Equation =>(n = Density in Bytes of any 1 sector/256)h

[upper byte]

0000h

82

S29NS-P MirrorBit^TMFlash Family

S29NS-P_00_A1 February 20, 2007

D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )

Table 11.5 Device Geometry Definition (Sheet 2 of 2)

Addresses

Data

Description

Erase Block Region 3 Information

[lower byte] – Number of sectors. 00h=1 sector; 01h=2 sectors... 03h=4 sectors

[upper byte]

[lower byte] – Equation =>(n = Density in Bytes of any 1 sector/256)h

[upper byte]

35h

36h

37h

38h

0000h

39h

3Ah

3Bh

3Ch

0000h

Erase Block Region 4 Information

Table 11.6 Primary Vendor-Specific Extended Query (Sheet 1 of 2)

Addresses

Data

Description

40h

41h

42h

0050h

0052h

0049h

Query-unique ASCII string PRI

43h

44h

0031h

0034h

Major CFI version number, ASCII

Minor CFI version number, ASCII

Address Sensitive Unlock (Bits 1 – 0)

00b = Required, 01b = Not Required

Silicon Technology (Bits 5 – 2) 0011b = 130 nm; 0100b = 110 nm; 0101b = 90 nm

001010b = 000Ah

45h

0014h

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

46h

47h

48h

49h

0002h

0001h

0000h

0008h

Sector Protection per Group

0 = Not Supported, X = Number of sectors in per group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

08h = Advanced Sector Protection; 07h = New Sector Protection Scheme

0078h (NS128P)

00F0h (NS256P)

01E0h (NS512P)

Simultaneous Operation

Number of Sectors in all banks except bank0

4Ah

Burst Mode Type

00 = Not Supported, 01 = Supported

4Bh

4Ch

4Dh

0001h

0000h

0085h

Not supported

V

(Acceleration) Supply Minimum

PP

00h = Not Supported, D7 – D4: Volt, D3 – D0: 100 mV

V

(Acceleration) Supply Maximum

PP

4Eh

4Fh

0095h

00h = Not Supported, D7 – D4: Volt, D3 – D0: 100 mV

Write Protect Function

00h = No Boot, 01h = Dual Boot, 02h = Bottom Boot, 03h = Top Boot, 04h = Uniform

Bottom, 05h = Uniform Top, 06h = All Sectors

0003h (NS128P)

0003h (NS256P)

0005h (NS512P)

50h

51h

52h

53h

0001h

0008h

0014h

Program Suspend. 00h = not supported

Unlock Bypass

00 = Not Supported, 01=Supported

Secured Silicon Sector (Customer OTP Area) Size 2^Nbytes

Hardware Reset Low Time-out during an embedded algorithm to read mode Maximum 2^N

ns (for example, 10 µs => n=14)

Hardware Reset Low Time-out not during an embedded algorithm to read mode Maximum

2^Nns (for example, 10 µs => n=14)

54h

0014h

55h

56h

57h

0005h

0010h

Erase Suspend Time-out Maximum 2^Nμs

Program Suspend Time-out Maximum 2^Nμs

Bank Organization: X = Number of banks

0008h (NS128P)

0010h (NS256P)

0020h (NS512P)

58h

Bank 0 Region Information. X = Number of sectors in bank

February 20, 2007 S29NS-P_00_A1

S29NS-P MirrorBit^TMFlash Family

83

D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )

Table 11.6 Primary Vendor-Specific Extended Query (Sheet 2 of 2)

Addresses

Data

Description

0008h (NS128P)

0010h (NS256P)

0020h (NS512P)

59h

Bank 1 Region Information. X = Number of sectors in bank

0008h (NS128P)

0010h (NS256P)

0020h (NS512P)

5Ah

5Bh

5Ch

5Dh

5Eh

5Fh

60h

61h

62h

63h

64h

65h

66h

67h

Bank 2 Region Information. X = Number of sectors in bank

Bank 3 Region Information. X = Number of sectors in bank

Bank 4 Region Information. X = Number of sectors in bank

Bank 5 Region Information. X = Number of sectors in bank

Bank 6 Region Information. X = Number of sectors in bank

Bank 7 Region Information. X = Number of sectors in bank

Bank 8 Region Information. X = Number of sectors in bank

Bank 9 Region Information. X = Number of sectors in bank

Bank 10 Region Information. X = Number of sectors in bank

Bank 11 Region Information. X = Number of sectors in bank

Bank 12 Region Information. X = Number of sectors in bank

Bank 13 Region Information. X = Number of sectors in bank

Bank 14 Region Information. X = Number of sectors in bank

Bank 15 Region Information. X = Number of sectors in bank

0008h (NS128P)

0010h (NS256P)

0020h (NS512P)

0008h (NS128P)

0010h (NS256P)

0020h (NS512P)

0008h (NS128P)

0010h (NS256P)

0020h (NS512P)

0008h (NS128P)

0010h (NS256P)

0020h (NS512P)

0008h (NS128P)

0010h (NS256P)

0020h (NS512P)

0008h (NS128P)

0010h (NS256P)

0020h (NS512P)

0008h (NS128P)

0010h (NS256P)

0020h (NS512P)

0008h (NS128P)

0010h (NS256P)

0020h (NS512P)

0008h (NS128P)

0010h (NS256P)

0020h (NS512P)

0008h (NS128P)

0010h (NS256P)

0020h (NS512P)

0008h (NS128P)

0010h (NS256P)

0020h (NS512P)

0008h (NS128P)

0010h (NS256P)

0020h (NS512P)

000Bh (NS128P)

0013h (NS256P)

0020h (NS512P)

84

S29NS-P MirrorBit^TMFlash Family

S29NS-P_00_A1 February 20, 2007

D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )

12. Revision History

Section

Description

Revision A (June 29, 2006)

Initial release

Revision A1 (February 20, 2007)

The tAVDS specification is changed from 4 ns to 5 ns

The wait state for 83 MHz is changed to 8

ICC3(Max) is changed to 70 µA and ICC6(Max) is changed to 40 µA

VIL (Min) is changed to -0.2 V

tOE (Max) in both Asynchronous & Synchronous modes is changed to 9 ns across all frequencies

tCEZ (Max) is changed to 10 ns across all frequencies

tOEZ (Max) in both Asynchronous & Synchronous modes is changed to 10 ns across all frequencies

tACH(Min) is changed to 6 ns (66 MHz) and 5 ns (83 MHz and 108 MHz)

tRDY(Max) is changed to 10 ns

Global

tRACC(Max) is changed to 7.6 ns for 108 MHz

tOEH(Min) in Asynchronous mode is changed to 10 ns for 108 MHz

Erase and Programing Performance table is updated

tCE in Asynchronous mode is changed to 83ns

February 20, 2007 S29NS-P_00_A1

S29NS-P MirrorBit^TMFlash Family

85

D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without

limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as

contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the

public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,

aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for

any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to

you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor

devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design

measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal

operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under

the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,

the prior authorization by the respective government entity will be required for export of those products.

Trademarks and Notice

The contents of this document are subject to change without notice. This document may contain information on a Spansion product under

development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this

document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,

merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any

damages of any kind arising out of the use of the information in this document.

thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.

86

S29NS-P MirrorBit^TMFlash Family

S29NS-P_00_A1 February 20, 2007


型号：	S29NS-P
厂家：	SPANSION
描述：	MirrorBit Flash Family 的MirrorBit闪存系列闪存
文件：	总86页 (文件大小：3142K)
中文：	中文翻译
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