S30MS01GP25TFW513 [SPANSION]
1Gb/512Mb, x8/x16, 1.8 Volt NAND Interface Memory Based on MirrorBit⑩ Technology; 1GB / 512MB， X8 / X16 ， 1.8伏的NAND接口存储基于MirrorBit⑩技术
| 型号： | S30MS01GP25TFW513 |
| 厂家： | 
SPANSION |
| 描述： | 1Gb/512Mb, x8/x16, 1.8 Volt NAND Interface Memory Based on MirrorBit⑩ Technology |
| 文件： | 总41页 (文件大小：948K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S30MS-P ORNANDTMFlash Family
S30MS01GP, S30MS512P
1Gb/512Mb, x8/x16, 1.8 Volt NAND Interface Memory Based on
MirrorBit™ Technology
S30MS-P ORNANDTMFlash Family Cover Sheet
Data Sheet (Preliminary)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S30MS-P_00
Revision A
Amendment 7
Issue Date August 4, 2006
D a t a S h e e t ( P r e l i m i n a r y )
Notice On Data Sheet Designations
Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion LLC is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
LLC therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion LLC.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion LLC reserves the right to change or discontinue work on this
proposed product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has been
completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a
description or to correct a typographical error or incorrect specification. Spansion LLC applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion LLC deems the products to have been in sufficient production volume
such that subsequent versions of this document are not expected to change. However, typographical
or specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
ii
S30MS-P ORNANDTMFlash Family
S30MS-P_00_A7 August 4, 2006
S30MS-P ORNANDTM Flash Family
S30MS01GP, S30MS512P
1Gb/512Mb, x8/x16, 1.8 Volt NAND Interface Memory Based on
MirrorBit™ Technology
Data Sheet (Preliminary)
Distinctive Characteristics
Single Power Supply Operation
Compatibility with NAND Flash I/O
– 1.8 volt read, erase, and program operations
– Provides pinout and command set compatibility with single-power
supply NAND flash
– V = 1.7 to 1.95V
CC
Manufactured on 90 nm MirrorBitTM Process Technology
High-Performance Cache Register
– Cache Register matches page size to improve programming
throughput
Bus widths - x8 and x16
Page Size
100,000 Program/Erase Cycles per Sector Typical
10-Year Data Retention Typical
– Full Page Read
2K + 64 Byte
– Partial Page Read
512 + 16 Byte
Operating Temperature Ranges
– Wireless (-25°C to +85°C)
Block (erase unit) Architecture
Package options
– 48-pin TSOP
– Number of Blocks
1Gb: 1K blocks
512Mb: 512 blocks
– Block Size
– 137-ball FBGA MCP Compatible
100% Valid Blocks
128K + 4K Byte
Performance Characteristics
Read Access Times (Maximum)
Current Consumption (typical)
Full Page Random Access
Partial Page Random Access
Serial Read
25 µs
8 µs
Read Current
40 mA
60 mA
60 mA
10 uA
Erase Current
Program Current
Standby Current
25ns
Read, Program and Erase Performance (typical)
x8
x16
Program
2.3 MB/s
2.7 MB/s
26.7 MB/s
24.3 MB/s
2.4 MB/s
2.7 MB/s
40.1 MB/s
34.9 MB/s
Erase
Full Page Read
Partial Page Read
Legend:
b = bit, B = Byte, K = 1024, M = 1048576
Publication Number S30MS-P_00
Revision A
Amendment 7
Issue Date August 4, 2006
This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qual-
ification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document
may be revised by subsequent versions or modifications due to changes in technical specifications.
D a t a S h e e t ( P r e l i m i n a r y )
Contents
Distinctive Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.
2.
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
2.2
137-Ball MS01GP MCP-Compatible FBGA Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
MS01GP and MS512P 48-Pin TSOP Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.
4.
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1
3.2
VBP137—137-Ball Fine Pitch Ball Grid Array (FBGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
48-Pin TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Names and Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1
4.2
Pin Names and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.
6.
7.
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.1
Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
8.
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Capacitance (Ta = 25°C, f = 1 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Program and Erase Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
9.
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
9.1 ID Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
10. Schematic Cell Layout and Address Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
10.1 Array Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
11. Operation Mode: Logic and Command Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
12. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
12.1 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
12.2 Page Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
12.3 Cache Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
12.4 Page Duplicate Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
12.5 Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
12.6 Write Operation Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
12.7 Status Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
12.8 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
13. Application Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
13.1 Power On/Off Sequence and Power-On Read Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
13.2 Status Read During a Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
14. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Tables
Table 9.1
Table 9.2
Table 9.3
ID Byte Settings Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4th ID Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
5th ID Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2
S30MS-P ORNANDTM Flash Family
S30MS-P_00_A7 August 4, 2006
D a t a S h e e t ( P r e l i m i n a r y )
Table 10.1
Table 10.2
Table 10.3
Table 10.4
Table 10.5
Table 11.1
Table 11.2
Table 11.3
Table 12.1
Table 12.2
Memory Addressing Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
(1Gb) x 8 device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
(512Mb) x8 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
(1Gb) x 16 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
(512) x 16 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Operation Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Command Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Read Mode Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Page Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Status Output Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Figures
Figure 9.1
Figure 9.2
Figure 9.3
Figure 9.4
Figure 9.5
Figure 9.6
Figure 9.7
Figure 9.8
Figure 9.9
Command Input Cycle Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Address Input Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Data Input Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Serial Read Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Status Read Cycle Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Column Address Change in Read Cycle Timing Diagram (1/2). . . . . . . . . . . . . . . . . . . . . . . 18
Column Address Change in Read Cycle Timing Diagram (2/2). . . . . . . . . . . . . . . . . . . . . . . 19
Program Operation Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 9.10 Block Erase Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9.11 Cache Program Operation Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9.12 Page Duplicate Program Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 9.13 ID Read Operation Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 10.1 Array Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 12.1 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 12.2 Column Address Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 12.3 Page Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 12.4 Serial Input Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 12.5 Cache Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 12.6 Page Duplicate Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 12.7 Page Duplicate Program Operation with Random Data Input . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 12.8 Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 12.9 Multiple Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 12.10 Status Read Timing Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 12.11 Reset (FFh) Command Input During Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 12.12 Reset (FFh) Command Input During Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 12.13 Reset (FFh) Command Input During a Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 12.14 Reset (FFh) Command During Operations Other Than Program, Erase, or Read . . . . . . . . 32
Figure 12.15 Status Read Command (70h) Input After a Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 13.1 Power-On/Off Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 13.2 Power-On Auto-read Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 13.3 Status Read During a Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 13.4 RY/BY#: Termination for the Ready/Busy Pin (RY/BY#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 13.5 WP# Signal—Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
August 4, 2006 S30MS-P_00_A7
S30MS-P ORNANDTM Flash Family
3
D a t a S h e e t ( P r e l i m i n a r y )
1. General Description
The S30MS-P is a 1.8V single voltage flash memory product manufactured using 90 nm MirrorBit™
technology. The S30MS01GP is a 1Gb device, organized as 64M Words or 128MB. The S30MS512P is a
512Mb device, organized as 32M Words or 64MB.
The S30MS-P family of devices offer advantages such as:
Fast write and sustained write speed suitable for data storage applications
Fast read speed and reliability suitable for demanding code storage applications
Proven MirrorBit™ technology
The devices are offered in a 48-pin TSOP, or FBGA MCP-compatible packages. Each device has separate
chip enable (CE#) controls for the FBGA package.
The S30MS-P is a byte/word serial-type memory device that utilizes the I/O pins for both address and data
input/output, as well as for command input. The Erase and Program operations are automatically executed
making the device most suitable for applications such as solid-state disks, pictures storage for still cameras,
cellular phones, and other systems that require high-density non-volatile data storage.
Typical application requirements are shown in the table below with reference to the ORNAND capabilities.
Application
2G Network
Minimum Requirements
14.4 Kbps (1.8 KB/sec)
2 Mbps (250 KB/sec)
2.5 MB/sec
Spansion ORNAND
9
9
9
9
9
9
9
9
3G Network
3.5G Network (HSPDA)
Full Speed USB
MP3 Playback
MPEG2 (H.262)
MPEG4 (H.264)
WiMax
1.5 MB/sec
320 Kbps (40 KB/sec)
3 MB/sec
1 MB/sec
0.25 MB/sec
The devices include the following features:
Automatic page 0 read, allows access of the data in page 0 without command and address input of read
command after power-up
Chip Enable Don't Care support for direct connection with microcontrollers
Compatible with NAND Flash command set. Commands are written to the device using standard
microprocessor write timing. Write cycles provide commands, addresses and data
Initiation of program and erase functions through command sequences. Once a program or erase
operation begins, the host system should only poll for status or monitor the Ready/Busy# (RY/BY#) output
to determine whether the operation is complete
Manufactured using MirrorBit™ flash technology resulting in the highest levels of quality, reliability, and cost
effectiveness
4
S30MS-P ORNANDTM Flash Family
S30MS-P_00_A7 August 4, 2006
D a t a S h e e t ( P r e l i m i n a r y )
2. Connection Diagrams
2.1
137-Ball MS01GP MCP-Compatible FBGA Pinout
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
DNU
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
RFU
Legend
RFU
RFU
VSS
RFU
RFU
RFU
N-PRE
N-ALE
N-CLE
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
N1-CE#
Flash Shared
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
RFU
RFU
RFU
RFU
RFU
RFU
DNU
RFU
RFU
RFU
ORNAND Flash
Do Not Use
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
RFU
RFU
RFU
RFU
RFU
RY/BY#
RFU
RFU
RFU
RFU
G1
G2
G3
G4
G6
G7
G8
G9
G10
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
H1
H2
H3
H4
H7
H8
H9
H10
RFU
RFU
RFU
VSS
DQ1
DQ6
RFU
RFU
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
RFU
RFU
RFU
DQ9
DQ3
DQ4
DQ13
DQ15
DNU
RFU
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
RFU
RFU
DNU
DQ0
DQ10
RFU
N-VCC
DQ12
DQ7
VSS
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
RFU
RFU
N-VCC
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
N-WP#
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
RFU
RFU
RFU
RFU
VSS
RFU
N2-CE#
DNU
RFU
RFU
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N-WE#
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
N-RE#
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
DNU
August 4, 2006 S30MS-P_00_A7
S30MS-P ORNANDTM Flash Family
5
D a t a S h e e t ( P r e l i m i n a r y )
2.2
MS01GP and MS512P 48-Pin TSOP Pinout
TSOP-48
X16
X8
X8
X16
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
PRE
VCC
VSS
N.C
N.C
N.C
N.C
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
N.C
N.C
N.C
N.C
N.C
1
2
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
N.C
3
4
N.C
N.C
5
N.C
6
RY/BY#
RY/BY#
7
RE#
CE#
RE#
CE#
8
9
N.C
N.C
VCC
N.C
N.C
VCC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PRE
VCC
VSS
N.C
VSS
VSS
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
N.C
N.C
N.C
CLE
ALE
WE#
N.C
N.C
CLE
ALE
WE#
N.C
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
VSS
WP#
N.C
N.C
N.C
N.C
N.C
WP#
N.C
N.C
N.C
N.C
N.C
6
S30MS-P ORNANDTM Flash Family
S30MS-P_00_A7 August 4, 2006
D a t a S h e e t ( P r e l i m i n a r y )
3. Physical Dimensions
3.1
VBP137—137-Ball Fine Pitch Ball Grid Array (FBGA)
D1
A
D
e
0.15
(2X)
C
10
9
8
SE
7
7
6
E
E1
5
4
3
2
e
1
N
L
J
H
G
F
E
D
C
B
A
P
M
K
PIN A1
9
PIN A1
CORNER
B
CORNER
7
INDEX MARK
0.15
(2X)
C
SD
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.10
0.08
C
C
A2
A
A1
C
6
137X
b
0.15
0.08
M
C
C
A B
M
NOTES:
PACKAGE
JEDEC
VBP 137
N/A
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
13.00 mm x 11.00 mm NOM
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT
AS NOTED).
SYMBOL
MIN
---
NOM
---
MAX
1.00
---
NOTE
OVERALL THICKNESS
BALL HEIGHT
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
A2
D
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE
"D" DIRECTION.
0.17
0.60
---
SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE
"E" DIRECTION.
---
0.76
BODY THICKNESS
BODY SIZE
13.00 BSC.
11.00 BSC.
10.40 BSC.
7.20 BSC.
14
N IS THE TOTAL NUMBER OF SOLDER BALLS.
E
BODY SIZE
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
D1
E1
MD
ME
N
BALL FOOTPRINT
BALL FOOTPRINT
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
ROW MATRIX SIZE D DIRECTION
ROW MATRIX SIZE E DIRECTION
TOTAL BALL COUNT
10
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,
RESPECTIVELY, SD OR SE = 0.000.
137
φb
0.35
0.40
0.45
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
e
0.80 BSC.
0.40 BSC.
G5,H5,H6
BALL PITCH
SD / SE
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
8. NOT USED.
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3549 \ 16-038.25 \ 2.16.6
August 4, 2006 S30MS-P_00_A7
S30MS-P ORNANDTM Flash Family
7
D a t a S h e e t ( P r e l i m i n a r y )
3.2
48-Pin TSOP
2X
0.10
STANDARD PIN OUT (TOP VIEW)
2X (N/2 TIPS)
2X
0.10
2
0.10
A2
1
N
REVERSE PIN OUT (TOP VIEW)
SEE DETAIL B
3
A
B
1
N
5
E
N
2
N
2
+1
e
9
5
D1
A1
N
+1
N
2
4
2
D
0.25
2X (N/2 TIPS)
C
B
SEATING
PLANE
A
B
SEE DETAIL A
0.08MM (0.0031")
M
C
6
A - B S
b
7
WITH PLATING
c1
(c)
7
b1
BASE METAL
SECTION B-B
R
(c)
e/2
GAUGE PLANE
0.25MM (0.0098") BSC
θ°
PARALLEL TO
SEATING PLANE
X
C
L
X = A OR B
DETAIL A
DETAIL B
NOTES:
Package
Jedec
TS/TSR 048
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).
(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)
MO-142 (D) DD
1
2
3
4
MIN
NOM MAX
1.20
Symbol
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE UP).
A
A1
A2
b1
b
c1
c
D
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.
0.15
0.05
0.95
0.17
0.17
0.10
0.10
1.00
0.20
1.05
0.23
0.27
0.16
0.21
TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF
CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT
HORIZONTAL SURFACE.
0.22
5
6
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS
0.15mm (.0059") PER SIDE.
19.80 20.00 20.20
18.30 18.40 18.50
11.90 12.00 12.10
DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE
0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE
BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").
D1
E
e
7
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND
0.25MM (0.0098") FROM THE LEAD TIP.
0.50 BASIC
L
0
R
N
0.50
0˚
0.08
0.60
0.70
8˚
0.20
8
9
LEAD COPLANARITY SHALL BE WITHIN 0.10mm (0.004") AS MEASURED FROM THE SEATING PLANE.
DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
48
3355 \ 16-038.10c
8
S30MS-P ORNANDTM Flash Family
S30MS-P_00_A7 August 4, 2006
D a t a S h e e t ( P r e l i m i n a r y )
4. Pin Names and Descriptions
4.1
Pin Names and Functions
Pin Name
I/O0 to I/O15
CLE
Pin Function
Data Input/Output
Command Latch Enable
Address Latch Enable
Chip Enable
ALE
CE#, CE1#, CE2#
RE#
Read Enable
WE#
Write Enable
WP#
Write Protect
PRE
Power on Read Enable
Ready/Busy Output
Power
RY/BY#
V
CC
V
Ground
SS
N.C.
No Connection
4.2
Pin Descriptions
The device is a byte/word serial access memory that utilizes time-sharing input of address information. The
device pin-outs are configured as shown in 137-Ball MS01GP MCP-Compatible FBGA Pinout on page 5.
Pin
Description
Command Latch Enable: The CLE input signal is used to control loading of the operation mode command into
the internal command register. The command is latched into the command register from the I/O port on the
rising edge of the WE# signal while CE# is low and CLE is High.
CLE
ALE
Address Latch Enable: The ALE signal is used to control loading of either address information or input data
into the internal address/data register. Address information is latched on the rising edge of WE# if CE# is low
and ALE is High.
Input data is latched if CE# is low and ALE is Low.
Chip Enable: The device enters a low-power Standby mode when the device is in Ready mode. The CE#
signal is ignored when the device is in a Busy state (RY/BY# = L), such as during a Page Buffer Load or Erase
operation, and will not enter Standby mode even if the CE# input goes high. The CE# signal may be inactive
during the Page Buffer write and Page Buffer load of the array data. The 2Gb device has two chip enable pins:
CE1# and CE2# (one per die).
CE#, CE1#, CE2#
WE#
RE#
Write Enable: The WE# signal is used to control the acquisition of data from the I/O port.
Read Enable: The RE# signal controls serial data output. Data is available t
after the falling edge of RE#.
REA
The internal column address counter is also incremented (Address = Address + 1) on this falling edge.
I/O Port: The I/O0 to I/O7 pins are used as a port for transferring address, command, and input/output data to
and from the device.
I/O0 to I/O7
I/O8 to I/O15
WP#
I/O Port: The I/O8 to I/O15 pins are used as a port for transferring input/output data to and from the device in
x16 mode only. I/O8 to I/O15 pins must be low level during address and command input.
Write Protect: The WP# signal is used to protect the device from accidental programming or erasing. This
signal is usually used for protecting the data during the power-on/off sequence when input signals are invalid.
Ready/Busy:The RY/BY# output signal is used to indicate the operating condition of the device. The RY/BY#
signal is in Busy state (RY/BY# = L) during the Program, Erase, and Read operations and return to Ready state
(RY/BY# = H) after completion of the operation. The output buffer for this signal is an open drain.
RY/BY#
PRE
Power-on Read Enable: The PRE controls auto read operation executed during power-on. The power-on auto-
read is enabled when PRE pin in tied to V
.
CC
V
Ground: V is the Ground.
SS
SS
N.C
No Connection: Lead is not internally connected.
August 4, 2006 S30MS-P_00_A7
S30MS-P ORNANDTM Flash Family
9
D a t a S h e e t ( P r e l i m i n a r y )
5. Block Diagram
VCC
VSS
RY/BY#
2Gb: (2048M + 64M) bit
1Gb: (1024M + 32M) bit
512 Mb: (512M + 16M) bit
Flash Array
Address
Register
& Decoders
Data Register & S/A
Cache Register
Y-Decoder
Command
Command
Register
VCC
VSS
I/O Buffers & Latches
Global Buffers
CE#
RE#
WE#
Control Logic
& High Voltage
Generator
I/00
Output
Driver
I/O7 or I/O15
CLE ALE PRE
WP#
6. Absolute Maximum Ratings
Parameter
Voltage on any pin relative to Vss
Storage Temperature
Symbol
Rating
Unit
V
-0.5 to Vcc + 0.5
-0.5 to + 2.5
-65 to +150
IN/OUT
V
V
CC
T
oC
STG
0 to +70 (Commercial)
-40 to +85 (Industrial)
Operating Temperature
T
oC
OPR
-25 to +85 (Wireless)
Temperature under bias
Short circuit current
T
-65 to 125
5
oC
BIAS
I
mA
OS
Notes:
1. Minimum DC voltage is -0.6v on input/output pins. During transitions, this level may undershoot to -2.0v for periods <30ns.
2. Maximum DC voltage on input/output pins is Vcc+0.3v which, during transitions, may overshoot to Vcc+2.0v for periods < 20ns.
3. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the
conditions as details in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
10
S30MS-P ORNANDTM Flash Family
S30MS-P_00_A7 August 4, 2006
D a t a S h e e t ( P r e l i m i n a r y )
7. Ordering Information
The order number is formed by a valid combinations of the following:
S30MS
01G
P
25
B
F
W
00
2
Packing Type
0
2
3
= Tray
= 7-inch Tape and Reel
= 13-inch Tape and Reel
Model Number (3) (4)
00 = x8; ECC-Free
01 = x16; ECC-Free
50 = x8; ECC-Required with Boot Block
51 = x16; ECC-Required with Boot Block
Temperature Range
W = Wireless (–25°C to +85°C)
Package Material Set
A
F
= Standard
= Pb-Free
Package Type
T
B
= Thin Small Outline Package
= Ball-Grid Array Package
Speed Option Serial Read Access Time
25 = 25 ns
Process Technology
P
= 90 nm MirrorBit™ Technology
Flash Density
01G=1Gb
512= 512Mb
Product Family
S30MS = 1.8 volt -only, NAND Interface Flash Memory
7.1
Valid Combinations
Valid Combination list configurations planned to be supported in volume for this device. Consult your local
sales office to confirm availability of specific valid combinations and to check on newly released
combinations.
Valid Combinations
Base Ordering
Part Number
Speed
Option
Package Type, Material,
and Temperature Range
Model
Number
Packing
Type
Package
Type
BAW, BFW
TAW, TFW
137-Ball FBGA
TSOP-48
S30MS01GP
S30MS512P
0, 3
00, 01,
50, 51
25
(Note 1)
Notes:
1. Type 0 is standard. Specify other options as required.
2. See the MCP ORNAND data sheet for further package details.
3. Model Numbers 50 and 51 must use 2-bit detection, 1-bit correction for applications that require 100% error-free read performance.
4. Model Numbers 50 and 51 may have up to 2% invalid blocks.
5. Model Numbers 50 and 51 have a boot block (Block 0 is valid upon shipment and error-free through 1000 cycles).
August 4, 2006 S30MS-P_00_A7
S30MS-P ORNANDTM Flash Family
11
D a t a S h e e t ( P r e l i m i n a r y )
8. Electrical Specifications
8.1
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
V
–0.5 to V + 0.5
CC
IN/OUT
Voltage on any pin relative to Vss
V
V
–0.5 to + 2.5
–65 to +150
–25 to +85 (Wireless)
–65 to +125
5
CC
Storage Temperature
Operating Temperature
Temperature under bias
Short circuit current
T
°C
°C
STG
T
OPR
BIAS
T
°C
I
mA
OS
Notes:
1. Minimum DC voltage is –0.6 V on input/output pins. During transitions, this level may undershoot to –2.0 V for periods <30 ns.
2. Maximum DC voltage on input/output pins is V +0.3 V which, during transitions, may overshoot to V +2.0 V for periods < 20 ns.
CC
CC
3. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the
conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
8.2
Capacitance (Ta = 25°C, f = 1 MHz)
Parameter
Symbol
Parameter
Description
Test
Condition
Typ.
—
Max.
10
Unit
pF
pF
pF
pF
pF
pF
C
Input Capacitance
V
= 0
IN
IN
—
10
C
C
CE# pin Input Capacitance
WE# pin Input Capacitance
V
V
= 0
= 0
—
17
IN2
IN3
IN
IN
—
32
—
10
C
Output Capacitance
V
= 0
OUT
OUT
—
10
Notes:
1. Test conditions T = 25°C, f = 1.0 MHz
a
2. Sampled, not 100% tested.
8.3
Valid Blocks
Valid Blocks are fully erased when the device is shipped from the factory. To identify blocks that are invalid at
the time of shipment, the system must read the lowest address in the first two pages of the spare area. If a
non-blank data pattern is read from either of these two addresses, the block is invalid.
Parameter
Symbol
Parameter
Description
Density
Model Number
50, 51
Min.
502
Max.
512
Unit
Blocks
Blocks
Blocks
Blocks
512Mb
00, 01
512
512
N
Number of Valid Blocks
VB
50, 51
1004
1024
1024
1024
1Gb
00, 01
12
S30MS-P ORNANDTM Flash Family
S30MS-P_00_A7 August 4, 2006
D a t a S h e e t ( P r e l i m i n a r y )
8.4
8.5
Recommended DC Operating Conditions
Parameter
Symbol
Parameter
Description
Min.
1.7
0
Typ.
1.8
0
Max.
1.95
0
Unit
V
V
Power Supply Voltage
Power Supply Voltage
CC
V
V
SS
DC Characteristics
Parameter
Symbol
Parameter
Description
Test Conditions
= 25 ns,
Min.
Typ.
Max.
Unit
V
active read current
(average during read cycle)
t
I
CC
RC
I
I
—
40
40
45
mA
mA
CC1
= 0 mA
OUT
V
current during data transfer
from memory cell array to Page Buffer
CC
—
—
45
CC2
I
I
I
V
current during data output
t
RC
= 25 ns
—
—
—
10
60
60
20
75
75
mA
mA
mA
CC3
CC4
CC5
CC
Program current (standard mode)
Erase Current (standard mode)
—
—
CE# = V
WP# = PRE# = V
,
IH
I
Stand-by Current (TTL)
—
—
—
1
mA
µA
SB1
SB2
IL
CE# = V –0.2 V,
CC
WP# = PRE# = 0.2 V
All other pins = -0.1 V
I
Stand-by Current (CMOS)
10
60
V
V
= 0 to V
,
CC
IN
I
Input Leakage Current
Output Leakage Current
—
—
—
—
1
1
µA
µA
LI
= V max
CC
CC
V
V
= 0 to V
,
CC
OUT
I
LO
= V max
CC
CC
V
(note 1)
(note 2)
Input High Voltage
Input Low Voltage
V
V
- 0.4
—
—
V + 0.2
CC
V
V
IH
CC
V
—
–0.3
0.4
IL
I
= –100 µA,
OH
V
Output High Voltage Level
Output Low Voltage Level
- 0.1
—
—
4
—
V
V
OH
CC
V
= V min
CC
CC
I
= 100 µA,
OL
V
—
0.1
—
OL
V
= V min
CC
CC
Output Low Current
(RY/BY#)
I
V
= 0.1 V
2
mA
OL
OL
Notes:
1.
V
can overshoot to V +0.4 V for durations of 20 ns or less.
CC
IH
2.
V
can undershoot to –0.4 V for durations of 20 ns or less.
IL
August 4, 2006 S30MS-P_00_A7
S30MS-P ORNANDTM Flash Family
13
D a t a S h e e t ( P r e l i m i n a r y )
8.6
AC Characteristics
Parameter
Symbols
Description
Min.
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
17
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CLE Setup Time
-1
8
CLS
CLH
t
CLE Hold Time
t
CE# Setup Time
0
CS
CH
WP
t
CE# Hold Time
8
t
Write Pulse Width
ALE Setup Time
25
-1
8
t
ALS
ALH
t
ALE Hold Time
t
Data Setup Time
Data Hold Time
15
8
DS
t
DH
t
t
Write Cycle Time
WE# High Hold Time
WP# High to WE# Low
Ready to RE# Falling Edge
Ready to WE# Falling Edge
Read Pulse Width
Read Cycle Time
RE# Access Time
CE# to RE# Time
ALE to RE# Time
CLE to RE# Time
Data Output Hold Time
40
10
100
20
20
17
25
—
10
10
10
5
WC
WH
t
WW
t
RR
t
RW
t
RP
t
RC
t
REA
t
CR
t
AR
t
CLR
t
—
15
OH
t
RE# High to Output High Impedance
CE# High to Output High Impedance
RE# High Hold Time
—
—
8
RHZ
CHZ
REH
t
15
t
—
t
Output High Impedance to RE# Falling Edge
RE# High to WE# Low
0
—
IR
t
t
t
30
30
60
—
—
—
—
—
—
RHW
WHC
WHR
WE# High to CE# Low
—
WE# High to RE# Low
—
Full Page Data Transfer from Memory Cell Array to Register
Partial Page Data Transfer from Memory Cell Array to Register
Full page Data Transfer to Register During Power On Read
WE# High to Busy
25
t
µs
R
8
t
50
µs
ns
µs
RPRE
t
100
1/1/15
WB
t
Device Resetting Time (Read/Program/Erase)
RST
8.7
AC Test Conditions
Operating Range
V
1.7 V to 1.95 V
CC
Input level
0.0 to V
CC
Input comparison level
Output data comparison level
V
V
/2
CC
CC
/2
Load capacitance (C )
30 pF
5 ns
L
Transition time (t ) (input rise and fall times)
T
14
S30MS-P ORNANDTM Flash Family
S30MS-P_00_A7 August 4, 2006
D a t a S h e e t ( P r e l i m i n a r y )
8.8
Program and Erase Characteristics
Typ.
Max.
Symbol
Parameter
Dummy Busy Time for Cache Programming (first 15h) (Note 2)
Dummy Busy Time for Cache Programming (next 15h) (Note 3)
Page Programming Time
Min.
—
(Note 4)
(Note 5)
Unit
µs
t
0.4
0.8
0.8
260
—
0.8
4.4
4.4
1400
8
CBSY1
CBSY2
t
—
ms
ms
µs
t
—
PROG
t
Partial Page Programming Time
—
PPROG
N
Number of Programming Cycles on Same Page (Note 1)
Block Erasing Time
—
t
—
50
150
ms
BERASE
Notes:
1. One programming cycle per segment. Refer to Page Program on page 27 for more information.
2. First cache programming of a sequence.
3. Following cache programming of a sequence - second page and following pages.
4. Typical program and erase times assume the following conditions: 25°C, 1.8 V V , 10,000 cycles; checkerboard data pattern.
CC
5. Under worst case conditions of 90°C, V =1.70 V, 100,000 cycles.
CC
9. Timing Diagrams
Figure 9.1 Command Input Cycle Timing Diagram
CLE
tCLS
tCS
tCLH
tCH
CE#
tWP
WE#
tALS
tALH
ALE
I/O
tDS
tDH
: VIL or VIH
August 4, 2006 S30MS-P_00_A7
S30MS-P ORNANDTM Flash Family
15
D a t a S h e e t ( P r e l i m i n a r y )
Figure 9.2 Address Input Cycle Timing Diagram
tCLH
tCLS
CLE
tWC
tCH
tCS
CE#
tWP
tWH
WE#
ALE
I/O
tALH tALS
tDS
tDH
Col. Add1
Col. Add2
Row Add1
Row Add2
: V or VIL
IH
Figure 9.3 Data Input Cycle Timing Diagram
t
t
CLS
CLH
CLE
t
CH
t
CS
CE#
t
WC
t
t
ALH ALS
ALE
t
t
WH
WP
WE#
t
DS
t
DH
D
0
IN
D
1
IN
D
I/O
IN
2111 (x8)
1055 (x16)
: V or V
IH IL
16
S30MS-P ORNANDTM Flash Family
S30MS-P_00_A7 August 4, 2006
D a t a S h e e t ( P r e l i m i n a r y )
Figure 9.4 Serial Read Cycle Timing Diagram
CE# don't care
tCH
tRC
tCR
CE#
tOH
ALE#
CLE#
RE#
tREH
tRP
tREA
tOH
tCHZ
I/Ox
Dout0
tRHZ
Dout1
DoutN
tRR
Figure 9.5 Status Read Cycle Timing Diagram
tCLR
CLE
tCLS
tCLH
tCS
CE#
tCH
tWP
tCR
WE#
tOH
tWHC
tWHR
RE#
I/Ox
tOH
tIR
tDS
tDH
tCHZ
tREA
Status
Output
70H
tRHZ
RY/BY#
: VIH or VIL
August 4, 2006 S30MS-P_00_A7
S30MS-P ORNANDTM Flash Family
17
D a t a S h e e t ( P r e l i m i n a r y )
Figure 9.6 Read Cycle Timing Diagram
CLR
t
CLE
tCLS
tCS
tCLH
tCH
CE#
tWC
tCR
WE#
ALE
tALH tALS
tALH tALS
tAR
tR
tRC
tWB
RE#
tDS tDH
tRR tREA
Col.
Add1
Col.
Add2
Row
Add1
Row
Add2
D
D
OUT
A+1
OUT
I/O
00h
30h
A
Data out from
Col. Add. A
Page Address P
Column Address A
RY/BY#
Figure 9.7 Column Address Change in Read Cycle Timing Diagram (1/2)
tCLR
CLE
tCLS
tCS
tCLH
tCH
CE#
tWC
tCR
WE#
tALH
tALS
tALH
tAR
tALS
ALE
tRC
tR
RE#
tWB
tREA
tDS tDH
tRR
Row
Add1
Row
Add2
Col.
Add1
Col.
Add2
D
D
OUT
A+1
D
OUT
A+N
OUT
A
I/O
00h
30h
Page address
P
Column address
A
Page address
P
RY/BY#
Column address
A
Part A
Part B
A
18
S30MS-P ORNANDTM Flash Family
S30MS-P_00_A7 August 4, 2006
D a t a S h e e t ( P r e l i m i n a r y )
Figure 9.8 Column Address Change in Read Cycle Timing Diagram (2/2)
tCLR
CLE
tCLS
tCS
tCLH
tCH
CE#
t
tCR
RHW
tWC
WE#
tALH tALS
tALH tALS
ALE
tRC
RE#
I/O
tDS tDH
tREA
tIR
D
A +N
Col.
Add1
Col.
Add2
D
D
OUT
B+1
D
OUT
B+N'
OUT
OUT
B
05h
E0h
Page address
P
Column address
B
RY/BY#
Part A
Part B
Column address
B
A
Figure 9.9 Program Operation Timing Diagram
tCLS
CLE
tCLS tCLH
tCS
tCS
CE#
tCH
WE#
tALH
tALH
tALS
tPROG
tALS
tWB
tRW
ALE
RE#
tDS
tDH
tDS tDH
Col.
Row
Add2
Col.
Row
Status
output
80h
D
D
D
10h
70h
I/O
IN0
A
IN1
IN
Add1 Add2 Add1
2111 (x8)
1055 (x16)
Column Address A
Page Address P
RY/BY#
: V or VIL
IH
: Do not input data while data is being output.
August 4, 2006 S30MS-P_00_A7
S30MS-P ORNANDTM Flash Family
19
D a t a S h e e t ( P r e l i m i n a r y )
Figure 9.10 Block Erase Timing Diagram
CLE
tCLS
tCS
tCLH
tCLS
CE#
WE#
tALH
tALS
tBERASE
tWB
ALE
RE#
tDS tDH
Row
Add1
Row
Add2
Status
output
60h
D0h
70h
I/O
Note 2
Note 1
Busy
Auto Block Erase Setup
command
Erase Start
command
Read Status
command
RY/BY#
: V or VIL
IH
: Do not input data while data is being output.
Notes:
1. If I/O 0 = 0, then the erase is successful. If I/O0 = 1, then there is an error in the erase.
2. Only the block address part of the Row Address bytes are used; page address is ignored.
Figure 9.11 Cache Program Operation Timing Diagram
C L E
C E#
tWC
W
E#
tCBSY2
tCBSY
tWB
tWB
A L E
R E#
Din
N
Din
N
Din
M
Din
Col Add2
Row Add1 Row Add2
Col Add1
Col Add2
Row Add1 Row Add2
15h
80h
10h
M
70h
I/O
Col Add1
80h
I/O
x
Program
Command
(Dummy)
Program Confirm
Command
(True)
Serial Data
Serial Input
Input Command
Column Address
Page Address
Page Address
Column Address
RY /BY#
Note:
CE#, CLE, and ALE are Don’t care.
20
S30MS-P ORNANDTM Flash Family
S30MS-P_00_A7 August 4, 2006
D a t a S h e e t ( P r e l i m i n a r y )
Figure 9.12 Page Duplicate Program Timing Diagram
C
C
W
A
L E
E#
E#
L E
E#
tWC
tWB
tPROG
tWB
R
tR
Col Add2 RowAdd1 RowAdd2
Column Address
ColAdd1
85h
I/O
x
00h
Col Add2 RowAdd1 RowAdd2
Column Address
10h
70h
I/O0
35h
ColAdd1
Data 1
Data N
Read Status
Command
Page Address
Page Address
R
Y/ BY#
Busy
Busy
I/O
I/O
0
=0 Successful P rogram
Page Duplicate Date
Input Command
0=1 Error in Program
Note:
CE#, CLE, and ALE are Don’t care.
9.1
ID Read
Figure 9.13 ID Read Operation Timing Diagram
CLE
tCLS
tCH
tCLS
tCS
CE#
tALH
tCS
WE#
tCR
tALS
tCH
tALH
tAR
ALE
tDS
RE#
tDH
2nd
byte
3rd
byte
4th
byte
5th
byte
I/O
00h
01h
90h
tREA
: VIH or VIL
Address Input
Maker Code
Device Code
Note:
CE#, CLE, and ALE are Don’t care.
August 4, 2006 S30MS-P_00_A7
S30MS-P ORNANDTM Flash Family
21
D a t a S h e e t ( P r e l i m i n a r y )
Table 9.1 ID Byte Settings Summary
Byte
Description
Hex Data
01h
1st Byte
Maker Code
512 Mb (x8)
81h
512 Mb (x16)
91h
2nd Byte
Device Code 1st Byte
1 Gb (x8)
A1h
B1h
00h
1 Gb (x16)
Model Numbers 50 and 51 (ECC Required)
Model Numbers 00 and 01
3rd Byte
Device Code 2nd Byte
01h
4th Byte
5th Byte
Block Size, Simultaneous Programmed Pages, RFU
Page Size, Spare Size, RFU
00h
22h
Note:
In x16, I/O15 - I/O8 = 00h
Table 9.2 4th ID Byte
Description
I/O7
X
I/O6
X
I/O5
X
I/O4
X
I/O3
X
I/O2
0
I/O1
I/O0
0
Block Size: 128 KBytes
Block Size: 512 KBytes
Block Size: 2048 KBytes
0
0
X
X
X
X
X
0
1
X
X
X
X
X
0
1
0
1
2
4
8
X
X
X
0
0
X
X
X
X
X
X
X
X
X
0
1
X
X
Number of simultaneously programmed pages
X
X
X
1
0
X
X
X
X
X
1
1
X
X
Table 9.3 5th ID Byte
Description
I/O7
X
I/O6
X
I/O5
X
X
X
X
X
0
I/O4
X
X
X
X
X
0
I/O3
X
X
X
X
X
0
I/O2
0
I/O1
I/O0
Page Size: 512 KBytes
Page Size: 1024 KBytes
Page Size: 2048 KBytes
Page Size: 4096 KBytes
Page Size: 8192 KBytes
Spare Size: 0 Bytes
0
0
0
1
X
X
0
X
X
0
1
0
X
X
0
1
1
X
X
1
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Spare Size: 8 Bytes
X
X
0
0
1
Spare Size: 16 Bytes
Spare Size: 32 Bytes
Spare Size: 64 Bytes
X
X
0
1
0
X
X
0
1
1
X
X
1
0
0
22
S30MS-P ORNANDTM Flash Family
S30MS-P_00_A7 August 4, 2006
D a t a S h e e t ( P r e l i m i n a r y )
10. Schematic Cell Layout and Address Assignment
The Program operation works on page units while the Erase operation works on block units.
10.1 Array Organization
Figure 10.1 Array Organization
I/O0
2048
64
I/O7
64 pages = 1 block
1Gb device
64K pages
1024 blocks
512Mb device
32K pages
512 blocks
8 I/O for x8
16I/O for x16
2112 Bytes
A page consists of 2112 Bytes in which 2048 Bytes are used for main memory storage and 64 Bytes are for
redundancy or for other uses.
1 page = 2112 Bytes
1 block = 2112 Bytes x 64 pages = (128K + 4K) Bytes
1Gb density = 2112 Bytes x 64 pages x 1024 blocks
Table 10.1 shows a summary of the addressing for the memory array components.
Table 10.1 Memory Addressing Key
Row Address
Column Address
Main
Spare
Colum
n
Addres
s
Colum
Block
Addres
s
Page
Address
in Block
Main
Page
Segment
n
Addres
s
Spare
Page
Segment
Bus
Density
1 Gb
Width
Main/Spare Area
Blocks
1024
1024
512
x8
x16
x8
A
A
A
A
:A
A
A
A
A
:A
A
A
A
A
(0=Main, 1=Spare)
(0=Main, 1=Spare)
(0=Main, 1=Spare)
(0=Main, 1=Spare)
A
:A
A :A
A :A
A :A
3
27 18
17 12
11
10
11
10
10
9
8
0
0
0
0
5
4
3
4
3
0
0
0
0
1 Gb
:A
:A
A :A
A :A
A :A
A :A
2
26 17
16 11
9
8
7
4
512 Mb
512 Mb
:A
:A
A
:A
A :A
A :A
A :A
3
26 18
17 12
10
9
8
5
x16
:A
:A
A :A
A :A
A :A
A :A
512
25 17
16 11
9
8
7
4
2
An address is read through the I/O port over four consecutive clock cycles, as shown in Table 10.2 and
Table 10.3. The Notes for Table 10.2 and Table 10.3 are listed below Table 10.3.
Table 10.2 (1Gb) x 8 device
1Gbit
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
1st Cycle
A
A
A
A
A
A
A
A
A
A
7
0
1
9
2
3
4
5
6
L
L
L
L
2nd Cycle
A
A
8
10
11
(Note 1)
(Note 1)
(Note 1)
(Note 1)
3rd Cycle
4th Cycle
A
A
A
A
A
A
A
A
A
A
A
A
A
A
12
20
13
14
22
15
16
24
17
25
18
26
19
27
A
A
21
23
August 4, 2006 S30MS-P_00_A7
S30MS-P ORNANDTM Flash Family
23
D a t a S h e e t ( P r e l i m i n a r y )
Table 10.3 (512Mb) x8 Addressing
512Mb
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
1st Cycle
A
A
A
A
A
A
A
A
A
7
0
8
1
9
2
3
4
5
6
L
L
L
L
2nd Cycle
3rd Cycle
4th Cycle
A
A
A
A
A
A
A
10
14
22
11
15
23
(Note 1)
(Note 1)
(Note 1)
(Note 1)
A
A
A
A
A
A
A
A
A
A
19
12
20
13
21
16
24
17
25
18
26
L
A
(Note 1)
Notes:
1. L = V
IL.
2. A0 to A11:Column address (12 bits for 2,112 Bytes).
A12 to A27: Row address, consists of:
A12 to A17: Page address in block (6 bits for 64 pages).
3. A18 to A27: Block address (1 Gb device: A18 to A27, 10 bits for 1024 blocks; 512Mb device: A18 to A26, 9 bits for 512 blocks.)
Table 10.4 (1Gb) x 16 Addressing
1Gb
I/O0 I/O1 I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8 – I/O15
L (Note 1)
L (Note 1)
L (Note 1)
L (Note 1)
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
A
A
A
A
A
A
A
A
A
A
7
0
8
1
9
2
3
4
5
6
A
A
A
L (Note 1)
L (Note 1)
L (Note 1)
L (Note 1)
L (Note 1)
10
13
21
A
A
A
A
A
A
A
A
A
A
A
A
A
A
11
19
12
20
14
22
15
23
16
24
17
25
18
26
Table 10.5 (512) x 16 Addressing
512Mb
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
I/O0 I/O1 I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8 – I/O15
L (Note 1)
L (Note 1)
L (Note 1)
L (Note 1)
A
A
A
A
A
A
A
A
A
A
7
0
8
1
9
2
3
4
5
6
A
A
A
L (Note 1)
L (Note 1)
L (Note 1)
L (Note 1)
L (Note 1)
10
13
21
A
A
A
A
A
A
A
A
A
A
A
A
18
11
19
12
20
14
22
15
23
16
24
17
25
A
L (Note 1)
Notes:
1. L = V
IL.
2. A0 to A1 :Column address (11 bits for 1,056 words)
0
3. A11 to A26: Row address, consists of:
A11 to A16: Page address in block (6 bits for 64 pages).
A17 to A26: Block address (1 Gb device: A to A : 10 bits for 1024 blocks; 512Mb device: A17 to A25: 9 bits for 512 blocks.)
17
26
24
S30MS-P ORNANDTM Flash Family
S30MS-P_00_A7 August 4, 2006
D a t a S h e e t ( P r e l i m i n a r y )
11. Operation Mode: Logic and Command Tables
The operation modes such as Program, Erase, Read, and Reset are controlled by the thirteen different
command operations shown in Table 11.2 on page 25. Address input, command input and data input/output
are controlled by the CLE, ALE, CE#, WE#, RE# and WP# signals, as shown in Table 11.1.
Table 11.1 Operation Table
CLE
H
L
ALE
L
CE#
L
WE#
RE#
H
PRE
X
WP#
X
Mode
Command Input
Address Input (4 clock cycles)
Read Mode
H
L
L
H
X
X
L
X
L
H
H
H
X
X
During Read (Busy)
L
L
X
X
Sequential Read & Data Output
H
L
L
L
H
H
H
X
X
X
X
X
H
Command Input
Program Mode
H
L
L
X
H
Address Input (4 clock cycles)
L
L
X
H
Data Input
X
X
X
X
X
H
X
X
X
X
X
H
During Program (Busy)
During Erase (Busy)
Write Protect
X
X
X
H
X
X
X
L
X
X
0 V/V
0 V/V
Stand-by
CC
CC
Notes:
1. H: V , L: V , X: V or V
IH
IL
IH
IL
2. WP# should be biased to CMOS high or CMOS low for standby.
Table 11.2 Command Table
Command Accepted
During Busy State
Function
1st Cycle
00h
2nd Cycle
30h
31h
35h
—
Page Read
No
No
No
No
No
No
No
No
No
No
Yes
Yes
Partial Page Read
00h
Read for Page Duplicate
ID Read
00h
90h
Page Program
80h
10h
15h
10h
—
Cache Program
80h
Page Duplicate Program
Data Input for Column Address Change
Read for Column Address Change
Block Erase
85h
85h
05h
E0h
D0h
—
60h
Reset
FFh
70h
Status Read
—
Notes:
1. Random Data Input/Output can be executed in a page or 1/4 page.
2. Input of a command other than those specified in Table 11.2 is prohibited. Stored data may be corrupted if an unknown command is
entered during the command cycle.
3. During the Busy state, input commands are restricted to 70h and FFh.
August 4, 2006 S30MS-P_00_A7
S30MS-P ORNANDTM Flash Family
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D a t a S h e e t ( P r e l i m i n a r y )
Table 11.3 Read Mode Operation Status
Operation
Output Select
Output Deselect
Standby
CLE
L
ALE
L
CE#
L
WE#
H
RE#
L
I/O0 to I/O15
Data Output
Power
Active
L
L
X
H
H
High Impedance
High Impedance
Active
X
X
H
X
X
Standby
Notes:
1. H = V
IH
2. L = V
IL
3. X = V or V
IH
IL
12. Device Operation
12.1 Read Mode
There are two types of read operations: random read and serial page read. The device defaults to Read
mode after power-up or a Reset or may be initiated by writing 00h-30h to the command register along with
four address cycles. A partial page read may be initiated by writing 00h-31h to the command register along
with the four address cycles. The random data read is enabled by a page or partial page address change.
The addressed page of data is loaded into the page register and the completion of the loading process is
detected by polling the RY/BY# pin or reading the status register. Once the data is loaded into the page
register, it may be read by clocking RE#. The high to low transition of the RE# signal outputs data
sequentially, starting with the first selected column address and ending with the last selected column address.
Subsequent reads will output the last column address data. See Figure 12.1 for timing details.
The device may output random data in a page instead of the consecutive sequential data upon entering the
random data output command. The column address of the next data to be read can be changed to the
address which follows the random data output command. The random data output command may be issued
multiple times, but must be within the same page.
Figure 12.1 Read Mode
CLE
CE#
WE#
ALE
RE#
Busy
RY/BY#
I/O
Column Address A
Page Address
P
00h
30h
A
A+1
A+2
Page Address P
Start-address input
A data transfer operation from the cell array to the
page buffer starts on the rising edge of WE# in the
30h command input cycle (after the address
information has been latched). The device is in
Busy state during this transfer period.
After the transfer period the device returns to
Ready state. Serial data can be output
A
n
Select
page
P
Cell array
synchronously with the RE# clock from the start
pointer designated in the address input cycle.
x8: n=2112 Bytes
x16: n=1056 Words
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D a t a S h e e t ( P r e l i m i n a r y )
Figure 12.2 Column Address Read
CLE
CE#
WE#
ALE
RE#
RY/BY#
Busy
Col. A
E0h
A’+4
A
A+1 A+2 A+3
A’+1
A’+2 A’+3
Page A
30h
05h
00h
A’
I/O
Col. A
Page P
Col. A’
Page P
Start from Col. A
Start from Col. A'
Start-address input
A
During the serial data output from the register
the column address can be changed by inputting
a new column address using the 05h and E0
commands. The data is read out in serial starting
at the new column address. Random column
address Change operation can be done multiple times
within the same page.
A’
Select page
P
Cell array
12.2 Page Program
The device conducts an Automatic Page Program operation when it receives a 10h Program confirm
command after the address and data are input. The sequence of command and address and data input is
shown below. (See Figure 12.3.)
Partial page programming is allowed for this device. A page is divisible into eight segments and each
segment may be programmed individually or in any combination of segments simultaneously. For example, in
x8 devices the first data segment of 512 bytes and the first spare area segment of 16 bytes, are
programmable at the same time. Table 12.1 describes the page segments:
Table 12.1 Page Segments
x8
x16
Data Area
1st segment
2nd segment
3rd segment
4th segment
Spare Area
1st segment
2nd segment
3rd segment
4th segment
512 Bytes x 4 Segments / Page
Column Address 0 to 511
512 Bytes x 4 Segments / Page
Column Address 0 to 255
Column Address 512 to 1023
Column Address 1024 to 1535
Column Address 1536 to 2047
16 Bytes x 4 Segments / Page
Column Address 2048 to 2063
Column Address 2064 to 2079
Column Address 2080 to 2095
Column Address 2096 to 2111
Column Address 256 to 511
Column Address 512 to 767
Column Address 768 to 1023
16 Bytes x 4 Segments / Page
Column Address 1024 to 1031
Column Address 1032 to 1039
Column Address 1040 to 1047
Column Address 1048 to 1055
The maximum number of consecutive partial page program operations allowed in the same segment is one.
Each of the eight segments may be programmed once before a block erase is required and each of the eight
segments is independent with respect to the single program operation allowed.
The device also supports random data programming within a page by using the random data input command
(85h). Random data input requires the command to be entered between column addresses during the page
program command cycle. Once the new column address is entered, the system can continue the page
August 4, 2006 S30MS-P_00_A7
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D a t a S h e e t ( P r e l i m i n a r y )
program command cycle by entering the page address and the data. The Page Program confirm command
(10h) initiates the programming operation.
Once the program operation starts, the Read Status Register command may be entered to read the status
register. The system controller can detect the completion of a program cycle by monitoring the RY/BY#
output, or the Status bit (I/O6) of the Status Register. Only the Read Status command and Reset command
are valid while programming is in progress. When the Page Program is complete, the Write Status Bit (I/O0)
may be verified. The internal write verify detects only errors for 1s that are not successfully programmed to
0s. The command register remains in Read Status command mode until another valid command is written to
the command register.
Figure 12.3 Page Program
CLE
CE#
WE#
ALE
RE#
RY/BY#
Din Din Din
70h
80h
Din
10h
I/O
Col. A
Data input
Page P
Data
The data is transferred (programmed) from the page
buffer to the selected page on the rising edge of WE#
following input of the 10h command. After programming,
the programmed data is transferred back to the register
to be automatically verified by the device. If the
programming does not succeed, the Program/Verify
operation is repeated by the device until success is
achieved or until the maximum loop number set in
the device is reached.
Program
Read and verification
Once the Serial Input command 80h is input, the only acceptable commands are the programming
commands 10h, 85h or the Reset command FFh. If any other input command is used, the program operation
is not performed and the device must be reset.
Figure 12.4 Serial Input Command Sequence
80
XXX
10
Note:
If XXX is a command other than 10h, 85h, or FFh, the operation does not execute. When this occurs, the reset command (FFH) must be
entered to return the device to a valid state.
12.3 Cache Program
Cache Program is a double buffer scheme for faster programming. The Cache buffer size is identical to the
page buffer size (i.e. 2112Byte (x8) or 1056Word (x16) data registers). Data may be written into the cache
register while other data stored in the page buffer are programmed into the memory array.
After writing the first set of data up to 2112Byte (x8) or 1056Word (x16) into the cache register, the Cache
program command (15h) must be entered instead of the standard Page Program command (10h) in order to
free up the cache register and start the internal program operation. To transfer data from the cache register to
the data register, the device remains in the Busy state for a short period of time (tCBSY) and has its cache
register ready for the next data-input while the internal programming starts with the data loaded into the data
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S30MS-P ORNANDTM Flash Family
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D a t a S h e e t ( P r e l i m i n a r y )
register. The Read Status command (70h) may be issued to verify that the cache register is ready by polling
the Cache-Busy status bit (I/O6). Pass/Fail status of the previous page is available upon the return to the
Ready state. When the next set of data is input with the Cache Program command, tCBSY is affected by the
progress of pending internal programming. The programming of the cache register is initiated only when the
pending program cycle is finished and the data register is available for the transfer of data from the cache
register. The status bit (I/O5) for internal Ready/Busy may be polled to identify the completion of internal
programming.
If the system monitors the progress of programming with RY/BY# only, the last page of the target
programming sequence must be programmed with Page Program command (10h). Alternatively, if the last
page to be programmed is accomplished using the Cache Program command (15h), status bit (I/O5) must be
polled to verify that the last program is actually finished before starting other operations.
Following the Cache Program Command (15h), the pass/fail status information is available as follows:
1. I/O1 returns the status of the previous page (when ready or when the I/O6 bit is changing to a 1).
2. I/O0 returns the status of the current page (upon true ready, or when the IO5 bit is changing to a 1).
3. I/O0 and I/O1 may be read together.
Figure 12.5 Cache Program
tPROG
tCBSY1
tCBSY2
tCBSY2
RY/BY#
Address &
Data Input
Address &
Data Input
Address &
Data Input*
Address &
Data Input
80h
70h
10h
80h
15h
80h
80h
15h
15h
Col Add1,2 & Row Add1,2
Data
Col Add1,2 & Row Add1,2
Data
Col Add1,2 & Row Add1,2
Data
Col Add1,2 & Row Add1,2
Data
tCBSY1
tCBSY2
tCBSY2
RY/BY#
I/Ox
Address &
Data Input
Status
output
Address &
Data Input
Status
output
Address &
Data Input
80h
80h
80h
15h
70h
15h
70h
15h
Col Add1,2 & Row Add1,2
Data
Col Add1,2 & Row Add1,2
Data
Col Add1,2 & Row Add1,2
Data
tCBSY2
Address &
Data Input
Status
Status
output
Status
output
80h
70h
70h
15h
output
Col Add1,2 & Row Add1,2
Data
Check I/O1 for pass/fail
Check I/O5 for internal ready/busy
Check I/O0,1 for pass/fail
Note:
Since programming the last page does not employ caching, the program time has to be that of Page Program. However, if the previous
program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after completion of the previous
cycle, which can be expressed as the following formula: t
command time + data loading time of last page).
= Program time of last page + program time of the (last -1) page - (program
PROG
12.4 Page Duplicate Program
The Page Duplicate program is configured to quickly and efficiently rewrite data stored in one full page (no
partial page) without utilizing an external memory. Since the time-consuming serial access and re-loading
cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of
a block is updated and the block also needs to be copied to the newly assigned free block. A Page Duplicate
program operation is performed by first initiating a read operation with command 35h and the address of the
source which then duplicates the whole 2112Byte (x8) or 1056Word (x16) data into the internal data buffer.
As soon as the device is ready, the Program Confirm command (10h) is required to actually begin the
programming operation to the address of the destination page. Once the Page Duplicate Program is finished,
any additional partial page programming into the copied pages is prohibited before erasure. The data input
cycle for modifying a portion or multiple distant portions of the source page is allowed as shown in Figure 12.6
on page 30. Page data duplicates directly to another Page in a Block.
August 4, 2006 S30MS-P_00_A7
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D a t a S h e e t ( P r e l i m i n a r y )
Figure 12.6 Page Duplicate Program Operation
tR
tPROG
RY/BY#
I/Ox
Add.(4Cycles)
Pass
00h
35h
Add.(4Cycles)
10h
I/O0
Fail
85h
70h
Col. Add1,2 & Row Add1,2
Destination Address
Col. Add1,2 & Row Add1,2
Source Address
Figure 12.7 Page Duplicate Program Operation with Random Data Input
tPROG
tR
RY/BY#
I/Ox
Add.(2Cycles)
Col Add1,2
Add.(4Cycles)
35h
Add.(4Cycles)
70h
00h
85h
Data
85h
Data
10h
Col. Add1,2 & Row Add1,2
Source Address
Col. Add1,2 & Row Add1,2
Destination Address
There is no limitation for the number of repetition.
12.5 Block Erase
The Block Erase process starts with the block erase setup command 60h, followed by two cycles of row
address, followed by the block erase execute command D0h. Note that the page address part of the row
address is ignored.
The Block Erase operation starts on the rising edge of WE# after the Erase Start command D0h which follows
the Erase Setup command 60h. This two-cycle process for Erase operations acts as an extra layer of
protection from accidental erasure of data due to external noise. The device automatically executes the Erase
and Verify operations.
Figure 12.8 Block Erase
Pass
I/O
60
D0
70
Block Address
input: 2 cycles
Erase Status
command
Status Read
command
Fail
Busy
RY/BY#
12.6 Write Operation Status
The device provides a RY/BY# output pin and Status Register bits to determine the status of a write
operation. The status register bits can be used to determine which stage the write operation is in.
12.7 Status Read
The device contains a Status Register which may be read to find out whether a program or erase operation is
completed, and whether the program or erase operation completed successfully. After writing a 70h
command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on
the falling edge of CE# or RE#, whichever occurs last. The control by two lines allows the system to poll the
progress of each device in multiple device connection even if the RY/BY# pins are common wired. RE# or
CE# does not have to be toggled for update status. Refer to Table 12.2 for specific Status Register
definitions. The command register remains in Status Read mode until further commands are issued.
Therefore, if the status register is read during a random read cycle, the read command (00h) should be given
before starting read cycles. The Status Register clears after another valid command is entered, excluding a
status read. An application example with multiple devices is shown in Figure 12.9.
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S30MS-P ORNANDTM Flash Family
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Table 12.2 Status Output Table
During Program or
I/O
Erase Operation
Page Program
Block Erase
Cache Program
Read
Definition
0 = Pass;
I/O0
Reserved
Pass/Fail
Pass/Fail
Pass/Fail(N)
Reserved
1 = Fail
0 = Pass;
1 = Fail
I/O1
Reserved
Reserved
Reserved
Pass/Fail(N-1)
Reserved
I/O2
I/O3
I/O4
Reserved
Reserved
Reserved
Normal
Reserved
Reserved
Normal
Reserved
Reserved
Normal
Reserved
Reserved
Normal
Reserved
Reserved
0 = Normal
0 = Busy;
1 = Ready
I/O5
I/O6
I/O7
Busy
Busy
True Ready/Busy
Cache Ready/Busy
Write Protect
Ready/Busy
Ready/Busy
Write Protect
True Ready/Busy
Cache Ready/Busy
Write Protect
Ready/Busy
Ready/Busy
Write Protect
0 = Busy;
1 = Ready
0 = Protected;
1 = Unprotected
Reserved
Notes:
1. True Ready/Busy represents internal program operation status which is being executed in cache program mode.
2. I/Os defined ‘Not use’ are recommended to be masked out when Read Status in being executed.
Figure 12.9 Multiple Devices
CE(1)#
CE(2)#
CE(N)#
ALE
CLE
WE#
RE#
Device(1)
Device(2)
Device(N)
n
I/On
RY/BY#
If the RY/BY# pin signals from multiple devices are wired together as shown in Figure 12.9, the Status Read
function can be used to determine the status of each individual device.
Figure 12.10 Status Read Timing Application Example
RY/BY#
CLE
Busy
V
IL
ALE
WE#
CE1#
CEN#
RE#
I/O
70H
70H
Status on Device 1
Status on Device N
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12.8 Reset
The Reset mode aborts all operations in progress including read, erase and program. For example, in the
case of a Program or Erase operation the internally generated voltage is discharged to 0 volts and the device
enters standby. Any attempted memory data alteration is invalidated if interrupted by a reset command.
The response to an FFh Reset command input during the various device operations is shown in Figure 12.11
to Figure 12.15.
Figure 12.11 Reset (FFh) Command Input During Programming
80
10
FF
00
Internal VPP
RY/BY#
tRST (see Note)
Note:
The reset time (t
) is not the same for program, erase, and read operations.
RST
Figure 12.12 Reset (FFh) Command Input During Erasing
D0
FF
00
Internal
erase
voltage
RY/BY#
tRST (see Note)
Note:
The reset time (t
) is not the same for program, erase, and read operations.
RST
Figure 12.13 Reset (FFh) Command Input During a Read Operation
00
FF
00
RY/BY#
tRST (see Note)
Note:
The reset time (t
) is not the same for program, erase, and read operations.
RST
Figure 12.14 Reset (FFh) Command During Operations Other Than Program, Erase, or Read
00
FF
00
RY/BY#
tRST (see Note)
Note:
The reset time (t
) is not the same for program, erase, and read operations.
RST
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D a t a S h e e t ( P r e l i m i n a r y )
Figure 12.15 Status Read Command (70h) Input After a Reset
FF
70
I/O status:
Ready/Busy
Ready
Busy
RY/BY#
I/O status:
Ready/Busy
FF
70
RY/BY#
13. Application Notes
13.1 Power On/Off Sequence and Power-On Read Enable
13.1.1 Power-On/Off Sequence
The WP# signal is useful for protecting against data corruption at power-on/off. The following timing
sequence is necessary. The WP# signal may be negated any time after the VCC reaches 1.6 V and the CE#
signal is kept high in power up sequence. A reset command issued during the power up sequence is ignored.
Figure 13.1 Power-On/Off Sequence
1.7 V
1.6 V
1.7 V
1.6 V
V
CC
0 V
Don’t
Care
Don’t
Care
CE# RE#
CLE, ALE
WP#
WE#
Don’t
Care
Don’t
Care
t
PRE
10 μs
Operation
Don’t
Care
Don’t
Care
RY/BY#
For stable operation, it is recommended to start accessing the device 200 µs after VCC becomes 1.6 V. There
is no restriction regarding the VCC ramp rate.
13.1.2
Power-On Read Enable
Power on read is a feature for certain architectures that requires the system to read data from page 0 without
a command sequence on power-up. To enable power on read, PRE must be tied to VCC to ensure a
simultaneous ramp rate. Please refer to the following waveform. Page zero data is read from the memory
array to the page buffer without any command and address input sequence following power-on. The function
will be performed when VCC attains about 1.6 V. The PRE pin controls activation of auto-page read function.
August 4, 2006 S30MS-P_00_A7
S30MS-P ORNANDTM Flash Family
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D a t a S h e e t ( P r e l i m i n a r y )
Serial access may begin after tRPRE. A reset command issued during the power-on read enable is
acceptable. Figure 13.2 shows the timing diagram.
Figure 13.2 Power-On Auto-read Enable
1.7 V
1.6 V
1.7 V
1.6 V
V
CC
0 V
Don’t
Care
Don’t
Care
CE# RE#
CLE, ALE
WP#
WE#
Don’t
Care
Don’t
Care
t
RPRE
10 μs
Operation
Don’t
Care
Don’t
Care
RY/BY#
PRE#
13.2 Status Read During a Read Operation
Figure 13.3 Status Read During a Read Operation
00
[A]
30
00
70
command
CE#
WE#
BRYY#/
RE#
2nd Cycle of
the Read Command
Address N
Status Read
command input
Status Read
Data output
The device status can be read by inputting the Status Read command 70h in Read mode.
Once the device is set to Status Read mode by a 70h command, the device will not return to Read mode.
However, when the Read command 00h is input during [A], the Status mode is reset and the device returns to
Read mode. In this case, data output starts automatically from address N and address input is unnecessary.
A pull-up resistor must be used for termination because the RY/BY# buffer consists of an open drain circuit.
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S30MS-P ORNANDTM Flash Family
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D a t a S h e e t ( P r e l i m i n a r y )
Figure 13.4 RY/BY#: Termination for the Ready/Busy Pin (RY/BY#)
VCC
VCC
VOL=0.1V, VOH= VCC - 0.1V
Read y
V
CC
VOL
VOH
R
Busy
VOL
Device
RY/BY#
CL
t
r
t
f
VSS
VCC max - VOL
R =
=
IOL + IL
1.95 V
This data may vary from device to device.
We recommend that you use this data as a
reference when selecting a resistor value.
3 mA + IL
13.2.1
When WP# Signal Goes Low
Holding the WP# pin low protects the device during power transitions. If WP# is low during the program/erase
command input period, the device is protected and does not enter the program/erase operation. If WP# is
high during the program/erase command input period, the device can execute the program/erase operation.
The user should keep the WP# pin either high or low during the complete command & program/erase
operation. The operations are enabled and disabled as shown in the following timing diagrams:
August 4, 2006 S30MS-P_00_A7
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35
D a t a S h e e t ( P r e l i m i n a r y )
Figure 13.5 WP# Signal—Low
[Enable Programming]
WE#
80
10
10
D0
D0
D
IN
WP#
RY/BY#
t
(100 ns min)
WW
[Disable Programming]
WE#
80
D
IN
WP#
RY/BY#
t
(100 ns min)
WW
[Enable Erasing]
WE#
60
D
IN
WP#
RY/BY#
t
(100 ns min)
WW
[Disable Erasing]
WE#
60
D
IN
WP#
RY/BY#
t
(100 ns min)
WW
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S30MS-P_00_A7 August 4, 2006
D a t a S h e e t ( P r e l i m i n a r y )
13.2.2
CE# Don’t Care Feature
CE# does not need to be continuously asserted across command and address write operations or during
busy periods as was required by some earlier generation NAND interface devices.
August 4, 2006 S30MS-P_00_A7
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D a t a S h e e t ( P r e l i m i n a r y )
14. Revision History
Section
Description
Revision A (January 3, 2005)
Initial release
Revision A1 (May 16, 2005)
Performance Characteristics table
Updated specifications.
Program and Erase Performance table Updated entire table
Connection Diagrams
Block Diagram
Updated all diagrams
Corrected the RY/BY# command
DC Characteristics table
Added standard and low power mode specifications to: ICC4 and ICC5
AC Characteristics and Recommended
Operating Conditions table
Updated Min. specifications for: tWP, tDS, and tDH
Updated entire table
Program and Erase Characteristics
table
ID Definition table
Updated entire table
Updated the figure
Updated the figure
Updated section
x8 Array Organization
x16 Array Organization
When WP# Signal Goes Low
Revision A2 (July 6, 2005)
Front Page
Added 100% Valid Blocks statement
Revised and corrected various parameters
Added model numbers 02 and 03
Ordering Information
Removed Industrial temperature grade
DC Characteristics Table
AC Characteristics Table
Revised various parameters
Revised and added various timing parameters
Revised tCBSY1 and tCBSY2
Corrected P/E Specification
Program and Erase Characteristics
Table
Removed 7th ID Byte table
Byte Tables
Pin Names
Updated Device ID Bytes 2, 3, 4, and 5
Removed VIO pin
Removed RY/BY#1 and RY/BY#2
Command Table
Added Pipeline Read—Full Page no additional requests command
Revised feature description and timing diagram
Removed section
Pipeline Read
Reset After Power-on
Timing Diagrams
Corrected multiple timing diagrams
Updated the entire table
Capacitance Table
Valid Blocks Table
Updated the entire table
Power-on Read Enable
Revision A3 (September 12, 2005)
Title
Added Section and timing diagrams
Added ECC-free
Connection Diagrams
Program and Erase Characteristics
Distinctive Characteristics
Updated entire diagram
Changed various program and erase specifications
Changed data retention value
Schematic Cell Layout and Address
Assignment
Added the Memory Addressing Key table
Format
Converted Data Sheet to Standard Format
Updated and Added Content
Spansion Xtreme Mode
Revision A4 (November 11, 2005)
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S30MS-P ORNANDTM Flash Family
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D a t a S h e e t ( P r e l i m i n a r y )
Section
Description
Removed specifications
Global
Removed 2 Gb specifications
Distinctive Characteristics
Status Read Output table
Reset Timing Diagrams
Power On/Off Sequence
Changed write performance value
Updated table
Changed the tRST values
Updated section
Revision A5 (December 16, 2005)
Valid Blocks Table
Updated Table
DC Characteristics
Removed the specifications for low power mode
Corrected Reset Pin Signal
Serial Read Cycle Timing Diagram
Revision A6 (March 22, 2006)
Xtreme Mode Command Definitions
Ordering Revisions
Defined WP# State during Block Status Read
Added Model Number descriptions to include boot block product
Clarified notes on Program/Erase Characteristics table
Changed the Dummy Busy Time During Cache Programming
Changed the timing for Partial Page Data Transfer to Memory Cell Array to Register (tR)
Clarified Power on Read Operation
Programming
Program and Erase Characteristics
AC Characteristics
Power on Read Enable
Revision A7 (August 4, 2006)
Global
Removed all references to Xtreme Mode
Updated tables
Performance Characteristics
Connection Diagrams
Capacitance
Updated diagram
Added the Capacitance Values for WP# and CE# pins
Updated table
Valid Blocks
DC Characteristics
Changed ICC4 and ICC5
Changed Read Cycle Timing Parameters
AC Characteristics
Changed Timing for Command Latch Enable and Address Latch Enable
Program and Erase Characteristics
Timing Diagrams
Updated table
Corrected Page Transfer Timing on Page Duplicate Program Timing Diagram
Update Models Numbers for parts that require ECC
Ordering Information
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
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The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
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Copyright © 2006 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are
trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.
August 4, 2006 S30MS-P_00_A7
S30MS-P ORNANDTM Flash Family
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