S70WS512N00BAWA23_技术文档

S70WS512N00 Based MCPs

Same-Die Stacked Multi-Chip Product (MCP)

512 Megabit (32M x 16 bit) CMOS

1.8 Volt-only Simultaneous Read/Write,

Burst-mode Flash Memory

ADVANCE

INFORMATION

Data Sheet

Notice to Readers: This document states the current technical specifications

regarding the Spansion product(s) described herein. Each product described

herein may be designated as Advance Information, Preliminary, or Full

Production. See Notice On Data Sheet Designations for definitions.

Publication Number S70WS512N00_00 Revision A Amendment 0 Issue Date March 14, 2005

This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not

design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.

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This page intentionally left blank.

S70WS512N00 Based MCPs

S70WS512N00_00_A0 March 14, 2005

S70WS512N00 Based MCPs

Same-Die Stacked Multi-Chip Product (MCP)

512 Megabit (32M x 16 bit) CMOS

1.8 Volt-only Simultaneous Read/Write,

Burst-mode Flash Memory

ADVANCE

INFORMATION

General Description

The S70WS512N Series is a product line of stacked Multi-Chip Product (MCP) packages and con-

sists of two S29WS-N flash memory die.

Distinctive Characteristics

MCP Features

Power supply voltage of 1.7 V to 1.95 V

Burst Speed: 54 MHz, 66 MHz

Package

— 8 x 11.6 mm

Operating Temperature

— Wireless, –25°C to +85°C

Publication Number S70WS512N00_00 Revision A Amendment 0 Issue Date March 14, 2005

This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do

not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.

A d v a n c e I n f o r m a t i o n

Notice On Data Sheet Designations

Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise

readers of product information or intended specifications throughout the product life cycle, includ-

ing development, qualification, initial production, and full production. In all cases, however,

readers are encouraged to verify that they have the latest information before finalizing their de-

sign. The following descriptions of Spansion data sheet designations are presented here to

highlight their presence and definitions.

Advance Information

The Advance Information designation indicates that Spansion LLC is developing one or more spe-

cific products, but has not committed any design to production. Information presented in a

document with this designation is likely to change, and in some cases, development on the prod-

uct may discontinue. Spansion LLC therefore places the following conditions upon Advance

Information content:

“This document contains information on one or more products under development at Spansion LLC. The

information is intended to help you evaluate this product. Do not design in this product without con-

tacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed

product without notice.”

Preliminary

The Preliminary designation indicates that the product development has progressed such that a

commitment to production has taken place. This designation covers several aspects of the prod-

uct life cycle, including product qualification, initial production, and the subsequent phases in the

manufacturing process that occur before full production is achieved. Changes to the technical

specifications presented in a Preliminary document should be expected while keeping these as-

pects of production under consideration. Spansion places the following conditions upon

Preliminary content:

“This document states the current technical specifications regarding the Spansion product(s) described

herein. The Preliminary status of this document indicates that product qualification has been completed,

and that initial production has begun. Due to the phases of the manufacturing process that require

maintaining efficiency and quality, this document may be revised by subsequent versions or modifica-

tions due to changes in technical specifications.”

Combination

Some data sheets will contain a combination of products with different designations (Advance In-

formation, Preliminary, or Full Production). This type of document will distinguish these products

and their designations wherever necessary, typically on the first page, the ordering information

page, and pages with the DC Characteristics table and the AC Erase and Program table (in the

table notes). The disclaimer on the first page refers the reader to the notice on this page.

Full Production (No Designation on Document)

When a product has been in production for a period of time such that no changes or only nominal

changes are expected, the Preliminary designation is removed from the data sheet. Nominal

changes may include those affecting the number of ordering part numbers available, such as the

addition or deletion of a speed option, temperature range, package type, or V_IOrange. Changes

may also include those needed to clarify a description or to correct a typographical error or incor-

rect specification. Spansion LLC applies the following conditions to documents in this category:

“This document states the current technical specifications regarding the Spansion product(s) described

herein. Spansion LLC deems the products to have been in sufficient production volume such that sub-

sequent versions of this document are not expected to change. However, typographical or specification

corrections, or modifications to the valid combinations offered may occur.”

Questions regarding these document designations may be directed to your local AMD or Fujitsu

sales office.

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Contents

S70WS512N00 Based MCPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Input/Output Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

MCP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Connection Diagrams/Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.1 Special Handling Instructions for FBGA Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

5.2 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

2

3

4

5

5.2.1

Same-Die Stack Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

5.2.2 Look-Ahead Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

5.3 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

5.3.1

TSB084—84-ball Fine-Pitch Ball Grid Array (FBGA) 11.6 x 8.0 x 1.2 mm . . . . . . . . . . . . . . . . . . . . . . . . .16

S29WS-N MirrorBit™ Flash Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6

7

Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Product Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8.1 Device Operation Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8.2 Asynchronous Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8.3 Synchronous (Burst) Read Mode and Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8

8.3.1

Continuous Burst Read Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

8.3.2 8-, 16-, 32-Word Linear Burst Read with Wrap Around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8.3.3 8-, 16-, 32-Word Linear Burst without Wrap Around. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8.3.4 Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8.4 Autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8.5 Program/Erase Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

8.5.1

Single Word Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

8.5.2 Write Buffer Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

8.5.3 Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8.5.4 Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.5.5 Erase Suspend/Erase Resume Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.5.6 Program Suspend/Program Resume Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8.5.7 Accelerated Program/Chip Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

8.5.8 Unlock Bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

8.5.9 Write Operation Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.6 Simultaneous Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

8.7 Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

8.8 Handshaking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

8.9 Hardware Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

8.10 Software Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Advanced Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

9.1 Lock Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

9.2 Persistent Protection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

9.3 Dynamic Protection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

9.4 Persistent Protection Bit Lock Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

9.5 Password Protection Method. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

9.6 Advanced Sector Protection Software Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

9.7 Hardware Data Protection Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

9

9.7.1

WP# Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

9.7.2 ACC Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

9.7.3 Low V_CCWrite Inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

9.7.4 Write Pulse Glitch Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

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9.7.5 Power-Up Write Inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

10 Power Conservation Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

10.1 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

10.2 Automatic Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

10.3 Hardware RESET# Input Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

10.4 Output Disable (OE#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

11 Secured Silicon Sector Flash Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

11.1 Factory Secured SiliconSector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

11.2 Customer Secured Silicon Sector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

11.3 Secured Silicon Sector Entry and Secured Silicon Sector Exit Command Sequences. . . . . . . . . . . . . . . . . . . . . 62

12 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

12.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

12.2 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

12.3 Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

12.4 Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

12.5 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

12.6

V_CCPower-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

12.7 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

12.8 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

12.8.1 CLK Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

12.8.2 Synchronous/Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

12.8.3 Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

12.8.4 AC Characteristics—Asynchronous Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

12.8.5 Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

12.8.6 Erase/Program Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

12.8.7 Erase and Programming Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

12.8.8 BGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

13 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

13.1 Common Flash Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

14 Commonly Used Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

15 Revisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

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Tables

Table 2.1

Table 3.1

Table 7.1

Table 7.2

Table 7.3

Table 8.1

Table 8.2

Table 8.3

Table 8.4

Table 8.5

Table 8.6

Table 8.7

Table 8.8

Table 8.9

MCP Configurations and Valid Combinations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

S29WS256N Sector & Memory Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

S29WS128N Sector & Memory Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

S29WS064N Sector & Memory Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Device Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Address Latency (S29WS256N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Address Latency (S29WS128N/S29WS064N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Address/Boundary Crossing Latency (S29WS256N @ 80/66 MHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Address/Boundary Crossing Latency (S29WS256N @ 54MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Address/Boundary Crossing Latency (S29WS128N/S29WS064N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Burst Address Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Autoselect Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 8.10 Autoselect Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 8.11 Autoselect Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 8.12 Single Word Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 8.13 Write Buffer Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 8.14 Sector Erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 8.15 Chip Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 8.16 Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 8.17 Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 8.18 Program Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 8.19 Program Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 8.20 Unlock Bypass Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 8.21 Unlock Bypass Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 8.22 Unlock Bypass Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 8.23 Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 8.24 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 9.1

Table 9.2

Table 11.1

Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Sector Protection Schemes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 11.2 Secured Silicon Sector Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 11.3 Secured Silicon Sector Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 11.4 Secured Silicon Sector Exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 12.1 Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 13.1 Memory Array Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 13.2 Sector Protection Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 13.3 CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 13.4 System Interface String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 13.5 Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 13.6 Primary Vendor-Specific Extended Query. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

March 14, 2005 S70WS512N00_00_A0

S70WS512N00 Based MCPs

5

A d v a n c e I n f o r m a t i o n

Figures

Figure 8.1

Figure 8.2

Figure 8.3

Figure 8.4

Figure 8.5

Figure 8.6

Figure 9.1

Figure 9.2

Figure 9.3

Figure 12.1

Figure 12.2

Figure 12.3

Figure 12.4

Figure 12.5

Figure 12.6

Figure 12.7

Figure 12.8

Figure 12.9

Synchronous/Asynchronous State Diagram...........................................................................................23

Synchronous Read ............................................................................................................................26

Single Word Program.........................................................................................................................32

Write Buffer Programming Operation ...................................................................................................36

Sector Erase Operation ......................................................................................................................38

Write Operation Status Flowchart ........................................................................................................45

Advanced Sector Protection/Unprotection .............................................................................................51

PPB Program/Erase Algorithm.............................................................................................................54

Lock Register Program Algorithm.........................................................................................................57

Maximum Negative Overshoot Waveform .............................................................................................64

Maximum Positive Overshoot Waveform...............................................................................................64

Test Setup .......................................................................................................................................65

Input Waveforms and Measurement Levels...........................................................................................65

V_CCPower-up Diagram ......................................................................................................................66

CLK Characterization .........................................................................................................................68

CLK Synchronous Burst Mode Read......................................................................................................69

8-word Linear Burst with Wrap Around.................................................................................................70

8-word Linear Burst without Wrap Around ............................................................................................70

Figure 12.10 Linear Burst with RDY Set One Cycle Before Data..................................................................................71

Figure 12.11 Asynchronous Mode Read...................................................................................................................72

Figure 12.12 Reset Timings...................................................................................................................................72

Figure 12.13 Chip/Sector Erase Operation Timings...................................................................................................74

Figure 12.14 Asynchronous Program Operation Timings............................................................................................75

Figure 12.15 Synchronous Program Operation Timings .............................................................................................76

Figure 12.16 Accelerated Unlock Bypass Programming Timing ...................................................................................76

Figure 12.17 Data# Polling Timings (During Embedded Algorithm).............................................................................77

Figure 12.18 Toggle Bit Timings (During Embedded Algorithm)..................................................................................77

Figure 12.19 Synchronous Data Polling Timings/Toggle Bit Timings ............................................................................78

Figure 12.20 DQ2 vs. DQ6....................................................................................................................................78

Figure 12.21 Latency with Boundary Crossing when Frequency > 66 MHz....................................................................79

Figure 12.22 Latency with Boundary Crossing into Program/Erase Bank......................................................................80

Figure 12.23 Example of Wait State Insertion..........................................................................................................81

Figure 12.24 Back-to-Back Read/Write Cycle Timings ...............................................................................................82

6

S70WS512N00 Based MCPs

S70WS512N00_00_A0 March 14, 2005

A d v a n c e I n f o r m a t i o n

1 Product Selector Guide

DYB

Power-Up

State

Flash

Speed

(MHz)

Model

Numbers

Package

(mm)

Device

Flash

(See Note)

A2

A3

AB

0 (protected)

1 (unprotected)

0 (protected)

66 MHz

54 Mhz

TSB084

11.6x8.0x1.2

S70WS512N00

2 x WS256N

1 (unprotected)

Note: 0 (Protected), 1 (Unprotected [Default State])

March 14, 2005 S70WS512N00_00_A0

S70WS512N00 Based MCPs

7

A d v a n c e I n f o r m a t i o n

2 Ordering Information

The ordering part number is formed by a valid combination of the following:

S70WS 512

N

0

BA

W

A

3

0

Packing Type

0

2

3

=

Tray

7” Tape and Reel

13” Tape and Reel

DYB Power Up, Speed Combinations

3

B

2

A

=

0, 54 MHz

1, 54 MHz

0, 66 MHz

1, 66 MHz

Package Modifier

1.2 mm, 8 x 11.6, 84-ball FBGA (TSB084)

A

=

Temperature Range

Wireless (-25°C to +85°C)

W

=

Package Type

BA

=

Very Thin Fine-Pitch BGA

Lead (Pb)-free Compliant Package

Very Thin Fine-Pitch BGA

Lead (Pb)-free Package

BF

=

Chip Contents—2

No content

pSRAM Density

No content

Process Technology

N

=

110nm MirrorBit™ Technology

Flash Density

512 512Mb (2x256Mb)

=

Device Family

S70WS= Multi-Chip Product

1.8 Volt-only Simultaneous Read/Write Burst Mode

Flash Memory Same-Die Stack

Table 2.1 MCP Configurations and Valid Combinations

Valid Combinations

S70WS512N00

Package Marking Note:

0

BA, BF

W

A

2, A, 3, B

The package marking omits the leading S from the ordering part number.

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult

your local sales office to confirm availability of specific valid combinations and to check on newly

released combinations.

8

S70WS512N00 Based MCPs

S70WS512N00_00_A0 March 14, 2005

A d v a n c e I n f o r m a t i o n

3 Input/Output Descriptions

Table 3.1 identifies the input and output package connections provided on the device.

Table 3.1 Input/Output Descriptions

Symbol

A23-A0

Description

Address inputs

DQ15-DQ0

OE#

Data input/output

Output Enable input. Asynchronous relative to CLK for the Burst mode.

WE#

Write Enable input.

V

Ground

SS

NC

No Connect; not connected internally

RDY

Ready output. Indicates the status of the Burst read.

Clock input. In burst mode, after the initial word is output, subsequent active edges of CLK increment

CLK

the internal address counter. Should be at V or V while in asynchronous mode

IL

IH

Address Valid input. Indicates to device that the valid address is present on the address inputs.

Low = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be

latched.

AVD#

High = device ignores address inputs

F-RST#

F-WP#

Hardware reset input. Low = device resets and returns to reading array data

Hardware write protect input. At V , disables program and erase functions in the four outermost

IL

sectors. Should be at V for all other conditions.

IH

Accelerated input. At V , accelerates programming; automatically places device in unlock bypass

HH

F-ACC

mode. At V , disables all program and erase functions. Should be at V for all other conditions.

IL

IH

F1-CE#

F2-CE#

F-VCC

DNU

Chip-enable input for Flash 1. Asynchronous relative to CLK for Burst Mode.

Chip-enable input for Flash 2. Asynchronous relative to CLK for Burst Mode.

Flash 1.8 Volt-only single power supply.

Do Not Use

March 14, 2005 S70WS512N00_00_A0

S70WS512N00 Based MCPs

9

A d v a n c e I n f o r m a t i o n

4 MCP Block Diagram

F-RST#

RST#

ACC

WP#

CE#

OE#

WE#

AVD#

CLK

F-ACC

F-WP#

F1-CE#

F-OE#

F-WE#

AVD#

RDY

F-RDY

FLASH

MEMORY

WS256N

DQ15-DQ0

F-CLK

Amax-A0

RST#

ACC

WP#

CE#

OE#

WE#

AVD#

CLK

RDY

FLASH

MEMORY

WS256N

F2-CE#

DQ15-DQ0

Amax-A0

10

S70WS512N00 Based MCPs

S70WS512N00_00_A0 March 14, 2005

A d v a n c e I n f o r m a t i o n

5 Connection Diagrams/Physical Dimensions

This section contains the I/O designations and package specifications for the S70WS512N.

5.1

Special Handling Instructions for FBGA Packages

Special handling is required for Flash Memory products in FBGA packages.

Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning meth-

ods. The package and/or data integrity may be compromised if the package body is exposed to

temperatures above 150°C for prolonged periods of time.

5.2 Connection Diagrams

5.2.1

Same-Die Stack Pinout

84-ball Fine-Pitch Ball Grid Array

Same-Die Stack Pinout (Top View, Balls Facing Down)

Legend

A10

A1

DNU

B2

B3

RFU

C3

A7

D3

A6

E3

B4

CLK

C4

B5

F2-CE#

C5

B6

RFU

C6

B7

RFU

C7

B8

RFU

C8

B9

RFU

C9

Shared

AVD#

C2

F-WP#

D2

Flash Shared only

RFU

D9

RFU

D4

F-ACC

D5

WE#

D6

A8

A11

D8

D7

1st Flash only

2nd Flash only

A3

RFU

E4

F-RST#

E5

RFU

E6

A19

E7

A12

E8

A15

E9

E2

A2

F2

A1

G2

A0

A5

F3

A18

F4

F-RDY

F5

A20

F6

A9

A13

F8

A21

F9

F7

RAM only

A4

A17

G4

A10

G7

A14

G8

A22

G9

RFU

G5

A23

G6

G3

RFU

(Reserved for

Future Use)

V_SS

DQ1

RFU

DQ6

RFU

A16

H2

H3

H4

H5

H6

H7

H8

H9

F1-CE# OE#

DQ9

DQ3

DQ4

DQ13

DQ15

RFU

J9

J2

J3

J4

DQ10

K4

J5

J6

J7

J8

RFU

DQ0

F-VCC

RFU

DQ12

DQ7

V_SS

K2

K8

K3

K5

K7

K6

RFU

L6

K9

DQ14

DQ8

DQ2

DQ5

RFU

DQ11

RFU

L2

L3

L4

L5

L7

L8

L9

RFU

F-VCC

RFU

M10

DNU

M1

DNU

March 14, 2005 S70WS512N00_00_A0

S70WS512N00 Based MCPs

11

A d v a n c e I n f o r m a t i o n

5.2.2

Look-Ahead Connection Diagram

A2

RFU

B2

A10

RFU

B10

RFU

A9

RFU

B9

A1

RFU

B1

Legend:

X

RFU

(Reserved for

Future Use)

RFU

C2

RFU

C9

C8

C3

VSS

D3

A7

C4

CLK

D4

C5

F2-CE#

D5

C6

F-VCC

D6

C7

X

AVD#

D2

F-CLK# R-OE# F2-OE#

Code Flash Only

D7

A8

D8

A11

E8

D9

F3-CE#

E9

WP#

E2

R-LB#

D4

ACC

WE#

E6

X

E3

E7

C7

MirrorBit Data

Only

A3

A6

R-UB# F-RST# R1-CE2

A19

A12

A15

F2

F3

F4

F5

F6

F7

F8

F9

X

A2

A5

A18 RDY/WAIT# A20

A9

A13

A21

Flash/Data

Shared

G2

A1

G3

A4

G4

A17

H4

G5

G6

A23

H6

G7

A10

H7

G8

A14

H8

G9

A22

H9

R2-CE1

X

H2

H3

H5

Flash/xRAM

Shared

A0

VSS

DQ1

R2-VCC R2-CE2

DQ6

A24

A16

J9

J3

J4

J5

J6

J7

J8

J2

X

F1-CE#

OE#

DQ9

DQ3

DQ4

DQ13

DQ15 R-CRE or

R-MRS

pSRAM Only

K2

R1-CE1#

L2

K3

DQ0

L3

K4

DQ10

L4

E6

R1-VCC

L6

K7

K8

DQ7

L8

K9

K5

F-VCC

L5

DQ12

VSS

X

L7

DQ5

M7

L9

WP#

M9

xRAM Shared

R-VCC

M2

DQ8

M3

DQ2

M4

DQ11

M5

A25

DQ14

M8

M6

A27

A26

VSS

F-VCC

F4-CE# R-VCCQ F-VCCQ R-CLK#

N1

N2

N1

N10

F-DQS1

P10

N9

RFU

P9

RFU

P2

F-DQS0

P1

RFU

Notes:

Ball

3.0 V V

1.8 V V

CC

1. In a 3.0V system, the GL device used as Data has to have WP tied to V

2. F1 and F2 denote XIP/Flash, F3 and F4 denote Data/Companion Flash

D2

D5

F5

NC

F-WP#

ACC

CC

WP#/ACC

RY/BY

F-RDY/R-WAIT#

12

S70WS512N00 Based MCPs

S70WS512N00_00_A0 March 14, 2005

A d v a n c e I n f o r m a t i o n

5.3

Physical Dimensions

5.3.1

TSB084—84-ball Fine-Pitch Ball Grid Array (FBGA) 11.6 x 8.0 x 1.2 mm

A

D1

D

eD

0.15

(2X)

C

10

9

8

7

6

5

4

3

2

1

SE

7

E

B

E1

eE

L

J

H

G

F

E

D

C

B

A

M

K

INDEX MARK

10

PIN A1

CORNER

PIN A1

CORNER

7

SD

0.15

(2X)

C

TOP VIEW

SIDE VIEW

BOTTOM VIEW

0.20

0.08

C

A2

A

C

A1

6

84X

b

0.15

0.08

M

C

A B

M

NOTES:

PACKAGE

JEDEC

TSB 084

N/A

1. DIMENSIONING AND TOLERANCING METHODS PER

ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

D x E

11.60 mm x 8.00 mm

PACKAGE

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.

SYMBOL

MIN

NOM

---

MAX

1.20

---

NOTE

4.

e REPRESENTS THE SOLDER BALL GRID PITCH.

A

A1

---

PROFILE

5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"

DIRECTION.

0.17

0.81

---

BALL HEIGHT

SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE

"E" DIRECTION.

A2

---

0.97

BODY THICKNESS

BODY SIZE

D

11.60 BSC.

8.00 BSC.

8.80 BSC.

7.20 BSC.

12

n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS

FOR MATRIX SIZE MD X ME.

E

BODY SIZE

D1

E1

MATRIX FOOTPRINT

6

7

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A

AND B AND DEFINE THE POSITION OF THE CENTER SOLDER

BALL IN THE OUTER ROW.

MD

ME

n

MATRIX SIZE D DIRECTION

MATRIX SIZE E DIRECTION

BALL COUNT

10

84

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE

OUTER ROW SD OR SE = 0.000.

φb

0.35

0.40

0.45

BALL DIAMETER

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE

OUTER ROW, SD OR SE = e/2

eE

0.80 BSC

0.40 BSC

BALL PITCH

eD

SD / SE

BALL PITCH

8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

BALLS.

SOLDER BALL PLACEMENT

A2,A3,A4,A5,A6,A7,A8,A9

B1,B10,C1,C10,D1,D10

DEPOPULATED SOLDER BALLS

9. N/A

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

E1,E10,F1,F10,G1,G10

H1,H10,J1,J10,K1,K10,L1,L10

M2,M3,M4,M5,M6,M7,M8,M9

3439 \ 16-038.22 \ 01.04.05

March 14, 2005 S70WS512N00_00_A0

S70WS512N00 Based MCPs

13

S29WS-N MirrorBit™ Flash Family

S29WS256N, S29WS128N, S29WS064N

256/128/64 Megabit (16/8/4 M x 16-Bit) CMOS 1.8 Volt-only

Simultaneous Read/Write, Burst Mode Flash Memory

ADVANCE

INFORMATION

Data Sheet

General Description

The Spansion S29WS256/128/064N are Mirrorbit™Flash products fabricated on 110 nm process technology. These burst

mode Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate

banks using separate data and address pins. These products can operate up to 80 MHz and use a single V_CCof

1.7 V to 1.95 V that makes them ideal for today’s demanding wireless applications requiring higher density, better per-

formance and lowered power consumption.

Distinctive Characteristics

Single 1.8 V read/program/erase (1.70–1.95 V)

110 nm MirrorBit™ Technology

Simultaneous Read/Write operation with zero

latency

Hardware (WP#) protection of top and bottom

sectors

Dual boot sector configuration (top and bottom)

Offered Packages

— WS064N: 80-ball FBGA (7 mm x 9 mm)

— WS256N/128N: 84-ball FBGA (8 mm x 11.6 mm)

32-word Write Buffer

Sixteen-bank architecture consisting of 16/8/4

Mwords for WS256N/128N/064N, respectively

Four 16 Kword sectors at both top and bottom of

memory array

254/126/62 64 Kword sectors (WS256N/128N/

064N)

Programmable burst read modes

— Linear for 32, 16 or 8 words linear read with or

without wrap-around

Low V_CCwrite inhibit

Persistent and Password methods of Advanced

Sector Protection

Write operation status bits indicate program and

erase operation completion

Suspend and Resume commands for Program and

Erase operations

Unlock Bypass program command to reduce

programming time

Synchronous or Asynchronous program operation,

independent of burst control register settings

ACC input pin to reduce factory programming time

Support for Common Flash Interface (CFI)

Industrial Temperature range (contact factory)

— Continuous sequential read mode

Secured Silicon Sector region consisting of 128

words each for factory and customer

20-year data retention (typical)

Cycling Endurance: 100,000 cycles per sector

(typical)

RDY output indicates data available to system

Command set compatible with JEDEC (42.4)

standard

Performance Characteristics

Read Access Times

Current Consumption (typical values)

Speed Option (MHz)

Max. Synch. Latency, ns (t

80

66

80

54

80

Continuous Burst Read @ 66 MHz

35 mA

50 mA

19 mA

20 µA

)

Simultaneous Operation (asynchronous)

Program (asynchronous)

IACC

Max. Synch. Burst Access, ns (t

)

9

11.2

80

13.5

80

BACC

Max. Asynch. Access Time, ns (t

)

80

Erase (asynchronous)

ACC

Max CE# Access Time, ns (t

)

80

Standby Mode (asynchronous)

CE

Max OE# Access Time, ns (t

)

13.5

OE

Typical Program & Erase Times

Single Word Programming

Effective Write Buffer Programming (V ) Per Word

40 µs

9.4 µs

6 µs

CC

Effective Write Buffer Programming (V

Sector Erase (16 Kword Sector)

Sector Erase (64 Kword Sector)

) Per Word

ACC

150 ms

600 ms

Publication Number S70WS512N00_00 Revision A Amendment 0 Issue Date March 14, 2005

A d v a n c e I n f o r m a t i o n

6 Additional Resources

Visit www.amd.com and www.fujitsu.com to obtain the following related documents:

Application Notes

Using the Operation Status Bits in AMD Devices

Understanding Burst Mode Flash Memory Devices

Simultaneous Read/Write vs. Erase Suspend/Resume

MirrorBit™ Flash Memory Write Buffer Programming and Page Buffer Read

Design-In Scalable Wireless Solutions with Spansion Products

Common Flash Interface Version 1.4 Vendor Specific Extensions

Specification Bulletins

Contact your local sales office for details.

Drivers and Software Support

Spansion low-level drivers

Enhanced Flash drivers

Flash file system

CAD Modeling Support

VHDL and Verilog

IBIS

ORCAD

Technical Support

Contact your local sales office or contact Spansion LLC directly for additional technical support:

Email

US and Canada: HW.support@amd.com

Asia Pacific: asia.support@amd.com

Europe, Middle East, and Africa

Japan: http://edevice.fujitsu.com/jp/support/tech/#b7

Frequently Asked Questions (FAQ)

http://ask.amd.com/

http://edevice.fujitsu.com/jp/support/tech/#b7

Phone

US: (408) 749-5703

Japan (03) 5322-3324

Spansion LLC Locations

915 DeGuigne Drive, P.O. Box 3453

Sunnyvale, CA 94088-3453, USA

Telephone: 408-962-2500 or

1-866-SPANSION

Spansion Japan Limited

4-33-4 Nishi Shinjuku, Shinjuku-ku

Tokyo, 160-0023

Telephone: +81-3-5302-2200

Facsimile: +81-3-5302-2674

http://www.spansion.com

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7 Product Overview

The S29WS-N family consists of 256, 128 and 64Mbit, 1.8 volts-only, simultaneous read/write

burst mode Flash device optimized for today’s wireless designs that demand a large storage array,

rich functionality, and low power consumption.

These devices are organized in 16, 8 or 4 Mwords of 16 bits each and are capable of continuous,

synchronous (burst) read or linear read (8-, 16-, or 32-word aligned group) with or without wrap

around. These products also offer single word programming or a 32-word buffer for programming

with program/erase and suspend functionality. Additional features include:

Advanced Sector Protection methods for protecting sectors as required

256 words of Secured Silicon area for storing customer and factory secured information. The

Secured Silicon Sector is One Time Programmable.

7.1

Memory Map

The S29WS256/128/064N Mbit devices consist of 16 banks organized as shown in Tables

Table 7.1, Table 7.2, and Table 7.3.

Table 7.1 S29WS256N Sector & Memory Address Map

Bank Sector Sector Size

Sector/

Sector Range

Bank

Address Range

Notes

Size Count

(KB)

SA000

000000h–003FFFh

SA001

004000h–007FFFh

Contains four smaller sectors at

bottom of addressable memory.

4

32

2 MB

0

SA002

008000h–00BFFFh

SA003

00C000h–00FFFFh

15

128

SA004 to SA018

SA019 to SA034

SA035 to SA050

SA051 to SA066

SA067 to SA082

SA083 to SA098

SA099 to SA114

SA115 to SA130

SA131 to SA146

SA147 to SA162

SA163 to SA178

SA179 to SA194

SA195 to SA210

SA211 to SA226

SA227 to SA242

SA243 to SA257

SA258

010000h–01FFFFh to 0F0000h–0FFFFFh

100000h–10FFFFh to 1F0000h–1FFFFFh

200000h–20FFFFh to 2F0000h–2FFFFFh

300000h–30FFFFh to 3F0000h–3FFFFFh

400000h–40FFFFh to 4F0000h–4FFFFFh

500000h–50FFFFh to 5F0000h–5FFFFFh

600000h–60FFFFh to 6F0000h–6FFFFFh

700000h–70FFFFh to 7F0000h–7FFFFFh

800000h–80FFFFh to 8F0000h–8FFFFFh

900000h–90FFFFh to 9F0000h–9FFFFFh

A00000h–A0FFFFh to AF0000h–AFFFFFh

B00000h–B0FFFFh to BF0000h–BFFFFFh

C00000h–C0FFFFh to CF0000h–CFFFFFh

D00000h–D0FFFFh to DF0000h–DFFFFFh

E00000h–E0FFFFh to EF0000h–EFFFFFh

F00000h–F0FFFFh to FE0000h–FEFFFFh

FF0000h–FF3FFFh

2 MB

16

15

1

2

3

4

5

6

All 128 KB sectors.

Pattern for sector address

range is xx0000h–xxFFFFh.

(see note)

7

8

9

10

11

12

13

14

2 MB

15

SA259

FF4000h–FF7FFFh

Contains four smaller sectors

at top of addressable memory.

4

32

SA260

FF8000h–FFBFFFh

SA261

FFC000h–FFFFFFh

Note: This table has been condensed to show sector-related information for an entire device on a single page.

Sectors and their address ranges that are not explicitly listed (such as SA005–SA017) have sector

starting and ending addresses that form the same pattern as all other sectors of that size. For example,

all 128 KB sectors have the pattern xx00000h–xxFFFFh.

March 14, 2005 S70WS512N00_00_A0

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A d v a n c e I n f o r m a t i o n

Table 7.2 S29WS128N Sector & Memory Address Map

Bank Sector Sector Size

Sector/

Sector Range

Bank

Address Range

Notes

Size Count

(KB)

32

SA000

000000h–003FFFh

32

SA001

004000h–007FFFh

Contains four smaller sectors at

bottom of addressable memory.

4

1 MB

32

0

SA002

008000h–00BFFFh

32

SA003

00C000h–00FFFFh

7

128

32

SA004 to SA010

SA011 to SA018

SA019 to SA026

SA027 to SA034

SA035 to SA042

SA043 to SA050

SA051 to SA058

SA059 to SA066

SA067 to SA074

SA075 to SA082

SA083 to SA090

SA091 to SA098

SA099 to SA106

SA107 to SA114

SA115 to SA122

SA123 to SA129

SA130

010000h–01FFFFh to 070000h–07FFFFh

080000h–08FFFFh to 0F0000h–0FFFFFh

100000h–10FFFFh to 170000h–17FFFFh

180000h–18FFFFh to 1F0000h–1FFFFFh

200000h–20FFFFh to 270000h–27FFFFh

280000h–28FFFFh to 2F0000h–2FFFFFh

300000h–30FFFFh to 370000h–37FFFFh

380000h–38FFFFh to 3F0000h–3FFFFFh

400000h–40FFFFh to 470000h–47FFFFh

480000h–48FFFFh to 4F0000h–4FFFFFh

500000h–50FFFFh to 570000h–57FFFFh

580000h–58FFFFh to 5F0000h–5FFFFFh

600000h–60FFFFh to 670000h–67FFFFh

680000h–68FFFFh to 6F0000h–6FFFFFh

700000h–70FFFFh to 770000h–77FFFFh

780000h–78FFFFh to 7E0000h–7EFFFFh

7F0000h–7F3FFFh

1 MB

8

7

1

2

3

4

5

6

All 128 KB sectors.

Pattern for sector

address range is

xx0000h–xxFFFFh.

(See Note)

7

8

9

10

11

12

13

14

1 MB

32

15

SA131

7F4000h–7F7FFFh

Contains four smaller sectors

at top of addressable memory.

4

32

SA132

7F8000h–7FBFFFh

32

SA133

7FC000h–7FFFFFh

Note: This table has been condensed to show sector-related information for an entire device on a single page.

Sectors and their address ranges that are not explicitly listed (such as SA005–SA009) have sector

starting and ending addresses that form the same pattern as all other sectors of that size. For example,

all 128 KB sectors have the pattern xx00000h–xxFFFFh.

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Table 7.3 S29WS064N Sector & Memory Address Map

Bank Sector Sector Size

Sector/

Sector Range

Bank

Address Range

Notes

Size

Count

(KB)

SA000

SA001

000000h–003FFFh

004000h–007FFFh

Contains four smaller sectors

at bottom of addressable memory.

4

32

SA002

008000h–00BFFFh

0.5 MB

0

SA003

00C000h–00FFFFh

SA004

010000h–01FFFFh

3

128

SA005

020000h–02FFFFh

SA006

030000h–03FFFFh

0.5 MB

4

128

1

2

SA007–SA010

SA011–SA014

SA015–SA018

SA019–SA022

SA023–SA026

SA027–SA030

SA031–SA034

SA035–SA038

SA039–SA042

SA043–SA046

SA047–SA050

SA051–SA054

SA055–SA058

SA059–SA062

SA063

040000h–04FFFFh to 070000h–07FFFFh

080000h–08FFFFh to 0B0000h–0BFFFFh

0C0000h–0CFFFFh to 0F0000h–0FFFFFh

100000h–10FFFFh to 130000h–13FFFFh

140000h–14FFFFh to 170000h–17FFFFh

180000h–18FFFFh to 1B0000h–1BFFFFh

1C0000h–1CFFFFh to 1F0000h–1FFFFFh

200000h–20FFFFh to 230000h–23FFFFh

240000h–24FFFFh to 270000h–27FFFFh

280000h–28FFFFh to 2B0000h–2BFFFFh

2C0000h–2CFFFFh to 2F0000h–2FFFFFh

300000h–30FFFFh to 330000h–33FFFFh

340000h–34FFFFh to 370000h–37FFFFh

380000h–38FFFFh to 3B0000h–3BFFFFh

3C0000h–3CFFFFh

3

4

5

6

All 128 KB sectors.

Pattern for sector

address range is

xx0000h–xxFFFFh.

(see note)

7

8

9

10

11

12

13

14

3

128

SA064

3D0000h–3DFFFFh

SA065

3E0000h–3EFFFFh

0.5 MB

15

SA066

3F0000h–3F3FFFh

SA067

3F4000h–3F7FFFh

Contains four smaller sectors a

t top of addressable memory.

4

32

SA068

3F8000h–3FBFFFh

SA069

3FC000h–3FFFFFh

Note: This table has been condensed to show sector-related information for an entire device on a single page.

Sectors and their address ranges that are not explicitly listed (such as SA008–SA009) have sector

starting and ending addresses that form the same pattern as all other sectors of that size. For example,

all 128 KB sectors have the pattern xx00000h–xxFFFFh.

March 14, 2005 S70WS512N00_00_A0

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A d v a n c e I n f o r m a t i o n

8 Device Operations

This section describes the read, program, erase, simultaneous read/write operations, handshak-

ing, and reset features of the Flash devices.

Operations are initiated by writing specific commands or a sequence with specific address and

data patterns into the command registers (see Table 13.1 and Table 13.2). The command regis-

ter itself does not occupy any addressable memory location; rather, it is composed of latches that

store the commands, along with the address and data information needed to execute the com-

mand. The contents of the register serve as input to the internal state machine and the state

machine outputs dictate the function of the device. Writing incorrect address and data values or

writing them in an improper sequence may place the device in an unknown state, in which case

the system must write the reset command to return the device to the reading array data mode.

8.1

Device Operation Table

The device must be setup appropriately for each operation. Table 8.1 describes the required state

of each control pin for any particular operation.

Table 8.1 Device Operations

Operation

CE# OE#

WE#

Addresses

Addr In

X

DQ15–0

Data Out

I/O

RESET#

CLK

X

AVD#

Asynchronous Read - Addresses Latched

Asynchronous Read - Addresses Steady State

Asynchronous Write

L

H

L

H

L

X

L

H

X

Synchronous Write

L

I/O

Standby (CE#)

H

X

HIGH Z

X

Hardware Reset

X

Burst Read Operations (Synchronous)

Load Starting Burst Address

L

X

L

H

Addr In

X

H

Advance Burst to next address with appropriate Data

presented on the Data Bus

Burst

Data Out

H

Terminate current Burst read cycle

H

X

H

X

HIGH Z

H

L

X

Terminate current Burst read cycle via RESET#

X

Terminate current Burst read cycle and start new Burst

read cycle

L

X

H

Addr In

I/O

H

Legend: L = Logic 0, H = Logic 1, X = Don’t Care, I/O = Input/Output.

8.2 Asynchronous Read

All memories require access time to output array data. In an asynchronous read operation, data

is read from one memory location at a time. Addresses are presented to the device in random

order, and the propagation delay through the device causes the data on its outputs to arrive asyn-

chronously with the address on its inputs.

The device defaults to reading array data asynchronously after device power-up or hardware re-

set. Asynchronous read requires that the CLK signal remain at V_ILduring the entire memory read

operation. To read data from the memory array, the system must first assert a valid address on

A_max–A0, while driving AVD# and CE# to V_IL. WE# must remain at V_IH. The rising edge of AVD#

latches the address. The OE# signal must be driven to V_IL, once AVD# has been driven to V_IH.

Data is output on A/DQ15-A/DQ0 pins after the access time (t_OE) has elapsed from the falling

edge of OE#.

22

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A d v a n c e I n f o r m a t i o n

8.3 Synchronous (Burst) Read Mode and Configuration Register

When a series of adjacent addresses needs to be read from the device (in order from lowest to

highest address), the synchronous (or burst read) mode can be used to significantly reduce the

overall time needed for the device to output array data. After an initial access time required for

the data from the first address location, subsequent data is output synchronized to a clock input

provided by the system.

The device offers both continuous and linear methods of burst read operation, which are dis-

cussed in sections 8.3.1, 8.3.2, and 8.3.3.

Since the device defaults to asynchronous read mode after power-up or a hardware reset, the

configuration register must be set to enable the burst read mode. Other Configuration Register

settings include the number of wait states to insert before the initial word (t_IACC) of each burst

access, the burst mode in which to operate, and when RDY indicates data is ready to be read.

Prior to entering the burst mode, the system should first determine the configuration register set-

tings (and read the current register settings if desired via the Read Configuration Register

command sequence), and then write the configuration register command sequence. See 8.3.4

and Table 13.1 for further details.

Power-up/

Hardware Reset

Asynchronous Read

Mode Only

Set Burst Mode

Configuration Register

Command for

Set Burst Mode

Configuration Register

Command for

Synchronous Mode

(CR15 = 0)

Asynchronous Mode

(CR15 = 1)

Synchronous Read

Mode Only

Figure 8.1 Synchronous/Asynchronous State Diagram

The device outputs the initial word subject to the following operational conditions:

t_IACCspecification: the time from the rising edge of the first clock cycle after addresses are

latched to valid data on the device outputs.

Configuration register setting CR13–CR11: the total number of clock cycles (wait states)

that occur before valid data appears on the device outputs. The effect is that t_IACCis

lengthened.

The device outputs subsequent words t_BACCafter the active edge of each successive clock cycle,

which also increments the internal address counter. The device outputs burst data at this rate sub-

ject to the following operational conditions:

March 14, 2005 S70WS512N00_00_A0

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A d v a n c e I n f o r m a t i o n

Starting address: whether the address is divisible by four (where A[1:0] is 00). A divisible-

by-four address incurs the least number of additional wait states that occur after the initial

word. The number of additional wait states required increases for burst operations in which

the starting address is one, two, or three locations above the divisible-by-four address (i.e.,

where A[1:0] is 01, 10, or 11).

Boundary crossing: There is a boundary at every 128 words due to the internal architecture

of the device. One additional wait state must be inserted when crossing this boundary if the

memory bus is operating at a high clock frequency. Please refer to the tables below.

Clock frequency: the speed at which the device is expected to burst data. Higher speeds

require additional wait states after the initial word for proper operation.

In all cases, with or without latency, the RDY output indicates when the next data is available to

be read.

Tables 8.2 – 8.6 reflect wait states required for S29WS256/128/064N devices. Refer to the Con-

figuration Register table (CR11 – CR14) and timing diagrams for more details.

Table 8.2 Address Latency (S29WS256N)

Word

Wait States

x ws

Cycle

D4

0

1

2

3

D0

D1

D2

D3

D1

D2

D3

D5

D6

D7

D8

x ws

1 ws

D4

x ws

D3

1 ws

D4

x ws

1 ws

D4

Table 8.3 Address Latency (S29WS128N/S29WS064N)

Word

Wait States

Cycle

D4

0

1

2

3

5, 6, 7 ws

D0

D1

D2

D3

D1

D2

D3

D5

D6

D7

D8

1 ws

D4

D3

1 ws

D4

1 ws

D4

Table 8.4 Address/Boundary Crossing Latency (S29WS256N @ 80/66 MHz)

Word

Wait States

7, 6 ws

Cycle

1 ws

0

1

2

3

D0

D1

D2

D3

D1

D2

D3

D4

D5

D6

D7

7, 6 ws

1 ws

7, 6 ws

D3

1 ws

7, 6 ws

1 ws

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A d v a n c e I n f o r m a t i o n

Table 8.5 Address/Boundary Crossing Latency (S29WS256N @ 54MHz)

Word

Wait States

5 ws

Cycle

D4

0

1

2

3

D0

D1

D2

D3

D1

D2

D3

D5

D6

D7

D8

5 ws

1 ws

D4

5 ws

D3

1 ws

D4

5 ws

1 ws

D4

Table 8.6 Address/Boundary Crossing Latency (S29WS128N/S29WS064N)

Word

Wait States

5, 6, 7 ws

Cycle

1 ws

0

1

2

3

D0

D1

D2

D3

D1

D2

D3

D4

D5

D6

D7

1 ws

D3

1 ws

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A d v a n c e I n f o r m a t i o n

Note: Setup Configuration Register parameters

Write Unlock Cycles:

Address 555h, Data AAh

Address 2AAh, Data 55h

Unlock Cycle 1

Unlock Cycle 2

Write Set Configuration Register

Command and Settings:

Address 555h, Data D0h

Address X00h, Data CR

Command Cycle

CR = Configuration Register Bits CR15-CR0

Load Initial Address

Address = RA

RA = Read Address

CR13-CR11 sets initial access time

(from address latched to

valid data) from 2 to 7 clock cycles

Wait t_IACC

Programmable Wait State Setting

+

Read Initial Data

RD = DQ[15:0]

RD = Read Data

Wait X Clocks:

Additional Latency Due to Starting

Address, Clock Frequency, and

Boundary Crossing

Read Next Data

RD = DQ[15:0]

Delay X Clocks

Crossing

Boundary?

No

End of Data?

Yes

Completed

Figure 8.2 Synchronous Read

Continuous Burst Read Mode

8.3.1

In the continuous burst read mode, the device outputs sequential burst data from the starting

address given and then wrap around to address 000000h when it reaches the highest addressable

memory location. The burst read mode continues until the system drives CE# high, or RESET=

V_IL. Continuous burst mode can also be aborted by asserting AVD# low and providing a new ad-

dress to the device.

If the address being read crosses a 128-word line boundary (as mentioned above) and the sub-

sequent word line is not being programmed or erased, additional latency cycles are required as

reflected by the configuration register table (Table 8.8).

If the address crosses a bank boundary while the subsequent bank is programming or erasing,

the device provides read status information and the clock is ignored. Upon completion of status

read or program or erase operation, the host can restart a burst read operation using a new ad-

dress and AVD# pulse.

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8.3.2

8-, 16-, 32-Word Linear Burst Read with Wrap Around

In a linear burst read operation, a fixed number of words (8, 16, or 32 words) are read from con-

secutive addresses that are determined by the group within which the starting address falls. The

groups are sized according to the number of words read in a single burst sequence for a given

mode (see Table 8.7).

For example, if the starting address in the 8-word mode is 3Ch, the address range to be read

would be 38-3Fh, and the burst sequence would be 3C-3D-3E-3F-38-39-3A-3Bh. Thus, the device

outputs all words in that burst address group until all word are read, regardless of where the start-

ing address occurs in the address group, and then terminates the burst read.

In a similar fashion, the 16-word and 32-word Linear Wrap modes begin their burst sequence on

the starting address provided to the device, then wrap back to the first address in the selected

address group.

Note that in this mode the address pointer does not cross the boundary that occurs every 128

words; thus, no additional wait states are inserted due to boundary crossing.

Table 8.7 Burst Address Groups

Mode

Group Size

8 words

Group Address Ranges

0-7h, 8-Fh, 10-17h,...

0-Fh, 10-1Fh, 20-2Fh,...

00-1Fh, 20-3Fh, 40-5Fh,...

8-word

16-word

32-word

16 words

32 words

8.3.3

8-, 16-, 32-Word Linear Burst without Wrap Around

If wrap around is not enabled for linear burst read operations, the 8-word, 16-word, or 32-word

burst executes up to the maximum memory address of the selected number of words. The burst

stops after 8, 16, or 32 addresses and does not wrap around to the first address of the selected

group.

For example, if the starting address in the 8- word mode is 3Ch, the address range to be read

would be 39-40h, and the burst sequence would be 3C-3D-3E-3F-40-41-42-43h if wrap around

is not enabled. The next address to be read requires a new address and AVD# pulse. Note that

in this burst read mode, the address pointer may cross the boundary that occurs every 128 words,

which will incur the additional boundary crossing wait state.

8.3.4

Configuration Register

The configuration register sets various operational parameters associated with burst mode. Upon

power-up or hardware reset, the device defaults to the asynchronous read mode, and the config-

uration register settings are in their default state. The host system should determine the proper

settings for the entire configuration register, and then execute the Set Configuration Register

command sequence, before attempting burst operations. The configuration register is not reset

after deasserting CE#. The Configuration Register can also be read using a command sequence

(see Table 13.1). The following list describes the register settings.

March 14, 2005 S70WS512N00_00_A0

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Table 8.8 Configuration Register

CR Bit

Function

Settings (Binary)

Set Device Read

Mode

0 = Synchronous Read (Burst Mode) Enabled

1 = Asynchronous Read Mode (default) Enabled

CR15

54 MHz 66 Mhz 80 MHz

S29WS064N

S29WS128N

N/A

0

N/A

1

N/A

1

Default value is 0

CR14 Boundary Crossing

0 = No extra boundary crossing latency

1 = With extra boundary crossing latency (default)

Must be set to 1 greater than 54 MHz.

S29WS256N

S29WS064N

S29WS128N

011 = Data valid on 5th active CLK

edge after addresses latched

100 = Data valid on 6th active CLK

edge after addresses latched

CR13

0

1

0

1

0

1

S29WS256N

101 = Data valid on 7th active CLK

edge after addresses latched (default)

110 = Reserved

S29WS064N

S29WS128N

Programmable

CR12

Wait State

S29WS256N

111 = Reserved

Inserts wait states before initial data

is available. Setting greater number of wait

states before initial data reduces latency

after initial data. (Notes 1, 2)

S29WS064N

S29WS128N

CR11

S29WS256N

0 = RDY signal active low

CR10

CR9

RDY Polarity

Reserved

1 = RDY signal active high (default)

1 = default

0 = RDY active one clock cycle before data

1 = RDY active with data (default)

When CR13-CR11 are set to 000,

CR8

RDY

RDY is active with data regardless of CR8 setting.

CR7

CR6

CR5

CR4

Reserved

1 = default

0 = default

0 = No Wrap Around Burst

1 = Wrap Around Burst (default)

CR3

Burst Wrap Around

000 = Continuous (default)

010 = 8-Word Linear Burst

011 = 16-Word Linear Burst

100 = 32-Word Linear Burst

(All other bit settings are reserved)

CR2

CR1

CR0

Burst Length

Notes:

1. Refer to Tables 8.2 - 8.6 for wait states requirements.

2. Refer to Synchronous Burst Read timing diagrams

3. Configuration Register is in the default state upon power-up or hardware reset.

Reading the Configuration Table. The configuration register can be read with a four-cycle com-

mand sequence. See Table 13.1 for sequence details. Once the data has been read from the

configuration register, a software reset command is required to set the device into the correct

state.

8.4 Autoselect

The Autoselect is used for manufacturer ID, Device identification, and sector protection informa-

tion. This mode is primarily intended for programming equipment to automatically match a device

with its corresponding programming algorithm. The Autoselect codes can also be accessed in-sys-

tem. When verifying sector protection, the sector address must appear on the appropriate highest

order address bits (see Table 8.9). The remaining address bits are don't care. The most significant

four bits of the address during the third write cycle selects the bank from which the Autoselect

codes are read by the host. All other banks can be accessed normally for data read without exiting

the Autoselect mode.

To access the Autoselect codes, the host system must issue the Autoselect command.

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The Autoselect command sequence may be written to an address within a bank that is either

in the read or erase-suspend-read mode.

The Autoselect command may not be written while the device is actively programming or

erasing. Autoselect does not support simultaneous operations or burst mode.

The system must write the reset command to return to the read mode (or erase-suspend-

read mode if the bank was previously in Erase Suspend).

See Table 13.1 for command sequence details.

Table 8.9 Autoselect Addresses

Description

Manufacturer ID

Device ID, Word 1

Address

Read Data

(BA) + 00h 0001h

(BA) + 01h 227Eh

2230 (WS256N)

Device ID, Word 2

Device ID, Word 3

(BA) + 0Eh 2231 (WS128N)

2232 (WS064N)

(BA) + 0Fh 2200

DQ15 - DQ8 = Reserved

DQ7 (Factory Lock Bit): 1 = Locked, 0 = Not Locked

DQ6 (Customer Lock Bit): 1 = Locked, 0 = Not Locked

DQ5 (Handshake Bit): 1 = Reserved, 0 = Standard Handshake

DQ4, DQ3 (WP# Protection Boot Code): 00 = WP# Protects both Top Boot and

Bottom Boot Sectors. 01, 10, 11 = Reserved

Indicator Bits

(See Note)

(BA) + 03h

DQ2 = Reserved

DQ1 (DYB Power up State [Lock Register DQ4]): 1 = Unlocked (user option),

0 = Locked (default)

DQ0 (PPB Eraseability [Lock Register DQ3]): 1 = Erase allowed,

0 = Erase disabled

Sector Block Lock/

Unlock

(SA) + 02h 0001h = Locked, 0000h = Unlocked

Note: For WS128N and WS064, DQ1 and DQ0 are reserved.

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Software Functions and Sample Code

Table 8.10 Autoselect Entry

(LLD Function = lld_AutoselectEntryCmd)

Cycle

Operation

Write

Byte Address

BAxAAAh

BAx555h

Word Address

BAx555h

Data

Unlock Cycle 1

Unlock Cycle 2

Autoselect Command

0x00AAh

0x0055h

0x0090h

Write

BAx2AAh

Write

BAxAAAh

BAx555h

Table 8.11 Autoselect Exit

(LLD Function = lld_AutoselectExitCmd)

Cycle

Operation

Write

Byte Address

Word Address

base + XXXh

Data

Unlock Cycle 1

base + XXXh

0x00F0h

Notes:

1. Any offset within the device works.

2. BA = Bank Address. The bank address is required.

3. base = base address.

The following is a C source code example of using the autoselect function to read the manu-

facturer ID. Refer to the Spansion Low Level Driver User Guide (available on www.amd.com

and www.fujitsu.com) for general information on Spansion Flash memory software develop-

ment guidelines.

/* Here is an example of Autoselect mode (getting manufacturer ID) */

/* Define UINT16 example: typedef unsigned short UINT16; */

UINT16 manuf_id;

/* Auto Select Entry */

*( (UINT16 *)bank_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */

*( (UINT16 *)bank_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */

*( (UINT16 *)bank_addr + 0x555 ) = 0x0090; /* write autoselect command */

/* multiple reads can be performed after entry */

manuf_id = *( (UINT16 *)bank_addr + 0x000 ); /* read manuf. id */

/* Autoselect exit */

*( (UINT16 *)base_addr + 0x000 ) = 0x00F0; /* exit autoselect (write reset command) */

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8.5 Program/Erase Operations

These devices are capable of several modes of programming and or erase operations which are

described in detail in the following sections. However, prior to any programming and or erase op-

eration, devices must be setup appropriately as outlined in the configuration register (Table 8.8).

For any program and or erase operations, including writing command sequences, the system

must drive AVD# and CE# to V_IL, and OE# to V_IHwhen providing an address to the device, and

drive WE# and CE# to V_IL, and OE# to V_IHwhen writing commands or programming data.

Addresses are latched on the last falling edge of WE# or CE#, while data is latched on the 1st

rising edge of WE# or CE#.

Note the following:

When the Embedded Program algorithm is complete, the device returns to the read mode.

The system can determine the status of the program operation by using DQ7 or DQ6. Refer

to the Write Operation Status section for information on these status bits.

A 0 cannot be programmed back to a 1. Attempting to do so causes the device to set DQ5 = 1

(halting any further operation and requiring a reset command). A succeeding read shows that

the data is still 0. Only erase operations can convert a 0 to a 1.

Any commands written to the device during the Embedded Program Algorithm are ignored

except the Program Suspend command.

Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a program oper-

ation is in progress.

A hardware reset immediately terminates the program operation and the program command

sequence should be reinitiated once the device has returned to the read mode, to ensure data

integrity.

Programming is allowed in any sequence and across sector boundaries for single word pro-

gramming operation.

8.5.1

Single Word Programming

Single word programming mode is the simplest method of programming. In this mode, four Flash

command write cycles are used to program an individual Flash address. The data for this pro-

gramming operation could be 8-, 16- or 32-bits wide. While this method is supported by all

Spansion devices, in general it is not recommended for devices that support Write Buffer Pro-

gramming. See Table 13.1 for the required bus cycles and Figure 8.3 for the flowchart.

When the Embedded Program algorithm is complete, the device then returns to the read mode

and addresses are no longer latched. The system can determine the status of the program oper-

ation by using DQ7 or DQ6. Refer to the Write Operation Status section for information on these

status bits.

During programming, any command (except the Suspend Program command) is ignored.

The Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a program op-

eration is in progress.

A hardware reset immediately terminates the program operation. The program command se-

quence should be reinitiated once the device has returned to the read mode, to ensure data

integrity.

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Write Unlock Cycles:

Address 555h, Data AAh

Address 2AAh, Data 55h

Unlock Cycle 1

Unlock Cycle 2

Write Program Command:

Address 555h, Data A0h

Setup Command

Program Address (PA),

Program Data (PD)

Program Data to Address:

PA, PD

Perform Polling Algorithm

(see Write Operation Status

flowchart)

Yes

Polling Status

= Busy?

No

Yes

Polling Status

= Done?

Error condition

(Exceeded Timing Limits)

No

PASS. Device is in

read mode.

FAIL. Issue reset command

to return to read array mode.

Figure 8.3 Single Word Program

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Software Functions and Sample Code

Table 8.12 Single Word Program

(LLD Function = lld_ProgramCmd)

Cycle

Operation

Write

Byte Address

Base + AAAh

Base + 554h

Base + AAAh

Word Address

Base + 555h

Base + 2AAh

Base + 555h

Word Address

Data

00AAh

Unlock Cycle 1

Unlock Cycle 2

Program Setup

Program

Write

0055h

Write

00A0h

Write

Data Word

Note: Base = Base Address.

The following is a C source code example of using the single word program function. Refer to

the Spansion Low Level Driver User’s Guide (available on www.amd.com and

www.fujitsu.com) for general information on Spansion Flash memory software development

guidelines.

/* Example: Program Command

*/

*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;

*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;

*( (UINT16 *)base_addr + 0x555 ) = 0x00A0;

/* write unlock cycle 1

/* write unlock cycle 2

/* write program setup command

/* write data to be programmed

*/

*( (UINT16 *)pa )

= data;

/* Poll for program completion */

8.5.2

Write Buffer Programming

Write Buffer Programming allows the system to write a maximum of 32 words in one program-

ming operation. This results in a faster effective word programming time than the standard word

programming algorithms. The Write Buffer Programming command sequence is initiated by first

writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load

command written at the Sector Address in which programming occurs. At this point, the system

writes the number of word locations minus 1 that are loaded into the page buffer at the Sector

Address in which programming occurs. This tells the device how many write buffer addresses are

loaded with data and therefore when to expect the Program Buffer to Flash confirm command.

The number of locations to program cannot exceed the size of the write buffer or the operation

aborts. (Number loaded = the number of locations to program minus 1. For example, if the sys-

tem programs 6 address locations, then 05h should be written to the device.)

The system then writes the starting address/data combination. This starting address is the first

address/data pair to be programmed, and selects the write-buffer-page address. All subsequent

address/data pairs must fall within the elected-write-buffer-page.

The write-buffer-page is selected by using the addresses A_MAX- A5.

The write-buffer-page addresses must be the same for all address/data pairs loaded into the write

buffer. (This means Write Buffer Programming cannot be performed across multiple write-buffer-

pages. This also means that Write Buffer Programming cannot be performed across multiple sec-

tors. If the system attempts to load programming data outside of the selected write-buffer-page,

the operation ABORTs.)

After writing the Starting Address/Data pair, the system then writes the remaining address/data

pairs into the write buffer.

Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter

is decremented for every data load operation. Also, the last data loaded at a location before the

Program Buffer to Flash confirm command is programmed into the device. It is the software's re-

sponsibility to comprehend ramifications of loading a write-buffer location more than once. The

March 14, 2005 S70WS512N00_00_A0

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A d v a n c e I n f o r m a t i o n

counter decrements for each data load operation, NOT for each unique write-buffer-address loca-

tion. Once the specified number of write buffer locations have been loaded, the system must then

write the Program Buffer to Flash command at the Sector Address. Any other address/data write

combinations abort the Write Buffer Programming operation. The device goes busy. The Data Bar

polling techniques should be used while monitoring the last address location loaded into the write

buffer. This eliminates the need to store an address in memory because the system can load the

last address location, issue the program confirm command at the last loaded address location,

and then data bar poll at that same address. DQ7, DQ6, DQ5, DQ2, and DQ1 should be monitored

to determine the device status during Write Buffer Programming.

The write-buffer embedded programming operation can be suspended using the standard sus-

pend/resume commands. Upon successful completion of the Write Buffer Programming operation,

the device returns to READ mode.

The Write Buffer Programming Sequence is ABORTED under any of the following conditions:

Load a value that is greater than the page buffer size during the Number of Locations to Pro-

gram step.

Write to an address in a sector different than the one specified during the Write-Buffer-Load

command.

Write an Address/Data pair to a different write-buffer-page than the one selected by the

Starting Address during the write buffer data loading stage of the operation.

Write data other than the Confirm Command after the specified number of data load cycles.

The ABORT condition is indicated by DQ1 = 1, DQ7 = Data# (for the last address location loaded),

DQ6 = TOGGLE, DQ5 = 0. This indicates that the Write Buffer Programming Operation was

ABORTED. A Write-to-Buffer-Abort reset command sequence is required when using the write

buffer Programming features in Unlock Bypass mode. Note that the Secured Silicon sector, au-

toselect, and CFI functions are unavailable when a program operation is in progress.

Write buffer programming is allowed in any sequence of memory (or address) locations. These

flash devices are capable of handling multiple write buffer programming operations on the same

write buffer address range without intervening erases.

Use of the write buffer is strongly recommended for programming when multiple words are to be

programmed. Write buffer programming is approximately eight times faster than programming

one word at a time.

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Software Functions and Sample Code

Table 8.13 Write Buffer Program

(LLD Functions Used = lld_WriteToBufferCmd, lld_ProgramBufferToFlashCmd)

Cycle

Description

Unlock

Operation

Write

Byte Address

Base + AAAh

Base + 554h

Word Address

Base + 555h

Base + 2AAh

Data

00AAh

1

2

3

4

Unlock

Write

0055h

Write Buffer Load Command

Write Word Count

Write

Program Address

0025h

Write

Word Count (N–1)h

Number of words (N) loaded into the write buffer can be from 1 to 32 words.

5 to 36

Last

Load Buffer Word N

Write Buffer to Flash

Write

Program Address, Word N

Sector Address

Word N

0029h

Notes:

1. Base = Base Address.

2. Last = Last cycle of write buffer program operation; depending on number of words written, the total

number of cycles may be from 6 to 37.

3. For maximum efficiency, it is recommended that the write buffer be loaded with

the highest number of words (N words) possible.

The following is a C source code example of using the write buffer program function. Refer to

the Spansion Low Level Driver User Guide (available on www.amd.com and

www.fujitsu.comm) for general information on Spansion Flash memory software develop-

ment guidelines.

/* Example: Write Buffer Programming Command

*/

/* NOTES: Write buffer programming limited to 16 words. */

/*

All addresses to be written to the flash in

one operation must be within the same flash

page. A flash page begins at addresses

evenly divisible by 0x20.

*/

UINT16 *src = source_of_data;

UINT16 *dst = destination_of_data;

/* address of source data

/* flash destination address

/* word count (minus 1)

/* write unlock cycle 1

/* write unlock cycle 2

*/

UINT16 wc

= words_to_program -1;

*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;

*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;

*( (UINT16 *)sector_address )

= 0x0025;

= wc;

/* write write buffer load command */

/* write word count (minus 1) */

loop:

*dst = *src; /* ALL dst MUST BE SAME PAGE */ /* write source data to destination */

dst++;

src++;

/* increment destination pointer

/* increment source pointer

*/

if (wc == 0) goto confirm

wc--;

goto loop;

/* done when word count equals zero */

/* decrement word count

/* do it again

*/

confirm:

*( (UINT16 *)sector_address )

/* poll for completion */

= 0x0029;

/* write confirm command

*/

/* Example: Write Buffer Abort Reset */

*( (UINT16 *)addr + 0x555 ) = 0x00AA;

*( (UINT16 *)addr + 0x2AA ) = 0x0055;

*( (UINT16 *)addr + 0x555 ) = 0x00F0;

/* write unlock cycle 1

/* write unlock cycle 2

/* write buffer abort reset

*/

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Write Unlock Cycles:

Address 555h, Data AAh

Address 2AAh, Data 55h

Unlock Cycle 1

Unlock Cycle 2

Issue

Write Buffer Load Command:

Address 555h, Data 25h

Load Word Count to Program

Program Data to Address:

SA = wc

wc = number of words – 1

Yes

Confirm command:

wc = 0?

No

SA 29h

Wait 4 µs

Write Next Word,

Decrement wc:

PA data , wc = wc – 1

No

Write Buffer

Abort Desired?

Perform Polling Algorithm

(see Write Operation Status

flowchart)

Yes

Write to a Different

Sector Address to Cause

Write Buffer Abort

Yes

Polling Status

= Done?

No

Error?

Yes

No

Yes

Write Buffer

Abort?

No

RESET. Issue Write Buffer

Abort Reset Command

PASS. Device is in

read mode.

FAIL. Issue reset command

to return to read array mode.

Figure 8.4 Write Buffer Programming Operation

8.5.3

Sector Erase

The sector erase function erases one or more sectors in the memory array. (See Table 13.1 and

Figure 8.5) The device does not require the system to preprogram prior to erase. The Embedded

Erase algorithm automatically programs and verifies the entire memory for an all zero data pat-

tern prior to electrical erase. After a successful sector erase, all locations within the erased sector

contain FFFFh. The system is not required to provide any controls or timings during these

operations.

After the command sequence is written, a sector erase time-out of no less than t_SEAoccurs. Dur-

ing the time-out period, additional sector addresses and sector erase commands may be written.

Loading the sector erase buffer may be done in any sequence, and the number of sectors may be

from one sector to all sectors. The time between these additional cycles must be less than t_SEA

.

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Any sector erase address and command following the exceeded time-out (t_SEA) may or may not

be accepted. Any command other than Sector Erase or Erase Suspend during the time-out period

resets that bank to the read mode. The system can monitor DQ3 to determine if the sector erase

timer has timed out (see DQ3: Sector Erase Timeout State Indicator). The time-out begins from

the rising edge of the final WE# pulse in the command sequence.

When the Embedded Erase algorithm is complete, the bank returns to reading array data and ad-

dresses are no longer latched. Note that while the Embedded Erase operation is in progress, the

system can read data from the non-erasing banks. The system can determine the status of the

erase operation by reading DQ7 or DQ6/DQ2 in the erasing bank. See Write Operation Status for

information on these status bits.

Once the sector erase operation has begun, only the Erase Suspend command is valid. All other

commands are ignored. However, note that a hardware reset immediately terminates the erase

operation. If that occurs, the sector erase command sequence should be reinitiated once that

bank has returned to reading array data, to ensure data integrity.

Figure 8.5 illustrates the algorithm for the erase operation. See Erase/Program Timing for param-

eters and timing diagrams.

Software Functions and Sample Code

Table 8.14 Sector Erase

(LLD Function = lld_SectorEraseCmd)

Cycle

Description

Unlock

Operation

Write

Byte Address

Base + AAAh

Base + 554h

Base + AAAh

Base + 554h

Sector Address

Word Address

Base + 555h

Base + 2AAh

Base + 555h

Base + 2AAh

Sector Address

Data

1

2

3

4

5

6

00AAh

0055h

0080h

00AAh

0055h

0030h

Unlock

Write

Setup Command

Unlock

Write

Unlock

Write

Sector Erase Command

Write

Unlimited additional sectors may be selected for erase; command(s) must be written within t_SEA

.

The following is a C source code example of using the sector erase function. Refer to the

Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)

for general information on Spansion Flash memory software development guidelines.

/* Example: Sector Erase Command */

*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;

*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;

*( (UINT16 *)base_addr + 0x555 ) = 0x0080;

*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;

*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;

/* write unlock cycle 1

/* write unlock cycle 2

/* write setup command

/* write additional unlock cycle 1 */

/* write additional unlock cycle 2 */

*/

*( (UINT16 *)sector_address )

= 0x0030;

/* write sector erase command

*/

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Write Unlock Cycles:

Address 555h, Data AAh

Address 2AAh, Data 55h

Unlock Cycle 1

Unlock Cycle 2

Write Sector Erase Cycles:

Address 555h, Data 80h

Address 555h, Data AAh

Address 2AAh, Data 55h

Sector Address, Data 30h

Command Cycle 1

Command Cycle 2

Command Cycle 3

Specify first sector for erasure

Select

Additional

Sectors?

No

Yes

Write Additional

Sector Addresses

• Each additional cycle must be written within t_SEAtimeout

• Timeout resets after each additional cycle is written

• The host system may monitor DQ3 or wait t_SEAto ensure

acceptance of erase commands

Yes

Last Sector

Selected?

No

• No limit on number of sectors

Poll DQ3.

DQ3 = 1?

• Commands other than Erase Suspend or selecting

additional sectors for erasure during timeout reset device

to reading array data

No

Yes

Wait 4 µs

Perform Write Operation

Status Algorithm

Status may be obtained by reading DQ7, DQ6 and/or DQ2.

Yes

Done?

No

DQ5 = 1?

Yes

Error condition (Exceeded Timing Limits)

PASS. Device returns

to reading array.

FAIL. Write reset command

to return to reading array.

Notes:

1. See Table 13.1 for erase command sequence.

2. See the section on DQ3 for information on the sector erase timeout.

Figure 8.5 Sector Erase Operation

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8.5.4

Chip Erase Command Sequence

Chip erase is a six-bus cycle operation as indicated by Table 13.1. These commands invoke the

Embedded Erase algorithm, which does not require the system to preprogram prior to erase. The

Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all

zero data pattern prior to electrical erase. After a successful chip erase, all locations of the chip

contain FFFFh. The system is not required to provide any controls or timings during these oper-

ations. Table 13.1 and Table 13.2 in the appendix show the address and data requirements for

the chip erase command sequence.

When the Embedded Erase algorithm is complete, that bank returns to the read mode and ad-

dresses are no longer latched. The system can determine the status of the erase operation by

using DQ7 or DQ6/DQ2. See Write Operation Status for information on these status bits.

Any commands written during the chip erase operation are ignored. However, note that a hard-

ware reset immediately terminates the erase operation. If that occurs, the chip erase command

sequence should be reinitiated once that bank has returned to reading array data, to ensure data

integrity.

Software Functions and Sample Code

Table 8.15 Chip Erase

(LLD Function = lld_ChipEraseCmd)

Cycle

Description

Unlock

Operation

Write

Byte Address

Base + AAAh

Base + 554h

Base + AAAh

Base + 554h

Base + AAAh

Word Address

Base + 555h

Base + 2AAh

Base + 555h

Base + 2AAh

Base + 555h

Data

1

2

3

4

5

6

00AAh

0055h

0080h

00AAh

0055h

0010h

Unlock

Write

Setup Command

Unlock

Write

Unlock

Write

Chip Erase Command

Write

The following is a C source code example of using the chip erase function. Refer to the Span-

sion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for

general information on Spansion Flash memory software development guidelines.

/* Example: Chip Erase Command */

/* Note: Cannot be suspended

*/

*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;

*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;

*( (UINT16 *)base_addr + 0x555 ) = 0x0080;

*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;

*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;

*( (UINT16 *)base_addr + 0x000 ) = 0x0010;

/* write unlock cycle 1

/* write unlock cycle 2

/* write setup command

/* write additional unlock cycle 1 */

/* write additional unlock cycle 2 */

*/

/* write chip erase command

*/

8.5.5

Erase Suspend/Erase Resume Commands

When the Erase Suspend command is written during the sector erase time-out, the device imme-

diately terminates the time-out period and suspends the erase operation. The Erase Suspend

command allows the system to interrupt a sector erase operation and then read data from, or

program data to, any sector not selected for erasure. The bank address is required when writing

this command. This command is valid only during the sector erase operation, including the min-

imum t_SEAtime-out period during the sector erase command sequence. The Erase Suspend

command is ignored if written during the chip erase operation.

When the Erase Suspend command is written after the t_SEAtime-out period has expired and dur-

ing the sector erase operation, the device requires a maximum of t_ESL(erase suspend latency) to

suspend the erase operation.

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After the erase operation has been suspended, the bank enters the erase-suspend-read mode.

The system can read data from or program data to any sector not selected for erasure. (The de-

vice erase suspends all sectors selected for erasure.) Reading at any address within erase-

suspended sectors produces status information on DQ7-DQ0. The system can use DQ7, or DQ6,

and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to

Table 8.23 for information on these status bits.

After an erase-suspended program operation is complete, the bank returns to the erase-suspend-

read mode. The system can determine the status of the program operation using the DQ7 or DQ6

status bits, just as in the standard program operation.

In the erase-suspend-read mode, the system can also issue the Autoselect command sequence.

See Write Buffer Programming and Autoselect for details.

To resume the sector erase operation, the system must write the Erase Resume command. The

bank address of the erase-suspended bank is required when writing this command. Further writes

of the Resume command are ignored. Another Erase Suspend command can be written after the

chip has resumed erasing.

Software Functions and Sample Code

Table 8.16 Erase Suspend

(LLD Function = lld_EraseSuspendCmd)

Cycle

Operation

Byte Address

Word Address

Data

1

Write

Bank Address

00B0h

The following is a C source code example of using the erase suspend function. Refer to the

Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)

for general information on Spansion Flash memory software development guidelines.

/* Example: Erase suspend command */

*( (UINT16 *)bank_addr + 0x000 ) = 0x00B0;

/* write suspend command

*/

Table 8.17 Erase Resume

(LLD Function = lld_EraseResumeCmd)

Cycle

Operation

Byte Address

Word Address

Bank Address

Data

1

Write

Bank Address

0030h

The following is a C source code example of using the erase resume function. Refer to the

Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)

for general information on Spansion Flash memory software development guidelines.

/* Example: Erase resume command */

*( (UINT16 *)bank_addr + 0x000 ) = 0x0030;

/* write resume command

*/

/* The flash needs adequate time in the resume state */

8.5.6

Program Suspend/Program Resume Commands

The Program Suspend command allows the system to interrupt an embedded programming op-

eration or a Write to Buffer programming operation so that data can read from any non-

suspended sector. When the Program Suspend command is written during a programming pro-

cess, the device halts the programming operation within t_PSL(program suspend latency) and

updates the status bits. Addresses are don't-cares when writing the Program Suspend command.

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After the programming operation has been suspended, the system can read array data from any

non-suspended sector. The Program Suspend command may also be issued during a program-

ming operation while an erase is suspended. In this case, data may be read from any addresses

not in Erase Suspend or Program Suspend. If a read is needed from the Secured Silicon Sector

area, then user must use the proper command sequences to enter and exit this region.

The system may also write the Autoselect command sequence when the device is in Program Sus-

pend mode. The device allows reading Autoselect codes in the suspended sectors, since the codes

are not stored in the memory array. When the device exits the Autoselect mode, the device re-

verts to Program Suspend mode, and is ready for another valid operation. See Autoselect for

more information.

After the Program Resume command is written, the device reverts to programming. The system

can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in

the standard program operation. See Write Operation Status for more information.

The system must write the Program Resume command (address bits are don't care) to exit the

Program Suspend mode and continue the programming operation. Further writes of the Program

Resume command are ignored. Another Program Suspend command can be written after the de-

vice has resumed programming.

Software Functions and Sample Code

Table 8.18 Program Suspend

(LLD Function = lld_ProgramSuspendCmd)

Cycle

Operation

Byte Address

Word Address

Data

1

Write

Bank Address

00B0h

The following is a C source code example of using the program suspend function. Refer to the

Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)

for general information on Spansion Flash memory software development guidelines.

/* Example: Program suspend command */

*( (UINT16 *)base_addr + 0x000 ) = 0x00B0;

/* write suspend command

*/

Table 8.19 Program Resume

(LLD Function = lld_ProgramResumeCmd)

Cycle

Operation

Byte Address

Word Address

Bank Address

Data

1

Write

Bank Address

0030h

The following is a C source code example of using the program resume function. Refer to the

Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)

for general information on Spansion Flash memory software development guidelines.

/* Example: Program resume command */

*( (UINT16 *)base_addr + 0x000 ) = 0x0030;

/* write resume command

*/

8.5.7

Accelerated Program/Chip Erase

Accelerated single word programming, write buffer programming, sector erase, and chip erase

operations are enabled through the ACC function. This method is faster than the standard chip

program and erase command sequences.

The accelerated chip program and erase functions must not be used more than 10 times

per sector. In addition, accelerated chip program and erase should be performed at room tem-

perature (25°C ±10°C).

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If the system asserts V_HHon this input, the device automatically enters the aforementioned Un-

lock Bypass mode and uses the higher voltage on the input to reduce the time required for

program and erase operations. The system can then use the Write Buffer Load command se-

quence provided by the Unlock Bypass mode. Note that if a Write-to-Buffer-Abort Reset is

required while in Unlock Bypass mode, the full 3-cycle RESET command sequence must be used

to reset the device. Removing V_HHfrom the ACC input, upon completion of the embedded pro-

gram or erase operation, returns the device to normal operation.

Sectors must be unlocked prior to raising ACC to V_HH

.

The ACC pin must not be at V_HHfor operations other than accelerated programming and ac-

celerated chip erase, or device damage may result.

The ACC pin must not be left floating or unconnected; inconsistent behavior of the device may

result.

ACC locks all sector if set to V_IL. ACC should be set to V_IHfor all other conditions.

8.5.8

Unlock Bypass

The device features an Unlock Bypass mode to facilitate faster word programming. Once the de-

vice enters the Unlock Bypass mode, only two write cycles are required to program data, instead

of the normal four cycles.

This mode dispenses with the initial two unlock cycles required in the standard program command

sequence, resulting in faster total programming time. See the Appendix for the requirements for

the unlock bypass command sequences.

During the unlock bypass mode, only the Read, Unlock Bypass Program and Unlock Bypass Reset

commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock

bypass reset command sequence. The first cycle must contain the bank address and the data 90h.

The second cycle need only contain the data 00h. The bank then returns to the read mode.

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Software Functions and Sample Code

The following are C source code examples of using the unlock bypass entry, program, and exit

functions. Refer to the Spansion Low Level Driver User’s Guide (available soon on www.amd.com

and www.fujitsu.com) for general information on Spansion Flash “memory software development

guidelines.

Table 8.20 Unlock Bypass Entry

(LLD Function = lld_UnlockBypassEntryCmd)

Cycle

Description

Unlock

Operation

Write

*/

Byte Address

Base + AAAh

Base + 554h

Base + AAAh

Word Address

Base + 555h

Base + 2AAh

Base + 555h

Data

1

2

3

00AAh

0055h

0020h

Unlock

Entry Command

/* Example: Unlock Bypass Entry Command

*( (UINT16 *)bank_addr + 0x555 ) = 0x00AA;

*( (UINT16 *)bank_addr + 0x2AA ) = 0x0055;

*( (UINT16 *)bank_addr + 0x555 ) = 0x0020;

/* write unlock cycle 1

/* write unlock cycle 2

/* write unlock bypass command

*/

/* At this point, programming only takes two write cycles.

/* Once you enter Unlock Bypass Mode, do a series of like

/* operations (programming or sector erase) and then exit

/* Unlock Bypass Mode before beginning a different type of

/* operations.

*/

Table 8.21 Unlock Bypass Program

(LLD Function = lld_UnlockBypassProgramCmd)

Cycle

Description

Operation

Write

Byte Address

Base + xxxh

Word Address

Data

00A0h

1

2

Program Setup Command

Program Command

Base +xxxh

Write

Program Address

Program Data

/* Example: Unlock Bypass Program Command */

/* Do while in Unlock Bypass Entry Mode! */

*( (UINT16 *)bank_addr + 0x555 ) = 0x00A0;

/* write program setup command

/* write data to be programmed

*/

*( (UINT16 *)pa )

= data;

*/

/* Poll until done or error.

/* If done and more to program, */

/* do above two cycles again. */

Table 8.22 Unlock Bypass Reset

(LLD Function = lld_UnlockBypassResetCmd)

Cycle

Description

Reset Cycle 1

Reset Cycle 2

Operation

Write

Byte Address

Base + xxxh

Word Address

Data

1

2

Base +xxxh

0090h

0000h

Write

/* Example: Unlock Bypass Exit Command */

*( (UINT16 *)base_addr + 0x000 ) = 0x0090;

*( (UINT16 *)base_addr + 0x000 ) = 0x0000;

8.5.9

Write Operation Status

The device provides several bits to determine the status of a program or erase operation. The

following subsections describe the function of DQ1, DQ2, DQ3, DQ5, DQ6, and DQ7.

DQ7: Data# Polling. The Data# Polling bit, DQ7, indicates to the host system whether an Em-

bedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase

Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command se-

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quence. Note that the Data# Polling is valid only for the last word being programmed in the write-

buffer-page during Write Buffer Programming. Reading Data# Polling status on any word other

than the last word to be programmed in the write-buffer-page returns false status information.

During the Embedded Program algorithm, the device outputs on DQ7 the complement of the

datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend.

When the Embedded Program algorithm is complete, the device outputs the datum programmed

to DQ7. The system must provide the program address to read valid status information on DQ7.

If a program address falls within a protected sector, Data# polling on DQ7 is active for approxi-

mately t_PSP, then that bank returns to the read mode.

During the Embedded Erase Algorithm, Data# polling produces a 0 on DQ7. When the Embedded

Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling pro-

duces a 1 on DQ7. The system must provide an address within any of the sectors selected for

erasure to read valid status information on DQ7.

After an erase command sequence is written, if all sectors selected for erasing are protected,

Data# Polling on DQ7 is active for approximately t_ASP, then the bank returns to the read mode.

If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected

sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7

at an address within a protected sector, the status may not be valid.

Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asyn-

chronously with DQ6-DQ0 while Output Enable (OE#) is asserted low. That is, the device may

change from providing status information to valid data on DQ7. Depending on when the system

samples the DQ7 output, it may read the status or valid data. Even if the device has completed

the program or erase operation and DQ7 has valid data, the data outputs on DQ6-DQ0 may be

still invalid. Valid data on DQ7-D00 appears on successive read cycles.

See the following for more information: Table 8.23, Write Operation Status, shows the outputs

for Data# Polling on DQ7. Figure 8.6, Write Operation Status Flowchart, shows the Data# Polling

algorithm; and Figure 12.17, Data# Polling Timings (During Embedded Algorithm), shows the

Data# Polling timing diagram.

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START

(Note 6)

YES

Erase

Operation

Complete

DQ7=valid

data?

NO

YES

DQ5=1?

Read3=

valid data?

NO

Program

Operation

Failed

YES

Write Buffer

Programming?

YES

NO

Programming

Operation?

NO

Device BUSY,

Re-Poll

(Note 3)

(Note 5)

(Note 1)

YES

(Note 1)

YES

DQ6

toggling?

DQ6

toggling?

DEVICE

ERROR

TIMEOUT

NO

(Note 4)

NO

YES

DQ1=1?

(Note 2)

YES

NO

Device BUSY,

Re-Poll

DQ2

toggling?

NO

Device BUSY,

Re-Poll

Erase

Device in

Erase/Suspend

Mode

Operation

Complete

DQ1=1

YES

Write Buffer

AND DQ7 ≠

Valid Data?

Operation

Failed

NO

Notes:

1) DQ6 is toggling if Read2 DQ6 does not equal Read3 DQ6.

2) DQ2 is toggling if Read2 DQ2 does not equal Read3 DQ2.

3) May be due to an attempt to program a 0 to 1. Use the RESET

command to exit operation.

Device BUSY,

Re-Poll

4) Write buffer error if DQ1 of last read =1.

5) Invalid state, use RESET command to exit operation.

6) Valid data is the data that is intended to be programmed or all 1's for

an erase operation.

7) Data polling algorithm valid for all operations except advanced sector

protection.

Figure 8.6 Write Operation Status Flowchart

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DQ6: Toggle Bit I . Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algo-

rithm is in progress or complete, or whether the device has entered the Erase Suspend mode.

Toggle Bit I may be read at any address in the same bank, and is valid after the rising edge of

the final WE# pulse in the command sequence (prior to the program or erase operation), and dur-

ing the sector erase time-out.

During an Embedded Program or Erase algorithm operation, successive read cycles to any ad-

dress cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling.

After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6

toggles for approximately t_ASP[all sectors protected toggle time], then returns to reading array

data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unpro-

tected sectors, and ignores the selected sectors that are protected.

The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or

is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm

is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops tog-

gling. However, the system must also use DQ2 to determine which sectors are erasing or erase-

suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling).

If a program address falls within a protected sector, DQ6 toggles for approximately t_PAPafter the

program command sequence is written, then returns to reading array data.

DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embed-

ded Program Algorithm is complete.

See the following for additional information: Figure 8.6, Write Operation Status Flowchart;

Figure 12.18, Toggle Bit Timings (During Embedded Algorithm), and Table 8.23 and Table 8.24.

Toggle Bit I on DQ6 requires either OE# or CE# to be de-asserted and reasserted to show the

change in state.

DQ2: Toggle Bit II . The Toggle Bit II on DQ2, when used with DQ6, indicates whether a partic-

ular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether

that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse

in the command sequence. DQ2 toggles when the system reads at addresses within those sectors

that have been selected for erasure. But DQ2 cannot distinguish whether the sector is actively

erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively eras-

ing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus,

both status bits are required for sector and mode information. Refer to Table 8.23 to compare

outputs for DQ2 and DQ6. See the following for additional information: Figure 8.6, the DQ6: Tog-

gle Bit I section, and Figures 12.17–12.20.

Reading Toggle Bits DQ6/DQ2. Whenever the system initially begins reading toggle bit status,

it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typ-

ically, the system would note and store the value of the toggle bit after the first read. After the

second read, the system would compare the new value of the toggle bit with the first. If the toggle

bit is not toggling, the device has completed the program or erases operation. The system can

read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read

cycles, the system determines that the toggle bit is still toggling, the system also should note

whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then deter-

mine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just

as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed

the program or erases operation. If it is still toggling, the device did not complete the operation

successfully, and the system must write the reset command to return to reading array data. The

remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5

has not gone high. The system may continue to monitor the toggle bit and DQ5 through succes-

sive read cycles, determining the status as described in the previous paragraph. Alternatively, it

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may choose to perform other system tasks. In this case, the system must start at the beginning

of the algorithm when it returns to determine the status of the operation. Refer to Figure 8.6 for

more details.

DQ5: Exceeded Timing Limits. DQ5 indicates whether the program or erase time has exceeded

a specified internal pulse count limit. Under these conditions DQ5 produces a 1, indicating that

the program or erase cycle was not successfully completed. The device may output a 1 on DQ5 if

the system tries to program a 1 to a location that was previously programmed to 0 Only an erase

operation can change a 0 back to a 1. Under this condition, the device halts the operation, and

when the timing limit has been exceeded, DQ5 produces a 1. Under both these conditions, the

system must write the reset command to return to the read mode (or to the erase-suspend-read

mode if a bank was previously in the erase-suspend-program mode).

DQ3: Sector Erase Timeout State Indicator. After writing a sector erase command sequence,

the system may read DQ3 to determine whether or not erasure has begun. (The sector erase

timer does not apply to the chip erase command.) If additional sectors are selected for erasure,

the entire time-out also applies after each additional sector erase command. When the time-out

period is complete, DQ3 switches from a 0 to a 1. If the time between additional sector erase

commands from the system can be assumed to be less than t_SEA, the system need not monitor

DQ3. See Sector Erase Command Sequence for more details.

After the sector erase command is written, the system should read the status of DQ7 (Data# Poll-

ing) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and

then read DQ3. If DQ3 is 1, the Embedded Erase algorithm has begun; all further commands (ex-

cept Erase Suspend) are ignored until the erase operation is complete. If DQ3 is 0 the device

accepts additional sector erase commands. To ensure the command has been accepted, the sys-

tem software should check the status of DQ3 prior to and following each sub-sequent sector erase

command. If DQ3 is high on the second status check, the last command might not have been

accepted. Table 8.23 shows the status of DQ3 relative to the other status bits.

DQ1: Write to Buffer Abort. DQ1 indicates whether a Write to Buffer operation was aborted.

Under these conditions DQ1 produces a 1. The system must issue the Write to Buffer Abort Reset

command sequence to return the device to reading array data. See Write Buffer Programming

Operation for more details.

Table 8.23 Write Operation Status

INVALID

Program

Suspend

Mode

Reading within Program Suspended Sector

(Not

Allowed)

(Not

Allowed)

(Not

Allowed)

(Not

Allowed)

(Not

Allowed)

(Not

Allowed)

Reading within Non-Program Suspended

Sector

(Note 3)

Data

BUSY State

DQ7#

Toggle

0

1

0

N/A

0

1

Write to

Buffer

(Note 5)

Exceeded Timing Limits

ABORT State

Notes:

1. DQ5 switches to 1 when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the

section on DQ5 for more information.

2. DQ7 a valid address when reading status information. Refer to the appropriate subsection for further details.

3. Data are invalid for addresses in a Program Suspended sector.

4. DQ1 indicates the Write to Buffer ABORT status during Write Buffer Programming operations.

5. The data-bar polling algorithm should be used for Write Buffer Programming operations. Note that DQ7# during Write Buffer Programming

indicates the data-bar for DQ7 data for the Last Loaded Write-buffer Address location.

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8.6 Simultaneous Read/Write

The simultaneous read/write feature allows the host system to read data from one bank of mem-

ory while programming or erasing another bank of memory. An erase operation may also be

suspended to read from or program another location within the same bank (except the sector

being erased). Figure 12.24, Back-to-Back Read/Write Cycle Timings, shows how read and write

cycles may be initiated for simultaneous operation with zero latency. Refer to the DC Character-

istics table for read-while-program and read-while-erase current specification.

8.7 Writing Commands/Command Sequences

When the device is configured for Asynchronous read, only Asynchronous write operations are

allowed, and CLK is ignored. When in the Synchronous read mode configuration, the device is able

to perform both Asynchronous and Synchronous write operations. CLK and AVD# induced address

latches are supported in the Synchronous programming mode. During a synchronous write oper-

ation, to write a command or command sequence (which includes programming data to the

device and erasing sectors of memory), the system must drive AVD# and CE# to V_IL, and OE#

to V_IHwhen providing an address to the device, and drive WE# and CE# to V_IL, and OE# to V_IH

when writing commands or data. During an asynchronous write operation, the system must drive

CE# and WE# to V_ILand OE# to V_IHwhen providing an address, command, and data. Addresses

are latched on the last falling edge of WE# or CE#, while data is latched on the 1st rising edge of

WE# or CE#. An erase operation can erase one sector, multiple sectors, or the entire device.

Tables 7.1–7.3 indicate the address space that each sector occupies. The device address space is

divided into sixteen banks: Banks 1 through 14 contain only 64 Kword sectors, while Banks 0 and

15 contain both 16 Kword boot sectors in addition to 64 Kword sectors. A bank address is the set

of address bits required to uniquely select a bank. Similarly, a sector address is the address bits

required to uniquely select a sector. I_CC2in DC Characteristics represents the active current spec-

ification for the write mode. AC Characteristics-Synchronous and AC Characteristics—

Asynchronous Read contains timing specification tables and timing diagrams for write operations.

8.8 Handshaking

The handshaking feature allows the host system to detect when data is ready to be read by simply

monitoring the RDY (Ready) pin, which is a dedicated output and controlled by CE#.

When the device is configured to operate in synchronous mode, and OE# is low (active), the initial

word of burst data becomes available after either the falling or rising edge of the RDY pin (de-

pending on the setting for bit 10 in the Configuration Register). It is recommended that the host

system set CR13–CR11 in the Configuration Register to the appropriate number of wait states to

ensure optimal burst mode operation (see Table 8.8, Configuration Register).

Bit 8 in the Configuration Register allows the host to specify whether RDY is active at the same

time that data is ready, or one cycle before data is ready.

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8.9 Hardware Reset

The RESET# input provides a hardware method of resetting the device to reading array data.

When RESET# is driven low for at least a period of t_RP, the device immediately terminates any

operation in progress, tristates all outputs, resets the configuration register, and ignores all read/

write commands for the duration of the RESET# pulse. The device also resets the internal state

machine to reading array data.

To ensure data integrity the operation that was interrupted should be reinitiated once the device

is ready to accept another command sequence.

When RESET# is held at V_SS, the device draws CMOS standby current (I_CC4). If RESET# is held

at V_IL, but not at V_SS, the standby current is greater.

RESET# may be tied to the system reset circuitry which enables the system to read the boot-up

firmware from the Flash memory upon a system reset.

See Figures 12.5 and 12.12 for timing diagrams.

8.10 Software Reset

Software reset is part of the command set (see Table 13.1) that also returns the device to array

read mode and must be used for the following conditions:

1. to exit Autoselect mode

2. when DQ5 goes high during write status operation that indicates program or erase cycle was

not successfully completed

3. exit sector lock/unlock operation.

4. to return to erase-suspend-read mode if the device was previously in Erase Suspend mode.

5. after any aborted operations

Software Functions and Sample Code

Table 8.24 Reset

(LLD Function = lld_ResetCmd)

Cycle

Operation

Byte Address

Word Address

Data

Reset Command

Write

Base + xxxh

00F0h

Note: Base = Base Address.

The following is a C source code example of using the reset function. Refer to the Spansion

Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for general

information on Spansion Flash memory software development guidelines.

/* Example: Reset (software reset of Flash state machine) */

*( (UINT16 *)base_addr + 0x000 ) = 0x00F0;

The following are additional points to consider when using the reset command:

This command resets the banks to the read and address bits are ignored.

Reset commands are ignored once erasure has begun until the operation is complete.

Once programming begins, the device ignores reset commands until the operation is com-

plete

The reset command may be written between the cycles in a program command sequence be-

fore programming begins (prior to the third cycle). This resets the bank to which the system

was writing to the read mode.

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If the program command sequence is written to a bank that is in the Erase Suspend mode,

writing the reset command returns that bank to the erase-suspend-read mode.

The reset command may be also written during an Autoselect command sequence.

If a bank has entered the Autoselect mode while in the Erase Suspend mode, writing the reset

command returns that bank to the erase-suspend-read mode.

If DQ1 goes high during a Write Buffer Programming operation, the system must write the

Write to Buffer Abort Reset command sequence to RESET the device to reading array data.

The standard RESET command does not work during this condition.

To exit the unlock bypass mode, the system must issue a two-cycle unlock bypass reset com-

mand sequence [see command table for details].

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9 Advanced Sector Protection/Unprotection

The Advanced Sector Protection/Unprotection feature disables or enables programming or erase

operations in any or all sectors and can be implemented through software and/or hardware meth-

ods, which are independent of each other. This section describes the various methods of

protecting data stored in the memory array. An overview of these methods in shown in Figure 9.1.

Hardware Methods

Software Methods

Lock Register

(One Time Programmable)

ACC = V

IL

All sectors locked)

Persistent Method

Password Method

(

(DQ1)

(DQ2)

WP# = V

IL

(All boot

sectors locked)

64-bit Password

(One Time Protect)

1. Bit is volatile, and defaults to “1” on

reset.

PPB Lock Bit^1,2,3

2. Programming to “0” locks all PPBs to

their current state.

0 = PPBs Locked

1 = PPBs Unlocked

3. Once programmed to “0”, requires

hardware reset to unlock.

Persistent

Protection Bit

(PPB)^4,5

Dynamic

Protection Bit

(PPB)^6,7,8

Memory Array

Sector 0

Sector 1

Sector 2

PPB 0

PPB 1

PPB 2

DYB 0

DYB 1

DYB 2

Sector N-2

Sector N-1

Sector N³

PPB N-2

PPB N-1

PPB N

DYB N-2

DYB N-1

DYB N

3. N = Highest Address Sector.

4. 0 = Sector Protected,

1 = Sector Unprotected.

6. 0 = Sector Protected,

1 = Sector Unprotected.

5. PPBs programmed individually,

but cleared collectively

7. Protect effective only if PPB Lock Bit

is unlocked and corresponding PPB

is “1” (unprotected).

8. Volatile Bits: defaults to user choice

upon power-up (see ordering

options).

Figure 9.1 Advanced Sector Protection/Unprotection

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9.1

Lock Register

As shipped from the factory, all devices default to the persistent mode when power is applied, and

all sectors are unprotected, unless otherwise chosen through the DYB ordering option. The device

programmer or host system must then choose which sector protection method to use. Program-

ming (setting to 0) any one of the following two one-time programmable, non-volatile bits locks

the part permanently in that mode:

Lock Register Persistent Protection Mode Lock Bit (DQ1)

Lock Register Password Protection Mode Lock Bit (DQ2)

Table 9.1 Lock Register

Device

DQ15-05

DQ4

DQ3

DQ2

DQ1

DQ0

Customer

Secured Silicon

Sector

Password

Protection

Mode Lock Bit

Persistent

Protection

Mode Lock Bit

S29WS256N

1

Protection Bit

DYB Lock Boot Bit

PPB One-Time

0 = sectors

power up

protected

Programmable Bit

Password

Protection

Mode Lock Bit

Persistent

Protection

Mode Lock Bit

Secured Silicon

Sector

Protection Bit

S29WS128N/

S29WS064N

0 = All PPB erase

command disabled

Undefined

1 = sectors

power up

unprotected

1 = All PPB Erase

command enabled

For programming lock register bits refer to Table 13.2.

Notes

1. If the password mode is chosen, the password must be programmed before setting the cor-

responding lock register bit.

2. After the Lock Register Bits Command Set Entry command sequence is written, reads and

writes for Bank 0 are disabled, while reads from other banks are allowed until exiting this

mode.

3. If both lock bits are selected to be programmed (to zeros) at the same time, the operation

aborts.

4. Once the Password Mode Lock Bit is programmed, the Persistent Mode Lock Bit is permanently

disabled, and no changes to the protection scheme are allowed. Similarly, if the Persistent

Mode Lock Bit is programmed, the Password Mode is permanently disabled.

After selecting a sector protection method, each sector can operate in any of the following three

states:

1. Constantly locked. The selected sectors are protected and can not be reprogrammed unless

PPB lock bit is cleared via a password, hardware reset, or power cycle.

2. Dynamically locked. The selected sectors are protected and can be altered via software

commands.

3. Unlocked. The sectors are unprotected and can be erased and/or programmed.

These states are controlled by the bit types described in Sections 9.2–9.6.

9.2 Persistent Protection Bits

The Persistent Protection Bits are unique and nonvolatile for each sector and have the same en-

durances as the Flash memory. Preprogramming and verification prior to erasure are handled by

the device, and therefore do not require system monitoring.

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Notes

1. Each PPB is individually programmed and all are erased in parallel.

2. While programming PPB for a sector, array data can be read from any other bank, except

Bank 0 (used for Data# Polling) and the bank in which sector PPB is being programmed.

3. Entry command disables reads and writes for the bank selected.

4. Reads within that bank return the PPB status for that sector.

5. Reads from other banks are allowed while writes are not allowed.

6. All Reads must be performed using the Asynchronous mode.

7. The specific sector address (A23-A14 WS256N, A22-A14 WS128N, A21-A14 WS064N) are

written at the same time as the program command.

8. If the PPB Lock Bit is set, the PPB Program or erase command does not execute and times-

out without programming or erasing the PPB.

9. There are no means for individually erasing a specific PPB and no specific sector address is

required for this operation.

10. Exit command must be issued after the execution which resets the device to read mode and

re-enables reads and writes for Bank 0

11. The programming state of the PPB for a given sector can be verified by writing a PPB

Status Read Command to the device as described by the flow chart shown in Figure 9.2.

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Enter PPB

Command Set.

Addr = BA

Program PPB Bit.

Addr = SA

Read Byte Twice

Addr = SA0

No

DQ6 =

Toggle?

Yes

No

DQ5 = 1?

Yes

Wait 500 µs

Read Byte Twice

Addr = SA0

No

Read Byte.

Addr = SA

DQ6 =

Toggle?

Yes

DQ0 =

'1' (Erase)

'0' (Pgm.)?

No

FAIL

Yes

Issue Reset

Command

PASS

Exit PPB

Command Set

Figure 9.2 PPB Program/Erase Algorithm

9.3 Dynamic Protection Bits

Dynamic Protection Bits are volatile and unique for each sector and can be individually modified.

DYBs only control the protection scheme for unprotected sectors that have their PPBs cleared

(erased to 1). By issuing the DYB Set or Clear command sequences, the DYBs are set (pro-

grammed to 0) or cleared (erased to 1), thus placing each sector in the protected or unprotected

state respectively. This feature allows software to easily protect sectors against inadvertent

changes yet does not prevent the easy removal of protection when changes are needed.

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Notes

1. The DYBs can be set (programmed to 0) or cleared (erased to 1) as often as needed.

When the parts are first shipped, the PPBs are cleared (erased to 1) and upon power up or reset,

the DYBs can be set or cleared depending upon the ordering option chosen.

2. If the option to clear the DYBs after power up is chosen, (erased to 1), then the sectorsmay

be modified depending upon the PPB state of that sector (see Table 9.2).

3. The sectors would be in the protected state If the option to set the DYBs after power up is

chosen (programmed to 0).

4. It is possible to have sectors that are persistently locked with sectors that are left in the

dynamic state.

5. The DYB Set or Clear commands for the dynamic sectors signify protected or unprotected

state of the sectors respectively. However, if there is a need to change the status of the per-

sistently locked sectors, a few more steps are required. First, the PPB Lock Bit must be

cleared by either putting the device through a power-cycle, or hardware reset. The PPBs can

then be changed to reflect the desired settings. Setting the PPB Lock Bit once again locks

the PPBs, and the device operates normally again.

6. To achieve the best protection, it is recommended to execute the PPB Lock Bit Set command

early in the boot code and protect the boot code by holding WP# = V_IL. Note that the PPB

and DYB bits have the same function when ACC = V_HHas they do when ACC =V_IH.

9.4 Persistent Protection Bit Lock Bit

The Persistent Protection Bit Lock Bit is a global volatile bit for all sectors. When set (programmed

to 0), it locks all PPBs and when cleared (programmed to 1), allows the PPBs to be changed. There

is only one PPB Lock Bit per device.

Notes

1. No software command sequence unlocks this bit unless the device is in the password pro-

tection mode; only a hardware reset or a power-up clears this bit.

2. The PPB Lock Bit must be set (programmed to 0) only after all PPBs are configured to the

desired settings.

9.5 Password Protection Method

The Password Protection Method allows an even higher level of security than the Persistent Sector

Protection Mode by requiring a 64 bit password for unlocking the device PPB Lock Bit. In addition

to this password requirement, after power up and reset, the PPB Lock Bit is set 0 to maintain the

password mode of operation. Successful execution of the Password Unlock command by entering

the entire password clears the PPB Lock Bit, allowing for sector PPBs modifications.

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Notes

1. There is no special addressing order required for programming the password. Once the

Password is written and verified, the Password Mode Locking Bit must be set in order to pre-

vent access.

2. The Password Program Command is only capable of programming 0s. Programming a 1 after

a cell is programmed as a 0 results in a time-out with the cell as a 0.

3. The password is all 1s when shipped from the factory.

4. All 64-bit password combinations are valid as a password.

5. There is no means to verify what the password is after it is set.

6. The Password Mode Lock Bit, once set, prevents reading the 64-bit password on the data

bus and further password programming.

7. The Password Mode Lock Bit is not erasable.

8. The lower two address bits (A1–A0) are valid during the Password Read, Password Program,

and Password Unlock.

9. The exact password must be entered in order for the unlocking function to occur.

10. The Password Unlock command cannot be issued any faster than 1 µs at a time to prevent

a hacker from running through all the 64-bit combinations in an attempt to correctly match

a password.

11. Approximately 1 µs is required for unlocking the device after the valid 64-bit password is

given to the device.

12. Password verification is only allowed during the password programming operation.

13. All further commands to the password region are disabled and all operations are ignored.

14. If the password is lost after setting the Password Mode Lock Bit, there is no way to clear the

PPB Lock Bit.

15. Entry command sequence must be issued prior to any of any operation and it disables reads

and writes for Bank 0. Reads and writes for other banks excluding Bank 0 are allowed.

16. If the user attempts to program or erase a protected sector, the device ignores the com-

mand and returns to read mode.

17. A program or erase command to a protected sector enables status polling and returns to

read mode without having modified the contents of the protected sector.

18. The programming of the DYB, PPB, and PPB Lock for a given sector can be verified by writing

individual status read commands DYB Status, PPB Status, and PPB Lock Status to the

device.

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Write Unlock Cycles:

Address 555h, Data AAh

Address 2AAh, Data 55h

Unlock Cycle 1

Unlock Cycle 2

Write

Enter Lock Register Command:

Address 555h, Data 40h

XXXh = Address don’t care

* Not on future devices

Program Lock Register Data

Address XXXh, Data A0h

Address 77h*, Data PD

Program Data (PD): See text for Lock Register

definitions

Caution: Lock register can only be progammed

once.

Wait 4 µs

Perform Polling Algorithm

(see Write Operation Status

flowchart)

Yes

Done?

No

DQ5 = 1?

Error condition (Exceeded Timing Limits)

Yes

PASS. Write Lock Register

FAIL. Write rest command

to return to reading array.

Exit Command:

Address XXXh, Data 90h

Address XXXh, Data 00h

Device returns to reading array.

Figure 9.3 Lock Register Program Algorithm

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9.6 Advanced Sector Protection Software Examples

Table 9.2 Sector Protection Schemes

Unique Device PPB Lock Bit

0 = locked

Sector PPB

0 = protected

1 = unprotected

Sector DYB

0 = protected

1 = unprotected

1 = unlocked

Sector Protection Status

Protected through PPB

Unprotected

Any Sector

0

1

0

1

0

1

x

1

0

x

0

1

Protected through DYB

Protected through PPB

Protected through DYB

Unprotected

Table 9.2 contains all possible combinations of the DYB, PPB, and PPB Lock Bit relating to the sta-

tus of the sector. In summary, if the PPB Lock Bit is locked (set to 0), no changes to the PPBs are

allowed. The PPB Lock Bit can only be unlocked (reset to 1) through a hardware reset or power

cycle. See also Figure 9.1 for an overview of the Advanced Sector Protection feature.

9.7 Hardware Data Protection Methods

The device offers two main types of data protection at the sector level via hardware control:

When WP# is at V_IL, the four outermost sectors are locked (device specific).

When ACC is at V_IL, all sectors are locked.

There are additional methods by which intended or accidental erasure of any sectors can be pre-

vented via hardware means. The following subsections describes these methods:

9.7.1

WP# Method

The Write Protect feature provides a hardware method of protecting the four outermost sectors.

This function is provided by the WP# pin and overrides the previously discussed Sector Protec-

tion/Unprotection method.

If the system asserts V_ILon the WP# pin, the device disables program and erase functions in the

outermost boot sectors. The outermost boot sectors are the sectors containing both the lower and

upper set of sectors in a dual-boot-configured device.

If the system asserts V_IHon the WP# pin, the device reverts to whether the boot sectors were

last set to be protected or unprotected. That is, sector protection or unprotection for these sectors

depends on whether they were last protected or unprotected.

Note that the WP# pin must not be left floating or unconnected as inconsistent behavior of the

device may result.

The WP# pin must be held stable during a command sequence execution

9.7.2

9.7.3

ACC Method

This method is similar to above, except it protects all sectors. Once ACC input is set to V_IL, all

program and erase functions are disabled and hence all sectors are protected.

Low V

Write Inhibit

CC

When V_CCis less than V_LKO, the device does not accept any write cycles. This protects data during

V_CCpower-up and power-down.

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The command register and all internal program/erase circuits are disabled, and the device resets

to reading array data. Subsequent writes are ignored until V_CCis greater than V_LKO. The system

must provide the proper signals to the control inputs to prevent unintentional writes when V_CCis

greater than V_LKO

.

9.7.4

9.7.5

Write Pulse Glitch Protection

Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

Power-Up Write Inhibit

If WE# = CE# = RESET# = V_ILand OE# = V_IHduring power up, the device does not accept com-

mands on the rising edge of WE#. The internal state machine is automatically reset to the read

mode on power-up.

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10 Power Conservation Modes

10.1 Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby

mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the

high impedance state, independent of the OE# input. The device enters the CMOS standby mode

when the CE# and RESET# inputs are both held at V_CC± 0.2 V. The device requires standard

access time (t_CE) for read access, before it is ready to read data. If the device is deselected during

erasure or programming, the device draws active current until the operation is completed. I_CC3

in DC Characteristics represents the standby current specification

10.2 Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption while in asynchronous

mode. the device automatically enables this mode when addresses remain stable for t_ACC+ 20

ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Stan-

dard address access timings provide new data when addresses are changed. While in sleep mode,

output data is latched and always available to the system. While in synchronous mode, the auto-

matic sleep mode is disabled. Note that a new burst operation is required to provide new data.

I_CC6in DC Characteristics represents the automatic sleep mode current specification.

10.3 Hardware RESET# Input Operation

The RESET# input provides a hardware method of resetting the device to reading array data.

When RESET# is driven low for at least a period of t_RP, the device immediately terminates any

operation in progress, tristates all outputs, resets the configuration register, and ignores all read/

write commands for the duration of the RESET# pulse. The device also resets the internal state

machine to reading array data. The operation that was interrupted should be reinitiated once the

device is ready to accept another command sequence to ensure data integrity.

When RESET# is held at V_SS± 0.2 V, the device draws CMOS standby current (I_CC4). If RESET#

is held at V_ILbut not within V_SS± 0.2 V, the standby current is greater.

RESET# may be tied to the system reset circuitry and thus, a system reset would also reset the

Flash memory, enabling the system to read the boot-up firmware from the Flash memory.

10.4 Output Disable (OE#)

When the OE# input is at V_IH, output from the device is disabled. The outputs are placed in the

high impedance state.

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11 Secured Silicon Sector Flash Memory Region

The Secured Silicon Sector provides an extra Flash memory region that enables permanent part

identification through an Electronic Serial Number (ESN). The Secured Silicon Sector is 256 words

in length that consists of 128 words for factory data and 128 words for customer-secured areas.

All Secured Silicon reads outside of the 256-word address range returns invalid data. The Factory

Indicator Bit, DQ7, (at Autoselect address 03h) is used to indicate whether or not the Factory Se-

cured Silicon Sector is locked when shipped from the factory. The Customer Indicator Bit (DQ6)

is used to indicate whether or not the Customer Secured Silicon Sector is locked when shipped

from the factory.

Please note the following general conditions:

While Secured Silicon Sector access is enabled, simultaneous operations are allowed except

for Bank 0.

On power-up, or following a hardware reset, the device reverts to sending commands to the

normal address space.

Reads can be performed in the Asynchronous or Synchronous mode.

Burst mode reads within Secured Silicon Sector wrap from address FFh back to address 00h.

Reads outside of sector 0 return memory array data.

Continuous burst read past the maximum address is undefined.

Sector 0 is remapped from memory array to Secured Silicon Sector array.

Once the Secured Silicon Sector Entry Command is issued, the Secured Silicon Sector Exit

command must be issued to exit Secured Silicon Sector Mode.

The Secured Silicon Sector is not accessible when the device is executing an Embedded Pro-

gram or Embedded Erase algorithm.

Table 11.1 Addresses

Sector

Customer

Factory

Sector Size

128 words

Address Range

000080h-0000FFh

000000h-00007Fh

11.1 Factory Secured SiliconSector

The Factory Secured Silicon Sector is always protected when shipped from the factory and has

the Factory Indicator Bit (DQ7) permanently set to a 1. This prevents cloning of a factory locked

part and ensures the security of the ESN and customer code once the product is shipped to the

field.

These devices are available pre programmed with one of the following:

A random, 8 Word secure ESN only within the Factory Secured Silicon Sector

Customer code within the Customer Secured Silicon Sector through the Spansion^TMprogram-

ming service.

Both a random, secure ESN and customer code through the Spansion programming service.

Customers may opt to have their code programmed through the Spansion programming services.

Spansion programs the customer's code, with or without the random ESN. The devices are then

shipped from the Spansion factory with the Factory Secured Silicon Sector and Customer Secured

Silicon Sector permanently locked. Contact your local representative for details on using Spansion

programming services.

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11.2 Customer Secured Silicon Sector

The Customer Secured Silicon Sector is typically shipped unprotected (DQ6 set to 0), allowing

customers to utilize that sector in any manner they choose. If the security feature is not required,

the Customer Secured Silicon Sector can be treated as an additional Flash memory space.

Please note the following:

Once the Customer Secured Silicon Sector area is protected, the Customer Indicator Bit is

permanently set to 1.

The Customer Secured Silicon Sector can be read any number of times, but can be pro-

grammed and locked only once. The Customer Secured Silicon Sector lock must be used with

caution as once locked, there is no procedure available for unlocking the Customer Secured

Silicon Sector area and none of the bits in the Customer Secured Silicon Sector memory space

can be modified in any way.

The accelerated programming (ACC) and unlock bypass functions are not available when pro-

gramming the Customer Secured Silicon Sector, but reading in Banks 1 through 15 is avail-

able.

Once the Customer Secured Silicon Sector is locked and verified, the system must write the

Exit Secured Silicon Sector Region command sequence which return the device to the mem-

ory array at sector 0.

11.3 Secured Silicon Sector Entry and Secured Silicon Sector Exit

Command Sequences

The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured

Silicon Sector command sequence. The device continues to access the Secured Silicon Sector re-

gion until the system issues the four-cycle Exit Secured Silicon Sector command sequence.

See Command Definition Table [Secured Silicon Sector Command Table, Appendix

Table 13.1 for address and data requirements for both command sequences.

The Secured Silicon Sector Entry Command allows the following commands to be executed

Read customer and factory Secured Silicon areas

Program the customer Secured Silicon Sector

After the system has written the Enter Secured Silicon Sector command sequence, it may read

the Secured Silicon Sector by using the addresses normally occupied by sector SA0 within the

memory array. This mode of operation continues until the system issues the Exit Secured Silicon

Sector command sequence, or until power is removed from the device.

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Software Functions and Sample Code

The following are C functions and source code examples of using the Secured Silicon Sector

Entry, Program, and exit commands. Refer to the Spansion Low Level Driver User’s Guide

(available soon on www.amd.com and www.fujitsu.com) for general information on Spansion

Flash memory software development guidelines.

Table 11.2 Secured Silicon Sector Entry

(LLD Function = lld_SecSiSectorEntryCmd)

Cycle

Operation

Write

Byte Address

Base + AAAh

Base + 554h

Base + AAAh

Word Address

Base + 555h

Base + 2AAh

Base + 555h

Data

Unlock Cycle 1

Unlock Cycle 2

00AAh

0055h

0088h

Write

Entry Cycle

Write

Note: Base = Base Address.

/* Example: SecSi Sector Entry Command */

*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;

*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;

*( (UINT16 *)base_addr + 0x555 ) = 0x0088;

/* write unlock cycle 1

/* write unlock cycle 2

/* write Secsi Sector Entry Cmd

*/

Table 11.3 Secured Silicon Sector Program

(LLD Function = lld_ProgramCmd)

Cycle

Operation

Write

Byte Address

Base + AAAh

Base + 554h

Base + AAAh

Word Address

Base + 555h

Base + 2AAh

Base + 555h

Word Address

Data

00AAh

Unlock Cycle 1

Unlock Cycle 2

Program Setup

Write

0055h

Write

00A0h

Program

Write

Data Word

Note: Base = Base Address.

/* Once in the SecSi Sector mode, you program */

/* words using the programming algorithm. */

Table 11.4 Secured Silicon Sector Exit

(LLD Function = lld_SecSiSectorExitCmd)

Cycle

Operation

Write

Byte Address

Base + AAAh

Base + 554h

Base + AAAh

Word Address

Base + 555h

Base + 2AAh

Base + 555h

Data

Unlock Cycle 1

Unlock Cycle 2

00AAh

0055h

0090h

Write

Exit Cycle

Write

Note: Base = Base Address.

/* Example: SecSi Sector Exit Command */

*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;

*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;

*( (UINT16 *)base_addr + 0x555 ) = 0x0090;

*( (UINT16 *)base_addr + 0x000 ) = 0x0000;

/* write unlock cycle 1

/* write unlock cycle 2

/* write SecSi Sector Exit cycle 3 */

/* write SecSi Sector Exit cycle 4 */

*/

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12 Electrical Specifications

12.1 Absolute Maximum Ratings

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature

with Power Applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C

Voltage with Respect to Ground:

All Inputs and I/Os except

as noted below (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V_IO+ 0.5 V

V_CC(Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +2.5 V

V_IO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +2.5 V

ACC (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +9.5 V

Output Short Circuit Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

Notes:

1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs or I/Os may undershoot V to –2.0 V

SS

for periods of up to 20 ns. See Figure 12.1. Maximum DC voltage on input or I/Os is V + 0.5 V. During voltage

CC

transitions outputs may overshoot to V + 2.0 V for periods up to 20 ns. See Figure 12.2.

CC

2. Minimum DC input voltage on pin ACC is -0.5V. During voltage transitions, ACC may overshoot V to –2.0 V for periods

SS

of up to 20 ns. See Figure 12.1. Maximum DC voltage on pin ACC is +9.5 V, which may overshoot to 10.5 V for periods

up to 20 ns.

3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than

one second.

4. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a

stress rating only; functional operation of the device at these or any other conditions above those indicated in the

operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for

extended periods may affect device reliability.

20 ns

V_CC

+2.0 V

+0.8 V

V_CC

–0.5 V

–2.0 V

+0.5 V

1.0 V

20 ns

Figure 12.1 Maximum Negative

Overshoot Waveform

Figure 12.2 Maximum Positive

Overshoot Waveform

Note: The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document is

Preliminary for the S29W256N.

12.2 Operating Ranges

Wireless (W) Devices

Ambient Temperature (T_A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25°C to +85°C

Industrial (I) Devices

Ambient Temperature (T_A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Supply Voltages

V_CCSupply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+1.70 V to +1.95 V

V_IOSupply Voltages: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.70 V to +1.95 V

(Contact local sales office for V_IO= 1.35 to +1.70 V.)

Note: Operating ranges define those limits between which the device functionality is guaranteed.

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12.3 Test Conditions

Device

Under

Test

C

L

Figure 12.3 Test Setup

Table 12.1 Test Specifications

Test Condition

Output Load Capacitance, C_L

All Speed Options

Unit

30

pF

(including jig capacitance)

3.0 @ 54, 66 MHz

2.5 @ 80 MHz

Input Rise and Fall Times

ns

Input Pulse Levels

0.0–V_IO

V_IO/2

V

Input timing measurement reference levels

Output timing measurement reference levels

V_IO/2

Note: The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document

is Preliminary for the S29W256N.

12.4 Key to Switching Waveforms

Waveform

Inputs

Outputs

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State

(High Z)

Note: The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document

is Preliminary for the S29W256N.

12.5 Switching Waveforms

V_IO

All Inputs and Outputs

V_IO/2

Input

Measurement Level

Output

0.0 V

Figure 12.4 Input Waveforms and Measurement Levels

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12.6 V

Power-up

CC

Parameter

t_VCS

Description

Test Setup

Speed

Unit

V_CCSetup Time

Min

1

ms

Notes:

1.

V

>= V - 100mV and V ramp rate is > 1V / 100µs

IO CC

CC

2.

V

ramp rate <1V / 100µs, a Hardware Reset is required.

CC

3. The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document

is Preliminary for the S29W256N.

t_VCS

V_CC

V_IO

RESET#

Figure 12.5

V

Power-up Diagram

CC

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12.7 DC Characteristics

(CMOS Compatible)

Parameter

Description (Notes)

Input Load Current

Output Leakage Current (3)

Test Conditions (Notes 1, 2, 9)

= V to V , V = V max

Min

Typ

Max

±1

54

60

66

48

54

60

42

48

54

36

42

48

30

36

18

4

Unit

µA

I

V

LI

IN

SS

CC

I

= V to V , V = V max

µA

LO

OUT

SS

CC

54 MHz

66 MHz

80 MHz

54 MHz

66 MHz

80 MHz

54 MHz

66 MHz

80 MHz

54 MHz

66 MHz

80 MHz

27

28

30

28

30

32

29

32

34

32

35

38

20

27

13

3

mA

µA

CE# = V , OE# = V , WE#

IL

IH

= V , burst length = 8

IH

CE# = V , OE# = V , WE#

IL

IH

= V , burst length = 16

IH

I

V

Active burst Read Current

CCB

CC

CE# = V , OE# = V , WE#

IL

IH

= V , burst length = 32

IH

CE# = V , OE# = V , WE#

IL

IH

= V , burst length =

IH

Continuous

I

V

Non-active Output

OE# = V

IH

IO1

IO

10 MHz

5 MHz

1 MHz

mA

µA

Active Asynchronous

CE# = V , OE# = V , WE#

CC

IL

IH

I

CC1

= V

Read Current (4)

IH

V

1

5

ACC

CE# = V , OE# = V , ACC

IL

IH

I

V

Active Write Current (5)

Standby Current (6, 7)

CC2

CC3

CC

= V

IH

V

19

1

52.5

5

mA

µA

CC

V

ACC

CE# = RESET# =

± 0.2 V

V

CC

V

20

70

40

150

µA

CC

I

V

Reset Current (7)

Active Current

RESET# = V CLK = V

IL

µA

CC4

CC5

CC6

CC

IL,

CE# = V , OE# = V , ACC = V

@

IL

IH

50

60

mA

5 MHz

(Read While Write) (7)

V

Sleep Current (7)

CE# = V , OE# = V

IL

2

6

40

20

µA

mA

V

CC

IH

V

CE# = V , OE# = V

IL

ACC

IH,

I

Accelerated Program Current (8)

ACC

V

= 9.5 V

ACC

V

14

20

CC

V

Input Low Voltage

V

= 1.8 V

–0.5

0.4

IL

IO

V

Input High Voltage

V

– 0.4

V

+ 0.4

V

IH

IO

V

Output Low Voltage

I

= 100 µA, V = V

= V

IO

0.1

V

OL

OH

HH

OL

OH

CC

CC min

V

Output High Voltage

Voltage for Accelerated Program

= –100 µA, V = V

= V

IO

– 0.1

8.5

1.0

V

CC

CC min

IO

9.5

1.4

V

Low V Lock-out Voltage

V

LKO

CC

Notes:

1. Maximum I specifications are tested with V = V max.

CC

2.

3. CE# must be set high when measuring the RDY pin.

4. The I current listed is typically less than 3 mA/MHz, with OE# at V

V

= V .

CC IO

.

IH

CC

5.

I

active while Embedded Erase or Embedded Program is in progress.

CC

6. Device enters automatic sleep mode when addresses are stable for t

+ 20 ns. Typical sleep mode current is equal to

ACC

I

.

CC3

7.

V

= V ± 0.2 V and V > –0.1 V.

IH CC IL

8. Total current during accelerated programming is the sum of V

and V currents.

ACC

CC

9.

V

= V

on ACC input.

HH

ACC

10. The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document

is Preliminary for the S29W256N.

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12.8 AC Characteristics

12.8.1 CLK Characterization

Parameter

f_CLK

Description

CLK Frequency

54 MHz

54

66 MHz

66

80 MHz

80

Unit

MHz

ns

Max

Min

t_CLK

t_CH

CLK Period

18.5

15.1

12.5

CLK High Time

CLK Low Time

CLK Rise Time

CLK Fall Time

Min

7.4

3

6.1

3

5.0

2.5

ns

t_CL

t_CR

Max

t_CF

Note: The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document

is Preliminary for the S29W256N.

t

CLK

t

CL

CH

CLK

t

CF

CR

Figure 12.6 CLK Characterization

12.8.2 Synchronous/Burst Read

Parameter

JEDEC

Standard

t_IACC

t_BACC

t_ACS

t_ACH

t_BDH

t_CR

Description

54 MHz

66 MHz

80

80 MHz

Unit

ns

Latency

Max

Burst Access Time Valid Clock to Output Delay Max

13.5

5

11.2

9

Address Setup Time to CLK (Note 1)

Address Hold Time from CLK (Note 1)

Data Hold Time from Next Clock Cycle

Chip Enable to RDY Valid

Min

Max

Min

Max

Min

Max

4

6

3

7

4

13.5

11.2

9

t_OE

Output Enable to Output Valid

Chip Enable to High Z (Note 2)

Output Enable to High Z (Note 2)

CE# Setup Time to CLK

11.2

t_CEZ

10

4

t_OEZ

t_CES

t_RDYS

t_RACC

t_CAS

t_AVC

RDY Setup Time to CLK

5

4

3.5

9

Ready Access Time from CLK

CE# Setup Time to AVD#

AVD# Low to CLK

13.5

11.2

0

4

t_AVD

t_AOE

AVD# Pulse

8

AVD Low to OE# Low

38.4

Notes:

1. Addresses are latched on the first rising edge of CLK.

2. Not 100% tested.

3. The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document

is Preliminary for the S29W256N.

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12.8.3 Timing Diagrams

5 cycles for initial access shown.

18.5 ns typ. (54 MHz)

t_CEZ

t_CES

CE#

CLK

1

2

3

4

5

6

7

t_AVC

AVD#

t_AVD

t_ACS

Addresses

Data (n)

Aa

t_BACC

t_ACH

Hi-Z

t_IACC

Da

Da + 1

Da + 2

Da + n

t_OEZ

Da + 3

t_AOE

t_BDH

OE#

t_RACC

t_OE

Hi-Z

RDY (n)

t_CR

t_RDYS

Hi-Z

Data (n + 1)

RDY (n + 1)

Da

Da + 1

Da + 2

Da + n

Da + 2

Hi-Z

Data (n + 2)

RDY (n + 2)

Da

Da + 1

Da + n

Da + 1

Hi-Z

Data (n + 3)

Da

Da + n

Da

Hi-Z

RDY (n + 3)

Notes:

1. Figure shows total number of wait states set to five cycles. The total number of wait states can be programmed from two

cycles to seven cycles.

2. If any burst address occurs at address + 1 , address + 2, or address + 3, additional clock delay cycles are inserted, and

are indicated by RDY.

3. The device is in synchronous mode.

Figure 12.7 CLK Synchronous Burst Mode Read

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7 cycles for initial access shown.

t_CES

CE#

CLK

1

2

3

4

5

6

7

t_AVC

AVD#

t_AVD

t_ACS

Ac

Addresses

Data

t_BACC

t_ACH

t_IACC

DC

DD

DE

DF

D8

DB

t_BDH

t_AOE

OE#

RDY

t_CR

t_RACC

t_OE

Hi-Z

t_RDYS

Notes:

1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from

two cycles to seven cycles.

2. If any burst address occurs at address + 1 , address + 2, or address + 3, additional clock delay cycles are inserted, and

are indicated by RDY.

3. The device is in synchronous mode with wrap around.

4. D8–DF in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting

address in figure is the 4th address in range (0-F).

Figure 12.8 8-word Linear Burst with Wrap Around

7 cycles for initial access shown.

t_CES

CE#

1

2

3

4

5

6

7

CLK

t_AVC

AVD#

t_AVD

t_ACS

Ac

Addresses

Data

t_BACC

t_ACH

t_IACC

DC

DD

DE

DF

D10

D13

t_AOE

t_BDH

OE#

RDY

t_CR

t_RACC

t_OE

Hi-Z

t_RDYS

Notes:

1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from

two cycles to seven cycles. Clock is set for active rising edge.

2. If any burst address occurs at address + 1 , address + 2, or address + 3, additional clock delay cycles are inserted, and

are indicated by RDY.

3. The device is in asynchronous mode with out wrap around.

4. DC–D13 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest.

Starting address in figure is the 1st address in range (c-13).

Figure 12.9 8-word Linear Burst without Wrap Around

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t_CEZ

6 wait cycles for initial access shown.

t_CES

CE#

CLK

1

2

3

4

5

6

t_AVC

AVD#

t_AVD

t_ACS

Aa

Addresses

Data

t_BACC

t_ACH

Hi-Z

t_IACC

Da

Da+1

Da+2

Da+3

Da + n

t_BDH

t_AOE

t_OEZ

t_RACC

OE#

RDY

t_CR

t_OE

Hi-Z

t_RDYS

Notes:

1. Figure assumes 6 wait states for initial access and synchronous read.

2. The Set Configuration Register command sequence has been written with CR8=0; device outputs RDY one cycle before

valid data.

Figure 12.10 Linear Burst with RDY Set One Cycle Before Data

12.8.4 AC Characteristics—Asynchronous Read

Parameter

Description

54 MHz 66 MHz 80 MHz Unit

JEDEC Standard

t_CE

t_ACC

Access Time from CE# Low

Max

Min

Max

Min

Max

Min

80

8

ns

Asynchronous Access Time

t_AVDP

t_AAVDS

t_AAVDH

t_OE

AVD# Low Time

Address Setup Time to Rising Edge of AVD#

Address Hold Time from Rising Edge of AVD#

Output Enable to Output Valid

4

7

6

13.5

0

Read

Output Enable Hold Time

Data# Polling

t_OEH

10

0

t_OEZ

t_CAS

Output Enable to High Z (see Note)

CE# Setup Time to AVD#

Notes:

1. Not 100% tested.

2. The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document

is Preliminary for the S29W256N.

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A d v a n c e I n f o r m a t i o n

CE#

OE#

t_OE

t_OEH

WE#

Data

t_CE

t_OEZ

Valid RD

t_ACC

RA

Addresses

AVD#

t_AAVDH

t_CAS

t_AVDP

t_AAVDS

Note: RA = Read Address, RD = Read Data.

Figure 12.11 Asynchronous Mode Read

12.8.5 Hardware Reset (RESET#)

Parameter

JEDEC

Std.

Description

All Speed Options

Unit

µs

t_RP

t_RH

RESET# Pulse Width

Reset High Time Before Read (See Note)

Min

30

200

ns

Notes:

1. Not 100% tested.

2. The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document

is Preliminary for the S29W256N.

CE#, OE#

t_RH

RESET#

t_RP

Figure 12.12 Reset Timings

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12.8.6 Erase/Program Timing

Parameter

Description

Write Cycle Time (Note 1)

54 MHz 66 MHz 80 MHz Unit

JEDEC Standard

t

Min

80

5

ns

AVAV

WC

Synchronous

Asynchronous

Synchronous

Asynchronous

t

Address Setup Time (Notes 2, 3)

Address Hold Time (Notes 2, 3)

AVWL

AS

0

9

t

Min

ns

WLAX

AH

20

8

t

AVD# Low Time

Min

Max

Typ

ns

µs

ns

µs

AVDP

t

Data Setup Time

45

20

DVWH

DS

DH

t

Data Hold Time

0

WHDX

t

Read Recovery Time Before Write

CE# Setup Time to AVD#

CE# Hold Time

GHWL

t

0

CAS

t

0

WHEH

WLWH

WHWL

CH

t

Write Pulse Width

30

20

0

WP

t

Write Pulse Width High

WPH

t

Latency Between Read and Write Operations

SR/W

t

V

Rise and Fall Time

500

1

VID

ACC

t

Setup Time (During Accelerated Programming)

VIDS

t

Setup Time

CC

50

5

VCS

t

CE# Setup Time to WE#

ELWL

CS

t

AVD# Setup Time to WE#

5

AVSW

AVHW

t

AVD# Hold Time to WE#

5

t

AVD# Setup Time to CLK

5

AVSC

AVHC

t

AVD# Hold Time to CLK

5

t

Clock Setup Time to WE#

5

CSW

t

Noise Pulse Margin on WE#

Sector Erase Accept Time-out

Erase Suspend Latency

3

WEP

t

50

20

100

1

SEA

t

ESL

PSL

ASP

t

Program Suspend Latency

t

Toggle Time During Sector Protection

Toggle Time During Programming Within a Protected Sector

t

PSP

Notes:

1. Not 100% tested.

2. Asynchronous read mode allows Asynchronous program operation only. Synchronous read mode allows both

Asynchronous and Synchronous program operation.

3. In asynchronous program operation timing, addresses are latched on the falling edge of WE#. In synchronous program

operation timing, addresses are latched on the rising edge of CLK.

4. See the Erase and Programming Performance section for more information.

5. Does not include the preprogramming time.

6. The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document

is Preliminary for the S29W256N.

March 14, 2005 S70WS512N00_00_A0

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A d v a n c e I n f o r m a t i o n

Erase Command Sequence (last two cycles)

Read Status Data

V

IH

CLK

V

IL

t_AVDP

AVD#

t_AH

t_AS

SA

555h for

chip erase

VA

Addresses

Data

2AAh

10h for

chip erase

In

Complete

55h

30h

Progress

t_DS

t_DH

CE#

t_CH

OE#

WE#

t_WP

t_WHWH2

t_CS

t_WPH

t_WC

t_VCS

V_CC

Figure 12.13 Chip/Sector Erase Operation Timings

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Program Command Sequence (last two cycles)

Read Status Data

V

IH

CLK

AVD

V

IL

t_AVSW

t_AVHW

t_AVDP

t_AS

t_AH

Addresses

Data

555h

PA

VA

In

Progress

A0h

t_DS

Complete

PD

t_CAS

t_DH

CE#

t_CH

OE#

WE#

t_WP

t_WHWH1

t_CS

t_WPH

t_WC

t_VCS

V_CC

Notes:

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.

2. In progress and complete refer to status of program operation.

3. A23–A14 for the WS256N (A22–A14 for the WS128N, A21–A14 for the WS064N) are don’t care during command

sequence unlock cycles.

4. CLK can be either V or V

.

IH

IL

5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Configuration Register.

Figure 12.14 Asynchronous Program Operation Timings

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Program Command Sequence (last two cycles)

t_AVCH

Read Status Data

CLK

t_AS

t_AH

t_AVSC

AVD#

t_AVDP

Addresses

Data

PA

VA

555h

In

Progress

Complete

A0h

PD

t_DS

t_DH

t_CAS

CE#

t_CH

OE#

WE#

t_CSW

t_WP

t_WHWH1

t_WPH

t_WC

t_VCS

V_CC

Notes:

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.

2. In progress and complete refer to status of program operation.

3. A23–A14 for the WS256N (A22–A14 for the WS128N, A21–A14 for the WS064N) are don’t care during command

sequence unlock cycles.

4. Addresses are latched on the first rising edge of CLK.

5. Either CE# or AVD# is required to go from low to high in between programming command sequences.

6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register.

The Configuration Register must be set to the Synchronous Read Mode.

Figure 12.15 Synchronous Program Operation Timings

CE#

AVD#

WE#

Addresses

Data

PA

Don't Care

A0h

Don't Care

PD

Don't Care

OE#

ACC

t_VIDS

V

ID

t_VID

or V

IH

IL

Note: Use setup and hold times from conventional program operation.

Figure 12.16 Accelerated Unlock Bypass Programming Timing

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AVD#

CE#

t_CEZ

t_CE

t_OEZ

t_CH

t_OE

OE#

WE#

t_OEH

t_ACC

VA

High Z

Addresses

VA

Status Data

Data

Notes:

1. Status reads in figure are shown as asynchronous.

2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is

completeData# Polling outputs true data.

Figure 12.17 Data# Polling Timings (During Embedded Algorithm)

AVD#

t_CEZ

t_CE

CE#

t_OEZ

t_CH

t_OE

OE#

WE#

t_OEH

t_ACC

High Z

Addresses

VA

Data

Status Data

Notes:

1. Status reads in figure are shown as asynchronous.

2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is

complete, .

Figure 12.18 Toggle Bit Timings (During Embedded Algorithm)

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A d v a n c e I n f o r m a t i o n

CE#

CLK

AVD#

Addresses

OE#

VA

t_IACC

Data

Status Data

RDY

Notes:

1. The timings are similar to synchronous read timings.

2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is

complete, .

3. RDY is active with data (D8 = 1 in the Configuration Register). When D8 = 0 in the Configuration Register, RDY is active

one clock cycle before data.

Figure 12.19 Synchronous Data Polling Timings/Toggle Bit Timings

Enter

Erase

Suspend

Enter Erase

Suspend Program

Embedded

Erasing

Erase

Resume

Erase

Erase Suspend

Read

Erase

WE#

Erase

Erase Suspend

Read

Suspend

Program

Complete

DQ6

DQ2

Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to

toggle DQ2 and DQ6

Figure 12.20 DQ2 vs. DQ6

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Address boundary occurs every 128 words, beginning at address

00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.

C124

C125

7D

C126

7E

C127

7F

C127

7F

C128

80

C129

81

C130

82

C131

83

CLK

7C

Address (hex)

(stays high)

AVD#

t_RACC

RDY(1)

latency

t_RACC

RDY(2)

Data

latency

D124

D125

D126

D127

D128

D129

D130

OE#,

CE#

(stays low)

Notes:

1. RDY(1) active with data (D8 = 1 in the Configuration Register).

2. RDY(2) active one clock cycle before data (D8 = 0 in the Configuration Register).

3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60.

4. Figure shows the device not crossing a bank in the process of performing an erase or program.

5. RDY does not go low and no additional wait states are required if the Burst frequency is <=66 MHz and the Boundary

Crossing bit (D14) in the Configuration Register is set to 0

Figure 12.21 Latency with Boundary Crossing when Frequency > 66 MHz

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Address boundary occurs every 128 words, beginning at address

00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.

C124

C125

7D

C126

7E

C127

7F

C127

7F

CLK

7C

Address (hex)

(stays high)

AVD#

t_RACC

RDY(1)

latency

t_RACC

RDY(2)

Data

latency

D124

D125

D126

D127

Read Status

OE#,

CE#

(stays low)

Notes:

1. RDY(1) active with data (D8 = 1 in the Configuration Register).

2. RDY(2) active one clock cycle before data (D8 = 0 in the Configuration Register).

3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60.

4. Figure shows the device crossing a bank in the process of performing an erase or program.

5. RDY does not go low and no additional wait states are required if the Burst frequency is < 66 MHz and the Boundary

Crossing bit (D14) in the Configuration Register is set to 0.

Figure 12.22 Latency with Boundary Crossing into Program/Erase Bank

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Data

D0

D1

Rising edge of next clock cycle

following last wait state triggers

next burst data

AVD#

OE#

total number of clock cycles

following addresses being latched

1

2

0

3

1

4

5

6

4

7

5

CLK

2

3

number of clock cycles

programmed

Wait State Configuration Register Setup:

D13, D12, D11 = 111 ⇒ Reserved

D13, D12, D11 = 110 ⇒ Reserved

D13, D12, D11 = 101 ⇒ 5 programmed, 7 total

D13, D12, D11 = 100 ⇒ 4 programmed, 6 total

D13, D12, D11 = 011 ⇒ 3 programmed, 5 total

D13, D12, D11 = 010 ⇒ 2 programmed, 4 total

D13, D12, D11 = 001 ⇒ 1 programmed, 3 total

D13, D12, D11 = 000 ⇒ 0 programmed, 2 total

Note: 6.Figure assumes address D0 is not at an address boundary, and wait state is set to 101

Figure 12.23 Example of Wait State Insertion

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Last Cycle in

Program or

Sector Erase

Read status (at least two cycles) in same bank

and/or array data from other bank

Begin another

write or program

command sequence

Command Sequence

t_WC

t_RC

t_WC

CE#

OE#

t_OE

t_OEH

t_GHWL

WE#

Data

t_WPH

t_OEZ

t_WP

t_DS

t_ACC

t_OEH

t_DH

PD/30h

RD

AAh

t_SR/W

RA

Addresses

PA/SA

t_AS

RA

555h

AVD#

t_AH

Note: Breakpoints in waveforms indicate that system may alternately read array data from the non-busy bank while check-

ing the status of the program or erase operation in the busy bank. The system should read status twice to ensure

valid information.

Figure 12.24 Back-to-Back Read/Write Cycle Timings

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12.8.7 Erase and Programming Performance

Parameter

Typ (Note 1)

0.6

Max (Note 2)

Unit

Comments

64 Kword

16 Kword

V_CC

3.5

2

Sector Erase Time

s

<0.15

153.6 (WS256N)

77.4 (WS128N)

39.3 (WS064N)

308 (WS256N)

154 (WS128N)

78 (WS064N)

Excludes 00h

programming prior

to erasure (Note 4)

V_CC

Chip Erase Time

s

130.6 (WS256N)

65.8 (WS128N)

33.4 (WS064N)

262 (WS256N)

132 (WS128N)

66 (WS064N)

ACC

V_CC

ACC

V_CC

ACC

V_CC

ACC

40

24

400

240

94

Single Word Programming Time

(Note 8)

µs

9.4

6

Effective Word Programming Time

utilizing Program Write Buffer

60

300

192

3000

1920

Total 32-Word Buffer Programming

Time

157.3 (WS256N)

78.6 (WS128N)

39.3 (WS064N)

314.6 (WS256N)

157.3 (WS128N)

78.6 (WS064N)

V_CC

Excludes system

level overhead

(Note 5)

Chip Programming Time (Note 3)

s

100.7 (WS256N)

50.3 (WS128N)

25.2 (WS064N)

201.3 (WS256N)

100.7 (WS128N)

50.3 (WS064N)

ACC

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 1.8 V V , 10,000 cycles; checkerboard data

CC

pattern.

2. Under worst case conditions of 90°C, V = 1.70 V, 100,000 cycles.

CC

3. Typical chip programming time is considerably less than the maximum chip programming time listed, and is based on

utilizing the Write Buffer.

4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command.

See the Appendix for further information about command definitions.

6. Contact the local sales office for minimum cycling endurance values in specific applications and operating conditions.

7. Refer to Application Note Erase Suspend/Resume Timing for more details.

8. Word programming specification is based upon a single word programming operation not utilizing the write buffer.

9. The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document

is Preliminary for the S29W256N.

March 14, 2005 S70WS512N00_00_A0

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12.8.8 BGA Ball Capacitance

Parameter Symbol

Parameter Description

Test Setup

Typ.

5.3

5.8

6.3

Max

6.3

6.8

7.3

Unit

pF

C

Input Capacitance

Output Capacitance

Control Pin Capacitance

V

= 0

IN

C

V

pF

OUT

C

V

pF

IN2

IN

Notes:

1. Sampled, not 100% tested.

2. Test conditions T = 25°C; f = 1.0 MHz.

A

3. The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document

is Preliminary for the S29W256N.

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13 Appendix

This section contains information relating to software control or interfacing with the Flash device.

For additional information and assistance regarding software, see the Additional Resources on

page 18, or explore the Web at www.amd.com and www.fujitsu.com.

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Table 13.1 Memory Array Commands

Bus Cycles (Notes 1–5)

First

Addr

Second

Third

Addr

Fourth

Addr Data

Fifth

Addr

Sixth

Addr Data

Command Sequence

(Notes)

Data

RD

Addr

Data

Asynchronous Read (6)

Reset (7)

Manufacturer ID

1

4

6

RA

XXX

555

F0

AA

2AA

55

[BA]555

90

[BA]X00 0001

[BA]X01 227E

Device ID (9)

AA

BA+X0E

PA

Data

PD

BA+X0F 2200

Indicator Bits (10)

4

555

AA

2AA

55

[BA]555

90

[BA]X03

Data

Program

4

6

1

3

6

1

4

1

3

2

1

555

SA

555

BA

AA

29

AA

B0

30

AA

98

AA

A0

98

2AA

55

555

PA

A0

25

PA

PD

Write to Buffer (11)

Program Buffer to Flash

Write to Buffer Abort Reset (12)

Chip Erase

WC

WBL

PD

2AA

55

555

F0

80

555

AA

2AA

55

555

SA

10

30

Sector Erase

Erase/Program Suspend (13)

Erase/Program Resume (14)

Set Configuration Register (18)

Read Configuration Register

CFI Query (15)

BA

555

[BA]555

555

XXX

2AA

55

555

D0

C6

X00

CR

Entry

Program (16)

2AA

PA

55

PD

555

20

CFI (16)

Reset

2

XXX

90

XXX

00

Entry

3

4

1

555

00

AA

Data

2AA

55

555

88

A0

Program (17)

Read (17)

PA

PD

00

Exit (17)

4

555

AA

2AA

55

555

90

XXX

Legend:

X = Don’t care.

RA = Read Address.

RD = Read Data.

PA = Program Address. Addresses latch on the rising edge of the

AVD# pulse or active edge of CLK, whichever occurs first.

SA = Sector Address. WS256N = A23–A14; WS128N = A22–A14;

WS064N = A21–A14.

BA = Bank Address. WS256N = A23–A20; WS128N = A22–A20;

WS064N = A21–A18.

CR = Configuration Register data bits D15–D0.

WBL = Write Buffer Location. Address must be within the same write

buffer page as PA.

PD = Program Data. Data latches on the rising edge of WE# or CE#

pulse, whichever occurs first.

WC = Word Count. Number of write buffer locations to load minus 1.

Notes:

1. See Table 8.1 for description of bus operations.

2. All values are in hexadecimal.

11. Total number of cycles in the command sequence is determined

by the number of words written to the write buffer.

12. Command sequence resets device for next command after write-

to-buffer operation.

13. System may read and program in non-erasing sectors, or enter

the autoselect mode, when in the Erase Suspend mode. The

Erase Suspend command is valid only during a sector erase

operation, and requires the bank address.

14. Erase Resume command is valid only during the Erase Suspend

mode, and requires the bank address.

15. Command is valid when device is ready to read array data or

when device is in autoselect mode. Address equals 55h on all

future devices, but 555h for WS256N/128N/064N.

3. Shaded cells indicate read cycles.

4. Address and data bits not specified in table, legend, or notes are

don’t cares (each hex digit implies 4 bits of data).

5. Writing incorrect address and data values or writing them in the

improper sequence may place the device in an unknown state.

The system must write the reset command to return the device

to reading array data.

6. No unlock or command cycles required when bank is reading

array data.

7. Reset command is required to return to reading array data (or to

the erase-suspend-read mode if previously in Erase Suspend)

when a bank is in the autoselect mode, or if DQ5 goes high

(while the bank is providing status information) or performing

sector lock/unlock.

16. Requires Entry command sequence prior to execution. Unlock

Bypass Reset command is required to return to reading array

data.

17. Requires Entry command sequence prior to execution. Secured

Silicon Sector Exit Reset command is required to exit this mode;

device may otherwise be placed in an unknown state.

8. The system must provide the bank address. See Autoselect

section for more information.

9. Data in cycle 5 is 2230 (WS256N), 2232 (WS064N), or 2231

(WS128N).

18. Requires reset command to configure the Configuration Register.

10. See Table 8.9 for indicator bit values.

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Table 13.2 Sector Protection Commands

Bus Cycles (Notes 1–4)

First

Second

Third

Fourth

Fifth

Sixth

Seventh

Command Sequence

(Notes)

Addr

Data

AA

Addr

Data

55

Addr

Data

Addr Data Addr Data Addr Data Addr Data

Command Set Entry (5)

3

2

1

2

3

2

4

7

2

3

2

1

2

3

2

1

555

XX

2AA

555

40

Lock

Register

Bits

Program (6, 12)

Read (6)

A0

77/00

data

77

data

90

Command Set Exit (7)

Command Set Entry (5)

Program [0-3] (8)

Read (9)

XX

2AA

00

55

PWD[0-3]

PWD1

03

555

XX

AA

A0

555

60

Password

Protection

0...00 PWD0 0...01

0...02

00

PWD2 0...03 PWD3

Unlock

00

XX

555

XX

SA

XX

555

XX

BA

25

90

00

XX

PWD0

01

PWD1

02

PWD2

03

PWD3

00

29

Command Set Exit (7)

Command Set Entry (5)

PPB Program (10)

All PPB Erase (10, 11)

PPB Status Read

00

AA

2AA

SA

55

[BA]555

C0

A0

80

00

Non-Volatile

Sector

Protection (PPB)

00

30

RD(0)

90

Command Set Exit (7)

Command Set Entry (5)

PPB Lock Bit Set

XX

2AA

XX

00

55

00

Global

Volatile Sector

Protection

Freeze

AA

[BA]555

50

E0

A0

PPB Lock Bit Status Read

RD(0)

Command Set Exit (7)

2

XX

90

XX

00

(PPB Lock)

Command Set Entry (5)

DYB Set

3

2

1

2

555

XX

SA

XX

AA

A0

2AA

SA

55

00

01

Volatile Sector

Protection

(DYB)

DYB Clear

DYB Status Read

Command Set Exit (7)

A0

SA

RD(0)

90

XX

00

Legend:

X = Don’t care.

RA = Address of the memory location to be read.

PD(0) = Secured Silicon Sector Lock Bit. PD(0), or bit[0].

PD(1) = Persistent Protection Mode Lock Bit. PD(1), or bit[1], must

be set to ‘0’ for protection while PD(2), bit[2] must be left as ‘1’.

PD(2) = Password Protection Mode Lock Bit. PD(2), or bit[2], must

be set to ‘0’ for protection while PD(1), bit[1] must be left as ‘1’.

BA = Bank Address. WS256N = A23–A20; WS128N = A22–A20;

WS064N = A21–A18.

PWD3–PWD0 = Password Data. PD3–PD0 present four 16 bit

combinations that represent the 64-bit Password

PWA = Password Address. Address bits A1 and A0 are used to select

each 16-bit portion of the 64-bit entity.

PWD = Password Data.

RD(0), RD(1), RD(2) = DQ0, DQ1, or DQ2 protection indicator bit. If

protected, DQ0, DQ1, or DQ2 = 0. If unprotected, DQ0, DQ1,

DQ2 = 1.

PD(3) = Protection Mode OTP Bit. PD(3) or bit[3].

SA = Sector Address. WS256N = A23–A14; WS128N = A22–A14;

WS064N = A21–A14.

Notes:

1. All values are in hexadecimal.

2. Shaded cells indicate read cycles.

currently 77h for the WS256N only. See Table 9.1 and Table 9.2

for explanation of lock bits.

7. Exit command must be issued to reset the device into read

mode; device may otherwise be placed in an unknown state.

3. Address and data bits not specified in table, legend, or notes are

don’t cares (each hex digit implies 4 bits of data).

4. Writing incorrect address and data values or writing them in the

improper sequence may place the device in an unknown state.

The system must write the reset command to return the device

to reading array data.

5. Entry commands are required to enter a specific mode to enable

instructions only available within that mode.

6. If both the Persistent Protection Mode Locking Bit and the

Password Protection Mode Locking Bit are set at the same time,

the command operation aborts and returns the device to the

default Persistent Sector Protection Mode during 2nd bus cycle.

Note that on all future devices, addresses equal 00h, but is

8. Entire two bus-cycle sequence must be entered for each portion

of the password.

9. Full address range is required for reading password.

10. See Figure 9.2 for details.

11. The All PPB Erase command pre-programs all PPBs before

erasure to prevent over-erasure.

12. The second cycle address for the lock register program operation

is 77 for S29Ws256N; however, for WS128N and Ws064N this

address is 00.

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13.1 Common Flash Memory Interface

The Common Flash Interface (CFI) specification outlines device and host system software inter-

rogation handshake, which allows specific vendor-specified soft-ware algorithms to be used for

entire families of devices. Software support can then be device-independent, JEDEC ID-indepen-

dent, and forward- and back-ward-compatible for the specified flash device families. Flash

vendors can standardize their existing interfaces for long-term compatibility.

This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to

address (BA)555h any time the device is ready to read array data. The system can read CFI in-

formation at the addresses given in Tables 13.3–13.6) within that bank. All reads outside of the

CFI address range, within the bank, returns non-valid data. Reads from other banks are allowed,

writes are not. To terminate reading CFI data, the system must write the reset command.

The following is a C source code example of using the CFI Entry and Exit functions. Refer to

the Spansion Low Level Driver User’s Guide (available on www.amd.com and

www.fujitsu.com) for general information on Spansion Flash memory software development

guidelines.

/* Example: CFI Entry command */

*( (UINT16 *)bank_addr + 0x555 ) = 0x0098;

/* write CFI entry command

/* write cfi exit command

*/

/* Example: CFI Exit command */

*( (UINT16 *)bank_addr + 0x000 ) = 0x00F0;

For further information, please refer to the CFI Specification (see JEDEC publications JEP137-A

and JESD68.01and CFI Publication 100). Please contact your sales office for copies of these

documents.

Table 13.3 CFI Query Identification String

Addresses

Data

Description

10h

11h

12h

0051h

0052h

0059h

Query Unique ASCII string QRY

13h

14h

0002h

0000h

Primary OEM Command Set

15h

16h

0040h

0000h

Address for Primary Extended Table

17h

18h

0000h

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

19h

1Ah

0000h

Table 13.4 System Interface String

Addresses

Data

Description

V

Min. (write/erase)

CC

1Bh

0017h

D7–D4: volt, D3–D0: 100 millivolt

V

Max. (write/erase)

CC

1Ch

0019h

D7–D4: volt, D3–D0: 100 millivolt

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

0000h

0006h

0009h

000Ah

0000h

0004h

0003h

0000h

V

Min. voltage (00h = no V pin present)

PP

Max. voltage (00h = no V pin present)

PP

Typical timeout per single byte/word write 2^Nµs

Typical timeout for Min. size buffer write 2^Nµs (00h = not supported)

Typical timeout per individual block erase 2^Nms

Typical timeout for full chip erase 2^Nms (00h = not supported)

Max. timeout for byte/word write 2^Ntimes typical

Max. timeout for buffer write 2^Ntimes typical

Max. timeout per individual block erase 2^Ntimes typical

Max. timeout for full chip erase 2^Ntimes typical (00h = not supported)

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Table 13.5 Device Geometry Definition

Addresses

Data

Description

0019h (WS256N)

0018h (WS128N)

0017h (WS064N)

Device Size = 2^Nbyte

27h

28h

29h

0001h

0000h

Flash Device Interface description (refer to CFI publication 100)

Max. number of bytes in multi-byte write = 2^N

(00h = not supported)

2Ah

2Bh

0006h

0000h

2Ch

0003h

Number of Erase Block Regions within device

2Dh

2Eh

2Fh

30h

0003h

0000h

0080h

0000h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

00FDh (WS256N)

007Dh (WS128N)

003Dh (WS064N)

31h

Erase Block Region 2 Information

32h

33h

34h

0000h

0002h

35h

36h

37h

38h

0003h

0000h

0080h

0000h

Erase Block Region 3 Information

Erase Block Region 4 Information

39h

3Ah

3Bh

3Ch

0000h

Table 13.6 Primary Vendor-Specific Extended Query

Addresses

Data

Description

40h

41h

42h

0050h

0052h

0049h

Query-unique ASCII string PRI

43h

44h

0031h

0034h

Major version number, ASCII

Minor version number, ASCII

Address Sensitive Unlock (Bits 1-0), 0 = Required, 1 = Not Required

Silicon Technology (Bits 5-2) 0100 = 0.11 µm

45h

46h

47h

48h

49h

0100h

0002h

0001h

0000h

0008h

Erase Suspend,

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

Sector Protect,

0 = Not Supported, X = Number of sectors in per group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

08 = Advanced Sector Protection

00F3h (WS256N)

007Bh (WS128N)

003Fh (WS064N)

Simultaneous Operation

Number of Sectors in all banks except boot bank

4Ah

Burst Mode Type

00 = Not Supported, 01 = Supported

4Bh

4Ch

4Dh

0001h

0000h

0085h

Page Mode Type,

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page, 04 = 16 Word Page

ACC (Acceleration) Supply Minimum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

ACC (Acceleration) Supply Maximum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

Top/Bottom Boot Sector Flag

4Eh

0095h

4Fh

50h

0001h

0001h = Dual Boot Device

Program Suspend. 00h = not supported

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Table 13.6 Primary Vendor-Specific Extended Query (Continued)

Addresses

51h

Data

0001h

0007h

Description

Unlock Bypass, 00 = Not Supported, 01=Supported

Secured Silicon Sector (Customer OTP Area) Size 2^Nbytes

52h

Hardware Reset Low Time-out during an embedded

algorithm to read mode Maximum 2^Nns

53h

54h

0014h

Hardware Reset Low Time-out not during an embedded

algorithm to read mode Maximum 2^Nns

55h

56h

57h

0005h

Erase Suspend Time-out Maximum 2^Nns

Program Suspend Time-out Maximum 2^Nns

Bank Organization: X = Number of banks

0010h

0013h (WS256N)

58h

59h

5Ah

5Bh

5Ch

5Dh

5Eh

5Fh

60h

61h

62h

63h

64h

65h

66h

67h

000Bh (WS128N) Bank 0 Region Information. X = Number of sectors in bank

0007h (WS064N)

0010h (WS256N)

0008h (WS128N)

0004h (WS064N)

Bank 1 Region Information. X = Number of sectors in bank

Bank 2 Region Information. X = Number of sectors in bank

0010h (WS256N)

0008h (WS128N)

0004h (WS064N)

0010h (WS256N)

0008h (WS128N) Bank 3 Region Information. X = Number of sectors in bank

0004h (WS064N)

0010h (WS256N)

0008h (WS128N)

0004h (WS064N)

Bank 4 Region Information. X = Number of sectors in bank

Bank 5 Region Information. X = Number of sectors in bank

Bank 6 Region Information. X = Number of sectors in bank

Bank 7 Region Information. X = Number of sectors in bank

Bank 8 Region Information. X = Number of sectors in bank

Bank 9 Region Information. X = Number of sectors in bank

Bank 10 Region Information. X = Number of sectors in bank

0010h (WS256N)

0008h (WS128N)

0004h (WS064N)

0010h (WS256N)

0008h (WS128N)

0004h (WS064N)

0010h (WS256N)

0008h (WS128N)

0004h (WS064N)

0010h (WS256N)

0008h (WS128N)

0004h (WS064N)

0010h (WS256N)

0008h (WS128N)

0004h (WS064N)

0010h (WS256N)

0008h (WS128N)

0004h (WS064N)

0010h (WS256N)

0008h (WS128N) Bank 11 Region Information. X = Number of sectors in bank

0004h (WS064N)

0010h (WS256N)

0008h (WS128N)

0004h (WS064N)

Bank 12 Region Information. X = Number of sectors in bank

Bank 13 Region Information. X = Number of sectors in bank

0010h (WS256N)

0008h (WS128N)

0004h (WS064N)

0010h (WS256N)

0008h (WS128N) Bank 14 Region Information. X = Number of sectors in bank

0004h (WS064N)

0013h (WS256N)

000Bh (WS128N)

0007h (WS064N)

Bank 15 Region Information. X = Number of sectors in bank

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A d v a n c e I n f o r m a t i o n

14 Commonly Used Terms

Ter m

D efi niti on

ACCelerate. A special purpose input signal which allows for faster programming or

erase operation when raised to a specified voltage above V_CC. In some devices ACC

may protect all sectors when at a low voltage.

ACC

Most significant bit of the address input [A23 for 256Mbit, A22 for128Mbit, A21 for

64Mbit]

A_max

A_min

Least significant bit of the address input signals (A0 for all devices in this document).

Operation where signal relationships are based only on propagation delays and are

unrelated to synchronous control (clock) signal.

Asynchronous

Read mode for obtaining manufacturer and device information as well as sector

protection status.

Autoselect

Bank

Section of the memory array consisting of multiple consecutive sectors. A read

operation in one bank, can be independent of a program or erase operation in a

different bank for devices that offer simultaneous read and write feature.

Smaller size sectors located at the top and or bottom of Flash device address space.

The smaller sector size allows for finer granularity control of erase and protection for

code or parameters used to initiate system operation after power-on or reset.

Boot sector

Boundary

Burst Read

Byte

Location at the beginning or end of series of memory locations.

See synchronous read.

8 bits

Common Flash Interface. A Flash memory industry standard specification [JEDEC 137-

A and JESD68.01] designed to allow a system to interrogate the Flash to determine its

size, type and other performance parameters.

CFI

Clear

Zero (Logic Low Level)

Special purpose register which must be programmed to enable synchronous read

mode

Configuration Register

Synchronous method of burst read whereby the device reads continuously until it is

stopped by the host, or it has reached the highest address of the memory array, after

which the read address wraps around to the lowest memory array address

Continuous Read

Erase

Returns bits of a Flash memory array to their default state of a logical One (High Level).

Halts an erase operation to allow reading or programming in any sector that is not

selected for erasure

Erase Suspend/Erase Resume

Ball Grid Array package. Spansion LLC offers two variations: Fortified Ball Grid Array

and Fine-pitch Ball Grid Array. See the specific package drawing or connection diagram

for further details.

BGA

Synchronous (burst) read operation in which 8, 16, or 32 words of sequential data with

Linear Read

or without wraparound before requiring a new initial address

.

Multi-Chip Package. A method of combining integrated circuits in a single package by

stacking multiple die of the same or different devices.

MCP

Memory Array

MirrorBit™ Technology

The programmable area of the product available for data storage.

Spansion™ trademarked technology for storing multiple bits of data in the same

transistor.

March 14, 2005 S70WS512N00_00_A0

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91

A d v a n c e I n f o r m a t i o n

Ter m

D efi niti on

Group of words that may be accessed more rapidly as a group than if the words were

accessed individually.

Page

Asynchronous read operation of several words in which the first word of the group

takes a longer initial access time and subsequent words in the group take less page

access time to be read. Different words in the group are accessed by changing only the

least significant address lines.

Page Read

Sector protection method which uses a programmable password, in addition to the

Password Protection

Persistent Protection

Program

Persistent Protection method, for protection of sectors in the Flash memory device

.

Sector protection method that uses commands and only the standard core voltage

supply to control protection of sectors in the Flash memory device. This method

replaces a prior technique of requiring a 12V supply to control the protection method.

Stores data into a Flash memory by selectively clearing bits of the memory array in

order to leave a data pattern of ones and zeros.

Program Suspend/Program

Resume

Halts a programming operation to read data from any location that is not selected for

programming or erase.

Read

Host bus cycle that causes the Flash to output data onto the data bus.

Dynamic storage bits for holding device control information or tracking the status of

an operation.

Registers

Secured Silicon. An area consisting of 256 bytes in which any word may be

programmed once, and the entire area may be protected once from any future

programming. Information in this area may be programmed at the factory or by the

user. Once programmed and protected there is no way to change the secured

information. This area is often used to store a software readable identification such as

a serial number.

Secured Silicon

Use of one or more control bits per sector to indicate whether each sector may be

programmed or erased. If the Protection bit for a sector is set the embedded

algorithms for program or erase ignores program or erase commands related to that

sector.

Sector Protection

Sector

An Area of the memory array in which all bits must be erased together by an erase

operation.

Mode of operation in which a host system may issue a program or erase command to

one bank, that embedded algorithm operation may then proceed while the host

immediately follows the embedded algorithm command with reading from another

bank. Reading may continue concurrently in any bank other than the one executing

the embedded algorithm operation.

Simultaneous Operation

Operation that progresses only when a timing signal, known as a clock, transitions

between logic levels (that is, at a clock edge).

Synchronous Operation

VersatileIO™ (V_IO)

Separate power supply or voltage reference signal that allows the host system to set

the voltage levels that the device generates at its data outputs and the voltages

tolerated at its data inputs.

Mode that facilitates faster program times by reducing the number of command bus

cycles required to issue a write operation command. In this mode the initial two Unlock

write cycles, of the usual 4 cycle Program command, are not required – reducing all

Program commands to two bus cycles while in this mode.

Unlock Bypass

Word

Two contiguous bytes (16 bits) located at an even byte boundary. A double word is two

contiguous words located on a two word boundary. A quad word is four contiguous

words located on a four word boundary.

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A d v a n c e I n f o r m a t i o n

Ter m

D efi niti on

Special burst read mode where the read address wraps or returns back to the lowest

address boundary in the selected range of words, after reading the last Byte or Word

in the range, e.g. for a 4 word range of 0 to 3, a read beginning at word 2 would read

words in the sequence 2, 3, 0, 1.

Wraparound

Interchangeable term for a program/erase operation where the content of a register

and or memory location is being altered. The term write is often associated with writing

command cycles to enter or exit a particular mode of operation.

Write

Multi-word area in which multiple words may be programmed as a single operation. A

Write Buffer

Write Buffer may be 16 to 32 words long and is located on a 16 or 32 word boundary

respectively.

Method of writing multiple words, up to the maximum size of the Write Buffer, in one

Write Buffer Programming

Write Operation Status

operation. Using Write Buffer Programming results in

time than by using single word at a time programming commands.

≥

8 times faster programming

Allows the host system to determine the status of a program or erase operation by

reading several special purpose register bits

.

March 14, 2005 S70WS512N00_00_A0

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93

A d v a n c e I n f o r m a t i o n

15 Revisions

Revision A0 (March 14, 2005)

Initial Release

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary

industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that

includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal

injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,

medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and

artificial satellite). Please note that Spansion LLC will not be liable to you and/or any third party for any claims or damages arising in connection with above-

mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such

failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels

and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on ex-

port under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the

prior authorization by the respective government entity will be required for export of those products.

Trademarks and Notice

The contents of this document are subject to change without notice. This document may contain information on a Spansion LLC product under development

by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided

as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement

of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the

use of the information in this document.

names used in this publication are for identification purposes only and may be trademarks of their respective companies.

94

S70WS512N00 Based MCPs

S70WS512N00_00_A0 March 14, 2005


型号：	S70WS512N00BAWA23
厂家：	SPANSION
描述：	Same-Die Stacked Multi-Chip Product (MCP) 512 Megabit (32M x 16 bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst-mode Flash Memory 同模堆叠式多芯片产品（ MCP ） 512兆位（ 32M ×16位） CMOS 1.8伏只同步读/写，突发模式闪存闪存
文件：	总93页 (文件大小：1075K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

S70WS512N00BAWA23 [SPANSION]

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