S71AL016M40BFW0F0 [SPANSION]
Memory Circuit, 1MX16, CMOS, PBGA56, 7 X 9 MM, 1.20 MM HEIGHT, LEAD FREE, VFBGA-56;
| 型号： | S71AL016M40BFW0F0 |
| 厂家： | 
SPANSION |
| 描述： | Memory Circuit, 1MX16, CMOS, PBGA56, 7 X 9 MM, 1.20 MM HEIGHT, LEAD FREE, VFBGA-56 静态存储器 内存集成电路 |
| 文件： | 总68页 (文件大小：1726K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S71AL016M Based MCPs
Stacked Multi-Chip Product (MCP) Flash Memory and
RAM
16 Megabit (1 M x 16-bit) CMOS 3.0 Volt-only
Flash Memory and 4 Megabit (256K x 16-bit) Static RAM/
Pseudo Static RAM
ADVANCE
INFORMATION
Notice to Readers: The Advance Information status indicates that this
document contains information on one or more products under development
at Spansion LLC. The information is intended to help you evaluate this product.
Do not design in this product without contacting the factory. Spansion LLC
reserves the right to change or discontinue work on this proposed product
without notice.
Publication Number S71AL016M_00 Revision A Amendment 0 Issue Date February 23, 2005
This page intentionally left blank.
S71AL016M based MCPs
Stacked Multi-Chip Product (MCP) Flash Memory and
RAM
16 Megabit (1 M x 16-bit) CMOS 3.0 Volt-only Flash
Memory and 4 Megabit (256K x 16-bit) Static RAM/
Pseudo Static RAM
ADVANCE
INFORMATION
Distinctive Characteristics
Packages
— 7 x 9 x 1.2 mm 56 ball FBGA
MCP Features
Power supply voltage of 2.7 to 3.1 volt
Operating Temperature
High performance
— –25°C to +85°C (Wireless)
— 90 ns
General Description
The S71AL series is a product line of stacked Multi-Chip Product (MCP) packages
and consists of:
One S29AL Flash memory die
pSRAM or SRAM
The products covered by this document are listed in the table below:
Flash Memory Density
16Mb
SRAM / pSRAM Density
4Mb
S71AL016M40
Publication Number S71AL016M_00_A0 Revision A Amendment 0 Issue Date February 23, 2005
A d v a n c e I n f o r m a t i o n
Notice On Data Sheet Designations
Spansion LLC issues data sheets with Advance Information or Preliminary designa-
tions to advise readers of product information or intended specifications throughout
the product life cycle, including development, qualification, initial production, and full
production. In all cases, however, readers are encouraged to verify that they have the
latest information before finalizing their design. The following descriptions of Spansion
data sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion LLC is developing one
or more specific products, but has not committed any design to production. Informa-
tion presented in a document with this designation is likely to change, and in some
cases, development on the product may discontinue. Spansion LLC therefore places
the following conditions upon Advance Information content:
“This document contains information on one or more products under development
at Spansion LLC. The information is intended to help you evaluate this product. Do
not design in this product without contacting the factory. Spansion LLC reserves
the right to change or discontinue work on this proposed product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed
such that a commitment to production has taken place. This designation covers sev-
eral aspects of the product life cycle, including product qualification, initial production,
and the subsequent phases in the manufacturing process that occur before full pro-
duction is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under con-
sideration. Spansion places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion
product(s) described herein. The Preliminary status of this document indicates that
product qualification has been completed, and that initial production has begun.
Due to the phases of the manufacturing process that require maintaining efficiency
and quality, this document may be revised by subsequent versions or modifications
due to changes in technical specifications.”
Combination
Some data sheets will contain a combination of products with different designations
(Advance Information, Preliminary, or Full Production). This type of document will dis-
tinguish these products and their designations wherever necessary, typically on the
first page, the ordering information page, and pages with DC Characteristics table and
AC Erase and Program table (in the table notes). The disclaimer on the first page re-
fers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or
only nominal changes are expected, the Preliminary designation is removed from the
data sheet. Nominal changes may include those affecting the number of ordering part
numbers available, such as the addition or deletion of a speed option, temperature
range, package type, or VIO range. Changes may also include those needed to clarify
a description or to correct a typographical error or incorrect specification. Spansion
LLC applies the following conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion
product(s) described herein. Spansion LLC deems the products to have been in suf-
ficient production volume such that subsequent versions of this document are not
expected to change. However, typographical or specification corrections, or modi-
fications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local AMD
or Fujitsu sales office.
4
S71AL016M based MCPs
S71AL016M_00_A0 February 23, 2005
A d v a n c e I n f o r m a t i o n
Table of Contents
RY/BY#: Ready/Busy# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
DQ6: Toggle Bit I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
DQ2: Toggle Bit II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Reading Toggle Bits DQ6/DQ2 . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 8. Toggle Bit Algorithm............................................ 42
DQ5: Exceeded Timing Limits . . . . . . . . . . . . . . . . . . . . . . . . . .42
DQ3: Sector Erase Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Table 11. Write Operation Status . . . . . . . . . . . . . . . . . . . . 43
Figure 9. Maximum Negative Overshoot Waveform ............... 44
Figure 10. Maximum Positive Overshoot Waveform............... 44
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 12. CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 11. Test Setup ....................................................... 46
Table 13. Test Specifications . . . . . . . . . . . . . . . . . . . . . . . 46
Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . .46
Figure 12. Input Waveforms and Measurement Levels........... 46
Table 14. Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 13. Read Operations Timings.................................... 47
Table 15. Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . 48
Figure 14. RESET# Timings ............................................... 48
Figure 15. Program Operation Timings ................................ 50
Figure 16. Chip/Sector Erase Operation Timings ................... 51
Figure 17. Data# Polling Timings
(During Embedded Algorithms) .......................................... 52
Figure 18. Toggle Bit Timings
(During Embedded Algorithms) .......................................... 52
Figure 19. DQ2 vs. DQ6 for Erase and
S71AL016M based MCPs ............................. 3
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .6
16 Mb Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .7
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . .8
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 10
Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . 11
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 12
S29AL016M .................................................13
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . 13
General Description . . . . . . . . . . . . . . . . . . . . . . . . 14
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 1. S29AL016M Device Bus Operations . . . . . . . . . . . . .17
Requirements for Reading Array Data . . . . . . . . . . . . . . . . . . .17
Writing Commands/Command Sequences . . . . . . . . . . . . . . . 18
Program and Erase Operation Status . . . . . . . . . . . . . . . . . . . 18
Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Automatic Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
RESET#: Hardware Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Output Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 2. Sector Address Tables (Model 01, Top Boot
Device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 3. Sector Address Tables (Model 02, Bottom Boot
Device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Autoselect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 4. Autoselect Codes (High Voltage Method) . . . . . . . . .22
Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . 22
Temporary Sector Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 1. Temporary Sector Unprotect Operation................... 23
Figure 2. In-System Single High Voltage Sector Protect/
Erase Suspend Operations................................................. 53
Table 16. Temporary Sector Unprotect . . . . . . . . . . . . . . . . 53
Figure 20. Temporary Sector Unprotect/Timing Diagram........ 53
Figure 21. Sector Protect/Unprotect Timing Diagram............. 54
Table 17. Alternate CD# Controlled Erase/Program
Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 22. Alternate CE# Controlled Write Operation T
imings ............................................................................ 56
Table 18. Erase and Programming Performance . . . . . . . . . . 57
Table 19. TSOP Pin and BGA Package Capcitance . . . . . . . . . 57
Unprotect Algorithms ........................................................ 24
SecSi (Secured Silicon) Sector Flash Memory Region . . . . . . . 25
Table 5. SecSi Sector Addressing . . . . . . . . . . . . . . . . . . . . .25
Figure 3. SecSi Sector Protect Verify ................................... 26
Common Flash Memory Interface (CFI) . . . . . . . . . . . . . . . . . 26
Table 6. CFI Query Identification String . . . . . . . . . . . . . . . .27
Table 7. System Interface String . . . . . . . . . . . . . . . . . . . . .27
Table 8. Device Geometry Definition . . . . . . . . . . . . . . . . . .28
Table 9. Primary Vendor-Specific Extended Query . . . . . . . . .28
Type 4 pSRAM .......................................... 59
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Functional Description. . . . . . . . . . . . . . . . . . . . . . 59
Product Portfolio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . 60
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 20. DC Electrical Characteristics (Over the
Hardware Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Reading Array Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Autoselect Command Sequence . . . . . . . . . . . . . . . . . . . . . . . 30
Word Program Command Sequence . . . . . . . . . . . . . . . . . . . .31
Figure 4. Program Operation .............................................. 32
Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . 32
Sector Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . 33
Erase Suspend/Erase Resume Commands . . . . . . . . . . . . . . . . 33
Figure 5. Erase Operation .................................................. 35
Program Suspend/Program Resume Command Sequence . . . 35
Figure 6. Program Suspend/Program Resume....................... 36
Table 10. Command Definitions . . . . . . . . . . . . . . . . . . . . . .37
DQ7: Data# Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 7. Data# Polling Algorithm ....................................... 39
Operating Range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . .61
AC Test Loads and Waveforms . . . . . . . . . . . . . . .61
Figure 23. AC Test Loads and Waveforms............................ 61
Table 21. Switching Characteristics . . . . . . . . . . . . . . . . . . . 62
Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . 63
Figure 24. Read Cycle 1 (Address Transition Controlled)........ 63
Figure 25. Read Cycle 2 (OE# Controlled)............................ 63
Figure 26. Write Cycle 1 (WE# Controlled)........................... 64
Figure 27. Write Cycle 2 (CE#1 or CE2 Controlled) ............... 65
Figure 28. Write Cycle 3 (WE# Controlled, OE# Low)............ 66
Figure 29. Write Cycle 4 (BHE#/BLE# Controlled, OE# Low) .. 66
Truth Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . 68
February 23, 2005 S71AL016M_00_A0_A0
S71AL016M based MCPs
5
A d v a n c e I n f o r m a t i o n
Product Selector Guide
16 Mb Flash Memory
Device-Model#
S71AL016M40-0B
S71AL016M40-0F
Flash Access time (ns)
pSRAM density
4 M pSRAM
4 M pSRAM
(p)SRAM Access time (ns) pSRAM type Package
90
90
70
70
pSRAM4
pSRAM4
TLC056
TLC056
6
S71AL016M based MCPs
S71AL016M_00_A0 February 23, 2005
A d v a n c e I n f o r m a t i o n
MCP Block Diagram
VCC
f
VCC
CE#f
Flash 1
RST#f
Flash-only Address
A19-A18
A17-A0
Shared Address
OE#
WE#
RY/BY#
DQ15 to DQ0
VCCS
VCC
A17-A0
pSRAM/SRAM
IO15-IO0
CE1#s
UB#
CE1#
UB#
LB#
LB#
CE2s
CE2
February 23, 2005 S71AL016M_0M_A0
S71AL016M
7
A d v a n c e I n f o r m a t i o n
Connection Diagram
56-ball Fine-Pitch Ball Grid Array
(Top View, Balls Facing Down)
Legend
A2
A7
A3
LB#
B3
A4
RFU
A5
WE#
B5
A6
A8
A7
A11
B7
B1
A3
B2
B4
B8
A15
C8
B6
A19
C6
Flash only
RAM only
A6
UB#
C3
RST#f
C4
CE2s
C5
A12
C7
C1
C2
A2
A5
A18
D3
RY/BY#
RFU
A9
A13
D7
RFU
D8
D1
D2
D6
A1
A4
A17
E3
A10
E6
A14
E7
RFU
E8
Reserved for
Future Use
E1
E2
A0
VSS
F2
DQ1
F3
DQ6
F6
RFU
F7
A16
F8
F1
F4
DQ3
G4
F5
DQ4
G5
Shared
CE1#f
G1
OE#
G2
DQ9
G3
DQ13
G6
DQ15
G7
RFU
G8
CE1#s
DQ0
H2
DQ10
H3
VCCf
H4
VCCs
H5
DQ12
H6
DQ7
H7
VSS
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
MCP
Flash Only Address
Shared Addresses
A17 - A0
S71AL016M40
A19 - A18
8
S71AL016M
S71AL016M_0M_A0 February 23, 2005
A d v a n c e I n f o r m a t i o n
Pin Description
A17–A0
A19–A18
DQ15–DQ0
CE1#f
CE1#s
CE2s
=
=
=
=
=
=
=
=
=
=
=
=
=
Address Inputs (Common)
Address Inputs (Flash-only)
16 Data Inputs/Outputs (Common)
Chip Enable 1 (Flash)
Chip Enable 1 (pSRAM)
Chip Enable 2 (pSRAM)
OE#
WE#
Output Enable (Common)
Write Enable (Common)
RY/BY#
UB#
LB#
Ready/Busy Output (Flash-only)
Upper Byte Control (pSRAM)
Lower Byte Control (pSRAM)
Hardware Reset Pin, Active Low (Flash)
Flash 3.0 volt-only single power supply (see Product
Selector Guide for speed options and voltage supply
tolerances)
RST#f
VCC
f
VCC
VSS
NC
s
=
=
=
=
pSRAM Power Supply
Device Ground (Common)
Pin Not Connected Internally
Reserved for Future Use
RFU
Logic Symbol
18
A17–A0
A19–A18
16
DQ15–DQ0
CE#
CE1#s
CE2s
RY/BY#
OE#
WE#
RST#f
UB#
LB#
February 23, 2005 S71AL016M_0M_A0
S71AL016M
9
A d v a n c e I n f o r m a t i o n
Ordering Information
The order number is formed by a valid combinations of the following:
S71AL
016
M
40 BA
W
0
F
0
PACKING TYPE
0
2
3
=
=
=
Tray
7” Tape and Reel
13” Tape and Reel
MODEL NUMBER
See the Valid Combinations table.
Package Modifier
0
= 7x9x1.2mm, 56-ball
TEMPERATURE RANGE
Wireless (-25 C to +85 C)
W
=
°
°
PACKAGE TYPE
BA
BF
=
=
Fine-pitch BGA Lead (Pb)-free compliant package
Fine-pitch BGA Lead (Pb)-free package
SRAM DENSITY
40 4Mb pSRAM
=
PROCESS TECHNOLOGY
230 nm, MirrorBit Technology
M
=
FLASH DENSITY
016 16Mb
=
PRODUCT FAMILY
S71AL Multi-chip Product (MCP)
3.0-volt Flash Memory and RAM
10
S71AL016M
S71AL016M_0M_A0 February 23, 2005
A d v a n c e I n f o r m a t i o n
Valid Combinations
S71AL016D Valid Combinations
(p)SRAM
Type/Access
Time (ns)
Base Ordering
Part Number
Package &
Temperature
Package Modifier/
Model Number
Speed Options
(ns)
Package
Marking
Packing Type
Bottom-Boot
Top-Boot
S71AL016M40
S71AL016M40
0B
0F
pSRAM4/ 70
pSRAM4 / 70
(Note 2)
BAW,
BFW
90
Notes:
Valid Combinations
1. Type 0 is standard. Specify other options as required.
2. BGA package marking omits leading S and packing type
designator from ordering part number.
Valid Combinations list configurations planned to be supported in vol-
ume for this device. Consult your local sales office to confirm avail-
ability of specific valid combinations and to check on newly released
combinations.
February 23, 2005 S71AL016M_0M_A0
S71AL016M
11
A d v a n c e I n f o r m a t i o n
Physical Dimensions
TLC056—56-ball Fine-Pitch Ball Grid Array (FBGA)
9 x 7 mm Package
A
D1
D
eD
0.15
(2X)
C
8
7
6
5
4
3
2
1
SE
7
E
B
E1
eE
H
G
F
E
D
C
B
A
INDEX MARK
10
PIN A1
CORNER
PIN A1
CORNER
7
SD
0.15
(2X)
C
TOP VIEW
BOTTOM VIEW
0.20
0.08
C
C
A2
A
C
A1
SIDE VIEW
6
56X
b
0.15
M
C
C
A
B
0.08
M
NOTES:
PACKAGE
JEDEC
TLC 056
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
9.00 mm x 7.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
---
NOM
---
MAX
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
1.20
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.20
0.81
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
0.97
BODY THICKNESS
BODY SIZE
D
9.00 BSC.
7.00 BSC.
5.60 BSC.
5.60 BSC.
8
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
E1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
8
56
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
φb
0.35
0.40
0.45
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
eE
0.80 BSC.
0.80 BSC
0.40 BSC.
BALL PITCH
eD
SD / SE
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SOLDER BALL PLACEMENT
A1,A8,D4,D5,E4,E5,H1,H8
DEPOPULATED SOLDER BALLS
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3348 \ 16-038.22a
12
S71AL016M
S71AL016M_0M_A0 February 23, 2005
S29AL016M
16 Megabit (M x 16-Bit)
3.0 Volt-only Boot Sector Flash Memory
Featuring MirrorBitTM Te c hn o l og y
ADVANCE
INFORMATION
MCP Flash Module
Performance Characteristics
Distinctive Characteristics
Architectural Advantages
High performance
— 90/100 ns access time
— 0.7 s typical sector erase time
Single power supply operation
— 3 V for read, erase, and program operations
Manufactured on 0.23 µm MirrorBitTM process
technology
SecSiTM (Secured Silicon) Sector region
— 128-word sector for permanent, secure identification
through an 8-word random Electronic Serial Number,
accessible through a command sequence
Low power consumption (typical values at 5 MHz)
— 400 nA standby mode current
— 15 mA read current
— 40 mA program/erase current
— 400 nA Automatic Sleep mode current
Software Features
— May be programmed and locked at the factory or by
the customer
— Program Suspend & Resume: read other sectors
before programming operation is completed
— Erase Suspend & Resume: read/program other
sectors before an erase operation is completed
— Data# polling & toggle bits provide status
— Unlock Bypass Program command reduces overall
multiple-word programming time
— CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
Flexible sector architecture
— One 8 Kword, two 4 Kword, one 16 Kword, and thirty-
one 32 Kword sectors (word mode)
Compatibility with JEDEC standards
— Provides pinout and software compatibility for single-
power supply flash, and superior inadvertent write
protection
Top or bottom boot block configurations available
100,000 erase cycle typical per sector
20-year typical data retention
Hardware Features
— Sector Protection: hardware-level method of
preventing write operations within a sector
— Temporary Sector Unprotect: VID-level method of
changing code in locked sectors
— Hardware reset input (RESET#) resets device
— Ready/Busy# output (RY/BY#) indicates program or
erase cycle completion
Publication Number S71AL016M_M0 Revision A Amendment 0 Issue Date February 23, 2005
A d v a n c e I n f o r m a t i o n
General Description
The S29AL016M is a 16 Mbit, 3.0 Volt-only Flash memory organized as
1,048,576 words. The word-wide data (x16) appears on DQ15–DQ0. The device
requires only a single 3.0 volt power supply for both read and write func-
tions, designed to be programmed in-system with the standard system 3.0 volt
VCC supply. The device can also be programmed in standard
EPROM programmers.
To eliminate bus contention the device contains separate chip enable (CE#),
write enable (WE#) and output enable (OE#) controls.
The device is entirely command set compatible with the JEDEC single-power-
supply Flash standard. Commands are written to the device using standard
microprocessor write timing. Write cycles also internally latch addresses and
data needed for the programming and erase operations.
The sector erase architecture allows memory sectors to be erased and repro-
grammed without affecting the data contents of other sectors. The device is fully
erased when shipped from the factory.
Device programming and erasure are initiated through command sequences.
Once a program or erase operation begins, the host system need only poll the
DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy#
(RY/BY#) output to determine whether the operation is complete. To facilitate
programming, an Unlock Bypass mode reduces command sequence overhead
by requiring only two write cycles to program data instead of four.
Hardware data protection measures include a low VCC detector that automat-
ically inhibits write operations during power transitions. The hardware sector
protection feature disables both program and erase operations in any combina-
tion of sectors of memory. This can be achieved in-system or via programming
equipment.
The Erase Suspend/Erase Resume feature allows the host system to pause
an erase operation in a given sector to read or program any other sector and
then complete the erase operation. The Program Suspend/Program Resume
feature enables the host system to pause a program operation in a given sector
to read any other sector and then complete the program operation.
The hardware RESET# pin terminates any operation in progress and resets
the device, after which it is then ready for a new operation. The RESET# pin
may be tied to the system reset circuitry. A system reset would thus also reset
the device, enabling the host system to read boot-up firmware from the Flash
memory device.
The device reduces power consumption in the standby mode when it detects
specific voltage levels on CE# and RESET#, or when addresses are stable for a
specified period of time.
The SecSi™ (Secured Silicon) Sector provides a 128-word area for code or
data that can be permanently protected. Once this sector is protected, no fur-
ther changes within the sector can occur.
MirrorBit flash technology combines years of Flash memory manufacturing ex-
perience to produce the highest levels of quality, reliability and cost
effectiveness. The device electrically erases all bits within a sector simulta-
neously via hot-hole assisted erase. The data is programmed using hot electron
injection.
14
S71AL016M
S71AL016M_M0 A0 February 23, 2005
A d v a n c e I n f o r m a t i o n
Product Selector Guide
Family Part Number
S29AL016M
Speed Option
Full Voltage Range: VCC = 2.7–3.6 V
90
100
100
100
25
Max access time (ns)
Max CE# access time (ns)
Max OE# access time (ns)
90
90
25
Notes:
1. See AC Characteristics on page 47 for full specifications.
2. Contact sales office or representative for availability and ordering information.
Block Diagram
DQ15–DQ0 (A-1)
RY/BY#
VCC
Sector Switches
VSS
Erase Voltage
Generator
Input/Output
Buffers
RESET#
WE#
State
Control
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE#
OE#
Y-Decoder
Y-Gating
STB
VCC Detector
Timer
Cell Matrix
X-Decoder
A19–A0
February 23, 2005 S71AL016M_M0_A0
S71AL016M
15
A d v a n c e I n f o r m a t i o n
Pin Configuration
A19–A0
DQ14–DQ0
DQ15/A-1
CE#
OE#
WE#
RESET#
RY/BY#
VCC
=
20 addresses
=
=
=
=
=
=
=
=
15 data inputs/outputs
DQ15 (data input/output, word mode),
Chip enable
Output enable
Write enable
Hardware reset pin
Ready/Busy output
3.0 volt-only single power supply
(see Product Selector Guide for speed
options and voltage supply tolerances)
VSS
NC
=
=
Device ground
Pin not connected internally
Logic Symbol
20
A19–A0
16
DQ15–DQ0
(A-1)
CE#
OE#
WE#
RESET#
RY/BY#
16
S71AL016M
S71AL016M_M0 A0 February 23, 2005
A d v a n c e I n f o r m a t i o n
Device Bus Operations
This section describes the requirements and use of the device bus operations,
which are initiated through the internal command register. The command regis-
ter itself does not occupy any addressable memory location. The register is
composed of latches that store the commands, along with the address and data
information needed to execute the command. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the
function of the device. Table 1 lists the device bus operations, the inputs and
control levels they require, and the resulting output. The following subsections
describe each of these operations in further detail.
Table 1. S29AL016M Device Bus Operations
Addresses
(Note 1)
DQ00–
Operation
CE#
OE#
WE#
RESET#
DQ15
DOUT
DIN
Read
Write
L
L
L
H
L
H
H
AIN
AIN
H
VCC
0.3 V
VCC
0.3 V
Standby
X
X
X
High-Z
Output Disable
Reset
L
H
X
H
X
H
L
X
X
High-Z
High-Z
X
Sector Address,
A6 = L, A1 = H,
A0 = L
Sector Protect (Note 2)
L
H
L
VID
DIN
Sector Address,
A6 = H, A1 = H,
A0 = L
Sector Unprotect (Note 2)
L
H
X
L
VID
VID
DIN
DIN
Temporary Sector
Unprotect
X
X
AIN
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT
= Data Out
Notes:
1. Addresses are A19:A0 in word mode.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE#
pins to VIL. CE# is the power control and selects the device. OE# is the output
control and gates array data to the output pins. WE# should remain at VIH.
The internal state machine is set for reading array data upon device power-up,
or after a hardware reset. This ensures that no spurious alteration of the mem-
ory content occurs during the power transition. No command is necessary in this
mode to obtain array data. Standard microprocessor read cycles that assert
valid addresses on the device address inputs produce valid data on the device
data outputs. The device remains enabled for read access until the command
register contents are altered.
See Reading Array Data on page 29 for more information. Refer to Table 14 on
page 47 for timing specifications and to Figure 13, on page 47 for the timing di-
agram. ICC1 in the DC Characteristics table represents the active current
specification for reading array data.
February 23, 2005 S71AL016M_M0_A0
S71AL016M
17
A d v a n c e I n f o r m a t i o n
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data
to the device and erasing sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
The device features an Unlock Bypass mode to facilitate faster programming.
Once the device enters the Unlock Bypass mode, only two write cycles are re-
quired to program a word, instead of four. The Word Program Command
Sequence on page 31 contains details on programming data to the device using
both standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device.
Tables 2 and 3 indicate the address space that each sector occupies. A “sector
address” consists of the address bits required to uniquely select a sector. The
Command Definitions on page 29 contains details on erasing a sector or the en-
tire chip, or suspending/resuming the erase operation.
After the system writes the autoselect command sequence, the device enters
the autoselect mode. The system can then read autoselect codes from the inter-
nal register (which is separate from the memory array) on DQ7–DQ0. Standard
read cycle timings apply in this mode. Refer to the Autoselect Mode on page 22
and Autoselect Command Sequence on page 30 sections for more information.
ICC2 in the DC Characteristics table represents the active current specification
for the write mode. The AC Characteristics on page 47 section contains timing
specification tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may check the status of the
operation by reading the status bits on DQ7–DQ0. Standard read cycle timings
and ICC read specifications apply. Refer to Write Operation Status on page 38
for more information, and to AC Characteristics on page 47 for timing
diagrams.
Standby Mode
When the system is not reading or writing to the device, it can place the device
in the standby mode. In this mode, current consumption is greatly reduced, and
the outputs are placed in the high impedance state, independent of the OE#
input.
The device enters the CMOS standby mode when the CE# and RESET# pins are
both held at VCC 0.3 V. (Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are held at VIH, but not within VCC 0.3 V, the device
is in the standby mode, but the standby current is greater. The device requires
standard access time (tCE) for read access when the device is in either of these
standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws ac-
tive current until the operation is completed.
In the DC Characteristics table, ICC3 and ICC4 represents the standby current
specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The de-
vice automatically enables this mode when addresses remain stable for tACC
+
30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE#
control signals. Standard address access timings provide new data when ad-
dresses are changed. While in sleep mode, output data is latched and always
18
S71AL016M
S71AL016M_M0 A0 February 23, 2005
A d v a n c e I n f o r m a t i o n
available to the system. ICC4 in the DC Characteristics table represents the auto-
matic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading
array data. When the system drives the RESET# pin to VIL for at least a period
of tRP, the device immediately terminates any operation in progress, tristates
all data output pins, and ignores all read/write attempts for the duration of the
RESET# pulse. The device also resets the internal state machine to reading
array data. The operation that was interrupted should be reinitiated once the de-
vice is ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held
at VSS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held
at VIL but not within VSS±0.3 V, the standby current is greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would
thus also reset the Flash memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin re-
mains a “0” (busy) until the internal reset operation is complete, which requires
a time of tREADY (during Embedded Algorithms). The system can thus monitor
RY/BY# to determine whether the reset operation is complete. If RESET# is as-
serted when a program or erase operation is not executing (RY/BY# pin is “1”),
the reset operation is completed within a time of tREADY (not during Embedded
Algorithms). The system can read data tRH after the RESET# pin returns to VIH.
Refer to the AC Characteristics on page 47 tables for RESET# parameters and
to Figure 14, on page 48 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output
pins are placed in the high impedance state.
February 23, 2005 S71AL016M_M0_A0
S71AL016M
19
A d v a n c e I n f o r m a t i o n
Table 2. Sector Address Tables (Model 01, Top Boot Device)
Address Range (in
Sector Size
(Kbytes/
Kwords)
hexadecimal)
Sector A19 A18 A17 A16 A15 A14 A13 A12
Word Mode (x16)
000000–007FFF
008000–00FFFF
010000–017FFF
018000–01FFFF
020000–027FFF
028000–02FFFF
030000–037FFF
038000–03FFFF
040000–047FFF
048000–04FFFF
050000–057FFF
058000–05FFFF
060000–067FFF
068000–06FFFF
070000–077FFF
078000–07FFFF
080000–087FFF
088000–08FFFF
090000–097FFF
098000–09FFFF
0A0000–0A7FFF
0A8000–AFFFF
0B0000–0B7FFF
0B8000–0BFFFF
0C0000–0C7FFF
0C8000–0CFFFF
0D0000–0D7FFF
0D8000–0DFFFF
0E0000–0E7FFF
0E8000–0EFFFF
0F0000–0F7FFF
0F8000–0FBFFF
0FC000–0FCFFF
0FD000–0FDFFF
0FE000–0FFFFF
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
X
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
32/16
8/4
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
8/4
16/8
Note: Address range is A19:A0 in word mode.
20
S71AL016M
S71AL016M_M0 A0 February 23, 2005
A d v a n c e I n f o r m a t i o n
Table 3. Sector Address Tables (Model 02, Bottom Boot Device)
Address Range (in
hexadecimal)
Sector Size
(Kbytes/
Kwords)
Sector A19 A18 A17 A16 A15 A14 A13 A12
Word Mode (x16)
000000–001FFF
002000–002FFF
003000–003FFF
004000–007FFF
008000–00FFFF
010000–017FFF
018000–01FFFF
020000–027FFF
028000–02FFFF
030000–037FFF
038000–03FFFF
040000–047FFF
048000–04FFFF
050000–057FFF
058000–05FFFF
060000–067FFF
068000–06FFFF
070000–077FFF
078000–07FFFF
080000–087FFF
088000–08FFFF
090000–097FFF
098000–09FFFF
0A0000–0A7FFF
0A8000–0AFFFF
0B0000–0B7FFF
0B8000–0BFFFF
0C0000–0C7FFF
0C8000–0CFFFF
0D0000–0D7FFF
0D8000–0DFFFF
0E0000–0E7FFF
0E8000–0EFFFF
0F0000–0F7FFF
0F8000–0FFFFF
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
16/8
8/4
SA2
8/4
SA3
32/16
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
Note: Address range is A19:A0. n.
February 23, 2005 S71AL016M_M0_A0
S71AL016M
21
A d v a n c e I n f o r m a t i o n
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sec-
tor protection verification, through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment to automatically match
a device to be programmed with its corresponding programming algorithm.
However, the autoselect codes can also be accessed in-system through the com-
mand register.
When using programming equipment, the autoselect mode requires VID (11.5 V
to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in
Table 4. In addition, when verifying sector protection, the sector address must
appear on the appropriate highest order address bits (see Table 2 on page 20
and Table 3 on page 21). Table 4 on page 22 shows the remaining address bits
that are don’t care. When all necessary bits are set as required, the program-
ming equipment may then read the corresponding identifier code on DQ7-DQ0.
To access the autoselect codes in-system, the host system can issue the autose-
lect command via the command register, as shown in Table 10 on page 37 and
Table 11 on page 43. This method does not require VID. See Command
Definitions on page 29 for details on using the autoselect mode.
Table 4. Autoselect Codes (High Voltage Method)
A19 A11
to to
CE# OE# WE# A12 A10 A9
A8
to
A7
A5
to
A2
DQ8
to
A1 A0 DQ15
DQ7
to
DQ0
Description
A6
Manufacturer ID
(Spansion Products)
L
L
L
L
H
H
X
X
X
X
VID
VID
X
X
L
X
X
L
L
L
X
01h
Device ID:
S29AL016M (Model 01)
(Top Boot Block)
22h
X
C4h
C4h
L
L
H
Device ID:
S29AL016M (Model 02)
(Bottom Boot Block)
22h
X
49h
L
L
L
L
H
H
X
X
X
VID
X
X
X
X
L
H
L
49h
X
01h (protected)
Sector Protection
Verification
SA
VID
L
H
00h
(unprotected)
X
83 (factory
locked
03h (not
SecSi Sector Indicator
Bit (DQ7)
L
L
H
X
X
VID
X
H
X
L
H
X
factory locked)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Note: The autoselect codes may also be accessed in-system via command sequences. See Table 10 on page 37 and
Table 11 on page 43.
Sector Protection/Unprotection
The hardware sector protection feature disables both program and erase opera-
tions in any sector. The hardware sector unprotection feature re-enables both
program and erase operations in previously protected sectors.
The device is normally shipped with all sectors unprotected. However, the Ex-
pressFlash™ Service offers the option of programming and protecting sectors at
the factory prior to shipping the device. Contact a sales office or representative
for details.
22
S71AL016M
S71AL016M_M0 A0 February 23, 2005
A d v a n c e I n f o r m a t i o n
It is possible to determine whether a sector is protected or unprotected. See
Autoselect Mode on page 22 for details.
Sector protection and unprotection requires VID on the RESET# pin only, and
can be implemented either in-system or via programming equipment. Figure 2,
on page 24 shows the algorithms and Figure 21, on page 54 shows the timing
diagram. This method uses standard microprocessor bus cycle timing. For sector
unprotect, all unprotected sectors must first be protected prior to the first sector
unprotect write cycle.
Temporary Sector Unprotect
This feature allows temporary unprotection of previously protected sectors to
change data in-system. The Sector Unprotect mode is activated by setting the
RESET# pin to VID. During this mode, formerly protected sectors can be pro-
grammed or erased by selecting the sector addresses. Once VID is removed
from the RESET# pin, all the previously protected sectors are protected again.
Figure 1 shows the algorithm, and Figure 22, on page 56 shows the timing dia-
grams, for this feature.
START
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once again.
Figure 1. Temporary Sector Unprotect Operation
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A d v a n c e I n f o r m a t i o n
START
START
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
PLSCNT = 1
PLSCNT = 1
RESET# = VID
RESET# = VID
Wait 1 ms
Wait 1 ms
unprotect address
No
First Write
No
First Write
Cycle = 60h?
Temporary Sector
Unprotect Mode
Temporary Sector
Unprotect Mode
Cycle = 60h?
Yes
Yes
Set up sector
address
No
All sectors
protected?
Sector Protect:
Yes
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Set up first sector
address
Sector Unprotect:
Wait 150 µs
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
Reset
PLSCNT = 1
Increment
PLSCNT
Wait 15 ms
A1 = 1, A0 = 0
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Read from
sector address
with A6 = 1,
A1 = 1, A0 = 0
Data = 01h?
Yes
No
Yes
Set up
next sector
address
Yes
No
PLSCNT
= 1000?
Protect another
sector?
Data = 00h?
Yes
Device failed
No
Yes
Remove VID
No
from RESET#
Last sector
verified?
Device failed
Write reset
command
Yes
Remove VID
In-System Single
High Voltage
from RESET#
In-System Single
High Voltage
Sector Protect
Algorithm
Sector Protect
complete
Write reset
command
Sector Unprotect
Algorithm
Sector Unprotect
complete
Figure 2. In-System Single High Voltage Sector Protect/Unprotect Algorithms
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SecSi (Secured Silicon) Sector Flash Memory Region
The SecSi (Secured Silicon) Sector feature provides a Flash memory region that
enables permanent part identification through an Electronic Serial Number
(ESN). The SecSi Sector is 256 bytes in length, and uses a SecSi Sector Indica-
tor Bit (DQ7) to indicate whether or not the SecSi Sector is locked when shipped
from the factory. This bit is permanently set at the factory and cannot be
changed, which prevents cloning of a factory locked part. This ensures the secu-
rity of the ESN once the product is shipped to the field.
The device is offered with the SecSi Sector either customer lockable (standard
shipping option) or factory locked (contact a sales office or representative for or-
dering information). The customer-lockable version is shipped with the SecSi
Sector unprotected, allowing customers to program the sector after receiving
the device. The customer-lockable version also contains the SecSi Sector Indica-
tor Bit permanently set to a 0. The factory-locked version is always protected
when shipped from the factory, and contains the SecSi (Secured Silicon) Sector
Indicator Bit permanently set to a 1. Thus, the SecSi Sector Indicator Bit pre-
vents customer-lockable devices from being used to replace devices that are
factory locked. Note that the ACC function and unlock bypass modes are not
available when the SecSi Sector is enabled.
The SecSi sector address space in this device is allocated as follows:
Table 5. SecSi Sector Addressing
SecSi Sector Address Range
ESN Factory
Locked
ExpressFlash
Factory Locked
Customer Lockable
x16
0F8000h–
0F8007h
ESN or determined
by customer
ESN
Determined by
customer
0F8008h–
0F807Fh
Determined
by customer
Unavailable
The system accesses the SecSi Sector through a command sequence (see “En-
ter SecSi Sector/Exit SecSi Sector Command Sequence”). After the system
writes the Enter SecSi Sector command sequence, it may read the SecSi Sector
by using the addresses given in Table 5. This mode of operation continues until
the system issues the Exit SecSi Sector command sequence, or until power is
removed from the device. On power-up, or following a hardware reset, the de-
vice reverts to sending commands to sector SA0.
Customer Lockable: SecSi Sector NOT Programmed or Protected
At the Factory
Unless otherwise specified, the device is shipped such that the customer may
program and protect the 256-byte SecSi sector.
The system may program the SecSi Sector using the write-buffer, accelerated
and/or unlock bypass methods, in addition to the standard programming com-
mand sequence. See Command Definitions.
Programming and protecting the SecSi Sector must be used with caution since,
once protected, there is no procedure available for unprotecting the SecSi Sec-
tor area and none of the bits in the SecSi Sector memory space can be modified
in any way.
The SecSi Sector area can be protected using one of the following procedures:
Write the three-cycle Enter SecSi Sector Region command sequence, and
then follow the in-system sector protect algorithm as shown in Figure 2, on
page 24, except that RESET# may be at either VIH or VID. This allows in-sys-
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A d v a n c e I n f o r m a t i o n
tem protection of the SecSi Sector without raising any device pin to a high
voltage. Note that this method is only applicable to the SecSi Sector.
To verify the protect/unprotect status of the SecSi Sector, follow the algo-
rithm shown in Figure 3, on page 26.
Once the SecSi Sector is programmed, locked and verified, the system must
write the Exit SecSi Sector Region command sequence to return to reading and
writing within the remainder of the array.
Factory Locked: SecSi Sector Programmed and Protected At the
Factory
In devices with an ESN, the SecSi Sector is protected when the device is shipped
from the factory. The SecSi Sector cannot be modified in any way. An ESN Fac-
tory Locked device has a 16-byte random ESN at addresses given in Table 5 on
page 25. Please contact your local sales office or representative for details on or-
dering ESN Factory Locked devices.
Customers may opt to have their code programmed by the manufacturer
through the ExpressFlash service (Express Flash Factory Locked). The devices
are then shipped from the factory with the SecSi Sector permanently locked.
Contact an sales office or representative for details on using the ExpressFlash
service.
START
If data = 00h,
RESET# =
SecSi Sector is
unprotected.
VIH or VID
If data = 01h,
SecSi Sector is
protected.
Wait 1 ms
Write 60h to
any address
Remove VIH or VID
from RESET#
Write 40h to SecSi
Sector address
with A6 = 0,
Write reset
command
A1 = 1, A0 = 0
SecSi Sector
Protect Verify
complete
Read from SecSi
Sector address
with A6 = 0,
A1 = 1, A0 = 0
Figure 3. SecSi Sector Protect Verify
Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system
software interrogation handshake, which allows specific vendor-specified soft-
ware algorithms to be used for entire families of devices. Software support can
then be device-independent, JEDEC ID-independent, and forward- and back-
ward-compatible for the specified flash device families. Flash vendors can
standardize their existing interfaces for long-term compatibility.
26
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A d v a n c e I n f o r m a t i o n
This device enters the CFI Query mode when the system writes the CFI Query
command, 98h, to address 55h anytime the device is ready to read array data.
The system can read CFI information at the addresses given in Table 6 on
page 27, Table 7 on page 27, Table 8 on page 28, and Table 9 on page 28. In
word mode, the upper address bits (A7–MSB) must be all zeros. To terminate
reading CFI data, the system must write the reset command.
The system can also write the CFI query command when the device is in the au-
toselect mode. The device enters the CFI query mode, and the system can read
CFI data at the addresses given in Table 6 on page 27, Table 7 on page 27,
Table 8 on page 28, and Table 9 on page 28. The system must write the reset
command to return the device to the read/reset mode.
For further information, please refer to the CFI Specification and CFI Publication
100, available online at http://www.amd.com/flash/cfi. Alternatively, contact an
sales office or representative for copies of these documents.
Table 6. CFI Query Identification String
Addresses
Data
Description
10h
11h
12h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
0002h
0000h
Primary OEM Command Set
15h
16h
0040h
0000h
Address for Primary Extended Table
17h
18h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
0000h
0000h
Table 7. System Interface String
Addresses
1Bh
Data
0027h
0036h
0000h
0000h
0007h
0000h
000Ah
0000h
0001h
0000h
0004h
0000h
Description
VCC Min. (write/erase). D7–D4: volt, D3–D0: 100 millivolt
VCC Max. (write/erase). D7–D4: volt, D3–D0: 100 millivolt
VPP Min. voltage (00h = no VPP pin present)
1Ch
1Dh
1Eh
VPP Max. voltage (00h = no VPP pin present)
1Fh
Typical timeout per single word write 2N µs
20h
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
Typical timeout per individual block erase 2N ms
21h
22h
Typical timeout for full chip erase 2N ms (00h = not supported)
Reserved for future use
23h
24h
Max. timeout for buffer write 2N times typical (00h = not supported)
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
25h
26h
Note: CFI data related to timeouts may differ from actual timeouts of the product. Consult the Ordering the Erase and
Programming Performance table for timeout guidelines.
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A d v a n c e I n f o r m a t i o n
Table 8. Device Geometry Definition
Addresses
Data
Description
27h
0015h
Device Size = 2N byte
28h
29h
0002h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
0000h
0000h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Ch
0004h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
0000h
0000h
0040h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
0001h
0000h
0020h
0000h
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
35h
36h
37h
38h
0000h
0000h
0080h
0000h
39h
3Ah
3Bh
3Ch
001Eh
0000h
0000h
0001h
Table 9. Primary Vendor-Specific Extended Query (Sheet 1 of 2)
Addresses
Data
Description
40h
41h
42h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
44h
0031h
0033h
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock (Bit 1–0)
0b = Required, 1b = Not Required
45h
0008h
Process Technology (Bits 7–2)
0010b = 0.23 µm MirrorBit
Erase Suspend
46h
47h
48h
49h
4Ah
0002h
0001h
0001h
0004h
0000h
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
04 = Standard Mode
Simultaneous Operation
00 = Not Supported, 01 = Supported
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A d v a n c e I n f o r m a t i o n
Table 9. Primary Vendor-Specific Extended Query (Sheet 2 of 2)
Addresses
Data
Description
Burst Mode Type
00 = Not Supported, 01 = Supported
4Bh
0000h
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
4Ch
0000h
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or eras-
ing provides data protection against inadvertent writes (refer to Table 10 on
page 37 and Table 11 on page 43 for command definitions). In addition, the fol-
lowing hardware data protection measures prevent accidental erasure or
programming, which might otherwise be caused by spurious system level sig-
nals during VCC power-up and power-down transitions, or from system noise.
Low V
Write Inhibit
CC
When VCC is less than VLKO, the device does not accept any write cycles. This
protects data during VCC power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the device resets. Subse-
quent writes are ignored until VCC is greater than VLKO. The system must
provide the proper signals to the control pins to prevent unintentional writes
when VCC is greater than VLKO
.
Write Pulse Glitch Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a
write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# =
VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept
commands on the rising edge of WE#. The internal state machine is automati-
cally reset to reading array data on power-up.
Command Definitions
Writing specific address and data commands or sequences into the command
register initiates device operations. Table 10 on page 37 and Table 11 on
page 43 define the valid register command sequences. Note that writing incor-
rect address and data values or writing them in the improper sequence may
place the device in an unknown state. A reset command is then required to set
the device for the next operation.
All addresses are latched on the falling edge of WE# or CE#, whichever happens
later. All data is latched on the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in AC Characteristics on page 47.
Reading Array Data
The device is automatically set to reading array data after device power-up. No
commands are required to retrieve data. The device is also ready to read array
data after completing an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the
Erase Suspend mode. The system can read array data using the standard read
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A d v a n c e I n f o r m a t i o n
timings, except that if it reads at an address within erase-suspended sectors,
the device outputs status data. After completing a programming operation in the
Erase Suspend mode, the system may once again read array data with the same
exception. See Erase Suspend/Erase Resume Commands on page 33 for more
information on this mode.
The system must issue the reset command to re-enable the device for reading
array data if DQ5 goes high, or while in the autoselect mode. See the “Reset
Command” section, next.
See also Requirements for Reading Array Data on page 17 for more informa-
tion. The Table 14 on page 47 provides the read parameters, and Figure 13, on
page 47 shows the timing diagram.
Reset Command
Writing the reset command to the device resets the device to reading array
data. Address bits are don’t care for this command.
The reset command may be written between the sequence cycles in an erase
command sequence before erasing begins. This resets the device to reading
array data. Once erasure begins, however, the device ignores reset commands
until the operation is complete.
The reset command may be written between the sequence cycles in a program
command sequence before programming begins. This resets the device to read-
ing array data (also applies to programming in Erase Suspend mode). Once
programming begins, however, the device ignores reset commands until the op-
eration is complete.
The reset command may be written between the sequence cycles in an autose-
lect command sequence. Once in the autoselect mode, the reset command must
be written to return to reading array data (also applies to autoselect during
Erase Suspend).
If DQ5 goes high during a program or erase operation, writing the reset com-
mand returns the device to reading array data (also applies during Erase
Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manu-
facturer and devices codes, and determine whether or not a sector is protected.
Table 10 on page 37 and Table 11 on page 43 show the address and data re-
quirements. This method is an alternative to that shown in Table 4 on page 22,
which is intended for PROM programmers and requires VID on address bit A9.
The autoselect command sequence is initiated by writing two unlock cycles, fol-
lowed by the autoselect command. The device then enters the autoselect mode,
and the system may read at any address any number of times, without initiating
another command sequence.
A read cycle at address XX00h retrieves the manufacturer code. A read cycle at
address XX01h returns the device code. A read cycle containing a sector address
(SA) and the address XX02h in word mode returns XX01h if that sector is pro-
tected, or 00h if it is unprotected. Refer to Table 2 on page 20 and Table 3 on
page 21 for valid sector addresses.
The system must write the reset command to exit the autoselect mode and re-
turn to reading array data.
30
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A d v a n c e I n f o r m a t i o n
Word Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is
initiated by writing two unlock write cycles, followed by the program set-up
command. The program address and data are written next, which in turn initiate
the Embedded Program algorithm. The system is not required to provide further
controls or timings. The device automatically generates the program pulses and
verifies the programmed cell margin. Tables 10–11 show the address and data
requirements for the program command sequence. Note that the SecSi Sector,
autoselect, and CFI functions are unavailable when a program operation is in
progress.
When the Embedded Program algorithm is complete, the device then returns to
reading array data and addresses are no longer latched. The system can deter-
mine the status of the program operation by using DQ7, DQ6, or RY/BY#. See
Write Operation Status on page 38 for information on these status bits.
Any commands written to the device during the Embedded Program Algorithm
are ignored. Note that a hardware reset immediately terminates the program-
ming operation. The Program command sequence should be reinitiated once the
device resets to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across sector boundaries. Pro-
gramming to the same address multiple times without intervening erases is
limited. For such application requirements, please contact your local Spansion
representative. Any bit in a word or byte cannot be programmed from 0
back to a 1. Attempting to do so may halt the operation and set DQ5 to “1,” or
cause the Data# Polling algorithm to indicate the operation was successful.
However, a succeeding read shows that the data is still 0. Only erase operations
can convert a 0 to a 1.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program words to the device
faster than using the standard program command sequence. The unlock bypass
command sequence is initiated by first writing two unlock cycles. This is followed
by a third write cycle containing the unlock bypass command, 20h. The device
then enters the unlock bypass mode. A two-cycle unlock bypass program com-
mand sequence is all that is required to program in this mode. The first cycle in
this sequence contains the unlock bypass program command, A0h; the second
cycle contains the program address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial two unlock cycles re-
quired in the standard program command sequence, resulting in faster total
programming time. Table 10 on page 37 and Table 11 on page 43 show the re-
quirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock
Bypass Reset commands are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset command sequence. The first
cycle must contain the data 90h; the second cycle the data 00h. Addresses are
don’t care for both cycles. The device then returns to reading array data.
Figure 4, on page 32 illustrates the algorithm for the program operation. See
Table 18 on page 57 for parameters, and to Figure 17, on page 55 for timing
diagrams.
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A d v a n c e I n f o r m a t i o n
START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
No
Yes
No
Increment Address
Last Address?
Yes
Programming
Completed
Notes: See Tables 10 and for program command sequence.
Figure 4. Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is ini-
tiated by writing two unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the chip erase command,
which in turn invokes the Embedded Erase algorithm. The device does not re-
quire the system to preprogram prior to erase. The Embedded Erase algorithm
automatically preprograms and verifies the entire memory for an all zero data
pattern prior to electrical erase. The system is not required to provide any con-
trols or timings during these operations. Table 10 on page 37 and Table 11 on
page 43 show the address and data requirements for the chip erase command
sequence. Note that the SecSi Sector, autoselect, and CFI functions are un-
available when an erase operation is in progress.
Any commands written to the chip during the Embedded Erase algorithm are ig-
nored. Note that a hardware reset during the chip erase operation
immediately terminates the operation. The Chip Erase command sequence
should be reinitiated once the device returns to reading array data, to ensure
data integrity.
The system can determine the status of the erase operation by using DQ7, DQ6,
DQ2, or RY/BY#. See Autoselect Command Sequence on page 30 for informa-
tion on these status bits. When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are no longer latched.
32
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A d v a n c e I n f o r m a t i o n
Figure 5, on page 35 illustrates the algorithm for the erase operation. See the
Table 18 on page 57 for parameters, and to Figure 18, on page 57 for timing
diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is
initiated by writing two unlock cycles, followed by a set-up command. Two addi-
tional unlock write cycles are then followed by the address of the sector to be
erased, and the sector erase command. Table 10 on page 37 and Table 11 on
page 43 show the address and data requirements for the sector erase command
sequence. Note that the SecSi Sector, autoselect, and CFI functions are un-
available when an erase operation is in progress.
The device does not require the system to preprogram the memory prior to
erase. The Embedded Erase algorithm automatically programs and verifies the
sector for an all zero data pattern prior to electrical erase. The system is not re-
quired to provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 50 µs begins.
During the time-out period, additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector to all sectors. The
time between these additional cycles must be less than 50 µs, otherwise the last
address and command might not be accepted, and erasure may begin. It is rec-
ommended that processor interrupts be disabled during this time to ensure all
commands are accepted. The interrupts can be re-enabled after the last Sector
Erase command is written. If the time between additional sector erase com-
mands can be assumed to be less than 50 µs, the system need not monitor
DQ3. Any command other than Sector Erase or Erase Suspend during
the time-out period resets the device to reading array data. The system
must rewrite the command sequence and any additional sector addresses and
commands.
The system can monitor DQ3 to determine if the sector erase timer has timed
out. (See DQ3: Sector Erase Timer on page 43.) The time-out begins from the
rising edge of the final WE# pulse in the command sequence.
Once the sector erase operation begins, only the Erase Suspend command is
valid. All other commands are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the operation. The Sector Erase
command sequence should be reinitiated once the device returns to reading
array data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the device returns to reading
array data and addresses are no longer latched. The system can determine the
status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. (Refer to
Write Operation Status on page 38 for information on these status bits.)
Figure 5, on page 35 illustrates the algorithm for the erase operation. Refer to
the Table 18 on page 57 for parameters, and to Figure 18, on page 52 for timing
diagrams.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt a sector erase op-
eration and then read data from, or program data to, any sector not selected for
erasure. This command is valid only during the sector erase operation, including
the 50 µs time-out period during the sector erase command sequence. The
Erase Suspend command is ignored if written during the chip erase operation or
Embedded Program algorithm. Writing the Erase Suspend command during the
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A d v a n c e I n f o r m a t i o n
Sector Erase time-out immediately terminates the time-out period and suspends
the erase operation. Addresses are “don’t-cares” when writing the Erase Sus-
pend command.
When the Erase Suspend command is written during a sector erase operation,
the device requires a maximum of 20 µs to suspend the erase operation. How-
ever, when the Erase Suspend command is written during the sector erase time-
out, the device immediately terminates the time-out period and suspends the
erase operation.
After the erase operation is suspended, the system can read array data from or
program data to any sector not selected for erasure. (The device “erase sus-
pends” all sectors selected for erasure.) Normal read and write timings and
command definitions apply. Reading at any address within erase-suspended sec-
tors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and
DQ2 together, to determine if a sector is actively erasing or is erase-suspended.
See Write Operation Status on page 38 for information on these status bits.
After an erase-suspended program operation is complete, the system can once
again read array data within non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or DQ6 status bits, just as in
the standard program operation. See Write Operation Status on page 38 for
more information.
The system may also write the autoselect command sequence when the device
is in the Erase Suspend mode. The device allows reading autoselect codes even
at addresses within erasing sectors, since the codes are not stored in the mem-
ory array. When the device exits the autoselect mode, the device reverts to the
Erase Suspend mode, and is ready for another valid operation. See Autoselect
Command Sequence on page 30 for more information.
The system must write the Erase Resume command (address bits are don’t
care) to exit the erase suspend mode and continue the sector erase operation.
Further writes of the Resume command are ignored. Another Erase Suspend
command can be written after the device resumes erasing.
Note: During an erase operation, this flash device performs multiple internal opera-
tions that are invisible to the system. When an erase operation is suspended, any of
the internal operations that were not fully completed must be restarted. As such, if
this flash device is continually issued suspend/resume commands in rapid succession,
erase progress is impeded as a function of the number of suspends. The result is a
longer cumulative erase time than without suspends. Note that the additional sus-
pends do not affect device reliability or future performance. In most systems rapid
erase/suspend activity occurs only briefly. In such cases, erase performance is not
significantly impacted.
34
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A d v a n c e I n f o r m a t i o n
START
Write Erase
Command Sequence
Data Poll
from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Table 10 on page 37 and Table 11 on page 43 for erase command sequence.
2. See DQ3: Sector Erase Timer on page 43 for more information.
Figure 5. Erase Operation
Program Suspend/Program Resume Command Sequence
The Program Suspend command allows the system to interrupt a programming
operation so that data can be read from any non-suspended sector. When the
Program Suspend command is written during a programming process, the de-
vice halts the program operation within 15 µs maximum (5 µs typical) and
updates the status bits. Addresses are not required when writing the Program
Suspend command.
After the programming operation is suspended, the system can read array data
from any non-suspended sector. The Program Suspend command may also be
issued during a programming operation while an erase is suspended. In this
case, data may be read from any addresses not in Erase Suspend or Program
Suspend. If a read is needed from the SecSi Sector area (One-time Program
area), then user must use the proper command sequences to enter and exit this
region.
The system may also write the autoselect command sequence when the device
is in the Program Suspend mode. The system can read as many autoselect
codes as required. When the device exits the autoselect mode, the device re-
verts to the Program Suspend mode, and is ready for another valid operation.
See Autoselect Command Sequence for more information.
After the Program Resume command is written, the device reverts to program-
ming. The system can determine the status of the program operation using the
DQ7 or DQ6 status bits, just as in the standard program operation. See Write
Operation Status on page 38 for more information.
February 23, 2005 S71AL016M_M0_A0
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35
A d v a n c e I n f o r m a t i o n
The system must write the Program Resume command (address bits are don’t
care) to exit the Program Suspend mode and continue the programming opera-
tion. Further writes of the Resume command are ignored. Another Program
Suspend command can be written after the device resumes programming.
Program Operation
Sequence in Progress
Write Program Suspend
Write address/data
XXXh/B0h
Command Sequence
Command is also valid for
Erase-suspended-program
operations
Wait 15 ms
Autoselect and SecSi Sector
Read data as
required
read operations are also allowed
Data cannot be read from erase- or
program-suspended sectors
Done
No
reading?
Yes
Write Program Resume
Command Sequence
Write address/data
XXXh/30h
Device reverts to
operation prior to
Program Suspend
Figure 6. Program Suspend/Program Resume
36
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A d v a n c e I n f o r m a t i o n
Command Definitions Tables
Table 10. Command Definitions
Bus Cycles (Notes 2–5)
Third Fourth
Command
Sequence
(Note 1)
First
Addr Data
Second
Fifth
Sixth
Addr
Data
Addr
Data
Addr
Data
Addr Data Addr Data
Read (Note 5)
Reset (Note 6)
1
1
4
6
6
4
RA
RD
F0
XXX
555
555
555
555
Manufacturer ID
AA
AA
AA
AA
2AA
2AA
2AA
2AA
55
55
55
55
555
555
555
555
90
90
90
90
X00
X01
X01
X41
0001
22C4
Device ID, Top Boot (Note 8)
Device ID, Bottom Boot (Note 8)
SecSi™ Sector Factory Protect
2249
(Note 9)
Sector Group Protect Verify
(Note 9)
4
555
AA
2AA
55
555
90
(SA)X02
00/01
Enter SecSi Sector Region
Exit SecSi Sector Region
Program
3
4
4
3
2
2
6
6
1
1
1
555
555
555
555
XXX
XXX
555
555
XXX
XXX
55
AA
AA
AA
AA
A0
90
AA
AA
B0
30
98
2AA
2AA
2AA
2AA
PA
55
55
55
55
PD
00
55
55
555
555
555
555
88
90
A0
20
XXX
PA
00
PD
Unlock Bypass
Unlock Bypass Program (Note 10)
Unlock Bypass Reset (Note 11)
Chip Erase
XXX
2AA
2AA
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
Sector Erase
Program/Erase Suspend (Note 12)
Program/Erase Resume (Note 13)
CFI Query (Note 14)
Legend:
X = Don’t care
RA = Read Address of memory location to be read.
RD = Read Data read from location RA during read operation.
PA = Program Address. Addresses latch on falling edge of WE# or CE# pulse, whichever happens later.
PD = Program Data for location PA. Data latches on rising edge of WE# or CE# pulse, whichever happens first.
SA = Sector Address of sector to be verified (in autoselect mode) or erased. Address bits A19–A15 uniquely select any sector.
Notes:
1. See Table 1 on page 17 for description of bus operations.
9. Data is 00h for an unprotected sector group and 01h for a
protected sector group.
2. All values are in hexadecimal.
10. Unlock Bypass command is required prior to Unlock
Bypass Program command.
3. Shaded cells indicate read cycles. All others are write
cycles.
11. Unlock Bypass Reset command is required to return to
read mode when device is in unlock bypass mode.
4. During unlock and command cycles, when lower address
bits are 555 or 2AA as shown in table, address bits above
A11 and data bits above DQ7 are don’t care.
12. System may read and program in non-erasing sectors, or
enter autoselect mode, when in Erase Suspend mode.
Erase Suspend command is valid only during a sector
erase operation.
5. No unlock or command cycles required when device is in
read mode.
6. Reset command is required to return to read mode (or to
erase-suspend-read mode if previously in Erase Suspend)
when device is in autoselect mode, or if DQ5 goes high
while device is providing status information.
13. Erase Resume command is valid only during Erase
Suspend mode.
14. Command is valid when device is ready to read array data
or when device is in autoselect mode.
7. Fourth cycle of the autoselect command sequence is a
read cycle. Data bits DQ15–DQ8 are don’t care. See
Autoselect Command Sequence on page 30 for more
information.
8. Device ID must be read in three cycles.
February 23, 2005 S71AL016M_M0_A0
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37
A d v a n c e I n f o r m a t i o n
Write Operation Status
The device provides several bits to determine the status of a write operation:
DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 12 on page 45 and the following
subsections describe the functions of these bits. DQ7, RY/BY#, and DQ6 each
offer a method for determining whether a program or erase operation is com-
plete or in progress. These three bits are discussed first.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded
Algorithm is in progress or completed, or whether the device is in Erase Sus-
pend. Data# Polling is valid after the rising edge of the final WE# pulse in the
program or erase command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the com-
plement of the datum programmed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to DQ7. The system must
provide the program address to read valid status information on DQ7. If a pro-
gram address falls within a protected sector, Data# Polling on DQ7 is active for
approximately 1 µs, then the device returns to reading array data.
During the Embedded Erase algorithm, Data# Polling produces a 0 on DQ7.
When the Embedded Erase algorithm is complete, or if the device enters the
Erase Suspend mode, Data# Polling produces a 1 on DQ7. This is analogous to
the complement/true datum output described for the Embedded Program algo-
rithm: the erase function changes all the bits in a sector to 1; prior to this, the
device outputs the complement, or 0. The system must provide an address
within any of the sectors selected for erasure to read valid status information on
DQ7.
After an erase command sequence is written, if all sectors selected for erasing
are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the
device returns to reading array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
When the system detects DQ7 changes from the complement to true data, it can
read valid data at DQ7–DQ0 on the following read cycles. This is because DQ7
may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is as-
serted low. Figure 17, on page 52 illustrates this.
Table 12 on page 45 shows the outputs for Data# Polling on DQ7. Figure 7, on
page 39 shows the Data# Polling algorithm.
38
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S71AL016M_M0 A0 February 23, 2005
A d v a n c e I n f o r m a t i o n
START
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
No
PASS
FAIL
Notes:
1. VA = Valid address for programming. During a sector erase operation, a valid
address is an address within any sector selected for erasure. During chip erase, a
valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simulta-
neously with DQ5.
Figure 7. Data# Polling Algorithm
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that indicates whether an Em-
bedded Algorithm is in progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command sequence. Since RY/BY#
is an open-drain output, several RY/BY# pins can be tied together in parallel
with a pull-up resistor to VCC
.
February 23, 2005 S71AL016M_M0_A0
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39
A d v a n c e I n f o r m a t i o n
If the output is low (Busy), the device is actively erasing or programming. (This
includes programming in the Erase Suspend mode.) If the output is high
(Ready), the device is ready to read array data (including during the Erase Sus-
pend mode), or is in the standby mode.
Table 11 on page 43 shows the outputs for RY/BY#. Figure 13, on page 47; Fig-
ure 14, on page 48; Figure 17, on page 52; and Figure 18, on page 52 show RY/
BY# for read, reset, program, and erase operations, respectively.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm
is in progress or complete, or whether the device entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is valid after the rising edge
of the final WE# pulse in the command sequence (prior to the program or erase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cy-
cles to any address cause DQ6 to toggle. (The system may use either OE# or
CE# to control the read cycles.) When the operation is complete, DQ6 stops
toggling.
After an erase command sequence is written, if all sectors selected for erasing
are protected, DQ6 toggles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected, the Embedded Erase algo-
rithm erases the unprotected sectors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to determine whether a sector is ac-
tively erasing or is erase-suspended. When the device is actively erasing (that
is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device
enters the Erase Suspend mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing or erase-suspended. Alter-
natively, the system can use DQ7 (see the subsection DQ7: Data# Polling on
page 38).
If a program address falls within a protected sector, DQ6 toggles for approxi-
mately 1 µs after the program command sequence is written, then returns to
reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling
once the Embedded Program algorithm is complete.
Table 12 shows the outputs for Toggle Bit I on DQ6. Figure 8, on page 42 shows
the toggle bit algorithm in flowchart form, and the section Reading Toggle Bits
DQ6/DQ2 on page 41 explains the algorithm. Figure 20, on page 53 shows the
toggle bit timing diagrams. Figure 21, on page 54 shows the differences be-
tween DQ2 and DQ6 in graphical form. See also the subsection DQ2: Toggle Bit
II on page 40.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular
sector is actively erasing (that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit II is valid after the rising
edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that were
selected for erasure. (The system may use either OE# or CE# to control the
read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing
or is erase-suspended. DQ6, by comparison, indicates whether the device is ac-
tively erasing, or is in Erase Suspend, but cannot distinguish which sectors are
40
S71AL016M
S71AL016M_M0 A0 February 23, 2005
A d v a n c e I n f o r m a t i o n
selected for erasure. Thus, both status bits are required for sector and mode in-
formation. Refer to Table 11 on page 43 to compare outputs for DQ2 and DQ6.
Figure 8, on page 42 shows the toggle bit algorithm in flowchart form, and the
section Reading Toggle Bits DQ6/DQ2 on page 41 explains the algorithm. See
also the DQ6: Toggle Bit I on page 40 subsection. Figure 18, on page 52 shows
the toggle bit timing diagram. Figure 19, on page 53 shows the differences be-
tween DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 8, on page 42 for the following discussion. Whenever the system
initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in
a row to determine whether a toggle bit is toggling. Typically, the system would
note and store the value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle bit with the first. If
the toggle bit is not toggling, the device completed the program or erase opera-
tion. The system can read array data on DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the tog-
gle bit is still toggling, the system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may have stopped tog-
gling just as DQ5 went high. If the toggle bit is no longer toggling, the device
successfully completed the program or erase operation. If it is still toggling, the
device did not complete the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit
is toggling and DQ5 did not go high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, determining the status as
described in the previous paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start at the beginning of the
algorithm when it returns to determine the status of the operation (top of Figure
8, on page 42).
February 23, 2005 S71AL016M_M0_A0
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41
A d v a n c e I n f o r m a t i o n
START
Read DQ7–DQ0
(Note 1)
Read DQ7–DQ0
No
Toggle Bit
= Toggle?
Yes
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Twice
(Notes
1, 2)
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Figure 8. Toggle Bit Algorithm
Notes:
1. Read toggle bit twice to determine whether or not it is toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5 changes to 1. See text.
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time exceeded a specified internal
pulse count limit. Under these conditions DQ5 produces a 1. This is a failure con-
dition that indicates the program or erase cycle was not successfully completed.
The DQ5 failure condition may appear if the system tries to program a 1 to a lo-
cation that is previously programmed to 0. Only an erase operation can
change a 0 back to a 1. Under this condition, the device halts the operation,
and when the operation exceeds the timing limits, DQ5 produces a 1.
42
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A d v a n c e I n f o r m a t i o n
Under both these conditions, the system must issue the reset command to re-
turn the device to reading array data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to
determine whether or not an erase operation begun. (The sector erase timer
does not apply to the chip erase command.) If additional sectors are selected for
erasure, the entire time-out also applies after each additional sector erase com-
mand. When the time-out is complete, DQ3 switches from 0 to 1. The system
may ignore DQ3 if the system can guarantee that the time between additional
sector erase commands is always less than 50 µs. See also Sector Erase Com-
mand Sequence on page 33.
After the sector erase command sequence is written, the system should read the
status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure the device ac-
cepted the command sequence, and then read DQ3. If DQ3 is 1, the internally
controlled erase cycle began; all further commands (other than Erase Suspend)
are ignored until the erase operation is complete. If DQ3 is 0, the device accepts
additional sector erase commands. To ensure the command is accepted, the sys-
tem software should check the status of DQ3 prior to and following each
subsequent sector erase command. If DQ3 is high on the second status check,
the last command might not have been accepted. Table 11 shows the outputs
for DQ3.
Table 11. Write Operation Status
DQ7
(Note
2)
DQ5
(Note 1)
DQ2
(Note 2)
Operation
DQ6
DQ3
N/A
1
RY/BY#
Embedded Program Algorithm
Embedded Erase Algorithm
Program-
Program-
Suspend Read
DQ7#
0
Toggle
Toggle
0
0
No toggle
Toggle
0
0
Standard
Mode
Invalid (not allowed)
Data
1
1
1
Program
Suspend
Mode
Suspended Sector
Non-Program
Suspended Sector
Reading within Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
Erase
Suspend Reading within Non-Erase Suspended
Data
Data
Data
0
Data
N/A
Data
N/A
1
0
Mode
Sector
Erase-Suspend-Program
DQ7#
Toggle
Notes:
1. DQ5 switches to 1 when an Embedded Program or Embedded Erase operation exceeds the maximum timing limits.
See DQ5: Exceeded Timing Limits on page 42 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.
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43
A d v a n c e I n f o r m a t i o n
Absolute Maximum Ratings
Storage Temperature, Plastic Packages. . . . . . . . . . . . . . . . .–65°C to +150°C
Ambient Temperature with Power Applied . . . . . . . . . . . . . . .–65°C to +125°C
Voltage with Respect to Ground
VCC (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
A9, OE#, and RESET# (Note 2) . . . . . . . . . . . . . . . .–0.5 V to +12.5 V
All other pins (Note 1). . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC+0.5 V
Output Short Circuit Current (Note 3). . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions,
input or I/O pins may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure
9. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage
transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns.
See Figure 10.
2. Minimum DC input voltage on pins A9, OE#, and RESET# is -0.5 V. During voltage
transitions, A9, OE#, and RESET# may overshoot VSS to –2.0 V for periods of up
to 20 ns. See Figure 9. Maximum DC input voltage on pin A9 is +12.5 V which
may overshoot to 14.0 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short
circuit should not be greater than one second.
Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those indicated in the operational sections of
this data sheet is not implied. Exposure of the device to absolute maximum rating con-
ditions for extended periods may affect device reliability.
20 ns
20 ns
20 ns
VCC
+2.0 V
+0.8 V
VCC
–0.5 V
–2.0 V
+0.5 V
2.0 V
20 ns
20 ns
20 ns
Figure 9. Maximum Negative
Overshoot Waveform
Figure 10. Maximum Positive
Overshoot Waveform
Operating Ranges
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
VCC Supply Voltages
VCC for full voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7 V to 3.6 V
VCC for regulated range . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.0 V to 3.6 V
Operating ranges define those limits between which the functionality of the device is
guaranteed.
44
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A d v a n c e I n f o r m a t i o n
DC Characteristics
Table 12. CMOS Compatible
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
VIN = VSS to VCC
VCC = VCC max
,
ILI
Input Load Current
1.0
µA
ILIT
A9 Input Load Current
Reset Leakage Current
VCC = VCC max; A9 = 12.5 V
VCC = VCC max; RESET# = 12.5 V
35
35
µA
µA
ILR
VOUT = VSS to VCC
VCC = VCC max
,
ILO
Output Leakage Current
1.0
µA
10 MHz
5 MHz
1 MHz
35
15
50
20
10
VCC Active Read Current
(Notes 1, 2)
CE# = VIL, OE# = VIH,
CE# = VIL, OE# = VIH
ICC1
mA
2.5
VCC Active Write Current
(Notes 2, 3, 5)
ICC2
ICC3
ICC4
40
0.4
0.8
60
5
mA
µA
µA
VCC Standby Current (Notes 2, 4) CE#, RESET# = VCC 0.3 V
VCC Standby Current During Reset
RESET# = VSS 0.3 V
(Notes 2, 4)
5
Automatic Sleep Mode
(Notes 2, 4, 6)
VIH = VCC 0.3 V;
-0.1 < VIL 0.3 V
ICC5
0.4
5
µA
≤
VIL
Input Low Voltage (Notes 6, 7)
Input High Voltage (Notes 6, 7)
-0.5
0.6
V
V
VIH
0.7 VCC
VCC + 0.5
Voltage for Autoselect and
Temporary Sector Unprotect
VID
VCC = 3.3 V
11.5
12.5
0.45
V
VOL
Output Low Voltage
IOL = 4.0 mA, VCC = VCC min
IOH = -2.0 mA, VCC = VCC min
IOH = -100 µA, VCC = VCC min
V
V
VOH1
VOH2
VLKO
0.85 x VCC
VCC–0.4
2.3
Output High Voltage
Low VCC Lock-Out Voltage (Note 4)
2.5
V
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V.
2. Maximum ICC specifications are tested with VCC = VCCmax.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. At extended temperature range (>+85°C), typical current is 5 µA and maximum current is 10 µA.
5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns.
6. Not 100% tested.
7. VCC voltage requirements.
February 23, 2005 S71AL016M_M0_A0
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45
A d v a n c e I n f o r m a t i o n
Test Conditions
3.3 V
Table 13. Test Specifications
Test Condition
Output Load
90, 100
Unit
2.7 k
Ω
Device
Under
Test
1 TTL gate
Output Load Capacitance, CL
(including jig capacitance)
30
pF
C
6.2 k
Ω
L
Input Rise and Fall Times
Input Pulse Levels
5
ns
V
0.0 or VCC
Input timing measurement
reference levels
0.5 VCC
0.5 VCC
V
V
Output timing measurement
reference levels
Note: Diodes are IN3064 or equivalent
Figure 11. Test Setup
Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
VCC
0.5 VCC
0.5 VCC
Input
Measurement Level
Output
0.0 V
Figure 12. Input Waveforms and Measurement Levels
46
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A d v a n c e I n f o r m a t i o n
AC Characteristics
Table 14. Read Operations
Parameter
Speed Options
JEDEC
Std
Description
Test Setup
Min
90
100
Unit
tAVAV
tRC
Read Cycle Time (Note 1)
Address to Output Delay
90
100
ns
CE# = VIL
OE# = VIL
tAVQV
tACC
Max
90
90
100
100
ns
tELQV
tGLQV
tEHQZ
tGHQZ
tCE
tOE
tDF
tDF
Chip Enable to Output Delay
OE# = VIL
Max
Max
Max
Max
Min
ns
ns
ns
ns
ns
Output Enable to Output Delay
25
20
20
0
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
Read
Output Enable
Hold Time (Note 1)
tOEH
Toggle and
Data# Polling
Min
Min
10
0
ns
ns
Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First (Note 1)
tAXQX
tOH
Notes:
1. Not 100% tested.
2. See Figure 11, on page 46 and Table 13 on page 46 for test specifications.
tRC
Addresses Stable
tACC
Addresses
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
Figure 13. Read Operations Timings
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A d v a n c e I n f o r m a t i o n
AC Characteristics
Table 15. Hardware Reset (RESET#)
Parameter
Test
JEDEC
Std
Description
Setup
All Speed Options
Unit
RESET# Pin Low (During Embedded Algorithms) to
Read or Write (See Note)
tREADY
Max
20
µs
RESET# Pin Low (NOT During Embedded Algorithms)
to Read or Write (See Note)
tREADY
Max
500
ns
tRP
tRH
tRPD
tRB
RESET# Pulse Width
Min
Min
Min
Min
500
50
20
0
ns
ns
µs
ns
RESET# High Time Before Read (See Note)
RESET# Low to Standby Mode
RY/BY# Recovery Time
Note: Not 100% tested.
RY/BY#
CE#, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Figure 14. RESET# Timings
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AC Characteristics
Erase/Program Operations
Parameter
Speed Options
JEDEC
tAVAV
Std
tWC
tAS
Description
90
100
Unit
ns
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Min
Min
Min
Min
Min
Min
90
100
tAVWL
tWLAX
tDVWH
tWHDX
0
45
35
0
ns
tAH
ns
tDS
ns
tDH
tOES
Data Hold Time
ns
Output Enable Setup Time
0
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHWL
tGHWL
Min
0
ns
tELWL
tWHEH
tCS
tCH
CE# Setup Time
Min
Min
Min
Min
Typ
Typ
Min
Min
Max
Max
0
0
ns
ns
ns
ns
µs
sec
µs
ns
ns
µs
CE# Hold Time
tWLWH
tWHWL
tWHWH1
tWHWH2
tWP
Write Pulse Width
35
30
18
1
tWPH
tWHWH1
tWHWH2
tVCS
Write Pulse Width High
Programming Operation (Note 2)
Sector Erase Operation (Note 2)
VCC Setup Time (Note 1)
Recovery Time from RY/BY#
Program/Erase Valid to RY/BY# Delay
Program Valid Before Status Polling (Note 3)
50
0
tRB
tBUSY
tPOLL
90
100
4
Notes:
1. Not 100% tested.
2. See Table 18 on page 57 for more information.
3. If a program suspend command is issued within tPOLL, the device requires tPOLL before reading status data, once
programming resumes (that is, the program resume command is written). If the suspend command was issued after tPOLL
status data is available immediately after programming resumes. See Figure 15, on page 50.
,
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A d v a n c e I n f o r m a t i o n
AC Characteristics
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
PA
tWC
Addresses
555h
PA
PA
tAH
CE#
OE#
tCH
tPOLL
tWP
WE#
Data
tWPH
tWHWH1
tCS
tDS
tDH
PD
DOUT
A0h
Status
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.
Figure 15. Program Operation Timings
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AC Characteristics
Erase Command Sequence (last two cycles)
Read Status Data
VA
tAS
SA
tWC
VA
Addresses
CE#
2AAh
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
Complete
55h
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
tVCS
VCC
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status on page 38).
2. Illustration shows device in word mode.
Figure 16. Chip/Sector Erase Operation Timings
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A d v a n c e I n f o r m a t i o n
AC Characteristics
tRC
VA
Addresses
VA
VA
tACC
tCE
tPOLL
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
High Z
High Z
DQ7
Valid Data
Complement
Complement
Status Data
True
DQ0–DQ6
Status Data
True
Valid Data
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array
data read cycle.
Figure 17. Data# Polling Timings
(During Embedded Algorithms)
tRC
Addresses
CE#
VA
tACC
tCE
VA
VA
VA
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
DQ6/DQ2
RY/BY#
Valid Status
(first read)
Valid Status
Valid Status
Valid Data
(second read)
(stops toggling)
tBUSY
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last
status read cycle, and array data read cycle.
Figure 18. Togg le B it T im ings
(During Embedded Algorithms)
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A d v a n c e I n f o r m a t i o n
AC Characteristics
Enter
Erase
Suspend
Enter Erase
Suspend Program
Embedded
Erase
Resume
Erasing
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
Figure 19. DQ2 vs. DQ6 for Erase and
Erase Suspend Operations
Table 16. Temporary Sector Unprotect
Parameter
JEDEC
Std
Description
All Speed Options
Unit
tVIDR
VID Rise and Fall Time (See Note)
Min
Min
500
ns
RESET# Setup Time for Temporary Sector
Unprotect
tRSP
4
µs
Note: Not 100% tested.
12 V
RESET#
0 or 3 V
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
RY/BY#
Figure 20. Temporary Sector Unprotect/Timing Diagram
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A d v a n c e I n f o r m a t i o n
AC Characteristics
V
ID
V
IH
RESET#
SA, A6,
A1, A0
Valid*
Valid*
Valid*
Status
Sector Protect/Unprotect
Verify
40h
Data
60h
60h
Sector Protect: 150 µs
Sector Unprotect: 15 ms
1 µs
CE#
WE#
OE#
Note: For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 21. Sector Protect/Unprotect Timing Diagram
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A d v a n c e I n f o r m a t i o n
AC Characteristics
Table 17. Alternate CD# Controlled Erase/Program Operations
Parameter
JEDEC
Speed Options
Std
tWC
tAS
Description
90
100
Unit
ns
tAVAV
tAVEL
tELAX
tDVEH
tEHDX
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Min
Min
Min
Min
Min
Min
90
100
0
45
35
0
ns
tAH
ns
tDS
ns
tDH
tOES
Data Hold Time
ns
Output Enable Setup Time
0
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHEL
tGHEL
Min
0
ns
tWLEL
tEHWH
tELEH
tWS
tWH
WE# Setup Time
Min
Min
Min
Min
Typ
Typ
Min
0
0
ns
ns
ns
ns
µs
sec
ns
WE# Hold Time
tCP
CE# Pulse Width
35
25
18
0.7
50
tEHEL
tCPH
CE# Pulse Width High
Programming Operation (Note 2)
Sector Erase Operation (Note 2)
RESET# High Time Before Write
tWHWH1
tWHWH2
tWHWH1
tWHWH2
tRH
Program Valid Before Status Polling
(Note 3)
tPOLL
Max
4
µs
Notes:
1. Not 100% tested.
2. See Table 18 on page 57 for more information.
3. If a program suspend command is issued within tPOLL, the device requires tPOLL before reading status data, once
programming resumes (that is, the program resume command is written). If the suspend command was issued after tPOLL
status data is available immediately after programming resumes. See Figure 22, on page 56.
,
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A d v a n c e I n f o r m a t i o n
AC Characteristics
555 for program
PA for program
2AA for erase
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tAS
tAH
tWH
WE#
OE#
tPOLL
tGHEL
tWHWH1 or 2
tCP
CE#
tWS
tCPH
tDS
tBUSY
tDH
DQ7#,
DQ15
DOUT
Data
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to
the device.
2. Figure indicates the last two bus cycles of the command sequence.
3. Word mode address used as an example.
Figure 22. Alternate CE# Controlled Write Operation Timings
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Table 18. Erase and Programming Performance
Parameter
Sector Erase Time
Typ (Note 1)
Max (Note 2)
Unit
s
Comments
0.7
32
18
7.5
Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time
s
Word Programming Time
µs
Excludes system level
overhead (Note 5)
Chip Programming Time
(Note 3)
Word Mode
19
s
Notes:
1. Typical program and erase times assume the following conditions: 25°C, VCC = 3.0 V, 10,000 cycles, checkerboard data
pattern.
2. Under worst case conditions of 90°C, VCC = 2.7 V, 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most words
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Table 2 on page 20 and Table 3 on page 21 for further information on command definitions.
Table 19. TSOP Pin and BGA Package Capcitance
Unit
Parameter Symbol
Parameter Description
Test Setup
Typ
6
Max
7.5
5.0
12
TSOP
BGA
pF
pF
pF
pF
pF
pF
CIN
Input Capacitance
VIN = 0
4.2
8.5
5.4
7.5
3.9
TSOP
BGA
COUT
Output Capacitance
VOUT = 0
VIN = 0
6.5
9
TSOP
BGA
CIN2
Control Pin Capacitance
4.7
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
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A d v a n c e I n f o r m a t i o n
Type 4 pSRAM
4 Mbit (256K x 16)
Features
Wide voltage range: 2.7V to 3.3V
Typical active current: 3 mA @ f = 1 MHz
Low standby power
Automatic power-down when deselected
Functional Description
The Type 4 pSRAM is a high-performance CMOS pseudo static RAM (pSRAM) or-
ganized as 256K words by 16 bits that supports an asynchronous memory
interface. This device features advanced circuit design to provide ultra-low active
current. The device can be put into standby mode reducing power consumption
dramatically when deselected (CE1# Low, CE2 High or both BHE# and BLE# are
High). The input/output pins (I/O0 through I/O15) are placed in a high-imped-
ance state when: deselected (CE1# High, CE2 Low, OE# is deasserted High), or
during a write operation (Chip Enabled and Write Enable WE# Low). Reading from
the device is accomplished by asserting the Chip Enables (CE1# Low and CE2
High) and Output Enable (OE#) Low while forcing the Write Enable (WE#) High.
If Byte Low Enable (BLE#) is Low, then data from the memory location specified
by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE#) is
Low, then data from memory will appear on I/O8 to I/O15. See Table 22 for a
complete description of read and write modes.
Product Portfolio
Power Dissipation
Operating, I (mA)
CC
V
Range (V)
Typ
f = 1 MHz
Typ. (note 1)
f = f
Standby (I ) (µA)
SB2
CC
max
Speed
(ns)
Min
Max
Max
Typ. (note 1)
Max
Typ. (note 1)
Max
2.7V
3.0V
3.3V
70 ns
3
5
TBD
25 mA
15
40
Notes:
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC
(typ) and TA = 25°C.
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested)
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Ambient Temperature with Power Applied . . . . . . . . . . . . . . . -40°C to +85°C
Supply Voltage to Ground Potential . . . . . . . . . . . . . . . . . . . . . -0.4V to 4.6V
DC Voltage Applied to Outputs in High-Z
State (note 1, 2, 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 3.7V
DC Input Voltage (note 1, 2, 3) . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 3.7V
Output Current into Outputs (Low). . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Static Discharge Voltage. . . . . . . . . >2001V (per MIL-STD-883, Method 3015)
Latch-up Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >200 mA
Notes:
1. VIH(MAX) = VCC + 0.5V for pulse durations less than 20 ns.
2. VIL(MIN) = –0.5V for pulse durations less than 20 ns.
3. Overshoot and undershoot specifications are characterized and are not 100% tested.
Operating Range
Ambient Temperature (T )
V
CC
A
-25°C to +85°C
2.7V to 3.3V
Table 20. DC Electrical Characteristics (Over the Operating Range)
Typ.
(note 1)
Parameter
VCC
Description
Supply Voltage
Test Conditions
Min.
Max
Unit
2.7
3.3
VOH
VOL
VIH
VIL
IIX
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
IOH = –1.0 mA
VCC - 0.4
IOL = 0.1 mA
0.4
V
0.8 * VCC
VCC + 0.4
F = 0
-0.4
-1
0.4
+1
+1
15
3
Input Leakage Current
Output Leakage Current
GND ≤ VIN ≤ VCC
µA
IOZ
GND ≤ VOUT ≤ VCC, Output Disabled
-1
f = fMAX = 1/tRC
f = 1 MHz
VCC = 3.3V
IOUT = 0 mA
CMOS Levels
TBD
ICC
VCC Operating Supply Current
mA
CE# ≥ VCC – 0.2V, CE2 ≤ 0.2V
VIN ≥ VCC – 0.2V, VIN ≤ 0.2V,
Automatic CE# Power-Down
Current—CMOS Inputs
ISB1
250
40
f = fmax (Address and Data Only),
f=0 (OE#, WE#, BHE# and BLE#)
µA
CE# ≥ VCC – 0.2V, CE2 ≤ 0.2V
VIN ≥ VCC – 0.2V or VIN ≤ 0.2V,
f = 0, VCC = 3.3V
Automatic CE# Power-Down
Current—CMOS Inputs
ISB2
Notes:
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC
CC(typ.), TA = 25°C.
=
V
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A d v a n c e I n f o r m a t i o n
Capacitance
Parameter
Description
Test Condition
Max
8
Unit
CIN
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
VCC = VCC(typ.)
pF
COUT
8
Note: Tested initially and after any design or process changes that may affect these parameters.
Thermal Resistance
Parameter
Description
Test Conditions
VFBGA
Unit
θ JA
Thermal Resistance (Junction to Ambient) Test conditions follow standard test methods
and procedures for measuring thermal
55
°C/W
θ JC
Thermal Resistance (Junction to Case)
17
impedance, per EIA / JESD51.
Note: Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
R1
VCC
ALL INPUT PULSES
90%
10%
Fall Time: 1 V/ns
V
CC
OUTPUT
90%
10%
GND
Rise Time: 1 V/ns
R2
30 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENINEQUIVALENT
RTH
OUTPUT
VTH
Figure 23. AC Test Loads and Waveforms
Parameters
3.0V V
Unit
CC
R1
R2
22000
22000
11000
1.50
Ω
RTH
VTH
V
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Table 21. Switching Characteristics
Min
Max
Parameter
Read Cycle
Description
Unit
tRC
Read Cycle Time
70
10
tAA
Address to Data Valid
70
tOHA
tACE
Data Hold from Address Change
CE#1 Low and CE2 High to Data Valid
OE# Low to Data Valid
70
35
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tDBE
tLZBE
tHZBE
OE# Low to Low Z (note 2, 3)
5
5
OE# High to High Z (note 2, 3)
CE#1 Low and CE2 High to Low Z (note 2, 3)
CE#1 High and CE2 Low to High Z (note 2, 3)
BHE# / BLE# Low to Data Valid
BHE# / BLE# Low to Low Z (note 2, 3)
BHE# / BLE# High to High Z (note 2, 3)
Address Skew
25
ns
25
70
5
25
10
t
SK (note 4)
Write Cycle (note 5)
tWC
tSCE
tAW
Write Cycle Time
70
55
55
0
CE#1 Low an CE2 High to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE# Pulse Width
tHA
tSA
0
tPWE
tBW
55
55
25
0
ns
BLE# / BHE# LOW to Write End
Data Set-up to Write End
tSD
tHD
Data Hold from Write End
tHZWE
tLZWE
WE# Low to High Z (note 2, 3)
WE# High to Low Z (note 2, 3)
25
5
Notes:
1. Test conditions assume signal transition time of 1V/ns or higher, timing reference levels of VCC(typ.) /2, input pulse levels of
0 to VCC(typ.), and output loading of the specified IOL/IOH and 30 pF load capacitance.
2.
tHZOE, tHZCE, tHZBE and tHZWE transitions are measured when the outputs enter a high-impedance state.
3. High-Z and Low-Z parameters are characterized and are not 100% tested.
4. To achieve 55-ns performance, the read access should be CE# controlled. In this case tACE is the critical parameter and tSK is
satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable
within 10 ns after the start of the read cycle.
5. The internal write time of the memory is defined by the overlap of WE#, CE#1 = VIL, CE2 = VIH, BHE and/or BLE =VIL. All
signals must be Active to initiate a write and any of these signals can terminate a write by going Inactive. The data input set-
up and hold timing should be referenced to the edge of the signal that terminates write.
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A d v a n c e I n f o r m a t i o n
Switching Waveforms
t
RC
ADDRESS
DATA OUT
t
AA
t
t
SK
OHA
PREVIOUS DATA VALID
DATA VALID
Figure 24. Read Cycle 1 (Address Transition Controlled)
Notes:
1. To achieve 55-ns performance, the read access should be CE# controlled. In this case tACE is the critical parameter and tSK is
satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable
within 10 ns after the start of the read cycle.
2. Device is continuously selected. OE#, CE# = VIL
.
3. WE# is High for Read Cycle.
ADDRESS
tRC
tSK
CE#1
tHZCE
CE
2
tACE
BHE#/BLE#
OE#
tDBE
tHZBE
t
LZBE
tHZOE
tDOE
t
HIGH
LZOE
IMPEDENCE
HIGH IMPEDENCE
DATA OUT
DATA VALID
t
LZCE
Figure 25. Read Cycle 2 (OE# Controlled)
Notes:
1. To achieve 55-ns performance, the read access should be CE# controlled. In this case tACE is the critical parameter and tSK is
satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable
within 10 ns after the start of the read cycle.
2. WE# is High for Read Cycle.
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Figure 26. Write Cycle 1 (WE# Controlled)
Notes:
1. High-Z and Low-Z parameters are characterized and are not 100% tested.
2. The internal write time of the memory is defined by the overlap of WE#, CE#1 = VIL, CE2 = VIH, BHE and/or BLE =VIL. All
signals must be Active to initiate a write and any of these signals can terminate a write by going Inactive. The data input set-
up and hold timing should be referenced to the edge of the signal that terminates write.
3. Data I/O is high impedance if OE# ≥ VIH
.
4. If Chip Enable goes Inactive simultaneously with WE# = High, the output remains in a high-impedance state.
5. During the Don’t Care period in the Data I/O waveform, the I/Os are in output state and input signals should not be applied.
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A d v a n c e I n f o r m a t i o n
t
WC
ADDRESS
CE#1
t
SCE
CE
2
t
SA
t
t
HA
AW
t
PWE
WE#
t
BHE#/BLE#
BW
OE#
t
t
SD
HD
DATAI/O
VALID DATA
DON’T CARE
t
HZOE
Figure 27. Write Cycle 2 (CE#1 or CE2 Controlled)
Notes:
1. High-Z and Low-Z parameters are characterized and are not 100% tested.
2. The internal write time of the memory is defined by the overlap of WE#, CE#1 = VIL, CE2 = VIH, BHE and/or BLE =VIL. All
signals must be Active to initiate a write and any of these signals can terminate a write by going Inactive. The data input set-
up and hold timing should be referenced to the edge of the signal that terminates write.
3. Data I/O is high impedance if OE# ≥ VIH
.
4. If Chip Enable goes Inactive simultaneously with WE# = High, the output remains in a high-impedance state.
5. During the Don’t Care period in the Data I/O waveform, the I/Os are in output state and input signals should not be applied.
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A d v a n c e I n f o r m a t i o n
tWC
ADDRESS
CE#1
tSCE
CE2
tBW
tAW
BHE#/BLE#
tHA
tSA
t
PWE
WE#
t
HD
tSD
DON’T CARE
DATA I/O
VALID DATA
t
tHZWE
LZWE
Figure 28. Write Cycle 3 (WE# Controlled, OE# Low)
Notes:
1. If Chip Enable goes Inactive simultaneously with WE# = High, the output remains in a high-impedance state.
2. During the Don’t Care period in the Data I/O waveform, the I/Os are in output state and input signals should not be applied.
CE#1
CE2
BHE#/BLE#
WE#
Figure 29. Write Cycle 4 (BHE#/BLE# Controlled, OE# Low)
Notes:
1. If Chip Enable goes Inactive simultaneously with WE# = High, the output remains in a high-impedance state.
2. During the Don’t Care period in the Data I/O waveform, the I/Os are in output state and input signals should not be applied.
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A d v a n c e I n f o r m a t i o n
Truth Table
Table 22. Truth Table
CE#1
CE2
X
WE# OE# BHE# BLE#
Inputs / Outputs
High-Z
Mode
Power
H
X
X
L
X
X
X
H
X
X
X
L
X
X
H
L
X
X
H
L
L
High-Z
Deselect/Power-Down
Standby (ISB)
X
High-Z
H
Data Out (I/O0–I/O15)
Read (Upper Byte and Lower Byte)
Read (Upper Byte only)
Data Out (I/O0 –I/O7);
I/O8–I/O15 in High Z
L
L
H
H
H
H
L
L
H
L
L
Data Out (I/O8–I/O15);
I/O0–I/O7 in High Z
H
Read (Lower Byte only)
L
L
L
L
H
H
H
H
H
H
H
L
H
H
H
X
L
H
L
L
L
High-Z
Output Disabled
High-Z
Output Disabled
Active (ICC)
H
L
High-Z
Output Disabled
L
Data In (I/O0–I/O15)
Write (Upper Byte and Lower Byte)
Data In (I/O0–I/O7);
I/O8–I/O15 in High Z
L
L
H
H
L
L
X
X
H
L
L
Write (Lower Byte Only)
Write (Upper Byte Only)
Data In (I/O8–I/O15);
I/O0 –I/O7 in High Z
H
February 23, 2005 S71AL016M_M0_A0
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A d v a n c e I n f o r m a t i o n
Revision Summary
Revision A 0 (February 23, 2005)
Initial release.
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary
industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that
includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal
injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and
artificial satellite). Please note that Spansion LLC will not be liable to you and/or any third party for any claims or damages arising in connection with above-
mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels
and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on ex-
port under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the
prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion LLC product under development
by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided
as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement
of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the
use of the information in this document.
Copyright ©2004-2005 Spansion LLC. All rights reserved. Spansion, the Spansion logo, and MirrorBit are trademarks of Spansion LLC. Other company and
product names used in this publication are for identification purposes only and may be trademarks of their respective companies
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