S71PL127JB0BFW9P3 [SPANSION]
Memory Circuit, 8MX16, CMOS, PBGA64, 8 X 11.60 MM, LEAD FREE, FBGA-64;
| 型号： | S71PL127JB0BFW9P3 |
| 厂家： | 
SPANSION |
| 描述： | Memory Circuit, 8MX16, CMOS, PBGA64, 8 X 11.60 MM, LEAD FREE, FBGA-64 |
| 文件： | 总37页 (文件大小：867K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S71PL127/129JB0
Stacked Multi-Chip Package (MCP) Flash Memory and
pSRAM
128 Megabit (8M x 16-Bit) CMOS 3.0 Volt-only
Simultaneous Operation Flash Memory and 32 Megabit
(2M x 16-Bit) CMOS Pseudo Static RAM with Page Mode
ADVANCE
Distinctive Characteristics
SecSiTM (Secured Silicon) Sector region
— Up to 128 words accessible through a command
sequence
MCP Features
Power supply voltage of 2.7 to 3.1 volt
High performance
— Up to 64 factory-locked words
— 70 ns maximum access time (Flash)
— 30 ns maximum page access time (Flash)
— 70 ns maximum access time (PSRAM)
— 30 ns maximum page access time (PSRAM)
Package
— Up to 64 customer-lockable words
Both top and bottom boot blocks in one device
Manufactured on 0.11 µm process technology
Data retention: 20 years typical
— 64-Ball FBGA
Cycling Endurance: 1 million cycles per sector
typical
Operating Temperature
— –25°C to +85°C
SOFTWARE FEATURES
Flash Memory Features
Software command-set compatible with JEDEC
42.4 standard
ARCHITECTURAL ADVANTAGES
— Backward compatible with Am29F and Am29LV
families
128 Mbit Page Mode device
— Page size of 8 words: Fast page read access from
random locations within the page
CFI (Common Flash Interface) compliant
— Provides device-specific information to the system,
allowing host software to easily reconfigure for
different Flash devices
Single power supply operation
— Full Voltage range: 2.7 to 3.1 volt read, erase, and
program operations for battery-powered applications
Erase Suspend / Erase Resume
— Suspends an erase operation to allow read or program
operations in other sectors of same bank
Dual Chip Enable inputs (PL129J)
— Two CE# inputs control selection of each half of the
memory space
Unlock Bypass Program command
Simultaneous Read/Write Operation
— Data can be continuously read from one bank while
executing erase/program functions in another bank
— Zero latency switching from write to read operations
— Reduces overall programming time when issuing
multiple program command sequences
HARDWARE FEATURES
FlexBank Architecture
— 4 separate banks, with up to two simultaneous
operations per device
— Bank A:
16Mbit (4Kw x 8 and 32Kw x 31)
— Bank B:
48Mbit ( 32Kw x 96)
— Bank C:
48 Mbit (32Kw x 96)
— Bank D:
Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting program or
erase cycle completion
Hardware reset pin (RESET#)
— Hardware method to reset the device to reading array
data
WP#/ ACC (Write Protect/Acceleration) input
— At VIL, hardware level protection for the first and last
two 4K word sectors.
— At VHH, provides accelerated programming in a
factory setting
16Mbit (4Kw x 8 and 32Kw x 31)
Persistent Sector Protection
— A command sector protection method to lock
combinations of individual sectors and sector groups
Publication Number S71PL127/129JB0_00 Revision A Amendment 0 Issue Date April 15, 2004
P r e l i m i n a r y
to prevent program or erase operations within that
sector
Password Sector Protection
— A sophisticated sector protection method to lock
combinations of individual sectors and sector groups
to prevent program or erase operations within that
sector using a user-defined 64-bit password
— Sectors can be locked and unlocked in-system at VCC
level
PSRAM Features
Power dissipation
— Operating: 40 mA maximum
— Standby: 135 µA maximum
Power down features using CE1#r and CE2r
Data retention supply voltage: 1.5 to 3.1 volt
Byte data control: LB# (DQ0–DQ7), UB#(DQ8–
DQ15)
CE1#r and CE2r Chip Select
Product Selector Guide
S71PL127JB0BAW9Z#
S71PL127JB0BAW9U#
S71PL127JB0BAW9P#
S71PL127JB0BFW9Z#
S71PL127JB0BFW9U#
S71PL127JB0BFW9P#
S71PL129JB0BAW9Z#
S71PL129JB0BAW9U#
S71PL129JB0BAW9P#
S71PL129JB0BFW9Z#
S71PL129JB0BFW9U#
S71PL129JB0BFW9P#
Part Number
Supply Voltage
V
= 2.7–3.1 V
V
= 2.7–3.1 V
CC
CC
Supply Voltage
Flash
70
PSRAM
70
Max Access Time, ns
Max CE# Access, ns
Max Page Access, ns
Max OE# Access, ns
70
70
30
30
30
40
Note:Both VCCf and VCCr must be the same level when
either part is being accessed.
2
S71PL127/129JB0
S71PL127/129JB0_00A0 April 15, 2004
A d v a n c e I n f o r m a t i o n
Figure 3. AC Measurement Output Load Circuit...................... 20
S71PL127/129JB0
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 4. Read TIming #1 (Basic Timing).............................. 21
Figure 5. Read Timing #2 (OE# and Address Access)............. 22
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 6. Read Timing #3 (LB#/UB# Byte Access)................. 23
Figure 7. Read Timing #4 (Page Access after CE1# Control Access)
24
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . 1
MCP Features ........................................................................................................ 1
Flash Memory Features ...................................................................................... 1
PSRAM Features ....................................................................................................2
Product Selector Guide . . . . . . . . . . .
2
Connection Diagram (S71PL127JB0) . . . . . . . . . . . .5
Special Handling Instructions For FBGA Package ...................................5
Input/Output Descriptions (S71PL127JB0) . . . . 6
Absolute Maximum Ratings . . . . . . . . . 10
Figure 1. Maximum Negative Overshoot Waveform................. 10
Figure 2. Maximum Positive
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 8. Read Timing #5 (Random and Page Address Access) 25
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 9. Write Timing #1 (Basic Timing).............................. 26
Figure 10. Write Timing #2 (WE# Control)............................ 27
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 28
Overshoot Waveform.......................................................... 10
Figure 11. Write Timing #3-1 (WE#/LB#/UB# Byte Write Control)
Operating Ranges . . . . . . . . . . . . . 10
BGA Pin Capacitance .......................................................................................... 11
TLA064—64-ball Fine-Pitch Ball Grid Array (FBGA)
28
Figure 12. Write Timing #3-2 (WE#/LB#/UB# Byte Write Control)
29
8 x 11.6 mm Package ........................................................................................... 12
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 13. Write Timing #3-3 (WE#/LB#/UB# Byte Write Control)
32Mb pSRAM (Supplier 1)
30
Figure 14. Write Timing #3-4 (WE#/LB#/UB# Byte Write Control)
31
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 15. Read/Write Timing #1-1 (CE1# Control) ............... 32
Figure 16. Read/Write Timing #1-2 (CE1#/WE#/OE# Control) 33
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 17. Read/Write Timing #2 (OE#, WE# Control) ........... 34
Figure 18. Read/Write Timing #3 (OE#, WE#, LB#, UB# Control)
35
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 19. Power-up Timing #1........................................... 35
Figure 20. Power-up Timing #2........................................... 36
pSRAM Block Diagram . . . . . . . . . . . . . . . . . . . . 14
Function Truth Table . . . . . . . . . . . . . . . . . . . . . . 15
Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power Down .....................................................................................................15
Power Down Program Sequence ...............................................................15
Address Key ..................................................................................................... 16
Recommended Operating Conditions . . . . . . . . 16
pSRAM DC Characteristics . . . . . . . . . . . . . . . . . 17
pSRAM AC Characteristics . . . . . . . . . . . . . . . . . 17
Read Operation ....................................................................................................17
PSRAM AC Characteristics . . . . . . . . . . . . . . . . . 19
Write Operation ................................................................................................. 19
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 20
Power Down Parameters ................................................................................ 20
Other Timing Parameters ............................................................................... 20
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 20
AC Test Conditions .......................................................................................... 20
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 21. Power-down Entry and Exit Timing........................ 36
Figure 22. Standby Entry Timing after Read or Write.............. 36
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 37
Revision Summary
April 15, 2004 S71PL127/129JB0_00A0
3
A d v a n c e I n f o r m a t i o n
MCP Block Diagram (S71PL127JB0)
VCC
f
VSS
A22 to A0
RY/BY#
A
22 to A0
WP#/ACC
128 M bit
Flash Memory
(Single CE)
RESET#
CE#f
DQ15 to DQ0
DQ15 to DQ0
VCC
r
VSS
A20 to A0
DQ15 to DQ0
32 M bit
PSRAM
LB#
UB#
WE#
OE#
CE1#r
CE2r
MCP Block Diagram (S71PL129JB0)
VCC
f
VSS
A21 to A0
RY/BY#
A
21 to A0
WP#/ACC
RESET#
128 M bit
Flash Memory
(Dual CE)
CE0#f
DQ15 to DQ0
CE1#f
DQ15 to DQ0
VCC
r
VSS
A20 to A0
DQ15 to DQ0
32 M bit
PSRAM
LB#
UB#
WE#
OE#
CE1#r
CE2r
April 15, 2004 S71PL127/129JB0_00A0
4
A d v a n c e I n f o r m a t i o n
Connection Diagram (S71PL127JB0)
64-ball Fine-Pitch Ball Grid Array
(Top View, Balls Facing Down)
A10
M10
N.C.
N.C.
D9
A15
D8
E9
A21
E8
F9
A22
F8
G9
A16
G8
H9
N. C.
H8
J9
VSS
J8
C8
A11
C7
K8
DQ14
K7
A12
D7
A13
E7
A14
F7
N.C.
G7
DQ15
H7
DQ7
J7
A8
A19
D6
A9
A10
DQ6
DQ13
H6
DQ12
J6
DQ5
K6
L6
B6
N.C.
B5
C6
E6
WE#
C5
CE2r
D5
A20
E5
DQ4
H5
VCCr
J5
N.C.
K5
N.C.
L5
N.C. WP#/ACC RESET# RY/BY#
DQ3
H4
VCCf
J4
DQ11
K4
N.C.
C4
LB#
C3
D4
UB#
D3
E4
A18
E3
F4
A17
F3
G4
DQ1
G3
DQ9
H3
DQ10
J3
DQ2
K3
A7
A6
A5
A4
F2
VSS
G2
OE#
H2
DQ0
J2
DQ8
D2
E2
A3
A2
A1
A0
CE#f
CE1#r
A1
M1
N.C.
N.C.
Connection Diagram (S71PL129JB0)
64-ball Fine-Pitch Ball Grid Array
(Top View, Balls Facing Down)
A10
M10
N.C.
N.C.
D9
A15
D8
E9
A21
E8
F9
CE1#f
F8
G9
A16
G8
H9
N. C.
H8
J9
VSS
J8
C8
A11
C7
K8
DQ14
K7
A12
D7
A13
E7
A14
F7
N.C.
G7
DQ15
H7
DQ7
J7
A8
A19
D6
A9
A10
DQ6
DQ13
H6
DQ12
J6
DQ5
K6
L6
B6
N.C.
B5
C6
E6
WE#
C5
CE2r
D5
A20
E5
DQ4
H5
VCCr
J5
N.C.
K5
N.C.
L5
N.C. WP#/ACC RESET# RY/BY#
DQ3
H4
VCCf
J4
DQ11
K4
N.C.
C4
LB#
C3
D4
UB#
D3
E4
A18
E3
F4
A17
F3
G4
DQ1
G3
DQ9
H3
DQ10
J3
DQ2
K3
A7
A6
A5
A4
F2
VSS
G2
OE#
H2
DQ0
J2
DQ8
D2
E2
A3
A2
A1
A0
CE0#f
CE1#r
A1
M1
N.C.
N.C.
Special Handling Instructions For FBGA Package
Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultra-
sonic cleaning methods. The package and/or data integrity may be compromised
if the package body is exposed to temperatures above 150°C for prolonged peri-
ods of time.
5
S71PL127/129JB0_00A0 April 15, 2004
A d v a n c e I n f o r m a t i o n
Input/Output Descriptions (S71PL127JB0)
Pin Name
A19to A0
A22 to A20
DQ15-DQ0
CE#f
Input / Output
Description
I
Address inputs (Common)
Address inputs (Flash)
Data input/output
I
I/O
I
Chip Enable (Flash)
CE1#r
CE2r
I
Chip Enable (PSRAM)
Chip Enable (PSRAM
Output Enable (Common)
Write Enable (Common)
I
OE#
I
WE#
I
RY/BY#
UB#
O
Ready/Busy Output (Flash) Open Drain Output
Upper Byte Control
I
LB#
I
Lower Byte Control
RESET#
WP#/ACC
N.C.
I
Hardware Reset Pin / Sector Protection Unlock (Flash)
Write Protect / Acceleration (Flash)
No Internal Connection
I
–
VSS
Power
Power
Power
Device Ground (Common)
V
CCf
Device Power Supply (Flash)
Device Power Supply (Flash)
V
CCr
Input/Output Descriptions (S71PL129JB0)
Pin Name
A19to A0
A21 to A20
DQ15-DQ0
CE0#f, CE1#f
CE1#r
Input / Output
Description
I
Address inputs (Common)
Address inputs (Flash)
Data input/output
I
I/O
I
Chip Enable (Flash)
I
Chip Enable (PSRAM)
Chip Enable (PSRAM
Output Enable (Common)
Write Enable (Common)
CE2r
I
OE#
I
WE#
I
RY/BY#
UB#
O
Ready/Busy Output (Flash) Open Drain Output
Upper Byte Control
I
LB#
I
Lower Byte Control
RESET#
WP#/ACC
N.C.
I
Hardware Reset Pin / Sector Protection Unlock (Flash)
Write Protect / Acceleration (Flash)
No Internal Connection
I
–
VSS
Power
Power
Power
Device Ground (Common)
V
CCf
Device Power Supply (Flash)
Device Power Supply (Flash)
V
CCr
April 15, 2004 S71PL127/129JB0_00A0
6
A d v a n c e I n f o r m a t i o n
Ordering Information
Valid Combinations
Flash
Initial/Page pSRAM
Speed (ns)
pSRAM
Initial/Page Compliant or
Speed (ns)
Pb-free
pSRAM
Supplier
MCP Package
Size (mm)
Ball
Count
Order Number
Flash
Pb-free
S71PL127JB0BAW9Z#
S71PL127JB0BAW9U#
S71PL127JB0BAW9P#
S71PL127JB0BFW9Z#
S71PL127JB0BFW9U#
S71PL127JB0BFW9P#
Supplier 1
Supplier 2
Supplier 3
Supplier 1
Supplier 2
Supplier 3
Pb-free
Compliant
S29PL127J
70/30
32Mb
70/30
8 x 11.6 x 1.2
64
Pb-free
S71PL129JB0BAW9Z#
S71PL129JB0BAW9U#
S71PL129JB0BAW9P#
S71PL129JB0BFW9Z#
S71PL129JB0BFW9U#
S71PL129JB0BFW9P#
Supplier 1
Supplier 2
Supplier 3
Supplier 1
Supplier 2
Supplier 3
Pb-free
Compliant
S29PL129J
70/30
32Mb
70/30
8 x 11.6 x 1.2
64
Pb-free
Notes:
1. # = 0 (Tray), 1 (7” Tape and Reel), or 3 (13” Tape and Reel)
Device Bus Operations (S71PL127B0)
WP/
A22 to DQ7 to DQ15 to
Operation (1), (2)
CEf# CE1r# CE2r OE# WE# LB# UB#
RESET
ACC
(7)
A0
DQ0
DQ8
Full Standby
H
H
L
H
L
H
H
X
H
X
H
X
X
X
X
X
High-Z
High-Z
High-Z
High-Z
H
H
X
X(6)
X
Output Disable
X
H
H
H
Read from Flash (3)
Write to Flash
L
H
H
L
H
L
X
X
L
X
X
L
Valid
Valid
DOUT
DIN
DOUT
DIN
H
H
X
X
L
H
DIN
DIN
Read from PSRAM
PSRAM No Read
Write to PSRAM
PSRAM No Write
H
H
H
L
L
L
H
H
H
L
L
H
H
L
H
L
L
Valid
Valid
Valid
High-Z
DIN
DIN
H
H
H
X
X
X
H
H
L
High-Z
High-Z
DIN
H
L
High-Z
DIN
H(5)
H
L
L
High-Z
DIN
DIN
H
H
High-Z
High-Z
H
X
X
X
X
L
X
H
X
X
H
X
H
X
L
H(5)
X
L
X
X
X
X
H
Valid
High-Z
H
VID
L
X
X
X
L
Flash Temporary Sector
Group Unprotection(4)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Flash Hardware Reset
X
High-Z
High-Z
Flash Boot Block Sector Write
Protection
X
X
X
X
X
X
PSRAM Power Down
X
X
X
Legend:Legend: L = VIL, H = VIH, X can be either VIL or VIH, Hihe-Z = High Impedance.
See DC Characteristics for voltage levels.
7
S71PL127/129JB0_00A0 April 15, 2004
A d v a n c e I n f o r m a t i o n
Note:
1. Other operations except for indicated this column are inhibited.
2. Do not apply for a following state two or more on the same time;
1) CEf# = VIL, 2) CE1r# = VIL and CE2r = VIH
,
3. WE# can be VIL if OE# is VIL, OE# at VIH initiates the write operations.
4. It is also used for the extended sector group protections.
5. OE# can be VIL during Write operation if the following conditions are satisfied;
1) Write pulse is initiated by CE1r# (refer to CE1r# Controlled Write timing), or cycle time of the previous
operation cycle is satisfied.
2) OE# stays VIL during Write cycle.
6. Can be either VIL or VIH but must be valid before Read or Write.
7. Protect “ outer most “ 2×8K bytes ( 4 words ) on both ends of the boot block sectors.
Device Bus Operations (S71PL129B0)
WP/
Operation
(1), (2)
A21 to DQ7 to DQ15 to
WE
#
RESET
#
CE0#f CE1#f CE1#r CE2r OE
LB# UB#
ACC
(7)
A0
DQ0
DQ8
Full Standby
H
H
L
H
H
H
L
H
L
H
H
X
H
X
H
X
X
X
X
X
High-Z
High-Z
H
H
X
X(6)
Output Disable
H
H
High-Z
High-Z
X
X
H
L
H
L
Read from Flash (3)
Write to Flash
H
H
L
H
X
X
Valid
DOUT
DOUT
H
X
H
L
H
L
H
H
H
H
H
H
L
L
X
X
L
X
X
L
Valid
Valid
DIN
DIN
DIN
DIN
H
H
X
X
H
DIN
DIN
Read from PSRAM
PSRAM No Read
Write to PSRAM
PSRAM No Write
H
H
H
H
H
H
L
L
L
H
H
H
L
L
H
H
L
H
L
L
Valid
Valid
Valid
High-Z
DIN
DIN
H
H
H
X
X
X
H
H
L
High-Z
High-Z
DIN
H
L
High-Z
DIN
H(5)
H
L
L
High-Z
DIN
DIN
H
H
High-Z
High-Z
H
X
X
X
X
H
X
X
X
X
L
X
H
X
X
H
X
H
X
L
H(5)
X
L
X
X
X
X
H
Valid
High-Z
H
VID
L
X
X
X
L
Flash Temporary Sector
Group Unprotection(4)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Flash Hardware Reset
X
High-Z
High-Z
Flash Boot Block Sector Write
Protection
X
X
X
X
X
X
PSRAM Power Down
X
X
X
Legend: L = VIL, H = VIH, X can be either VIL or VIH, Hihe-Z = High Impedance. See DC Characteristics for voltage levels.
Note:
1. Other operations except for indicated this column are inhibited.
2. Do not apply for a following state two or more on the same time;
1) CEf# = VIL, 2) CE1r# = VIL and CE2r = VIH
,
3. WE# can be VIL if OE# is VIL, OE# at VIH initiates the write operations.
4. It is also used for the extended sector group protections.
5. OE# can be VIL during Write operation if the following conditions are satisfied;
1) Write pulse is initiated by CE1r# (refer to CE1r# Controlled Write timing), or cycle time of the previous
April 15, 2004 S71PL127/129JB0_00A0
8
A d v a n c e I n f o r m a t i o n
operation cycle is satisfied.
2) OE# stays VIL during Write cycle.
6. Can be either VIL or VIH but must be valid before Read or Write.
7. Protect “ outer most “ 2×8K bytes ( 4 words ) on both ends of the boot block sectors.
9
S71PL127/129JB0_00A0 April 15, 2004
A d v a n c e I n f o r m a t i o n
Absolute Maximum Ratings
Rating
Parameter
Storage Temperature
Symbol
Tstg
Min.
–55
–25
Max.
+125
Unit
°C
°C
V
Ambient Temperature with Power Applied
Voltage with Respect to Ground All pins
except RESET ,WP/ACC *1
VCCf/VCCr Supply *1
RESET *2
WP/ACC *3
TA
+85
VCCf +0.3
VCCr +0.3
+3.3
VIN, VOUT
–0.3
V
VCCf,VCC
r
–0.3
–0.5
–0.5
V
VIN
+ 13.0
+10.5
V
VIN
V
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot VSS
to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. See Figure 1. During
voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 2.
2. Minimum DC input voltage on pins RESET#, and WP#/ACC is –0.5 V. During voltage transitions, WP#/ACC, and
RESET# may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 1. Maximum DC input voltage on pin
RESET# is +12.5 V which may overshoot to +14.0 V for periods up to 20 ns. Maximum DC input voltage on WP#/
ACC is +9.5 V which may overshoot to +12.0 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections
of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect
device reliability.
20 ns
20 ns
20 ns
VCC
+2.0 V
+0.8 V
VCC
–0.5 V
–2.0 V
+0.5 V
2.0 V
20 ns
20 ns
20 ns
Figure 1. Maximum Negative
Overshoot Waveform
Figure 2. Maximum Positive
Overshoot Waveform
Operating Ranges
Value
Parameter
Symbol
Min.
–25
Max.
+85
Unit
°C
Ambient Temperature
TA
V
CCf/VCCr Supply Voltages
VCCf,VCC
r
+2.7
+3.1
V
Note:Operating ranges define those limits between which the functionality of the device is guaranteed.
April 15, 2004 S71PL127/129JB0_00A0
10
A d v a n c e I n f o r m a t i o n
DC Characteristics
Electrical Characteristics (AC Characteristics)
CE# TIMING
Symbol
Value
Parameter
Condition
Unit
JEDEC
Standard
Min.
0
Max.
—
CE# Recover Time
—
—
—
tCCR
—
—
—
ns
ns
ns
CE# Hold Time
tCHOLD
tCHWX
3
—
CE1#r High to WE Invalid time for Standby Entry
10
—
TIMING DIAGRAM FOR ALTERNATING RAM TO FLASH
CE0#f or
CE1#f
tCCR
tCCR
CE1#r
WE#
tCHWX
tCHOLD
tCCR
tCCR
CE2r
Flash Characteristics
— Please refer to S29PL127J/S29PL129J specification on the S29PL032J/S29PL064J/S29PL127J/S29PL129J datasheet.
PSRAM Characteristics
— Please refer to “32Mb pSRAM (Supplier 1)” on page 14.
BGA Pin Capacitance
Parameter
Symbol
Parameter Description
Input Capacitance
Test Setup
VIN = 0
Typ
tbd
tbd
tbd
Max
tbd
Unit
pF
CIN
COUT
CIN2
Output Capacitance
Control Pin Capacitance
VOUT = 0
VIN = 0
tbd
pF
tbd
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
11
S71PL127/129JB0_00A0 April 15, 2004
A d v a n c e I n f o r m a t i o n
Physical Dimensions
TLA064—64-ball Fine-Pitch Ball Grid Array (FBGA)
8 x 11.6 mm Package
A
D1
D
eD
0.15
(2X)
C
10
9
8
7
6
5
4
3
2
1
SE
7
E
B
E1
eE
L
J
H
G
F
E
D
C
B
A
M
K
INDEX MARK
10
PIN A1
CORNER
PIN A1
CORNER
7
SD
0.15
(2X)
C
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.20
0.08
C
C
A2
A
C
A1
6
64X
b
0.15
0.08
M
C
C
A B
M
NOTES:
PACKAGE
JEDEC
TLA 064
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
11.60 mm x 8.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
---
NOM
---
MAX
1.20
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.17
0.81
---
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
0.97
BODY THICKNESS
BODY SIZE
D
11.60 BSC.
8.00 BSC.
8.80 BSC.
7.20 BSC.
12
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
E1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
10
64
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
φb
0.35
0.40
0.45
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
eE
0.80 BSC.
0.80 BSC
0.40 BSC.
BALL PITCH
eD
SD / SE
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
A2,A3,A4,A5,A6,A7,A8,A9
B1,B2,B3,B4,B7,B8,B9,B10
C1,C2,C9,C10,D1,D10,E1,E10,
F1,F5,F6,F10,G1,G5,G6,G10
H1,H10,J1,J10,K1,K2,K9,K10
L1,L2,L3,L4,L7,L8,L9,L10
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
M2,M3,M4,M5,M6,M7,M8,M9
3352 \ 16-038.22a
April 15, 2004 S71PL127/129JB0_00A0
12
P r e l i m i n a r y
32Mb pSRAM (Supplier 1)
32Mb (2 M word x 16 bit)
CMOS 2,097,152 x 16 BIT
pSRAM Block Diagram
VDD
VSS
MEMORY
CELL
A20
to
A0
ADDRESS
LATCH &
BUFFER
ROW
DECODER
ARRAY
33,554,432 bit
DQ15
to
INPUT /
OUTPUT
BUFFER
DQ8
INPUT DATA
LATCH &
CONTROL
OUTPUT
DATA
CONTROL
SENSE /
SWITCH
DQ7
to
DQ0
COLUMN /
DECODER
ADDRESS
LATCH &
BUFFER
POWER
CONTROL
CE2
CE1
WE
LB
TIMING
CONTROL
UB
OE
April 7, 2004 S71PL127/129JB0_00A0
32Mb pSRAM (Supplier 1)
14
P r e l i m i n a r y
Function Truth Table
Mode
CE2
CE1#
WE#
OE#
X
LB#
X
UB#
X
A20-0
DQ7-0
DQ15-8
High-Z
High-Z
High-Z
Standby (Deselect)
H
H
X
H
X
High-Z
Output Disable (Note 1)
Output Disable (No Read)
H
H
X
(Note 3) High-Z
H
H
Valid
High-Z
Output
Valid
Read (Upper Byte)
Read (Lower Byte)
Read (Word)
H
L
L
H
L
Valid
High-Z
H
L
Output
Valid
Valid
Valid
High-Z
Output
Valid
Output
Valid
H
L
L
No Write
H
H
H
L
Valid
Valid
Invalid
Invalid
Write (Upper Byte)
Invalid Input Valid
Input
Invalid
Valid
L
H (Note 4)
Write (Lower Byte)
Write (Word)
L
H
Valid
Input
L
L
Valid
X
Input Valid
Valid
Power Down (Note 2)
L
X
X
X
X
High-Z
High-Z
Note:
1. Should not be kept this logic condition longer than 1 µs.
2. Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. Data retention depends on the
selection of Power Down Program. Refer to Power down for details.
3. Can be either VIL or VIH but must be valid for read or write.
4. OE# can be VIL during Write operation if the following conditions are satisfied; Write pulse is initiated by CE1# (refer to
CE1# Controlled Write timing), or cycle time of the previous operation cycle is satisfied, OE stays during Write cycle.
Power Down
Power Down
The Power Down is to enter low power idle state when CE2 stays Low. The pSRAM
has two power down modes, Deep Sleep 4M Partial and 8M Partial. These can be
programmed by series of read/write operation. See the following table for mode
features.
Mode
Data Retention
Retention Address
Sleep
(default)
No
N/A
4M Partial
8M Partial
4M bit
8M bit
00000h to 3FFFFh
00000h to 7FFFFh
The default state is Sleep and it is the lowest power consumption but all data will
be lost once CE2 is brought to Low for Power Down. It is not required to program
to Sleep mode after power-up.
Power Down Program Sequence
The program requires total 6 read/write operation with unique address and data.
Between each read/write operation requires that device be in standby mode. The
following table shows the detail sequence.
15
32Mb pSRAM (Supplier 1)
S71PL127/129JB0_00A0 April 7, 2004
P r e l i m i n a r y
Cycle#
1st
Operation
Read
Address
Data
1FFFFFh (MSB) Read Data (RDa)
2nd
3rd
Write
1FFFFFh
1FFFFFh
RDa
RDa
Write
4th
Write
1FFFFFh
Don’t Care (X)
X
5th
Write
1FFFFFh
6th
Read
Address Key
Read Data (RDb)
The first cycle is to read from most significant address (MSB). The second and
third cycle are to write back the data (RDa) read by first cycle. If the second or
third cycle is written into the different address, the program is cancelled and the
data written by the second or third cycle is valid as a normal write operation. The
fourth and fifth cycle is to write to MSB. The data of fourth and fifth cycle is don’t
care. If the fourth or fifth cycle is written into different address, the program is
also cancelled but write data may not be wrote as normal write operation. The
last cycle is to read from specific address key for mode selection. Once this pro-
gram sequence is performed from a Partial mode, the write data may be lost. So,
it should perform this program prior to regular read/write operation if Partial
mode is used.
Address Key
The address key has the following format.
Address
Mode
A20
A19
A18-A0
Binary
Sleep
(default)
1
1
1
1FFFFFh
4M Partial
8M Partial
1
0
0
1
1
1
17FFFFh
07FFFFh
Recommended Operating Conditions
Parameter
Symbol
Min.
2.7
0
Max.
Unit
V
VDD
VSS
3.1
Supply Voltage
0
V
VDD + 0.2 and
VIH
0.8 VDD
V
≤+3.6
High Level Input Voltage
VIH
VIL
0.8 VDD
-0.3
VDD + 0.2
0.2 VDD
V
V
Low Level Input Voltage
Ambient Temperature
TA
–25
85
°
C
Notes:
1. Maximum DC voltage on input and I/O pins are VDD + 0.2 V. During voltage transitions, inputs may positive overshoot to VDD
+ 1.0 V for periods of up to 5 ns.
2. Minimum DC voltage on input or I/O pins are -0.3 V. During voltage transitions, inputs may negative overshoot VSS to -1.0 V
for periods of up to 5 ns.
April 7, 2004 S71PL127/129JB0_00A0
32Mb pSRAM (Supplier 1)
16
P r e l i m i n a r y
pSRAM DC Characteristics
Parameter
Symbol
Test Conditions
Min.
Max.
Unit
Input Leakage
Current
ILI
VIN = VSS to VDD
-1.0
+1.0
µ
A
A
OutputLeakage
Current
ILO
VOH
VOL
VOUT = VSS to VDD, Output Disable
VDD = VDD(min), IOH = –0.5mA
IOL = 1 mA
-1.0
2.4
–
+1.0
–
µ
Output High
Voltage Level
V
Output Low
Voltage Level
0.4
V
IDDPS
IDDP8
IDDS
SLEEP
8M Partial
–
–
–
10
50
µ
A
VDD Power
Down Current
VDD = VDD max., VIN = VIH or
VIL, CE2 0.2V
≤
µA
VDD = VDD max., VIN = VIH or VIL, CE1#
1.5
mA
VDD Standby
Current
VDD = VDD max., VIN
≤
0.2 V or VIN
≥ VDD – 0.2 V,
VDD – 0.2V
IDDS1
–
80
µA
CE1# =CE2
≥
VDD = VDD max., VIN = VIH or
VIL, CE1# = VIL and CE2 =
tRC/tWC =
minimum
IDDA1
IDDA2
IDDA3
–
–
–
30
3
mA
mA
mA
VDD Active
Current
VIH
,
tRC/tWC = 1 µs
IOUT = 0 mA
VDD Page Read
Current
VDD = VDD max., VIN = VIH or VIL, CE1# = VIL
and CE2 = VIH, IOUT = 0 mA, tPRC = min.
10
Notes:
1. All voltages are referenced to VSS
.
2. DC Characteristics are measured after following POWER-UP timing.
3. IOUT depends on the output load conditions.
pSRAM AC Characteristics
Read Operation
Value
Parameter
Read Cycle Time (Notes 1, 2)
Symbol
tRC
Min.
65
–
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1000
65
40
65
30
20
1000
–
CE1# Access Time (Note 3)
tCE
OE# Access Time (Note 3)
tOE
–
Address Access Time (Notes 3,5)
LB#/UB# Access Time (Note 3)
Page Address Access Time (Notes 3,6)
Page Read Cycle Time (Notes 1,6,7)
Output Data Hold Time (Note 3)
CE1# Low to Output Low-Z (Note 4)
OE# Low to Output Low-Z (Note 4)
LB#/UB# Low to Output High-Z (Note 4)
CE1# High to Output High-Z (Note 3)
OE# High to Output High-Z (Note 3)
tAA
–
tBA
–
tPAA
tPRC
tOH
–
25
5
tCLZ
tOLZ
tBLZ
tCHZ
tOHZ
5
–
0
–
0
–
–
20
20
–
17
32Mb pSRAM (Supplier 1)
S71PL127/129JB0_00A0 April 7, 2004
P r e l i m i n a r y
Value
Parameter
Symbol
tBHZ
Min.
–
Max.
20
–
Unit
ns
LB#/UB# High to Output High-Z (Note 3)
Address Setup Time to CE1# Low
Address Setup Time to OE# Low
Address Invalid Time (Notes 5,8)
Address Hold Time from CE1# High (Note 9)
Address Hold Time from OE# High
CE1# High Pulse Width
tASC
-5
10
–
ns
tASO
–
ns
tAX
ns
tCHAH
tOHAH
tCP
-5
-5
12
–
–
–
ns
ns
ns
April 7, 2004 S71PL127/129JB0_00A0
32Mb pSRAM (Supplier 1)
18
P r e l i m i n a r y
Notes:
1. Maximum value is applicable if CE1# is kept at Low without change of address input of A3 to A20.
2. Address should not be changed within minimum tRC.
3. The output load 50pF.
4. The output load 5pF.
5. Applicable to A3 to A20 when CE1# is kept at Low.
6. Applicable only to A0, A1 and A2 when CE1# is kept at Low for the page address access.
7. In case Page Read Cycle is continued with keeping CE1# stays Low, CE1# must be brought to High within 4
µs. In other words, Page Read Cycle must be closed within 4 µs.
8. Applicable when at least two of address inputs among applicable are switched from previous state.
9. tRC (min) and tPRC (min) must be satisfied.
PSRAM AC Characteristics
Write Operation
Value
Parameter
Symbol
tWC
Min.
65
0
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
ns
ns
ns
Write Cycle Time (Notes 1, 2)
Address Setup Time (Note 3)
1000
tAS
–
CE1# Write Pulse Width (Note 3)
tCW
40
40
40
-5
-5
12
7.5
12
12
0
–
WE# Write Pulse Width (Note 3)
tWP
–
LB#/UB# Write Pulse Width (Note 3)
LB#/UB# Byte Mask Setup Time (Note 4)
LB#/UB# Byte Mask Hold Time (Note 5)
CE1# Write Recovery Time (Note 6)
WE# Write Recovery Time (Note 6)
LB#/UB# Write Recovery Time (Note 6)
Data Setup Time
tBW
tBS
–
–
tBH
–
tWRC
tWR
–
1000
tBR
1000
tDS
tDH
–
–
–
–
–
–
–
–
Data Hold Time
OE# High to CE1# Low Setup Time for Write (Note 7)
OE# High to Address Setup Time for Write (Note 8)
WE#/UB#/LB# High to OE# Low Setup Time for Read (Note 10)
LB# and UB# Write Pulse Overlap
tOHCL
tOES
tWHOL
tBWO
tCP
-5
0
12
30
12
0
CE1# High Pulse Width
Address Hold Time for Write End (Note (Note 3)
tAH
Notes:
1. Maximum value is applicable if CE1# is kept at Low without any address change.
2. Minimum value must be equal or greater than the sum of write pulse (tCW, TWP, TBW) and write recovery time
(tWCR, TWR or tBR).
3. Write pulse is defined from High to Low transition of CE1#, WE#, or LB#/UB#, whichever occurs last.
4. Applicable for byte mask only. Byte mask setup time is defined to the High to Low transition of CE1# or WE#
whichever occurs last.
5. Applicable for byte mask only. Byte mask hold time is defined from the Low to High transition of CE1# or
WE# whichever occurs first.
6. Write recovery is defined from Low to High transition of CE1#, WE#, or LB#/UB#, whichever occurs first.
7. If OE# is Low after minimum tOHCL, read cycle is initiated. In other words, OE# must be brought to High
within 5 ns after CE1# is brought to Low. Once read cycle is initiated, new write pulse should be input after
minimum tRC is met
8. If OE# is Low after new address input, read cycle is initiated. In other words, OE# must be brought to High
at the same time or before new address valid. Once read cycle is initiated, new write pulse should be input
19
32Mb pSRAM (Supplier 1)
S71PL127/129JB0_00A0 April 7, 2004
P r e l i m i n a r y
after minimum tRC is met and data bus is in High-Z
9. Absolute minimum values and defined at minimum VIH level.
10.If the actual value of tWHOL is shorter than the specified minimum values, the actual tAA of following Read
may become longer by the amount of subtracting the actual value from the specified minimum value.
AC Characteristics
Power Down Parameters
Value
Parameter
CE2 Low Setup Time for Power Down Entry
CE2 Low Hold Time after Power Down Entry
Symbol
tCSP
Min.
10
Max.
Unit
ns
–
–
tC2LP
65
ns
CE1# High Hold Time following CE2 High after Power Down Exit
(SLEEP mode only) (Note 1)
tCHH
tCHHP
tCHS
300
1
–
–
–
µ
s
s
CE1# High Hold Time following CE2 High after Power Down Exit
(not in SLEEP mode) (Note 2)
µ
CE1# High Setup Time following CE2 High after Power Down Exit (Note
1)
0
ns
Notes:
1. Applicable also to power up.
2. Applicable when 8M Partial mode is programmed.
Other Timing Parameters
Value
Parameter
CE#1 High to OE# Invalid Time for Standby Entry
CE#1 High to WE# Invalid Time for Standby Entry (Note 1)
CE2 Low Hold Time after Power up
Symbol
tCHOX
tCHWX
tC2LH
tCHH
Min.
10
Max.
Unit
ns
-
-
10
ns
50
–
µ
s
s
CE1# High Hold Time following CE2 High after Power up
Input Transition Time (Note 2)
300
1
–
µ
tT
25
ns
Notes:
1. Some data might be written into any address location if tCHWX (min) is not satisfied
2. The Input Transition Time (tT) at AC testing is 5ns, as shown in AC Test Conditions below.. If actual tT is longer
than 5ns, it may violate AC specification of some timing parameters.
AC Characteristics
AC Test Conditions
Symbol
VIH
Description
Input High Level
Test Setup
15, 11
VDD * 0.8
VDD * 0.2
VDD * 0.5
5
Unit
V
VIL
Input Low Level
V
VREF
tT
Input Timing Measurement Level
Input Transition Time
V
Between VIL and VIH
ns
VDD
DEVICE
UNDER
TEST
OUT
0.1 F
VSS
50pF
Figure 3. AC Measurement Output Load Circuit
April 7, 2004 S71PL127/129JB0_00A0
32Mb pSRAM (Supplier 1)
20
P r e l i m i n a r y
Timing Diagrams
tRC
ADDRESS VALID
ADDRESS
tASC
tCHAH
tASC
tCE
CE1#
OE#
tCP
tCHZ
tOE
tOHZ
tBA
LB / UB#
tBHZ
tBLZ
tOLZ
tCLZ
tOH
DQ
(Output)
VALID DATA OUTPUT
Note: CE2 and WE# must be High for entire read cycle.
Figure 4. Read TIming #1 (Basic Timing)
21
32Mb pSRAM (Supplier 1)
S71PL127/129JB0_00A0 April 7, 2004
P r e l i m i n a r y
tAx
tRC
tRC
ADDRESS
CE1#
ADDRESS VALID
ADDRESS VALID
tAA
tAA
tOHAH
Low
tASO
tOE
OE#
LB / UB#
tOHZ
tOH
tOLZ
tOH
DQ
(Output)
VALID DATA OUTPUT
VALID DATA OUTPUT
Note: CE2 and WE# must be High for entire read cycle.
Figure 5. Read Timing #2 (OE# and Address Access)
April 7, 2004 S71PL127/129JB0_00A0
32Mb pSRAM (Supplier 1)
22
P r e l i m i n a r y
Timing Diagrams
tAX
tRC
tAx
ADDRESS
ADDRESS VALID
tAA
CE1#,OE#
Low
tBA
tBA
LB#
UB#
tBA
tBHZ
tOH
tBHZ
tOH
tBLZ
tBLZ
DQ0-DQ7
(Output)
VALID DATA
OUTPUT
VALID DATA
OUTPUT
tBHZ
tOH
tBLZ
DQ8-DQ15
(Output)
VALID DATA OUTPUT
Note: CE2 and WE# must be High for entire read cycle.
Figure 6. Read Timing #3 (LB#/UB# Byte Access)
23
32Mb pSRAM (Supplier 1)
S71PL127/129JB0_00A0 April 7, 2004
P r e l i m i n a r y
tRC
ADDRESS
(A20-A3)
ADDRESS VALID
tRC
tPRC
tPRC
tPRC
ADDRESS
(A2-A0)
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS VALID
tASC
tPAA
tPAA
tPAA
tCHAH
CE1#
OE#
tCE
tCHZ
LB# / UB#
tOH
tOH
tOH
tOH
tCLZ
DQ
(Output)
VALID DATA OUTPUT
(Page Access)
VALID DATA OUTPUT
(Normal Access)
Note:CE2 and WE# must be High for entire read cycle.
Figure 7. Read Timing #4 (Page Access after CE1# Control Access)
April 7, 2004 S71PL127/129JB0_00A0
32Mb pSRAM (Supplier 1)
24
P r e l i m i n a r y
Timing Diagrams
tRC
tAX
tRC
tAx
ADDRESS
(A20-A3)
ADDRESS VALID
ADDRESS VALID
tRC
tRC
tPRC
tPRC
ADDRESS
(A2-A0)
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
tPAA
tAA
tAA
tPAA
CE1#
Low
tASO
tOE
tBA
OE#
LB# / UB#
tOH
tOLZ
tBLZ
tOH
tOH
tOH
DQ
(Output)
VALID DATA OUTPUT
(Page Access)
VALID DATA OUTPUT
(Normal Access)
Note: CE2 and WE# must be High for entire read cycle. Either or both LB# and UB# must be Low when both
CE1# and OE# are Low.
Figure 8. Read Timing #5 (Random and Page Address Access)
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32Mb pSRAM (Supplier 1)
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P r e l i m i n a r y
Timing Diagrams
tWC
ADDRESS
CE1#
ADDRESS VALID
tCW
tAS
tAH
tAS
tWR
tAS
tWP
WE#
tAS
tAS
tBR
tBW
LB#, UB#
tAS
tOHCL
OE#
tDS
tDH
DQ
(Input)
VALID DATA INPUT
Note: CE2 must be High for Write Cycle.
Figure 9. Write Timing #1 (Basic Timing)
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P r e l i m i n a r y
t
WC
tWC
ADDRESS VALID
ADDRESS VALID
ADDRESS
CE1#
t
OHAH
Low
t
AS
t
WP
t
AH
tAS
t
WP
tWR
WE#
t
WR
LB#, UB#
OE#
tOES
tOHZ
t
DS
tDH
t
DS
t
DH
DQ
(Input)
VALID DATA INPUT
VALID DATA INPUT
Note: CE2 must be High for Write Cycle.
Figure 10. Write Timing #2 (WE# Control)
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Timing Diagrams
tWC
tWC
ADDRESS VALID
ADDRESS VALID
ADDRESS
CE1#
Low
tWR
tWR
WE#
LB#
tAS
tBW
tBS
tBH
tBH
tAS
tBW
tBS
UB#
tDS
tDH
DQ0-DQ8
(Input)
tDS
tDH
VALID DATA INPUT
DQ8-DQ15
(Input)
VALID DATA INPUT
Note: CE2 must be High for Write Cycle.
Figure 11. Write Timing #3-1 (WE#/LB#/UB# Byte Write Control)
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P r e l i m i n a r y
tWC
tWC
ADDRESS VALID
ADDRESS VALID
ADDRESS
CE1#
Low
WR
tWR
t
WE#
tAS
tBW
tBS
tBH
LB#
UB#
tBH
tAS
tBW
tBS
tDS
tDH
DQ0-DQ7
(Input)
tDS
tDH
VALID DATA INPUT
DQ8-DQ15
(Input)
VALID DATA INPUT
Note: CE2 must be High for Write Cycle.
Figure 12. Write Timing #3-2 (WE#/LB#/UB# Byte Write Control)
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32Mb pSRAM (Supplier 1)
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P r e l i m i n a r y
Timing Diagrams
tWC
tWC
ADDRESS VALID
ADDRESS VALID
ADDRESS
CE1#
Low
WE#
LB#
UB#
tAS
tBW
tBR
tBS
tBH
tAS
tBW
tBR
tBS
tBH
tDS
tDH
DQ0-DQ7
(Input)
tDS
tDH
VALID DATA INPUT
DQ8-DQ15
(Input)
VALID DATA INPUT
Note: CE2 must be High for Write Cycle.
Figure 13. Write Timing #3-3 (WE#/LB#/UB# Byte Write Control)
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P r e l i m i n a r y
tWC
tWC
ADDRESS VALID
ADDRESS VALID
ADDRESS
CE1#
Low
WE#
tAS
tBW
tBR
tAS
tBW
tBR
LB#
tBWO
tDS
tDH
tDS
tDH
DQ0-DQ7
(Input)
VALID
VALID
DATA INPUT
DATA INPUT
tBWO
tBW
tAS
tBW
tBR
tAS
tBR
UB#
tDS
tDH
tDS
tDH
DQ8-DQ15
(Input)
VALID
DATA INPUT
VALID
DATA INPUT
Note: CE2 must be High for Write Cycle.
Figure 14. Write Timing #3-4 (WE#/LB#/UB# Byte Write Control)
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32Mb pSRAM (Supplier 1)
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P r e l i m i n a r y
Timing Diagrams
tWC
tRC
ADDRESS
WRITE ADDRESS
READ ADDRESS
tCHAH
tWRC
tAS
tASC
tCHAH
tCW
tCE
CE1#
tCP
tCP
WE#
UB#,LB#
tOHCL
OE#
DQ
tCHZ
tDH
tOH
tDS
tCLZ
tOH
READ DATA OUTPUT
WRITE DATA INPUT
Note: Write address is valid from either CE1# or WE# of last falling edge.
Figure 15. Read/Write Timing #1-1 (CE1# Control)
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32
P r e l i m i n a r y
tWC
tRC
ADDRESS
CE1#
WRITE ADDRESS
READ ADDRESS
tCHAH
tAS
tWR
tASC
tCHAH
tCE
tCP
tCP
tWP
WE#
UB#,LB#
OE#
tOHCL
tOE
tCHZ
tOH
tDS
tDH
tOLZ
tOH
DQ
READ DATA OUTPUT
WRITE DATA INPUT
READ DATA OUTPUT
Note: OE# can be fixed Low during write operation if it is CE1# controlled write at Read-Write-Read sequence.
Figure 16. Read/Write Timing #1-2 (CE1#/WE#/OE# Control)
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32Mb pSRAM (Supplier 1)
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P r e l i m i n a r y
Timing Diagrams
tWC
tRC
ADDRESS
WRITE ADDRESS
READ ADDRESS
tAA
tOHAH
tOHAH
CE1#
WE#
Low
tAS
tWR
tWP
tOES
UB#,LB#
OE#
tASO
tOE
tOHZ
tOHZ
tOH
tDS
tDH
tOLZ
tOH
DQ
READ DATA OUTPUT
READ DATA OUTPUT
WRITE DATA INPUT
Note: CE1# can be tied to Low for WE# and OE# controlled operation.
Figure 17. Read/Write Timing #2 (OE#, WE# Control)
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P r e l i m i n a r y
tWC
tRC
ADDRESS
CE1#
WRITE ADDRESS
READ ADDRESS
tAA
tOHAH
tOHAH
Low
WE#
tOES
tAS
tBW
tBR
tBA
UB#,LB#
OE#
tASO
tBHZ
tBHZ
tOH
tDS
tDH
tBLZ
tOH
DQ
READ DATA OUTPUT
READ DATA OUTPUT
WRITE DATA INPUT
Note: CE#1 can be tied to Low for WE# and OE# controlled operation.
Figure 18. Read/Write Timing #3 (OE#, WE#, LB#, UB# Control)
Timing Diagrams
CE1#
tCHS
tC2LH
tCHH
CE2
VDD
VDD min
0V
Note: The tC2LH specifies after VDD reaches specified minimum level.
Figure 19. Power-up Timing #1
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P r e l i m i n a r y
CE1#
CE2
VDD
tCHH
VDD min
0V
Note: The tCHH specifies after VDD reaches specified minimum level and applicable to both CE1# and CE2.
Figure 20. Power-up Timing #2
Timing Diagrams
CE1#
tCHS
CE2
tCSP
tC2LP
tCHH (tCHHP)
High-Z
DQ
Power Down Entry
Power Down Mode
Power Down Exit
Note: This Power Down mode can be also used as a reset timing if Power-up timing above could not be satisfied
and Power-Down program was not performed prior to this reset.
Figure 21. Power-down Entry and Exit Timing
CE1#
tCHOX
tCHWX
OE#
WE#
Active (Read)
Standby
Active (Write)
Standby
Note: Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied,
it takes tRC (min) period for standby mode from CE1# Low to High transition.
Figure 22. Standby Entry Timing after Read or Write
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36
P r e l i m i n a r y
Timing Diagrams
tRC
tWC
tWC
tWC
tWC
tRC
MSB*1
MSB*1
MSB*1
MSB*1
MSB*1
Key*2
ADDRESS
tCP*3
tCP
tCP
tCP
tCP
tCP
CE1#
OE#
WE#
LB#,UB#
DQ*3
RDa
RDa
RDa
X
X
RDb
Cycle #1
Cycle #2
Cycle #3
Cycle #4
Cycle #5
Cycle #6
Notes:
1. The all address inputs must be High from Cycle #1 to #5.
2. After tCP following Cycle #6, the Power Down Program is completed and returned to the normal operation.
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Revision Summary
Revision A (April 15, 2004)
Initial release.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by
FASL LLC. FASL LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided ìas isî
without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of
third-party rights, or any other warranty, express, implied, or statutory. FASL LLC assumes no liability for any damages of any kind arising out of the use of
the information in this document.
Copyright © 2004 FASL LLC. All rights reserved. Spansion, the Spansion logo, MirrorBit, combinations thereof, and ExpressFlash are trademarks of FASL
LLC. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
April 15, 2004 S71PL127/129JB0_00A0
Revision Summary
38
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