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S71PL127JC0-9Z [SPANSION]

Based MCPs; 基于MCP的
S71PL127JC0-9Z
型号： S71PL127JC0-9Z
厂家： SPANSION    SPANSION
描述：

Based MCPs
基于MCP的
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S71PL-J Based MCPs  
Stacked Multi-Chip Product (MCP) Flash Memory and  
RAM 256M/128/64/32 Megabit (16/8/4/2M x 16-bit) CMOS 3.0  
Volt-only Simultaneous Operation Page Mode Flash  
Memory and 64/32/16/8/4 Megabit (4M/2M/1M/512K/256K x  
16-bit) Static RAM/Pseudo Static RAM  
ADVANCE  
INFORMATION  
Data Sheet  
Notice to Readers: The Advance Information status indicates that this  
document contains information on one or more products under development  
at Spansion LLC. The information is intended to help you evaluate this product.  
Do not design in this product without contacting the factory. Spansion LLC  
reserves the right to change or discontinue work on this proposed product  
without notice.  
Publication Number S71PL-J_00 Revision B Amendment 3 Issue Date March 17, 2006  
A d v a n c e I n f o r m a t i o n  
Notice On Data Sheet Designations  
Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise  
readers of product information or intended specifications throughout the product life cycle, in-  
cluding development, qualification, initial production, and full production. In all cases, however,  
readers are encouraged to verify that they have the latest information before finalizing their de-  
sign. The following descriptions of Spansion data sheet designations are presented here to high-  
light their presence and definitions.  
Advance Information  
The Advance Information designation indicates that Spansion LLC is developing one or more spe-  
cific products, but has not committed any design to production. Information presented in a doc-  
ument with this designation is likely to change, and in some cases, development on the product  
may discontinue. Spansion LLC therefore places the following conditions upon Advance Informa-  
tion content:  
“This document contains information on one or more products under development at Spansion LLC. The  
information is intended to help you evaluate this product. Do not design in this product without con-  
tacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed  
product without notice.”  
Preliminary  
The Preliminary designation indicates that the product development has progressed such that a  
commitment to production has taken place. This designation covers several aspects of the prod-  
uct life cycle, including product qualification, initial production, and the subsequent phases in the  
manufacturing process that occur before full production is achieved. Changes to the technical  
specifications presented in a Preliminary document should be expected while keeping these as-  
pects of production under consideration. Spansion places the following conditions upon Prelimi-  
nary content:  
“This document states the current technical specifications regarding the Spansion product(s) described  
herein. The Preliminary status of this document indicates that product qualification has been completed,  
and that initial production has begun. Due to the phases of the manufacturing process that require  
maintaining efficiency and quality, this document may be revised by subsequent versions or modifica-  
tions due to changes in technical specifications.”  
Combination  
Some data sheets will contain a combination of products with different designations (Advance In-  
formation, Preliminary, or Full Production). This type of document will distinguish these products  
and their designations wherever necessary, typically on the first page, the ordering information  
page, and pages with DC Characteristics table and AC Erase and Program table (in the table  
notes). The disclaimer on the first page refers the reader to the notice on this page.  
Full Production (No Designation on Document)  
When a product has been in production for a period of time such that no changes or only nominal  
changes are expected, the Preliminary designation is removed from the data sheet. Nominal  
changes may include those affecting the number of ordering part numbers available, such as the  
addition or deletion of a speed option, temperature range, package type, or V range. Changes  
IO  
may also include those needed to clarify a description or to correct a typographical error or incor-  
rect specification. Spansion LLC applies the following conditions to documents in this category:  
“This document states the current technical specifications regarding the Spansion product(s) described  
herein. Spansion LLC deems the products to have been in sufficient production volume such that sub-  
sequent versions of this document are not expected to change. However, typographical or specification  
corrections, or modifications to the valid combinations offered may occur.”  
Questions regarding these document designations may be directed to your local AMD or Fujitsu  
sales office.  
ii  
S71PL-J Based MCPs  
S71PL-J_00_B3 March 17, 2006  
S71PL-J Based MCPs  
Stacked Multi-Chip Product (MCP) Flash Memory and  
RAM 256M/128/64/32 Megabit (16/8/4/2M x 16-bit) CMOS 3.0  
Volt-only Simultaneous Operation Page Mode Flash  
Memory and 64/32/16/8/4 Megabit (4M/2M/1M/512K/256K x  
16-bit) Static RAM/Pseudo Static RAM  
ADVANCE  
INFORMATION  
Data Sheet  
Distinctive Characteristics  
MCP Features  
„
„
Power supply voltage of 2.7 V to 3.1 V  
High performance  
„
„
Packages  
—
—
—
7 x 9 x 1.2mm 56 ball FBGA  
8 x 11.6 x 1.2mm 64 ball FBGA  
8 x 11.6 x 1.4mm 84 ball FBGA  
—
65 ns (65 ns Flash, 70 ns pSRAM)  
Operating Temperature  
—
—
–25°C to +85°C  
–40°C to +85°C  
General Description  
The S71PL series is a product line of stacked Multi-Chip Product (MCP) packages and consists  
of:  
„
„
One or more S29PL (Simultaneous Read/Write) Flash memory die  
pSRAM or SRAM (See “Referenced Data Sheets” on page 2)  
The 256Mb Flash memory consists of two S29PL127J devices. In this case, CE#f2 is used to  
access the second Flash and no extra address lines are required.  
The products covered by this document are listed in the table below:  
Flash Memory Density  
32Mb  
64Mb  
128Mb (Note 2)  
256Mb (Note 2)  
4 Mb  
8 Mb  
S71PL032J40  
S71PL032J80  
S71PL032JA0  
S71PL064J80  
S71PL064JA0  
S71PL064JB0  
pSRAM Density  
16 Mb  
32 Mb  
64 Mb  
S71PL127JB0  
S71PL127JC0  
S71PL254JC0  
Flash Memory Density  
32Mb  
64Mb  
4 Mb  
8 Mb  
S71PL032J04  
S71PL032J08  
SRAM Density (Note 1)  
S71PL064J08  
S71PL064J0A  
16 Mb  
Notes:  
1. Not recommended for new designs; use pSRAM based MCPs instead.  
2. Not recommended for new designs: use S71PL127N and S71PL256N instead.  
Publication Number S71PL-J_00 Revision B Amendment 3 Issue Date March 17, 2006  
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you eval-  
uate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work  
on this proposed product without notice.  
A d v a n c e I n f o r m a t i o n  
For detailed specifications, please refer to the individual data sheets listed in the following table.  
Referenced Data Sheets  
Document  
S29PL-J  
pSRAM Type 1  
Publication Identification Number (PID)  
S29PL-J_M0  
psram_12  
psram_15  
psram_25  
psram_06  
psram_18  
psram_21  
psram_14  
psram_13  
sram_02  
pSRAM Type 2  
8 Mb pSRAM Type 3  
16 Mb pSRAM Type 3  
pSRAM Type 4  
pSRAM Type 5  
pSRAM Type 6  
pSRAM Type 7  
4 Mb/8 Mb SRAM Type 1  
16 Mb SRAM Type 1  
SRAM Type 4  
sram_06  
sram_07  
2
S71PL-J Based MCPs  
S71PL-J_00_B3 March 17, 2006  
A d v a n c e I n f o r m a t i o n  
Product Selector Guide  
32Mb Flash Memory  
Device-Model#  
S71PL032J04-0B  
S71PL032J04-0K  
S71PL032J40-0K  
S71PL032J08-0B  
S71PL032J80-0F  
S71PL032J80-Q7  
S71PL032J80-QF  
S71PL032JA0-0K  
S71PL032JA0-QF  
S71PL032JA0-0Z  
Flash Access time (ns) (p)SRAM density (p)SRAM Access time (ns) pSRAM type Package  
65  
65  
65  
65  
65  
65  
65  
65  
65  
65  
4M SRAM  
4M SRAM  
70  
70  
70  
70  
70  
70  
70  
70  
70  
70  
SRAM1  
SRAM4  
TSC056  
TSC056  
TLC056  
TSC056  
TSC056  
TSC056  
TSC056  
TSC056  
TSC056  
TLC056  
4M pSRAM  
8M SRAM  
pSRAM4  
SRAM1  
8M pSRAM  
8M pSRAM  
8M pSRAM  
16Mb pSRAM  
16Mb pSRAM  
16M pSRAM  
pSRAM5  
pSRAM1  
pSRAM3  
pSRAM1  
pSRAM3  
pSRAM7  
64Mb Flash Memory  
Device-Model#  
S71PL064J08-0B  
S71PL064J80-0K  
S71PL064J0A-0S  
S71PL064JA0-0Z  
S71PL064JA0-0B  
S71PL064JA0-07  
S71PL064JA0-0P  
S71PL064JB0-QB  
S71PL064JB0-0U  
Flash Access time (ns) (p)SRAM density (p)SRAM Access time (ns)  
(p)SRAM type  
SRAM1  
Package  
TLC056  
TSC056  
TLC056  
TLC056  
TLC056  
TLC056  
TLC056  
TLC056  
TLC056  
65  
65  
65  
65  
65  
65  
65  
65  
65  
8M SRAM  
8M pSRAM  
16M SRAM  
16M pSRAM  
16M pSRAM  
16M pSRAM  
16M pSRAM  
32M pSRAM  
32M pSRAM  
70  
70  
70  
70  
70  
70  
70  
70  
70  
pSRAM1  
SRAM1  
pSRAM7  
pSRAM3  
pSRAM1  
pSRAM7  
pSRAM2  
pSRAM6  
March 17, 2006 S71PL-J_00_B3  
S71PL-J Based MCPs  
3
A d v a n c e I n f o r m a t i o n  
128Mb Flash Memory (Not recommended for new designs; use S71PL127N instead)  
Device-Model#  
S71PL127JB0-9Z  
S71PL127JB0-9U  
S71PL127JB0-9B  
S71PL127JC0-9B  
S71PL127JC0-9Z  
S71PL127JC0-9U  
Flash Access time (ns)  
pSRAM density  
32M pSRAM  
32M pSRAM  
32M pSRAM  
64M pSRAM  
64M pSRAM  
64M pSRAM  
pSRAM Access time (ns) pSRAM type Package  
65  
65  
65  
65  
65  
65  
70  
70  
70  
70  
70  
70  
pSRAM7  
pSRAM6  
pSRAM2  
pSRAM2  
pSRAM7  
pSRAM6  
TLA064  
TLA064  
TLA064  
TLA064  
TLA064  
TLA064  
256Mb Flash Memory (2xS29PL127J) (Not recommended for new designs: use  
S71PL256N instead)  
Device-Model#  
S71PL254JC0-TB  
S71PL254JC0-TZ  
Flash Access time (ns)  
pSRAM density  
64M pSRAM  
64M pSRAM  
pSRAM Access time (ns) pSRAM type Package  
65  
65  
70  
70  
pSRAM2  
pSRAM7  
FTA084  
FTA084  
4
S71PL-J Based MCPs  
S71PL-J_00_B3 March 17, 2006  
A d v a n c e I n f o r m a t i o n  
MCP Block Diagram  
VCC  
f
VCC  
CE#f1  
WP#/ACC  
RESET#  
Flash-only Address  
Flash 1  
Shared Address  
OE#  
WE#  
RY/BY#  
Flash 2  
(Note 2)  
CE#f2  
(Note 1)  
DQ15 to DQ0  
VCCS  
VCC  
pSRAM/SRAM  
IO15-IO0  
CE#s  
UB#s  
CE#  
UB#  
LB#  
LB#s  
CE2  
Notes:  
1. For 1 Flash + pSRAM, CE#f1=CE#. For 2 Flash + pSRAM, CE#=CE#f1 and CE#f2 is the chip-enable for the second  
Flash.  
2. For 256Mb only, Flash 1 = Flash 2 = S29PL127J.  
March 17, 2006 S71PL-J_00_B3  
S71PL-J Based MCPs  
5
A d v a n c e I n f o r m a t i o n  
Connection Diagram (S71PL032J)  
56-ball Fine-Pitch Ball Grid Array  
(Top View, Balls Facing Down)  
Legend  
A2  
A7  
A3  
LB#  
B3  
A4  
WP/ACC  
B4  
A5  
WE#  
B5  
A6  
A8  
A7  
A11  
B7  
B1  
A3  
B2  
B6  
B8  
A15  
C8  
Shared  
(Note 1)  
A6  
UB#  
C3  
RST#f  
C4  
CE2s  
C5  
A19  
C6  
A12  
C7  
C1  
C2  
A2  
A5  
A18  
D3  
RY/BY#  
A20  
A9  
A13  
D7  
RFU  
D8  
Flash only  
RAM only  
D1  
D2  
D6  
A1  
A4  
A17  
E3  
A10  
E6  
A14  
E7  
RFU  
E8  
E1  
E2  
A0  
VSS  
F2  
DQ1  
F3  
DQ6  
F6  
RFU  
F7  
A16  
F8  
F1  
F4  
DQ3  
G4  
F5  
DQ4  
G5  
Reserved for  
Future Use  
CE1#f  
G1  
OE#  
G2  
DQ0  
H2  
DQ9  
G3  
DQ13  
G6  
DQ15  
G7  
RFU  
G8  
CE1#s  
DQ10  
H3  
VCCf  
H4  
VCCs  
H5  
DQ12  
H6  
DQ7  
H7  
VSS  
DQ8  
DQ2  
DQ11  
RFU  
DQ5  
DQ14  
Notes:  
1. May be shared depending on density.  
— A19 is shared for the 16M pSRAM configuration.  
— A18 is shared for the 8M pSRAM and above configurations.  
2. Connecting all V and V balls to V and V is recommended.  
CC  
SS  
CC  
SS  
MCP  
Flash-only Addresses  
A20  
Shared Addresses  
S71PL032JA0  
S71PL032J80  
S71PL032J08  
S71PL032J40  
S71PL032J04  
A19-A0  
A18-A0  
A18-A0  
A17-A0  
A17-A0  
A20-A19  
A20-A19  
A20-A18  
A20-A18  
6
S71PL-J Based MCPs  
S71PL-J_00_B3 March 17, 2006  
A d v a n c e I n f o r m a t i o n  
Connection Diagram (S71PL064J)  
56-ball Fine-Pitch Ball Grid Array  
(Top View, Balls Facing Down)  
Legend  
A2  
A7  
A3  
LB#  
B3  
A4  
WP/ACC  
B4  
A5  
WE#  
B5  
A6  
A8  
A7  
A11  
B7  
B1  
A3  
B2  
B6  
B8  
A15  
C8  
Shared  
(Note 1)  
A6  
UB#  
C3  
RST#f  
C4  
CE2s  
C5  
A19  
C6  
A12  
C7  
C1  
C2  
A2  
A5  
A18  
D3  
RY/BY#  
A20  
A9  
A13  
D7  
A21  
D8  
Flash only  
RAM only  
D1  
D2  
D6  
A1  
A4  
A17  
E3  
A10  
E6  
A14  
E7  
RFU  
E8  
E1  
E2  
A0  
VSS  
F2  
DQ1  
F3  
DQ6  
F6  
RFU  
F7  
A16  
F8  
F1  
F4  
DQ3  
G4  
F5  
DQ4  
G5  
Reserved for  
Future Use  
CE1#f  
G1  
OE#  
G2  
DQ0  
H2  
DQ9  
G3  
DQ13  
G6  
DQ15  
G7  
RFU  
G8  
CE1#s  
DQ10  
H3  
VCCf  
H4  
VCCs  
H5  
DQ12  
H6  
DQ7  
H7  
VSS  
DQ8  
DQ2  
DQ11  
RFU  
DQ5  
DQ14  
Notes:  
1. May be shared depending on density.  
— A20 is shared for the 32M pSRAM configuration.  
— A19 is shared for the 16M pSRAM and above configurations.  
— A18 is shared for the 8M pSRAM and above configurations.  
2. Connecting all V and V balls to V and V is recommended.  
CC  
SS  
CC  
SS  
MCP  
Flash-only Addresses  
A21  
Shared Addresses  
A20-A0  
S71PL064JB0  
S71PL064JA0  
S71PL064J0A  
S71PL064J80  
S71PL064J08  
A21-A20  
A19-A0  
A21-A20  
A19-A0  
A21-A19  
A18-A0  
A21-A19  
A18-A0  
March 17, 2006 S71PL-J_00_B3  
S71PL-J Based MCPs  
7
A d v a n c e I n f o r m a t i o n  
Connection Diagram (S71PL127J)  
64-ball Fine-Pitch Ball Grid Array  
(Top View, Balls Facing Down)  
A1  
A10  
NC  
NC  
B5  
RFU  
B6  
RFU  
C6  
Legend  
C3  
A7  
C
4
C5  
C7  
A8  
C8  
A11  
D8  
LB#  
WP/ACC  
D5  
WE#  
D2  
A3  
D9  
D3  
D
4
D
6
D
7
Shared  
(Note 1)  
A6  
UB#  
E4  
RST#f  
E5  
CE2s  
A19  
E7  
A12  
E8  
A15  
E2  
A2  
E3  
E
6
E9  
A5  
A18  
F4  
RY/BY#  
A20  
A9  
A13  
F8  
A21  
F9  
Flash only  
RAM only  
F2  
F3  
F7  
A1  
A4  
A17  
G4  
A10  
G7  
A14  
G8  
A22  
G9  
G2  
G3  
VSS  
H3  
A0  
DQ1  
H4  
DQ6  
H7  
RFU  
H8  
A16  
H9  
H2  
H5  
DQ3  
J5  
H6  
DQ4  
J6  
Reserved for  
Future Use  
CE#f  
J2  
OE#  
J3  
DQ9  
J4  
DQ13  
J7  
DQ15  
J8  
RFU  
J9  
CE1#s  
DQ0  
K3  
DQ10  
K4  
VCCf  
K5  
VCCs  
K6  
DQ12  
K7  
DQ7  
K8  
VSS  
DQ8  
DQ2  
DQ11  
RFU  
DQ5  
DQ14  
L5  
L6  
RFU*  
RFU  
M1  
NC  
M10  
NC  
*See notes below  
Notes:  
1. May be shared depending on density.  
— A21 is shared for the 64M pSRAM configuration.  
— A20 is shared for the 32M pSRAM and above configurations.  
2. A19 is shared for the 16M pSRAM and above configurations.  
MCP  
S71PL127JC0  
S71PL127JB0  
Flash-only Addresses  
Shared Addresses  
A21-A0  
A22  
A22-A21  
A20-A0  
3. Connecting all V and V balls to Vcc & Vss is recommended.  
CC  
SS  
4. Ball L5 will be V F in the 84-ball density upgrades. Do not connect to V or any other signal.  
CC  
SS  
8
S71PL-J Based MCPs  
S71PL-J_00_B3 March 17, 2006  
A d v a n c e I n f o r m a t i o n  
Connection Diagram (S71PL254J)  
84-ball Fine-Pitch Ball Grid Array  
(Top View, Balls Facing Down)  
A1  
A10  
NC  
NC  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
B9  
RFU  
RFU  
RFU  
CE#F2  
RFU  
RFU  
RFU  
RFU  
Legend  
C2  
C3  
A7  
C4  
LB#  
D4  
C5  
WP/ACC  
D5  
C6  
WE#  
D6  
C7  
A8  
C8  
A11  
D8  
C9  
RFU  
D9  
RFU  
D2  
D3  
D7  
Shared  
(Note 1)  
A3  
A6  
UB#  
E4  
RST#f  
E5  
CE2s  
A19  
E7  
A12  
E8  
A15  
E2  
A2  
E3  
E
6
E9  
A5  
A18  
F4  
RY/BY#  
H5  
A20  
H6  
A9  
A13  
F8  
A21  
F9  
Flash only  
RAM only  
F2  
F3  
F7  
RFU  
RFU  
A1  
A4  
A17  
G4  
A10  
G7  
A14  
G8  
A22  
G9  
G2  
G3  
VSS  
H3  
H5  
RFU  
H5  
H6  
RFU  
H6  
A0  
DQ1  
H4  
DQ6  
H7  
RFU  
H8  
A16  
H9  
H2  
Reserved for  
Future Use  
CE#f1  
J2  
OE#  
J3  
DQ9  
J4  
DQ3  
J5  
DQ4  
J6  
DQ13  
J7  
DQ15  
J8  
RFU  
J9  
CE1#s  
K2  
DQ0  
K3  
DQ10  
K4  
VCCf  
K5  
VCCs  
K6  
DQ12  
K7  
DQ7  
K8  
VSS  
K9  
2nd Flash Only  
RFU  
DQ8  
DQ2  
DQ11  
RFU  
DQ5  
DQ14  
RFU  
L2  
L3  
L4  
L5  
L6  
L7  
L8  
L9  
RFU  
RFU  
RFU  
VCCf  
RFU  
RFU  
RFU  
RFU  
M1  
NC  
M10  
NC  
Notes:  
1. May be shared depending on density.  
— A21 is shared for the 64M pSRAM configuration.  
— A20 is shared for the 32M pSRAM configuration.  
MCP  
S71PL254JC0  
Flash-only Addresses  
Shared Addresses  
A22  
A21-A0  
2. Connecting all Vcc & Vss balls to Vcc & Vss is recommended.  
Special Handling Instructions For FBGA Package  
Special handling is required for Flash Memory products in FBGA packages.  
Flash memory devices in FBGA packages may be damaged if exposed to ultra-  
sonic cleaning methods. The package and/or data integrity may be compromised  
if the package body is exposed to temperatures above 150°C for prolonged peri-  
ods of time.  
March 17, 2006 S71PL-J_00_B3  
S71PL-J Based MCPs  
9
A d v a n c e I n f o r m a t i o n  
Pin Description  
A21–A0  
DQ15–DQ0  
CE1#f  
CE#f2  
CE1#ps  
CE2ps  
OE#  
WE#  
RY/BY#  
UB#  
LB#  
=
=
=
=
=
=
=
=
=
=
=
=
=
=
22 Address Inputs (Common)  
16 Data Inputs/Outputs (Common)  
Chip Enable 1 (Flash)  
Chip Enable 2 (Flash)  
Chip Enable 1 (pSRAM)  
Chip Enable 2 (pSRAM)  
Output Enable (Common)  
Write Enable (Common)  
Ready/Busy Output (Flash 1)  
Upper Byte Control (pSRAM)  
Lower Byte Control (pSRAM)  
Hardware Reset Pin, Active Low (Flash 1)  
Hardware Write Protect/Acceleration Pin (Flash)  
Flash 3.0 volt-only single power supply (see Product  
Selector Guide for speed options and voltage supply  
tolerances)  
RESET#  
WP#/ACC  
VCC  
f
VCCps  
VSS  
NC  
=
=
=
pSRAM Power Supply  
Device Ground (Common)  
Pin Not Connected Internally  
Logic Symbol  
22  
A21–A0  
16  
CE1#f  
DQ15–DQ0  
R Y/BY#  
CE2#f  
CE1#ps  
CE2ps  
OE#  
WE#  
WP#/ACC  
RESET#  
UB#  
LB#  
10  
S71PL-J Based MCPs  
S71PL-J_00_B3 March 17, 2006  
A d v a n c e I n f o r m a t i o n  
Ordering Information  
The order number is formed by a valid combinations of the following:  
S71PL  
127  
J
B0 BA  
W
9
Z
0
PACKING TYPE  
0
2
3
=
=
=
Tray  
7” Tape and Reel  
13” Tape and Reel  
MODEL NUMBER  
See the Valid Combinations table.  
PACKAGE MODIFIER  
0
9
T
=
=
=
7 x 9mm, 1.2mm height, 56 balls (TLC056 or TSC065)  
8 x 11.6mm, 1.2mm height, 64 balls (TLA064 or TSB064)  
8 x 11.6mm, 1.4mm height, 84 balls (FTA084)  
TEMPERATURE RANGE  
Wireless (-25 C to +85°C)  
W
=
°
PACKAGE TYPE  
BA  
BF  
=
=
Fine-pitch BGA Lead (Pb)-free compliant package  
Fine-pitch BGA Lead (Pb)-free package  
pSRAM DENSITY  
C0  
B0  
A0  
80  
40  
0A  
08  
04  
=
=
=
=
=
=
=
=
64Mb pSRAM  
32Mb pSRAM  
16Mb pSRAM  
8Mb pSRAM  
4Mb pSRAM  
16Mb pSRAM  
8Mb SRAM  
4Mb SRAM  
PROCESS TECHNOLOGY  
110 nm, Floating Gate Technology  
J
=
FLASH DENSITY  
254  
127  
064  
032  
=
=
=
=
256Mb  
128Mb  
64Mb  
32Mb  
PRODUCT FAMILY  
S71PL Multi-chip Product (MCP)  
3.0-volt Simultaneous Read/Write, Page Mode Flash Memory and RAM  
March 17, 2006 S71PL-J_00_B3  
S71PL-J Based MCPs  
11  
A d v a n c e I n f o r m a t i o n  
S71PL032J Valid Combinations  
(p)SRAM  
Type/Access  
Time (ns)  
Base Ordering  
Part Number  
Package &  
Package Modifier/  
Model Number  
Speed Options  
(ns)  
Package  
Marking  
Temperature  
Packing Type  
S71PL032J04  
S71PL032J04  
S71PL032J40  
S71PL032J80  
S71PL032J08  
S71PL032J80  
S71PL032J80  
S71PL032JA0  
S71PL032JA0  
S71PL032JA0  
S71PL032J04  
S71PL032J04  
S71PL032J40  
S71PL032J80  
S71PL032J08  
S71PL032J80  
S71PL032J80  
S71PL032JA0  
S71PL032JA0  
S71PL032JA0  
0B  
0K  
0K  
0F  
0B  
Q7  
QF  
07  
QF  
0Z  
0B  
0K  
0K  
0F  
0B  
Q7  
QF  
07  
QF  
0Z  
SRAM2 / 70  
SRAM4 / 70  
pSRAM4 / 70  
pSRAM5 / 70  
SRAM2 / 70  
pSRAM1 / 70  
pSRAM3 / 70  
pSRAM1 / 70  
pSRAM3 / 70  
pSRAM2 / 70  
SRAM2 / 70  
SRAM4 / 70  
pSRAM4 / 70  
pSRAM5 / 70  
SRAM2 / 70  
pSRAM1 / 70  
pSRAM3 / 70  
pSRAM1 / 70  
pSRAM3 / 70  
pSRAM2 / 70  
BAW  
0, 2, 3 (Note 1)  
65  
(Note 2)  
BFW  
0, 2, 3 (Note 1)  
65  
(Note 2)  
S71PL064J Valid Combinations  
(p)SRAM Type/  
Access Time  
(ns)  
Base Ordering  
Part Number  
Package &  
Package Modifier/  
Model Number  
Speed Options  
(ns)  
Package  
Marking  
Temperature  
Packing Type  
S71PL064J08  
S71PL064J80  
S71PL064J0A  
S71PL064JA0  
S71PL064JA0  
S71PL064JA0  
S71PL064JB0  
S71PL064JB0  
S71PL064J08  
S71PL064J80  
S71Pl064J0A  
S71PL064JA0  
S71PL064JA0  
S71PL064JA0  
S71PL064JB0  
S71PL064JB0  
0B  
0K  
0S  
0B  
07  
0P  
QB  
0U  
0B  
0K  
0S  
0B  
07  
0P  
QB  
0U  
SRAM1 / 70  
pSRAM1 /70  
SRAM1 / 70  
pSRAM3 / 70  
pSRAM1 / 70  
pSRAM7 / 70  
pSRAM2 / 70  
pSRAM6 / 70  
SRAM1 / 70  
pSRAM1 /70  
SRAM1 / 70  
pSRAM3 / 70  
pSRAM1 / 70  
pSRAM7 / 70  
pSRAM2 / 70  
pSRAM6 / 70  
BAW  
0, 2, 3 (Note 1)  
65  
(Note 2)  
BFW  
0, 2, 3 (Note 1)  
65  
(Note 2)  
Notes:  
Valid Combinations  
1. Type 0 is standard. Specify other options as required.  
2. BGA package marking omits leading “S” and packing type  
designator from ordering part number.  
Valid Combinations list configurations planned to be supported in vol-  
ume for this device. Consult your local sales office to confirm avail-  
ability of specific valid combinations and to check on newly released  
combinations.  
12  
S71PL-J Based MCPs  
S71PL-J_00_B3 March 17, 2006  
A d v a n c e I n f o r m a t i o n  
S71PL127J Valid Combinations  
Package  
Modifier/Model  
Number  
(p)SRAM Type/  
Access Time  
(ns)  
Base Ordering  
Part Number  
Package &  
Temperature  
Speed Options  
(ns)  
Packing Type  
Package Marking  
S71PL127JB0  
S71PL127JB0  
S71PL127JC0  
S71PL127JC0  
S71PL127JC0  
S71PL127JB0  
S71PL127JB0  
S71PL127JB0  
S71PL127JC0  
S71PL127JC0  
S71PL127JC0  
S71PL127JB0  
9Z  
9U  
9B  
9Z  
9U  
9B  
9Z  
9U  
9B  
9Z  
9U  
9B  
pSRAM7 / 70  
pSRAM6 /70  
pSRAM2 /70  
pSRAM7 / 70  
pSRAM6 / 70  
pSRAM2 / 70  
pSRAM7 / 70  
pSRAM6 / 70  
pSRAM2 /70  
pSRAM7 / 70  
pSRAM6 / 70  
pSRAM2 / 70  
BAW  
BFW  
0, 2, 3 (Note 1)  
65  
65  
(Note 2)  
0, 2, 3 (Note 1)  
(Note 2)  
Notes:  
Valid Combinations  
1. Type 0 is standard. Specify other options as required.  
2. BGA package marking omits leading “S” and packing type  
designator from ordering part number.  
Valid Combinations list configurations planned to be supported in vol-  
ume for this device. Consult your local sales office to confirm avail-  
ability of specific valid combinations and to check on newly released  
combinations.  
S71PL254J Valid Combinations  
(p)SRAM  
Base Ordering  
Part Number  
Package &  
Temperature  
Speed Options  
(ns)  
Type/Access  
Time (ns)  
Package  
Marking  
Model Number  
Packing Type  
S71PL254JC0  
S71PL254JC0  
S71PL254JC0  
S71PL254JC0  
TB  
TZ  
TB  
TZ  
pSRAM2 / 70  
pSRAM7 / 70  
pSRAM2 / 70  
pSRAM7 / 70  
BAW  
BFW  
0, 2, 3 (Note1)  
65  
65  
(Note 2)  
(Note 2)  
0, 2, 3 (Note1)  
Notes:  
Valid Combinations  
1. Type 0 is standard. Specify other options as required.  
2. BGA package marking omits leading “S” and packing type  
designator from ordering part number.  
Valid Combinations list configurations planned to be supported in vol-  
ume for this device. Consult your local sales office to confirm avail-  
ability of specific valid combinations and to check on newly released  
combinations.  
March 17, 2006 S71PL-J_00_B3  
S71PL-J Based MCPs  
13  
A d v a n c e I n f o r m a t i o n  
Physical Dimensions  
TLC056—56-ball Fine-Pitch Ball Grid Array (FBGA) 9 x 7mm Package  
A
D1  
D
eD  
0.15  
(2X)  
C
8
7
6
5
4
3
2
1
SE  
7
E
B
E1  
eE  
H
G
F
E
D
C
B
A
INDEX MARK  
10  
PIN A1  
CORNER  
PIN A1  
CORNER  
7
SD  
0.15  
(2X)  
C
TOP VIEW  
BOTTOM VIEW  
0.20  
0.08  
C
C
A2  
A
C
A1  
SIDE VIEW  
6
56X  
b
0.15  
M
C
C
A
B
0.08  
M
NOTES:  
PACKAGE  
JEDEC  
TLC 056  
N/A  
1. DIMENSIONING AND TOLERANCING METHODS PER  
ASME Y14.5M-1994.  
2. ALL DIMENSIONS ARE IN MILLIMETERS.  
D x E  
9.00 mm x 7.00 mm  
PACKAGE  
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.  
SYMBOL  
MIN  
---  
NOM  
---  
MAX  
NOTE  
4.  
e REPRESENTS THE SOLDER BALL GRID PITCH.  
A
A1  
1.20  
---  
PROFILE  
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"  
DIRECTION.  
0.20  
0.81  
---  
BALL HEIGHT  
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE  
"E" DIRECTION.  
A2  
---  
0.97  
BODY THICKNESS  
BODY SIZE  
D
9.00 BSC.  
7.00 BSC.  
5.60 BSC.  
5.60 BSC.  
8
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS  
FOR MATRIX SIZE MD X ME.  
E
BODY SIZE  
D1  
E1  
MATRIX FOOTPRINT  
MATRIX FOOTPRINT  
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL  
DIAMETER IN A PLANE PARALLEL TO DATUM C.  
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A  
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER  
BALL IN THE OUTER ROW.  
MD  
ME  
n
MATRIX SIZE D DIRECTION  
MATRIX SIZE E DIRECTION  
BALL COUNT  
8
56  
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE  
OUTER ROW SD OR SE = 0.000.  
φb  
0.35  
0.40  
0.45  
BALL DIAMETER  
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE  
OUTER ROW, SD OR SE = e/2  
eE  
0.80 BSC.  
0.80 BSC  
0.40 BSC.  
BALL PITCH  
eD  
SD / SE  
BALL PITCH  
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED  
BALLS.  
SOLDER BALL PLACEMENT  
A1,A8,D4,D5,E4,E5,H1,H8  
DEPOPULATED SOLDER BALLS  
9. N/A  
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK  
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.  
3348 \ 16-038.22a  
14  
S71PL-J Based MCPs  
S71PL-J_00_B3 March 17, 2006  
A d v a n c e I n f o r m a t i o n  
TSC056—56-ball Fine-Pitch Ball Grid Array (FBGA) 9 x 7mm Package  
D1  
A
D
eD  
0.15  
(2X)  
C
8
7
6
5
4
3
2
1
SE  
7
E
B
E1  
eE  
H
G
F
E
D
C
B
A
INDEX MARK  
10  
PIN A1  
CORNER  
PIN A1  
CORNER  
7
SD  
0.15  
(2X)  
C
TOP VIEW  
BOTTOM VIEW  
0.20  
0.08  
C
C
A2  
A
C
A1  
SIDE VIEW  
6
56X  
b
0.15  
0.08  
M
C
C
A
B
M
NOTES:  
PACKAGE  
JEDEC  
TSC 056  
N/A  
1. DIMENSIONING AND TOLERANCING METHODS PER  
ASME Y14.5M-1994.  
2. ALL DIMENSIONS ARE IN MILLIMETERS.  
D x E  
9.00 mm x 7.00 mm  
PACKAGE  
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.  
SYMBOL  
MIN  
---  
NOM  
---  
MAX  
1.20  
---  
NOTE  
4.  
e REPRESENTS THE SOLDER BALL GRID PITCH.  
A
A1  
PROFILE  
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"  
DIRECTION.  
0.17  
0.81  
---  
BALL HEIGHT  
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE  
"E" DIRECTION.  
A2  
---  
0.97  
BODY THICKNESS  
BODY SIZE  
D
9.00 BSC.  
7.00 BSC.  
5.60 BSC.  
5.60 BSC.  
8
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS  
FOR MATRIX SIZE MD X ME.  
E
BODY SIZE  
D1  
E1  
MATRIX FOOTPRINT  
MATRIX FOOTPRINT  
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL  
DIAMETER IN A PLANE PARALLEL TO DATUM C.  
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A  
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER  
BALL IN THE OUTER ROW.  
MD  
ME  
n
MATRIX SIZE D DIRECTION  
MATRIX SIZE E DIRECTION  
BALL COUNT  
8
56  
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE  
OUTER ROW SD OR SE = 0.000.  
φb  
0.35  
0.40  
0.45  
BALL DIAMETER  
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE  
OUTER ROW, SD OR SE = e/2  
eE  
0.80 BSC.  
0.80 BSC  
0.40 BSC.  
BALL PITCH  
eD  
SD / SE  
BALL PITCH  
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED  
BALLS.  
SOLDER BALL PLACEMENT  
A1,A8,D4,D5,E4,E5,H1,H8  
DEPOPULATED SOLDER BALLS  
9. N/A  
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK  
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.  
3427 \ 16-038.22  
March 17, 2006 S71PL-J_00_B3  
S71PL-J Based MCPs  
15  
A d v a n c e I n f o r m a t i o n  
TLA064—64-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6mm Package  
A
D1  
D
eD  
0.15  
(2X)  
C
10  
9
8
7
6
5
4
3
2
1
SE  
7
E
B
E1  
eE  
L
J
H
G
F
E
D
C
B
A
M
K
INDEX MARK  
10  
PIN A1  
CORNER  
PIN A1  
CORNER  
7
SD  
0.15  
(2X)  
C
TOP VIEW  
SIDE VIEW  
BOTTOM VIEW  
0.20  
0.08  
C
C
A2  
A
C
A1  
6
64X  
b
0.15  
0.08  
M
C
C
A B  
M
NOTES:  
PACKAGE  
JEDEC  
TLA 064  
N/A  
1. DIMENSIONING AND TOLERANCING METHODS PER  
ASME Y14.5M-1994.  
2. ALL DIMENSIONS ARE IN MILLIMETERS.  
D x E  
11.60 mm x 8.00 mm  
PACKAGE  
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.  
SYMBOL  
MIN  
---  
NOM  
---  
MAX  
1.20  
NOTE  
4.  
e REPRESENTS THE SOLDER BALL GRID PITCH.  
A
A1  
PROFILE  
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"  
DIRECTION.  
0.17  
0.81  
---  
---  
BALL HEIGHT  
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE  
"E" DIRECTION.  
A2  
---  
0.97  
BODY THICKNESS  
BODY SIZE  
D
11.60 BSC.  
8.00 BSC.  
8.80 BSC.  
7.20 BSC.  
12  
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS  
FOR MATRIX SIZE MD X ME.  
E
BODY SIZE  
D1  
E1  
MATRIX FOOTPRINT  
MATRIX FOOTPRINT  
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL  
DIAMETER IN A PLANE PARALLEL TO DATUM C.  
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A  
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER  
BALL IN THE OUTER ROW.  
MD  
ME  
n
MATRIX SIZE D DIRECTION  
MATRIX SIZE E DIRECTION  
BALL COUNT  
10  
64  
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE  
OUTER ROW SD OR SE = 0.000.  
φb  
0.35  
0.40  
0.45  
BALL DIAMETER  
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE  
OUTER ROW, SD OR SE = e/2  
eE  
0.80 BSC.  
0.80 BSC  
0.40 BSC.  
BALL PITCH  
eD  
SD / SE  
BALL PITCH  
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED  
BALLS.  
SOLDER BALL PLACEMENT  
DEPOPULATED SOLDER BALLS  
A2,A3,A4,A5,A6,A7,A8,A9  
B1,B2,B3,B4,B7,B8,B9,B10  
C1,C2,C9,C10,D1,D10,E1,E10,  
F1,F5,F6,F10,G1,G5,G6,G10  
H1,H10,J1,J10,K1,K2,K9,K10  
L1,L2,L3,L4,L7,L8,L9,L10  
9. N/A  
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK  
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.  
M2,M3,M4,M5,M6,M7,M8,M9  
3352 \ 16-038.22a  
16  
S71PL-J Based MCPs  
S71PL-J_00_B3 March 17, 2006  
A d v a n c e I n f o r m a t i o n  
TSB064—64-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm Package  
A
D1  
D
eD  
0.15  
(2X)  
C
10  
9
8
7
6
5
4
3
2
1
SE  
7
E
B
E1  
eE  
L
J
H
G
F
E
D
C
B
A
M
K
INDEX MARK  
10  
PIN A1  
CORNER  
PIN A1  
CORNER  
7
SD  
0.15  
(2X)  
C
TOP VIEW  
SIDE VIEW  
BOTTOM VIEW  
0.20  
0.08  
C
C
A2  
A
C
A1  
6
64X  
b
0.15  
0.08  
M
C
C
A B  
M
NOTES:  
PACKAGE  
JEDEC  
TSB 064  
N/A  
1. DIMENSIONING AND TOLERANCING METHODS PER  
ASME Y14.5M-1994.  
D x E  
11.60 mm x 8.00 mm  
PACKAGE  
2. ALL DIMENSIONS ARE IN MILLIMETERS.  
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.  
SYMBOL  
MIN  
---  
NOM  
---  
MAX  
1.20  
NOTE  
4.  
e REPRESENTS THE SOLDER BALL GRID PITCH.  
A
A1  
PROFILE  
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"  
DIRECTION.  
017  
---  
---  
BALL HEIGHT  
A2  
0.81  
---  
0.97  
BODY THICKNESS  
BODY SIZE  
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE  
"E" DIRECTION.  
D
11.60 BSC.  
8.00 BSC.  
8.80 BSC.  
7.20 BSC.  
12  
E
BODY SIZE  
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS  
FOR MATRIX SIZE MD X ME.  
D1  
E1  
MATRIX FOOTPRINT  
MATRIX FOOTPRINT  
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL  
DIAMETER IN A PLANE PARALLEL TO DATUM C.  
MD  
ME  
n
MATRIX SIZE D DIRECTION  
MATRIX SIZE E DIRECTION  
BALL COUNT  
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A  
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER  
BALL IN THE OUTER ROW.  
10  
64  
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE  
OUTER ROW SD OR SE = 0.000.  
φb  
0.35  
0.40  
0.45  
BALL DIAMETER  
eE  
0.80 BSC.  
0.80 BSC  
0.40 BSC.  
BALL PITCH  
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE  
OUTER ROW, SD OR SE = e/2  
eD  
SD / SE  
BALL PITCH  
SOLDER BALL PLACEMENT  
DEPOPULATED SOLDER BALLS  
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED  
BALLS.  
A2,A3,A4,A5,A6,A7,A8,A9  
B1,B2,B3,B4,B7,B8,B9,B10  
C1,C2,C9,C10,D1,D10,E1,E10  
F1,F5,F6,F10,G1,G5,G6,G10  
H1,H10,J1,J10,K1,K2,K9,K10  
L1,L2,L3,L4,L7,L8,L9,L10  
9. N/A  
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK  
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.  
M2,M3,M4,M5,M6,M7,M8,M9  
3351 \ 16-038.22a  
March 17, 2006 S71PL-J_00_B3  
S71PL-J Based MCPs  
17  
A d v a n c e I n f o r m a t i o n  
FTA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6mm Package  
A
D1  
D
eD  
0.15  
(2X)  
C
10  
9
8
SE  
7
7
6
E
B
E1  
5
4
3
2
1
eE  
J
H
G
F
E
D
C
B
A
M
L K  
INDEX MARK  
10  
PIN A1  
CORNER  
PIN A1  
CORNER  
7
SD  
0.15  
(2X)  
C
TOP VIEW  
BOTTOM VIEW  
0.20  
0.08  
C
C
A2  
A
C
A1  
SIDE VIEW  
6
84X  
b
0.15  
M
C
C
A
B
0.08  
M
NOTES:  
PACKAGE  
JEDEC  
FTA 084  
N/A  
1. DIMENSIONING AND TOLERANCING METHODS PER  
ASME Y14.5M-1994.  
2. ALL DIMENSIONS ARE IN MILLIMETERS.  
D x E  
11.60 mm x 8.00 mm  
PACKAGE  
NOTE  
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.  
SYMBOL  
MIN  
---  
NOM  
---  
MAX  
4.  
e REPRESENTS THE SOLDER BALL GRID PITCH.  
A
A1  
1.40  
---  
PROFILE  
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"  
DIRECTION.  
0.17  
1.02  
---  
BALL HEIGHT  
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE  
"E" DIRECTION.  
A2  
---  
1.17  
BODY THICKNESS  
BODY SIZE  
D
11.60 BSC.  
8.00 BSC.  
8.80 BSC.  
7.20 BSC.  
12  
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS  
FOR MATRIX SIZE MD X ME.  
E
BODY SIZE  
D1  
E1  
MATRIX FOOTPRINT  
MATRIX FOOTPRINT  
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL  
DIAMETER IN A PLANE PARALLEL TO DATUM C.  
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A  
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER  
BALL IN THE OUTER ROW.  
MD  
ME  
n
MATRIX SIZE D DIRECTION  
MATRIX SIZE E DIRECTION  
BALL COUNT  
10  
84  
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE  
OUTER ROW SD OR SE = 0.000.  
φb  
0.35  
0.40  
0.45  
BALL DIAMETER  
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE  
OUTER ROW, SD OR SE = e/2  
eE  
0.80 BSC.  
0.80 BSC  
0.40 BSC.  
BALL PITCH  
eD  
SD / SE  
BALL PITCH  
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED  
BALLS.  
SOLDER BALL PLACEMENT  
A2,A3,A4,A5,A6,A7,A8,A9  
B1,B10,C1,C10,D1,D10,E1,E10  
F1,F10,G1,G10,H1,H10  
DEPOPULATED SOLDER BALLS  
9. N/A  
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK  
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.  
J1,J10,K1,K10,L1,L10  
M2,M3,M4,M5,M6,M7,M8,M9  
3388 \ 16-038.21a  
18  
S71PL-J Based MCPs  
S71PL-J_00_B3 March 17, 2006  
A d v a n c e I n f o r m a t i o n  
MCP Revision Summary  
Revision A (May 3, 2004)  
Initial release.  
Revision A1 (May 6, 2004)  
MCP Features  
Corrected the high performance access times.  
Connection Diagrams  
Added reference points on all diagrams.  
Ordering Information  
Corrected package types.  
Corrected the description of product family to Page Mode Flash memory.  
pSRAM Type 1  
Corrected the description of the 8Mb device to 512Kb Word x 16-bit.  
pSRAM Type 6  
Corrected the description of the 2Mb device to 128Kb Word x 16-bit.  
Corrected the description of the 4Mb device to 256Kb Word x 16-bit.  
Revision A2 (May 11, 2004)  
General Description  
Corrected the tables to reflect accurate device configurations.  
Revision A3 (June 16, 2004)  
Ordering Information  
Corrected the Valid Combinations tables to reflect accurate device configurations.  
SRAM  
New section added.  
Revision A4 (July 16, 2004)  
Global Changes  
Global Change of FASL to Spansion.  
Global change to remove space between M and Mb callouts.  
“32Mb Flash Memory” on page 3  
Replaced “S71PL032J08-07” with “S71PL032J08-0B”.  
Replaced “S71PL032JA0” with “S71PL032JA0-07”.  
Added row with the following content: S71PL032JA0-08; 65; 16Mb pSRAM; 70;  
pSRAM3; TLC056.  
“64Mb Flash Memory” on page 3  
Replaced “S71PL064J08-0K” with “S71PL064J08-0B”.  
Replaced “S71PL064J08-0P” with “S71PL064J08-0U”.  
Deleted “S71PL064J80-05” row.  
Replaced “S71PL064JA0-07” with “S71PL064JA0-0K”.  
March 17, 2006 S71PL-J_00_B3  
S71PL-J Based MCPs  
19  
A d v a n c e I n f o r m a t i o n  
Replaced “S71PL064JA0-0Z” with  
Added row with the following content:S71PL064JB0-07; 65; 32M pSRAM; 70; Psram  
1; TLC056.  
“32Mb Flash Memory” on page 3  
Replaced “S71PL032JA0-08” with “S71PL032JA0-0F”.  
“64Mb Flash Memory” on page 3  
Replaced “S71PL032JA0-07” with “S71PL032JA0-0K”.  
“128Mb Flash Memory” on page 4  
Added row with the following content: S71PL127JB0-9; 65; 32M pSRAM; 70;  
pSRAM; TLA064.  
Replaced “S71PL127JB0-97” with “S71PL127JB0-9Z”.  
Added row with the following content: S71PL127JC0-97; 65; 64M pSRAM; 70;  
pSRAM1; TLA064.  
Replaced “S71PL127JC0-9P” with “S71PL127JC0-9Z”.  
In the S71Pl254JB0-TB row changed pSRAM type from “pSRAM3” to “pSRAM2”.  
“256Mb Flash Memory (2xS29PL127J)” on page 4  
Added row with the following content: S71PL254JB0-TB; 65; 32M pSRAM; 70;  
pSRAM3; FTA084.  
Added row with the following content: S71PL254JC0-TB; 65; 64M pSRAM; 70;  
pSRAM2; FTA084.  
“Connection Diagram (S71PL127J)” on page 12  
Updated pins D8, D9, and L5.  
Added notes 2 and 3 to drawing.  
“Connection Diagram (S71PL254J)” on page 13  
Updated pins D8 and D9.  
Added Note 2 to drawing.  
“S71PL032J Valid Combinations” on page 16  
Changed S71PL032J08 (p)SRAM Type Access Time (ns) from “SRAM1” to  
“SRAM2” (4 changes made in table).  
Changed S71PL032JA0 (p)SRAM Type Access Time (ns) from “SRAM3 / 70” to  
pSRAM3 /70”.  
Deleted all cells with the following collaborated text: “BAW,BFW, BAI. BFI”.  
Merged previous place holder with cell above.  
“S71PL064J Valid Combinations” on page 17  
In (p)SRAM Type/Access Time (ns) changed all instances of “stet” to “pSRAM1/  
70”.  
In Package Modifier/Model Number changed all instances of “stet” to “07”.  
Added row to BAW Package and Temperature sections with the following content:  
S71PL064JB0; 07; 65 (previously inclusive); pSRAM1/70.  
“S71PL127J Valid Combinations” on page 18  
Changed the S71PL127JA0 Package Modifier/Model Number from “9Z” to “9P” (4  
instances).  
20  
S71PL-J Based MCPs  
S71PL-J_00_B3 March 17, 2006  
A d v a n c e I n f o r m a t i o n  
Added 4 rows with the following content: S71PL127JC0; 97; pSRAM1/70.  
“S71PL254J Valid Combinations” on page 20  
Added 4 rows with the following content: S71PL254JC0; TB; pSRAM2/70.  
Added 4 rows with the following content: S71PL254JB0; TB; pSRAM2/70.  
“S71PL-J based MCPs” on page 1  
Added 254M to Megabit indicator.  
Added 16 to CMOS indicator.  
Revision A5 (September 14, 2004)  
Product Selector Guide  
Updated the 128Mb Flash Memory table.  
Valid Combinations Table  
Updated the S71PL127J Valid Combinations table.  
Revision A6 (November 22, 2004)  
Product Selector Guide  
Updated the 32Mb and 64Mb tables.  
Valid Combinations Tables  
Updated the 32Mb and 64Mb combinations.  
Physical Dimensions  
Added the TSB064 package.  
Revision A7 (February 8, 2005)  
pSRAM Type 7  
Updated all information in this section.  
Revision A8 (April 6, 2005)  
S29PL-J Flash  
Updated all information in this section.  
Revision A9 (May 12, 2005)  
S71PL-J MCP  
Added the S71PL064J0A option to cover the inclusion of the 16M SRAM  
pSRAM Type 2  
Added the latest revision for the pSRAM Type 2  
SRAM Type 2  
Added this module to the S71PL-J MCP  
Revision A10 (June 22, 2005)  
S71PL-J MCP  
Removed 127/16 and 254/32 pSRAM and updated OPN for 64/16SRAM  
Revision A11 (July 29, 2005)  
pSRAM Type 7  
Updated module  
March 17, 2006 S71PL-J_00_B3  
S71PL-J Based MCPs  
21  
A d v a n c e I n f o r m a t i o n  
Revision B0 (September 29, 2005)  
S29PL-J  
Updated module  
SRAM Type 1  
Updated module  
Revision B1 (October 25, 2005)  
pSRAM Module Type 5  
Added module  
Revision B2 (January 25, 2006)  
Added notices for devices not recommended for new designs  
Modified the Product Selection Guide  
Modified the S71PL032J, S71PL064J, S71PL127JValid Combinations tables  
Revision B3 (March 17, 2006)  
Modified the stucture of the document. Related data sheets are referenced rather  
than be embedded. Added data sheet reference table to that effect.  
Added the SRAM Type 4 option  
Added the 8Mb pSRAM Type 3 option  
Colophon  
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary  
industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that  
includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal  
injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,  
medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and  
artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-  
mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such  
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels  
and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on ex-  
port under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the  
prior authorization by the respective government entity will be required for export of those products.  
Trademarks and Notice  
The contents of this document are subject to change without notice. This document may contain information on a Spansion LLC product under development  
by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided  
as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement  
of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the  
use of the information in this document.  
Copyright ©2004 – 2006 Spansion LLC. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, and combinations thereof are trademarks  
of Spansion LLC. Other names are for informational purposes only and may be trademarks of their respective owners.  
22  
S71PL-J Based MCPs  
S71PL-J_00_B3 March 17, 2006  

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