S71WS128JB0BAWAA1 [SPANSION]
Memory IC,;
| 型号： | S71WS128JB0BAWAA1 |
| 厂家： | 
SPANSION |
| 描述： | Memory IC, |
| 文件： | 总194页 (文件大小：2885K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S71WS-J Based MCPs
Stacked Multi-Chip Product (MCP)
Package-on-Package (PoP)
128/64 Megabit (8M/4M x 16-bit) CMOS 1.8 Volt-only,
Simultaneous Read/Write, Burst Mode Flash Memory
with CellularRAM
ADVANCE
INFORMATION
Data Sheet
Notice to Readers: The Advance Information status indicates that this
document contains information on one or more products under development
at Spansion LLC. The information is intended to help you evaluate this product.
Do not design in this product without contacting the factory. Spansion LLC
reserves the right to change or discontinue work on this proposed product
without notice.
Publication Number S71WS-J_03 Revision A Amendment 3 Issue Date November 28, 2005
A d v a n c e I n f o r m a t i o n
Notice On Data Sheet Designations
Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise
readers of product information or intended specifications throughout the product life cycle, in-
cluding development, qualification, initial production, and full production. In all cases, however,
readers are encouraged to verify that they have the latest information before finalizing their de-
sign. The following descriptions of Spansion data sheet designations are presented here to high-
light their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion LLC is developing one or more spe-
cific products, but has not committed any design to production. Information presented in a doc-
ument with this designation is likely to change, and in some cases, development on the product
may discontinue. Spansion LLC therefore places the following conditions upon Advance Informa-
tion content:
“This document contains information on one or more products under development at Spansion LLC. The
information is intended to help you evaluate this product. Do not design in this product without con-
tacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a
commitment to production has taken place. This designation covers several aspects of the prod-
uct life cycle, including product qualification, initial production, and the subsequent phases in the
manufacturing process that occur before full production is achieved. Changes to the technical
specifications presented in a Preliminary document should be expected while keeping these as-
pects of production under consideration. Spansion places the following conditions upon Prelimi-
nary content:
“This document states the current technical specifications regarding the Spansion product(s) described
herein. The Preliminary status of this document indicates that product qualification has been completed,
and that initial production has begun. Due to the phases of the manufacturing process that require
maintaining efficiency and quality, this document may be revised by subsequent versions or modifica-
tions due to changes in technical specifications.”
Combination
Some data sheets will contain a combination of products with different designations (Advance In-
formation, Preliminary, or Full Production). This type of document will distinguish these products
and their designations wherever necessary, typically on the first page, the ordering information
page, and pages with DC Characteristics table and AC Erase and Program table (in the table
notes). The disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal
changes are expected, the Preliminary designation is removed from the data sheet. Nominal
changes may include those affecting the number of ordering part numbers available, such as the
addition or deletion of a speed option, temperature range, package type, or V range. Changes
IO
may also include those needed to clarify a description or to correct a typographical error or incor-
rect specification. Spansion LLC applies the following conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s) described
herein. Spansion LLC deems the products to have been in sufficient production volume such that sub-
sequent versions of this document are not expected to change. However, typographical or specification
corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local AMD or Fujitsu
sales office.
ii
S71WS-J Based MCPs
S71WS-J_03_A3 November 28, 2005
S71WS-J Based MCPs
Stacked Multi-Chip Product (MCP)
Package-on-Package (PoP)
128/64 Megabit (8M/4M x 16-bit) CMOS 1.8 Volt-only,
Simultaneous Read/Write, Burst Mode Flash Memory with
CellularRAM
Data Sheet
ADVANCE INFORMATION
Distinctive Characteristics
!
!
Packages
MCP Features
— 8 x 11.6mm, 84 ball FBGA
— 12 x 12 x 1.10 mm, 128 ball PoP, 0.50 mm ball
Operating Temperature
!
Power supply voltage of 1.7 to 1.95V
Speed: 66MHz
!
— –25°C to +85°C
General Description
The S71WS series is a product line of stacked memory packages (MCP and PoP) and consists
of:
!
!
One or more flash memory die
pSRAM
The products covered by this document are listed in the table below. For details about their
specifications, please refer to the individual constituent datasheets for further details:
Flash Memory Density
256Mb
128Mb
64Mb
64Mb
32Mb
16Mb
S71WS256JC0
S71WS128JC0
S71WS128JB0
S71WS128JA0
pSRAM
Density
S71WS064JB0
S71WS064JA0
Publication Number S71WS-J_03 Revision A Amendment 3 Issue Date November 28, 2005
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not
design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
A d v a n c e I n f o r m a t i o n
Table of Contents
S71WS-J Based MCPs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
1
2
3
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Product Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Connection Diagram (CellularRAM Type-based) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 S71WS064JA0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.2 S71WS064JB0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 S71WS128J and S71WS256J. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.4 Special Handling Instructions For FBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.5 S71WS064JA0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
MCP Lookahead Connection Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Input/Output Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1 TLA084 – 84-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
7.2 FTA084 – 84-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.3 TSC080 - Fine-Pitch Ball Grid Array (FBGA) 7 x 9 mm Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
7.4 ALG128 - 128-ball Fine-Pitch Ball Grid Array (FBGA) 12 x 12 mm Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4
5
6
7
S29WS128J/064J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8
9
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10 Block Diagram of Simultaneous Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
11 Device Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
11.1 Requirements for Asynchronous ReadOperation (Non-Burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
11.2 Requirements for Synchronous (Burst) Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
11.3 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
11.4 Handshaking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
11.5 Simultaneous Read/Write Operations with Zero Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
11.6 Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
11.7 Accelerated Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
11.8 Autoselect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
11.9 Sector/Sector Block Protection and Unprotection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
12 Advanced Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
12.1 Lock Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
12.2 Persistent Protection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
12.3 Dynamic Protection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
12.4 Persistent Protection Bit Lock Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
12.5 Password Protection Method. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
12.6 Advanced Sector Protection Software Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
12.7 Hardware Data Protection Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
13 Common Flash Memory Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
14 Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
14.1 Reading Array Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
14.2 Set Configuration Register Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
14.2.1 Read Mode Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
14.2.2 Programmable Wait State Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
14.2.3 Standard wait-state Handshaking Option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
14.2.4 Read Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
14.2.5 Burst Active Clock Edge Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
14.2.6 RDY Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
14.3 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
14.4 Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
14.5 Autoselect Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
2
S71WS-J Based MCPs
S71WS-J_03_A3 November 28, 2005
A d v a n c e I n f o r m a t i o n
14.6 Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . 69
14.7 Program Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
14.7.1 Unlock Bypass Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
14.8 Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
14.9 Sector Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
14.10 Erase Suspend/Erase Resume Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
14.11 Password Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
14.12 Password Verify Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
14.13 Password Protection Mode Locking Bit Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
14.14 Persistent Sector Protection Mode Locking Bit Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
14.15 Secured Silicon Sector Protection Bit Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
14.16 PPB Lock Bit Set Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
14.17 DPB Write/Erase/Status Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
14.18 Password Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
14.19 PPB Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
14.20 All PPB Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
14.21 PPB Status Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
14.22 PPB Lock Bit Status Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
14.23 Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
15 Write Operation Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
15.1 DQ7: Data# Polling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
15.2 RDY: Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
15.3 DQ6: Toggle Bit I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
15.4 DQ2: Toggle Bit II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
15.5 Reading Toggle Bits DQ6/DQ2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
15.6 DQ5: Exceeded Timing Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
15.7 DQ3: Sector Erase Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
16 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
17 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
18 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
18.1 CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
19 Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
20 Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
21 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
22 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
22.1 CLK Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
22.2 Synchronous/Burst Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
22.3 Asynchronous Mode Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
22.4 Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
22.5 Erase/Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
22.6 Temporary Sector Unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
23 Erase and Programming Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
24 Flash Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
24.1 Revision A0 (July 22, 2004). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
24.2 Revision A1 (October 6, 2004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
24.3 Revision A2 (December 10, 2004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
24.4 Revision A3 (February 19, 2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
24.5 Revision A4 (June 24, 2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
CellularRAM Type 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
25 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
26 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
26.1 Power-Up Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
27 Bus Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
27.1 Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
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27.2 Page Mode Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
27.3 Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
27.4 Mixed-Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
27.5 Wait Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
27.6 LB#/UB# Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
28 Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
28.1 Standby Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
28.2 Temperature Compensated Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
28.3 Partial Array Refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
28.4 Deep Power-Down Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
29 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
29.1 Access Using CRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
29.2 Software Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
29.3 Bus Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
29.3.1 Burst Length (BCR[2:0]): Default = Continuous Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
29.3.2 Burst Wrap (BCR[3]): Default = No Wrap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
29.3.3 Output Impedance (BCR[5]): Default = Outputs Use Full Drive Strength. . . . . . . . . . . . . . . . . . . . . . . 133
29.3.4 Wait Configuration (BCR[8]): Default = Wait Transitions One Clock Before Data Valid/Invalid. . . . 133
29.3.5 Wait Polarity (BCR[10]): Default = Wait Active High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
29.3.6 Latency Counter (BCR[13:11]): Default = Three-Clock Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
29.3.7 Operating Mode (BCR[15]): Default = Asynchronous Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
29.4 Refresh Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
29.4.1 Partial Array Refresh (RCR[2:0]): Default = Full Array Refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
29.4.2 Deep Power-Down (RCR[4]): Default = DPD Disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
29.4.3 Temperature Compensated Refresh (RCR[6:5]): Default = +85ºC Operation . . . . . . . . . . . . . . . . . . . 136
29.4.4 Page Mode Operation (RCR[7]): Default = Disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
30 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
31 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
32 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
33 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
34 64M CellRAM Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Aysnc/Page CellularRAM Type 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
35 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
36 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
36.1 Power-Up Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
37 Bus Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
37.1 Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
37.2 Page Mode Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
37.3 LB#/UB# Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
38 Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
38.1 Standby Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
38.2 Temperature Compensated Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
38.3 Partial Array Refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
38.4 Deep Power-Down Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
39 Configuration Register Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
39.1 Access Using ZZ# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
39.2 Software Access to the Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
39.3 Partial Array Refresh (CR[2:0]) Default = Full Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
39.4 Sleep Mode (CR[4]) Default = PAR Enabled, DPD Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
39.5 Temperature Compensated Refresh (CR[6:5]) Default = On-Chip Temperature Sensor. . . . . . . . . . . . . . . . .179
39.6 Page Mode READ Operation (CR[7]) Default = Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
40 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
40.1 Maximum and Typical Standby Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
41 32/16M CellRAM Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
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42 MCP Revision Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
42.1 Revision A0 (October 14, 2004). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
42.2 Revision A1 (June 15, 2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
42.3 Revision A2 (October 28, 2005). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
42.4 Revision A3 (November 28, 2005). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
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Tables
Table 11.1
Table 11.2
Table 11.3
Table 11.4
Table 11.5
Table 12.1
Table 12.2
Table 13.1
Table 13.2
Table 13.3
Table 13.4
Table 13.5
Table 13.6
Table 14.1
Table 14.2
Table 14.3
Table 14.4
Table 14.5
Table 15.1
Table 15.2
Table 19.1
Table 25.1
Table 25.2
Table 25.3
Table 29.1
Table 29.2
Table 29.3
Table 29.4
Table 29.5
Table 31.1
Table 31.2
Table 31.3
Table 32.1
Table 32.2
Table 32.3
Table 32.4
Table 32.5
Table 32.6
Table 33.1
Table 35.1
Table 35.2
Table 39.1
Table 39.2
Table 40.1
Table 40.2
Table 40.3
Table 40.4
Table 40.5
Table 40.6
Table 40.7
Table 40.8
Table 40.9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Burst Address Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Autoselect Codes (High Voltage Method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
S29WS128J/064J Boot Sector/Sector Block Addresses for Protection/Unprotection. . . . . . . . . . . . . . . . . . . 33
S29WS064J Boot Sector/Sector Block Addresses for Protection/Unprotection. . . . . . . . . . . . . . . . . . . . . . . 35
Lock Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Sector Protection Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
System Interface String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Primary Vendor-Specific Extended Query. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
WS128J Sector Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
WS064J Sector Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Programmable Wait State Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Wait States for Standard wait-state Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Read Mode Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
DQ6 and DQ2 Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Bus Operations—Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Bus Operations—Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Bus Configuration Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Sequence and Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Variable Latency Configuration Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Refresh Configuration Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
64Mb Address Patterns for PAR (RCR[4] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Maximum Standby Currents for Applying PAR and TCR Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Deep Power-Down Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Output Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Asynchronous Read Cycle Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Burst Read Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Asynchronous Write Cycle Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Burst Write Cycle Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Initialization Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
32-Mb Address Patterns for PAR (CR[4] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
16-Mb Address Patterns for PAR (CR[4] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Maximum Standby Currents for Applying PAR and TCR Settings – 32Mb . . . . . . . . . . . . . . . . . . . . . . . . . 181
Maximum Standby Currents for Applying PAR and TCR Settings – 16Mb . . . . . . . . . . . . . . . . . . . . . . . . . 181
Deep Power-Down Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Capacitance Specifications and Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Output Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
READ Cycle Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 40.10 Load Configuration Register Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 40.11 Deep Power-Down Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
6
S71WS-J Based MCPs
S71WS-J_03_A3 November 28, 2005
A d v a n c e I n f o r m a t i o n
Table 40.12 Power-Up Initialization Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 40.13 Load Configuration Register Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 40.14 Deep Power-Down Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 40.15 Single READ Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 40.16 Page Mode READ Timing Parameters (WE# = VIH). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 40.17 WRITE Cycle Timing Parameters (WE# Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 40.18 WRITE Cycle Timing Parameters (CE# Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 40.19 WRITE Cycle Timing Parameters (LB#/UB# Control). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
November 28, 2005 S71WS-J_03_A3
S71WS-J Based MCPs
7
A d v a n c e I n f o r m a t i o n
Figures
Figure 12.1
Figure 12.2
Figure 12.3
Advanced Sector Protection/Unprotection .............................................................................................37
PPB Program/Erase Algorithm.............................................................................................................40
Lock Register Program Algorithm.........................................................................................................43
Figure 14.1
Figure 14.2
Synchronous/Asynchronous State Diagram...........................................................................................64
Program Operation............................................................................................................................70
Figure 14.3
Figure 15.1
Figure 15.2
Figure 16.1
Figure 16.2
Erase Operation................................................................................................................................73
Data# Polling Algorithm.....................................................................................................................81
Toggle Bit Algorithm..........................................................................................................................83
Maximum Negative Overshoot Waveform .............................................................................................87
Maximum Positive Overshoot Waveform...............................................................................................87
Figure 19.1
Figure 21.1
Figure 22.1
Figure 22.2
Test Setup .......................................................................................................................................90
Input Waveforms and Measurement Levels...........................................................................................90
V
Power-up Diagram ......................................................................................................................91
CC
CLK Characterization .........................................................................................................................92
CLK Synchronous Burst Mode Read (rising active CLK)...........................................................................93
CLK Synchronous Burst Mode Read (Falling Active Clock) .......................................................................94
Synchronous Burst Mode Read............................................................................................................94
8-word Linear Burst with Wrap Around.................................................................................................95
Linear Burst with RDY Set One Cycle Before Data..................................................................................95
Asynchronous Mode Read with Latched Addresses .................................................................................96
Asynchronous Mode Read...................................................................................................................97
Figure 22.3
Figure 22.4
Figure 22.5
Figure 22.6
Figure 22.7
Figure 22.8
Figure 22.9
Figure 22.10 Reset Timings...................................................................................................................................98
Figure 22.11 Asynchronous Program Operation Timings: AVD# Latched Addresses.....................................................100
Figure 22.12 Asynchronous Program Operation Timings: WE# Latched Addresses ......................................................101
Figure 22.13 Synchronous Program Operation Timings: WE# Latched Addresses........................................................102
Figure 22.14 Synchronous Program Operation Timings: CLK Latched Addresses.........................................................103
Figure 22.15 Chip/Sector Erase Command Sequence..............................................................................................104
Figure 22.16 Accelerated Unlock Bypass Programming Timing .................................................................................105
Figure 22.17 Data# Polling Timings (During Embedded Algorithm)...........................................................................105
Figure 22.18 Toggle Bit Timings (During Embedded Algorithm)................................................................................106
Figure 22.19 Synchronous Data Polling Timings/Toggle Bit Timings ..........................................................................106
Figure 22.20 DQ2 vs. DQ6..................................................................................................................................107
Figure 22.21 Temporary Sector Unprotect Timing Diagram......................................................................................107
Figure 22.22 Sector/Sector Block Protect and Unprotect Timing Diagram...................................................................108
Figure 22.23 Latency with Boundary Crossing........................................................................................................108
Figure 22.24 Latency with Boundary Crossing into Program/Erase Bank....................................................................109
Figure 22.25 Example of Wait States Insertion ......................................................................................................110
Figure 22.26 Back-to-Back Read/Write Cycle Timings .............................................................................................111
Figure 25.1
Figure 26.1
Figure 27.1
Figure 27.2
Functional Block Diagram.................................................................................................................116
Power-Up Initialization Timing...........................................................................................................120
Read Operation (ADV# Low).............................................................................................................121
Write Operation (ADV# Low) ............................................................................................................121
Figure 27.3
Figure 27.4
Figure 27.5
Figure 27.6
Figure 27.7
Figure 27.8
Figure 29.1
Figure 29.2
Figure 29.3
Figure 29.4
Figure 29.5
Figure 29.6
Figure 29.7
Page Mode Read Operation (ADV# Low).............................................................................................122
Burst Mode Read (4-word burst) .......................................................................................................123
Burst Mode Write (4-word burst).......................................................................................................124
Wired or Wait Configuration..............................................................................................................124
Refresh Collision During Read Operation.............................................................................................125
Refresh Collision During Write Operation ............................................................................................126
Configuration Register WRITE in Asynchronous Mode Followed by READ ARRAY Operation ........................128
Configuration Register WRITE in Synchronous Mode Followed by READ ARRAY Operation..........................128
Load Configuration Register..............................................................................................................129
Read Configuration Register .............................................................................................................130
Wait Configuration (BCR[8] = 0).......................................................................................................133
Wait Configuration (BCR[8] = 1).......................................................................................................133
Wait Configuration During Burst Operation .........................................................................................134
8
S71WS-J Based MCPs
S71WS-J_03_A3 November 28, 2005
A d v a n c e I n f o r m a t i o n
Figure 29.8
Latency Counter (Variable Initial Latency, No Refresh Collision).............................................................134
Figure 31.1
Figure 32.1
Figure 32.2
Typical Refresh Current vs. Temperature (I
AC Input/Output Reference Waveform ...............................................................................................140
Output Load Circuit .........................................................................................................................140
)...................................................................................139
TCR
Figure 33.1
Figure 33.2
Figure 33.3
Figure 33.4
Figure 33.5
Figure 33.6
Figure 33.7
Figure 33.8
Figure 33.9
Initialization Period..........................................................................................................................145
Asynchronous Read.........................................................................................................................146
Asynchronous Read Using ADV# .......................................................................................................147
Page Mode Read .............................................................................................................................148
Single-Access Burst Read Operation—Variable Latency.........................................................................149
Four-word Burst Read Operation—Variable Latency..............................................................................150
Four-word Burst Read Operation (with LB#/UB#)................................................................................151
Refresh Collision During Write Operation ............................................................................................152
Continuous Burst Read Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition.....................153
Figure 33.10 CE#-Controlled Asynchronous Write ..................................................................................................154
Figure 33.11 LB#/UB#-Controlled Asynchronous Write ...........................................................................................155
Figure 33.12 WE#-Controlled Asynchronous Write..................................................................................................156
Figure 33.13 Asynchronous Write Using ADV#.......................................................................................................157
Figure 33.14 Burst Write Operation......................................................................................................................158
Figure 33.15 Continuous Burst Write Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition ....................159
Figure 33.16 Burst Write Followed by Burst Read...................................................................................................160
Figure 33.17 Asynchronous Write Followed by Burst Read .......................................................................................161
Figure 33.18 Asynchronous Write (ADV# Low) Followed By Burst Read.....................................................................162
Figure 33.19 Burst Read Followed by Asynchronous Write (WE#-Controlled)..............................................................163
Figure 33.20 Burst Read Followed by Asynchronous Write Using ADV# .....................................................................164
Figure 33.21 Asynchronous Write Followed by Asynchronous Read—ADV# Low..........................................................165
Figure 33.22 Asynchronous Write Followed by Asynchronous Read ...........................................................................166
November 28, 2005 S71WS-J_03_A3
S71WS-J Based MCPs
9
A d v a n c e I n f o r m a t i o n
1 Product Selector Guide
pSRAM
Density
Flash Speed
(MHz)
pSRAM Speed
(MHz/ns)
Device-Model#
S71WS064JA0KFW5A
S71WS064JB0-2A
Flash Density
Supplier
Package
12x12x1.10 mm
.50 mm ball size
128-ball
16Mb
Cellular RAM Type 2
Cellular RAM Type 2
PoP
64Mb
7x9x1.2 mm
80-ball, MCP
32Mb
66
66/70
S71WS128JA0-AA
S71WS128JB0-AA
S71WS128JC0-AA
16Mb
32Mb
Cellular RAM Type 2
Cellular RAM Type 2
Cellular RAM Type 2
8x11.6x1.2mm
84-ball, MCP
128Mb
256Mb
64Mb
8x11.6x1.4mm
84-ball, MCP
S71WS256JC0-TA
Cellular RAM Type 2
10
S71WS-J Based MCPs
S71WS-J_03_A3 November 28, 2005
A d v a n c e I n f o r m a t i o n
2 Product Block Diagram
V
f
CC
Flash-only Address
Shared Address
V
V
ID
CC
DQ15 to DQ0
CLK
WP#
A22
16
DQ15 to DQ0
CLK
WP#
ACC
(Note 2) CE#f1
OE#
ACC
CE#
OE#
WE#
Flash 1
Flash 2
(Note 3)
WE#
RESET#
AVD#
RESET#
AVD#
RDY
RDY
(Note 2) CE#f2
V
SS
V
s
CC
A22
V
V
CCQ
CC
(Note 5)
CLK
16
CE#s
CE#
WE#
OE#
I/O15 to I/O0
pSRAM
UB#s
LB#s
UB#
LB#
V
SSQ
(Note 5)
AVD#
CRE
(Note 1) CREs
Notes:
1. CREs is only present in CellularRAM-compatible pSRAM.
2. For 1 Flash = pSRAM, CE#f1 = CE#. For 2 Flash + pSRAM, CE# = CE#f1 and CE#f2 is the chip-enable pin for the
second Flash.
3. Only needed for S71WS256JC0.
4. CLK and AVD# not applicable for 16Mb pSRAM.
November 28, 2005 S71WS-J_03_A3
S71WS-J Based MCPs
11
A d v a n c e I n f o r m a t i o n
3 Connection Diagram (CellularRAM Type-based)
3.1
S71WS064JA0
80-ball Fine-Pitch Ball Grid Array MCP
(Top View, Balls Facing Down)
A1
A2
A3
A4
A5
A6
A7
A8
RFU
CLK
RFU
RFU
RFU
RFU
RFU
AVD#
B1
B2
A7
B3
R-LB#
C3
B4
F-ACC
C4
B5
WE#
C5
B6
A8
B7
A11
C7
B8
RFU
C8
F-WP#
C1
C2
C6
1st Flash only
1st RAM only
A3
A6
R-UB#
D3
F-RST#
D4
RFU
D5
A19
D6
A12
D7
A15
D8
D1
A2
D2
A5
A18
E3
RDY
E4
A20
E5
A9
A13
E7
A21
E8
E1
E2
E6
Reserved for
Future Use
RFU
RFU
A1
A4
A17
F3
A10
F6
A14
F7
RFU
F8
F1
F2
F4
RFU
G4
F5
RFU
G5
A0
VSS
G2
OE#
H2
DQ1
G3
DQ6
G6
RFU
G7
A16
All Shared
G1
G8
R-CRE
H8
F-CE#
H1
DQ9
H3
DQ3
H4
DQ4
H5
DQ13
H6
DQ15
H7
R-CE1#
J1
DQ0
J2
DQ10
J3
F-VCC
J4
R-VCC
J5
DQ12
J6
DQ7
J7
VSS
J8
RFU
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
RFU
K4
K1
K2
K3
K5
K6
K7
K8
RFU
RFU
RFU
F-VCC
RFU
RFU
RFU
RFU
12
S71WS-J Based MCPs
S71WS-J_03_A3 November 28, 2005
A d v a n c e I n f o r m a t i o n
3.2
S71WS064JB0
80-ball Fine-Pitch Ball Grid Array MCP
(Top View, Balls Facing Down)
A1
A2
A3
A4
A5
A6
A7
A8
RFU
CLK
RFU
RFU
RFU
RFU
RFU
AVD#
B1
B2
A7
B3
R-LB#
C3
B4
F-ACC
C4
B5
WE#
C5
B6
A8
B7
A11
C7
B8
RFU
C8
F-WP#
C1
C2
C6
1st Flash only
1st RAM only
A3
A6
R-UB#
D3
F-RST#
D4
RFU
D5
A19
D6
A12
D7
A15
D8
D1
A2
D2
A5
A18
E3
RDY
E4
A20
E5
A9
A13
E7
A21
E8
E1
E2
E6
Reserved for
Future Use
RFU
RFU
A1
A4
A17
F3
A10
F6
A14
F7
RFU
F8
F1
F2
F4
RFU
G4
F5
RFU
G5
A0
VSS
G2
OE#
H2
DQ1
G3
DQ6
G6
RFU
G7
A16
All Shared
G1
G8
R-CRE
H8
F-CE#
H1
DQ9
H3
DQ3
H4
DQ4
H5
DQ13
H6
DQ15
H7
R-CE1#
J1
DQ0
J2
DQ10
J3
F-VCC
J4
R-VCC
J5
DQ12
J6
DQ7
J7
VSS
J8
RFU
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
RFU
K4
K1
K2
K3
K5
K6
K7
K8
RFU
RFU
RFU
F-VCC
RFU
RFU
RFU
RFU
November 28, 2005 S71WS-J_03_A3
S71WS-J Based MCPs
13
A d v a n c e I n f o r m a t i o n
3.3
S71WS128J and S71WS256J
84-ball Fine-Pitch Ball Grid Array MCP
(Top View, Balls Facing Down)
A1
A10
NC
NC
B2
B3
B4
B5
B6
B7
B8
B9
AVD#
RFU
CLK
RFU
RFU
RFU
RFU
RFU
Legend
C2
C3
A7
C4
LB#
D4
C5
ACC
D5
C6
WE#
D6
C7
A8
C8
A11
D9
C9
RFU
D10
A15
E9
WP#
D2
D3
D7
1st Flash only
1st RAM only
A3
A6
UB#
E4
RST#
E5
RFU
E6
A19
E7
A12
E8
E2
A2
E3
A5
A18
F4
RDY
F5
A20
F6
A9
A13
F8
A21
F9
F2
F3
F7
Reserved for
Future Use
RFU
RFU
A1
A4
A17
G4
A10
G7
A14
G8
A22
G9
G2
G3
VSS
H3
G5
RFU
H5
G6
RFU
H6
A0
DQ1
H4
DQ6
H7
RFU
H8
A16
Flash/RAM Shared
H2
H9
CREs
J9
CE1#f
J2
OE#
J3
DQ9
J4
DQ3
J5
DQ4
J6
DQ13
J7
DQ15
J8
CE1#s
K2
DQ0
K3
DQ10
K4
VCCf
K5
VCCs
K6
DQ12
K7
DQ7
K8
VSS
K9
RFU
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
RFU
L5
L2
L3
L4
L6
L7
L8
L9
RFU
RFU
RFU
VCCf
RFU
RFU
RFU
RFU
M1
NC
M10
NC
Notes:
1. In stacked products based on a single S29WS-J Flash Die, ball B5 is RFU. In MCP’s based on two S29WS-J (S71WS256J), ball
B5 is CE#f2 or F2-CE#.
2. Addresses are shared between Flash and RAM depending on the density of the pSRAM.
MCP
Flash-only Addresses
Shared Addresses
A19-A0
S71WS064JA0
S71WS128JA0
S71WS128JB0
S71WS128JC0
S71WS256JC0
A21-A20
A22-A20
A22-A21
A22
A19-A0
A19-A0
A21-A0
A22
A21-A0
3.4 Special Handling Instructions For FBGA Package
Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultra-
sonic cleaning methods. The package and/or data integrity may be compromised
if the package body is exposed to temperatures above 150°C for prolonged peri-
ods of time.
14
S71WS-J Based MCPs
S71WS-J_03_A3 November 28, 2005
A d v a n c e I n f o r m a t i o n
3.5
S71WS064JA0
128-ball Fine-Pitch Ball Grid Array PoP
(Top View, Balls Facing Down)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
A
B
C
D
E
NC
NC
NC
NC
A0
A2
A3
A4
A5
A6
A7
F-VCC
F-VSS
A8
A9
A10
A11
A12
A13
A14 F-VCC
A15 F-VSS
A16
A17
A18
A19
A20
A21
RFU
RFU
NC
NC
NC
NC
RFU
RFU
RFU
R-VSS
A1
R-VSS
RFU
RFU
RFU
Legend
P1-CRE
RFU
RFU
RFU
RFU
RFU
RFU
RFU
NOR
F
Reserved for
Future Use
G
H
RFU
F-VSS
RFU
R-VCC F-ADV
F-WE#/ F-OE#/
P1-CE#
P-WE#
P-OE#
pSRAM
J
RFU
RFU
RFU
RFU
RFU
RFU
K
L
RFU
RFU
F-CLK
F1-CE#
RFU
NOR+pSRAM
No Connect
RFU
RFU
M
N
P
R
T
U
V
F-WAIT
R-VSS
F-VSS
F-VCC2 R-VCC
DQ14 DQ15
VCCQ VSSQ
R-VCC F-VCC1
DQ1
DQ0
VSSQ VCCQ
RFU
NC
NC
RFU
NC
NC
RFU
NC
NC
RFU
NC
NC
RFU
RFU
DQ13 DQ11 VSSQ
DQ9
RFU
RFU
F-WP#1
RFU
DQ7
DQ6
VSSQ
VCCQ
DQ5
DQ4
DQ3
DQ2
RFU
RFU
F-
RST#
DQ12 DQ10 VCCQ DQ8
P-UB# F-VPP
P-LB#
Note: The V and V
(V ) signals must be ramped simultaneously to ensure a successful power up sequence.
CC
CCQ
IO
November 28, 2005 S71WS-J_03_A3
S71WS-J Based MCPs
15
A d v a n c e I n f o r m a t i o n
4 MCP Lookahead Connection Diagram
Contact your local Spansion representative for a complete PoP lookahead pinout.
A2
RFU
B2
A10
RFU
B10
RFU
A9
RFU
B9
A1
RFU
B1
Legend:
X
RFU
(Reserved for
Future Use)
RFU
RFU
C2
RFU
C9
C8
C3
VSS
D3
A7
C4
CLK
D4
C5
F2-CE#
D5
C6
F-VCC
D6
C7
X
AVD#
D2
F-CLK# R-OE# F2-OE#
Code Flash Only
D7
A8
D8
A11
E8
D9
F3-CE#
E9
WP#
E2
R-LB#
D4
ACC
WE#
E6
X
E3
E7
C7
MirrorBit Data
Only
A3
A6
R-UB# F-RST# R1-CE2
F4 F5 F6
A18 RDY/WAIT# A20
A19
A12
A15
F2
F3
F7
F8
F9
X
A2
A5
A9
A13
A21
Flash/Data
Shared
G2
A1
G3
A4
G4
A17
H4
G5
G6
A23
H6
G7
A10
H7
G8
A14
H8
G9
A22
H9
R2-CE1
X
H2
H3
H5
Flash/xRAM
Shared
A0
VSS
DQ1
R2-VCC R2-CE2
DQ6
A24
A16
J9
J3
J4
J5
J6
J7
J8
J2
X
F1-CE#
OE#
DQ9
DQ3
DQ4
DQ13
DQ15 R-CRE or
R-MRS
pSRAM Only
K2
R1-CE1#
L2
K3
DQ0
L3
K4
DQ10
L4
E6
R1-VCC
L6
K7
K8
DQ7
L8
K9
K5
F-VCC
L5
DQ12
VSS
X
L7
DQ5
M7
L9
WP#
M9
xRAM Shared
R-VCC
M2
DQ8
M3
DQ2
M4
DQ11
M5
A25
DQ14
M8
M6
A27
A26
VSS
F-VCC
F4-CE# R-VCCQ F-VCCQ R-CLK#
N2
N1
N10
F-DQS1
P10
N9
RFU
P9
RFU
P2
F-DQS0
P1
RFU
RFU
RFU
RFU
Notes:
1. F1 and F2 denote XIP/Code Flash, while F3 and F4 denote Data/Companion Flash.
2. In addition to being defined as F2-CE#, Ball C5 can also be assigned as F1-CE2# for code flash that has two chip
enable signals.
3. For MCPs requiring 3.0V Vcc and 1.8V Vio, use the 1.8V Look-ahead Pinout in order to accommodate extra AVD,
MRS and CLK pins for the pSRAM (if needed).
4. Refer to Application Note on pinout subsets to match the package size offerings.
16
S71WS-J Based MCPs
S71WS-J_03_A3 November 28, 2005
A d v a n c e I n f o r m a t i o n
5 Input/Output Descriptions
A22-A0
DQ15-DQ0
OE#
=
=
=
Address inputs
Data input/output
Output Enable input. Asynchronous relative to CLK
for the Burst mode.
WE#
VSS
NC
=
=
=
=
Write Enable input.
Ground
No Connect; not connected internally
Ready output. Indicates the status of the Burst read
(shared with WAIT# pin of RAM).
RDY
CLK
=
Clock input. In burst mode, after the initial word is
output, subsequent active edges of CLK increment
the internal address counter. Should be at VIL or VIH
while in asynchronous mode
AVD#
=
Address Valid input. Indicates to device that the
valid address is present on the address inputs.
Low = for asynchronous mode, indicates valid
address; for burst mode, causes starting address to
be latched.
High = device ignores address inputs
RESET#
WP#
=
=
Hardware reset input. Low = device resets and
returns to reading array data
Hardware write protect input. At VIL, disables
program and erase functions in the four outermost
sectors. Should be at VIH for all other conditions.
ACC
=
Accelerated input. At VHH, accelerates
programming; automatically places device in unlock
bypass mode. At VIL, disables all program and erase
functions. Should be at VIH for all other conditions.
CE1#s
CE#f1
=
=
Chip-enable input for pSRAM.
Chip-enable input for Flash 1. Asynchronous relative
to CLK for Burst Mode.
CREs
=
=
=
=
=
=
Control Register Enable (pSRAM).
Flash 1.8 Volt-only single power supply.
pSRAM Power Supply.
Upper Byte Control (pSRAM).
Lower Byte Control (pSRAM).
Chip-enable input for Flash 2. Asynchronous relative
to CLK for burst mode (needed only for
S71WS256J).
VCC
f
VCCs
UB#s
LB#s
CE#f2
RFU
CE2s
=
=
Reserved for future use.
Chip-enable input for pSRAM
November 28, 2005 S71WS-J_03_A3
S71WS-J Based MCPs
17
A d v a n c e I n f o r m a t i o n
6 Ordering Information
The order number is formed by a valid combinations of the following:
S71WS 256
J
C0 BA
W
A
K
0
PACKING TYPE
0
2
3
=
=
=
Tray
7” Tape and Reel
13” Tape and Reel
MODEL NUMBER
CellularRAM 2, 66MHz
A
=
PACKAGE MODIFIER
A
T
2
5
=
=
=
=
8 x 11.6 mm, 1.2 mm height, 84 balls, MCP FBGA
8 x 11.6 mm, 1.4 mm height, 84 balls, MCP FBGA
7 x 9 mm, 1.2 mm height, 80 balls, MCP FBGA
12x12 mm, 1.2 mm height, 128 balls, PoP FBGA, 0.50 mm ball size
TEMPERATURE RANGE
Wireless (-25 C to +85°C)
W
=
°
PACKAGE TYPE
BA
BF
KF
=
=
=
Very-thin Fine-pitch BGA Lead (Pb)-free compliant package
Very-thin Fine-pitch BGA Lead (Pb)-free package
Fine-Pitch Package on Package (POP) Lead (Pb)-free package
pSRAM DENSITY
C0
B0
A0
=
=
=
64 Mb pSRAM
32 Mb pSRAM
16 Mb pSRAM
PROCESS TECHNOLOGY
110 nm, Floating Gate Technology
J
=
FLASH DENSITY
256
128
064
=
=
=
2x128Mb
128Mb
64Mb
PRODUCT FAMILY
S71WS Multi-chip Product (MCP)
1.8-volt Simultaneous Read/Write, Burst Mode Flash Memory and pRAM
Valid Combinations
Base Ordering
Part Number
pSRAM Density
Package Type
Temperature
Package Modifier
Model Number
Packing Type
A0
B0
KF
5
2
A
T
S71WS064J
BA, BF
BA, BF
BA, BF
W
A
0, 2, 3 1
S71WS128J
S71WS256J
A0, B0, C0
C0
Notes:
Valid Combinations
1. Packing Type 0 is standard. Specify other options as required.
2. BGA package marking omits leading “S” and packing type
designator from ordering part number.
Valid Combinations list configurations planned to be supported in vol-
ume for this device. Consult your local sales office to confirm avail-
ability of specific valid combinations and to check on newly released
combinations.
18
S71WS-J Based MCPs
S71WS-J_03_A3 November 28, 2005
A d v a n c e I n f o r m a t i o n
7 Physical Dimensions
7.1
TLA084 – 84-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm Package
A
D1
D
eD
0.15
(2X)
C
10
9
8
7
6
5
4
3
2
1
SE
7
E
E1
eE
L
J
H
G
F
E
D
C
B
A
M
K
INDEX MARK
10
PIN A1
PIN A1
CORNER
B
CORNER
7
SD
0.15
(2X)
C
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.20
0.08
C
C
A2
A
C
A1
6
84X
b
0.15
0.08
M
C
C
A B
M
NOTES:
PACKAGE
JEDEC
TLA 084
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
11.60 mm x 8.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
NOM
---
MAX
1.20
---
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.17
0.81
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
0.97
BODY THICKNESS
BODY SIZE
D
11.60 BSC.
8.00 BSC.
8.80 BSC.
7.20 BSC.
12
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
E1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
10
84
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
φb
0.35
0.40
0.45
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
eE
0.80 BSC.
0.80 BSC
0.40 BSC.
BALL PITCH
eD
SD / SE
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SOLDER BALL PLACEMENT
A2,A3,A4,A5,A6,A7,A8,A9
B1,B10,C1,C10,D1,D10,
E1,E10,F1,F10,G1,G10,
H1,H10,J1,J10,K1,K10,L1,L10,
M2,M3,M4,M5,M6,M7,M8,M9
DEPOPULATED SOLDER BALLS
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3372 \ 16-038.22a
November 28, 2005 S71WS-J_03_A3
S71WS-J Based MCPs
19
A d v a n c e I n f o r m a t i o n
7.2 FTA084 – 84-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm Package
A
D1
D
eD
0.15
(2X)
C
10
9
8
SE
7
7
6
E
B
E1
5
4
3
2
1
eE
J
H
G
F
E
D
C
B
A
M
L K
INDEX MARK
10
PIN A1
CORNER
PIN A1
CORNER
7
SD
0.15
(2X)
C
TOP VIEW
BOTTOM VIEW
0.20
0.08
C
C
A2
A
C
A1
SIDE VIEW
6
84X
b
0.15
M
C
C
A
B
0.08
M
NOTES:
PACKAGE
JEDEC
FTA 084
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
11.60 mm x 8.00 mm
PACKAGE
NOTE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
---
NOM
---
MAX
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
1.40
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.17
1.02
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
1.17
BODY THICKNESS
BODY SIZE
D
11.60 BSC.
8.00 BSC.
8.80 BSC.
7.20 BSC.
12
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
E1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
10
84
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
φb
0.35
0.40
0.45
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
eE
0.80 BSC.
0.80 BSC
0.40 BSC.
BALL PITCH
eD
SD / SE
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SOLDER BALL PLACEMENT
A2,A3,A4,A5,A6,A7,A8,A9
B1,B10,C1,C10,D1,D10,E1,E10
F1,F10,G1,G10,H1,H10
DEPOPULATED SOLDER BALLS
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
J1,J10,K1,K10,L1,L10
M2,M3,M4,M5,M6,M7,M8,M9
3388 \ 16-038.21a
20
S71WS-J Based MCPs
S71WS-J_03_A3 November 28, 2005
A d v a n c e I n f o r m a t i o n
7.3
TSC080 - Fine-Pitch Ball Grid Array (FBGA) 7 x 9 mm Package
D1
A
D
eD
0.15
(2X)
C
8
7
SE
7
6
5
4
3
2
E
B
E1
eE
1
K
J
H
G
F
E
D
C
B
A
INDEX MARK
9
PIN A1
CORNER
PIN A1
CORNER
7
SD
0.15
(2X)
C
TOP VIEW
BOTTOM VIEW
0.20
0.08
C
C
A2
A
C
A1
SIDE VIEW
6
80X
b
0.15
M
C
C
A
B
0.08
M
NOTES:
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
PACKAGE
JEDEC
TSC 080
N/A
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
9.00 mm x 7.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3,
SPP-010.
SYMBOL
MIN
---
NOM
---
MAX
1.20
---
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.17
0.81
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
0.97
BODY THICKNESS
BODY SIZE
D
9.00 BSC.
7.00 BSC.
7.20 BSC.
5.60 BSC.
10
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
E1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
8
80
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
Øb
eE
0.35
0.40
0.45
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
0.80 BSC.
0.80 BSC
0.40 BSC.
BALL PITCH
eD
SD / SE
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3496 \ 16-038.22 \ 5.20.05
November 28, 2005 S71WS-J_03_A3
S71WS-J Based MCPs
21
A d v a n c e I n f o r m a t i o n
7.4 ALG128 - 128-ball Fine-Pitch Ball Grid Array (FBGA) 12 x 12 mm Package
A
D
PIN A1
CORNER
D1
PIN A1
CORNER
9
eD
SD
7
INDEX MARK
A
B
C
D
E
F
SE
7
G
H
J
E
B
E1
K
L
M
N
P
R
T
eE
U
V
0.10
(2X)
C
18 17 16
14 13 12 11
9
7
6
15
10
8
5
4
2
3
1
0.10
(2X)
C
TOP VIEW
BOTTOM VIEW
0.10
0.10
C
C
A2
A
A1
C
SIDE VIEW
6
128X
b
0.15
0.08
M
C
C
A
B
M
NOTES:
PACKAGE
JEDEC
ALG128
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
D x E
12.00 mm x 12.00 mm
PACKAGE
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JEP95, SECTION
3.0, SPP-010.
SYMBOL
MIN
NOM
---
MAX
NOTE
A
A1
A2
D
---
1.10
---
PROFILE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
0.40
0.55
---
BALL HEIGHT
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
---
0.65
BODY THICKNESS
BODY SIZE
12.00 BSC.
12.00 BSC.
11.05 BSC.
11.05 BSC.
18
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
E
BODY SIZE
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
D1
E1
MD
ME
n
MATRIX FOOTPRINT
MATRIX FOOTPRINT
N IS THE MAXIMUM NUMBER OF BALLS ON THE FBGA PACKAGE.
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
18
128
DATUM C IS THE SEATING PLANE AND IS DEFINED BY THE
CROWNS OF THE SOLDER BALLS.
N
128
MAXIMUM NUMBER OF BALLS
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
R
2
NUMBER OF LAND PERIMETERS
BALL DIAMETER
Øb
eE
eD
SE / SD
0.45
0.50
0.55
0.65 BSC.
0.65 BSC
0.325 BSC.
BALL PITCH
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
BALL PITCH
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
C3-C16,D3-D16,E3-E16,
F3-F16,G3-G16,H3-H16,
J3-J16,K3-K16,L3-L16,
M3-M16,N3-N16,P3-P16,
R3-R16,T3-T16
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
10 OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.
3526 16-038.24 \ 10.26.05
22
S71WS-J Based MCPs
S71WS-J_03_A3 November 28, 2005
S29WS128J/064J
128/64 Megabit (8/4 M x 16-Bit)
CMOS 1.8 Volt-only Simultaneous Read/Write,
Burst Mode Flash Memory
Data Sheet
Distinctive Characteristics
Architectural Advantages
Hardware Features
!
Single 1.8 volt read, program and erase (1.65 to
1.95 volt)
!
!
!
Handshaking feature available
—
Provides host system with minimum possible latency by
monitoring RDY
!
!
Manufactured on 0.11 µm process technology
Hardware reset input (RESET#)
Simultaneous Read/Write operation
—
Hardware method to reset the device for reading array
data
— Data can be continuously read from one bank while
executing erase/program functions in other bank
— Zero latency between read and write operations
WP# input
— Write protect (WP#) function allows protection of
four outermost boot sectors, regardless of sector
protect status
—
Four bank architecture: WS128J: 16Mb/48Mb/48Mb/
16Mb, WS064J: 8Mb/24Mb/24Mb/8Mb
!
Programable Burst Interface
— 2 Modes of Burst Read Operation
— Linear Burst: 8, 16, and 32 words with wrap-around
!
Persistent Sector Protection
—
A command sector protection method to lock
combinations of individual sectors and sector groups to
prevent program or erase operations within that sector
—
Continuous Sequential Burst
!
!
Secured Silicon Sector region
—
Sectors can be locked and unlocked in-system at V
level
CC
— 128 words accessible through a command sequence,
64words for the Factory Secured Silicon Sector and
64words for the Customer Secured Silicon Sector.
Sector Architecture
!
!
Password Sector Protection
A sophisticated sector protection method to lock
—
combinations of individual sectors and sector groups to
prevent program or erase operations within that sector
using a user-defined 64-bit password
—
4 Kword x 16 boot sectors, eight at the top of the address
range, and eight at the bottom of the address range
—
WS128J: 4 Kword X 16, 32 Kword x 254 sectors
ACC input: Acceleration function reduces
programming time; all sectors locked when ACC =
VIL
Bank A : 4 Kword x 8, 32 Kword x 31 sectors
Bank B : 32 Kword x 96 sectors
!
!
CMOS compatible inputs, CMOS compatible outputs
Low VCC write inhibit
Bank C : 32 Kword x 96 sectors
Bank D : 4 Kword x 8, 32 Kword x 31 sectors
—
WS064J: 4 Kword x 16, 32 Kword x 126 sectors.
Bank A : 4 Kword x 8, 32 Kword x 15 sectors
Software Features
!
Supports Common Flash Memory Interface (CFI)
Bank B : 32 Kword x 48 sectors
!
Software command set compatible with JEDEC
42.4 standards
Bank C : 32 Kword x 48 sectors
Bank D : 4 Kword x 8, 32 Kword x 15 sectors
—
Backwards compatible with Am29BDS, Am29BDD,
Am29BL, and MBM29BS families
!
!
Cyclling Endurance : 1,000,000 cycles per sector
typical
Data retention : 20-years typical
!
!
Data# Polling and toggle bits
— Provides a software method of detecting program
and erase operation completion
Performance Characteristics
Erase Suspend/Resume
!
Read access times at 80/66 MHz
Synchronous latency of 71/56 ns (at 30 pF)
—
Suspends an erase operation to read data from, or
program data to, a sector that is not being erased, then
resumes the erase operation
—
— Asynchronous random access times of 55/55 ns (at
30 pF)
!
Unlock Bypass Program command
—
Reduces overall programming time when issuing multiple
program command sequences
!
Power dissipation (typical values, CL = 30 pF)
— Burst Mode Read: 18 mA @ 80Mhz
— Simultaneous Operation: 60 mA @ 80Mhz
— Program/Erase: 15 mA
—
Standby mode: 0.2 µA
Publication Number S29WS-J_M0 Revision A Amendment 4 Issue Date June 24, 2005
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion LLC deems the products to have been in sufficient
production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to
the valid combinations offered may occur.
D a t a S h e e t
General Description
The S29WS128J/064J/S29WS064J is a 128/64 Mbit, 1.8 Volt-only, simultaneous Read/Write,
Burst Mode Flash memory device, organized as 8,388,608/4,194,304 words of 16 bits each. This
device uses a single VCC of 1.65 to 1.95 V to read, program, and erase the memory array. A 12.0-
volt VHH on ACC may be used for faster program performance if desired. The device can also be
programmed in standard EPROM programmers.
At 80 MHz, the device provides a burst access of 9.1 ns at 30 pF with a latency of 46 ns at 30 pF.
At 66 MHz, the device provides a burst access of 11.2 ns at 30 pF with a latency of 56 ns at 30
pF. The device operates within the wireless temperature range of -25°C to +85°C, and is offered
in Various FBGA packages.
The Simultaneous Read/Write architecture provides simultaneous operation by dividing the
memory space into four banks. The device can improve overall system performance by allowing
a host system to program or erase in one bank, then immediately and simultaneously read from
another bank, with zero latency. This releases the system from waiting for the completion of pro-
gram or erase operations.
The device is divided as shown in the following table:
Quantity
Bank
128Mb
8
64 Mb
8
Size
4 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
4 Kwords
A
31
96
96
31
8
15
48
48
15
8
B
C
D
The device uses Chip Enable (CE#), Write Enable (WE#), Address Valid (AVD#) and Output En-
able (OE#) to control asynchronous read and write operations. For burst operations, the device
additionally requires Ready (RDY), and Clock (CLK). This implementation allows easy interface
with minimal glue logic to a wide range of microprocessors/microcontrollers for high performance
read operations.
The burst read mode feature gives system designers flexibility in the interface to the device. The
user can preset the burst length and wrap through the same memory space, or read the flash
array in continuous mode.
The clock polarity feature provides system designers a choice of active clock edges, either rising
or falling. The active clock edge initiates burst accesses and determines when data will be output.
The device is entirely command set compatible with the JEDEC 42.4 single-power-supply
Flash standard. Commands are written to the command register using standard microprocessor
write timing. Register contents serve as inputs to an internal state-machine that controls the
erase and programming circuitry. Write cycles also internally latch addresses and data needed for
the programming and erase operations. Reading data out of the device is similar to reading from
other Flash or EPROM devices.
The Erase Suspend/Erase Resume feature enables the user to put erase or program on hold
for any period of time to read data from, or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved. If a read is needed from the Secured Silicon
Sector area (One Time Program area) after an erase suspend, then the user must use the proper
command sequence to enter and exit this region. Program suspend is also offered.
24
S29WS128J/064J
S29WS-J_M0_A4 June 24, 2005
D a t a S h e e t
The hardware RESET# pin terminates any operation in progress and resets the internal state
machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A sys-
tem reset would thus also reset the device, enabling the system microprocessor to read boot-up
firmware from the Flash memory device.
The host system can detect whether a program or erase operation is complete by using the device
status bit DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has
been completed, the device automatically returns to reading array data.
The sector erase architecture allows memory sectors to be erased and reprogrammed without
affecting the data contents of other sectors. The device is fully erased when shipped from the
factory.
Hardware data protection measures include a low VCC detector that automatically inhibits write
operations during power transitions. The device also offers two types of data protection at the
sector level. When at VIL, WP# locks the four outermost boot sectors.
The device offers two power-saving features. When addresses have been stable for a specified
amount of time, the device enters the automatic sleep mode. The system can also place the
device into the standby mode. Power consumption is greatly reduced in both modes.
Spansion™ Flash memory products combine years of Flash memory manufacturing experience to
produce the highest levels of quality, reliability and cost effectiveness. The device electrically
erases all bits within a sector simultaneously via Fowler-Nordheim tunnelling. The data is pro-
grammed using hot electron injection.
June 24, 2005 S29WS-J_M0_A4
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D a t a S h e e t
8 Product Selector Guide
Synchronous/Burst
Asynchronous
Speed Option
80MHz
(Note)
80 MHz
(Note)
Speed Option
66 MHz
66 MHz
Max Latency, ns (tIACC
)
56
71
Max Access Time, ns (tACC
Max CE# Access, ns (tCE
Max OE# Access, ns (tOE
)
55
55
55
55
Max Burst Access Time, ns (tBACC
)
11.2
11.2
9.1
)
Max OE# Access, ns (tOE
)
9.1
)
11.2
9.1
Note: 80 MHz option is available for S29WS064J only.
9 Block Diagram
VCC
VSS
DQ15–DQ0
VSSIO
RDY
Buffer
RDY
Erase Voltage
Generator
Input/Output
Buffers
WE#
RESET#
WP#
State
Control
ACC
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
CE#
OE#
Y-Decoder
Y-Gating
VCC
Detector
Timer
Cell Matrix
X-Decoder
Burst
State
Control
Burst
Address
Counter
AVD#
CLK
Amax–A0
Amax: WS064J (A21), WS128J (A22)
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D a t a S h e e t
10 Block Diagram of Simultaneous Operation Circuit
V
V
V
CC
SS
SSIO
Bank A Address
DQ15–DQ0
Bank A
Amax–A0
X-Decoder
OE#
Bank B Address
DQ15–DQ0
Bank B
WP#
ACC
X-Decoder
Amax–A0
STATE
CONTROL
&
COMMAND
REGISTER
RESET#
WE#
DQ15–DQ0
Status
CE#
AVD#
RDY
Control
Amax–A0
DQ15–DQ0
X-Decoder
Bank C
DQ15–DQ0
Bank C Address
Amax–A0
Amax–A0
X-Decoder
Bank D
Bank D Address
DQ15–DQ0
Note: Amax: WS064J (A21), WS128J (A22)
June 24, 2005 S29WS-J_M0_A4
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27
D a t a S h e e t
11 Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated
through the internal command register. The command register itself does not occupy any addres-
sable memory location. The register is composed of latches that store the commands, along with
the address and data information needed to execute the command. The contents of the register
serve as inputs to the internal state machine. The state machine outputs dictate the function of
the device. Table 11.1 lists the device bus operations, the inputs and control levels they require,
and the resulting output. The following subsections describe each of these operations in further
detail.
Table 11.1 Device Bus Operations
CLK
(See Note)
Operation
CE#
OE#
WE#
A22–0
DQ15–0
RESET#
AVD#
Asynchronous Read - Addresses Latched
Asynchronous Read - Addresses Steady State
Asynchronous Write
L
L
L
L
H
H
L
Addr In
Addr In
Addr In
Addr In
HIGH Z
HIGH Z
I/O
I/O
H
H
H
H
H
L
X
X
X
L
L
L
H
H
X
X
I/O
Synchronous Write
L
L
I/O
Standby (CE#)
H
X
X
X
HIGH Z
HIGH Z
X
X
X
X
Hardware Reset
Burst Read Operations
Load Starting Burst Address
L
L
X
L
H
H
Addr In
HIGH Z
X
H
H
Advance Burst to next address with appropriate Data
presented on the Data Bus
Burst
Data Out
H
Terminate current Burst read cycle
H
X
X
X
H
H
HIGH Z
HIGH Z
HIGH Z
HIGH Z
H
L
X
X
Terminate current Burst read cycle via RESET#
X
Terminate current Burst read cycle and start new
Burst read cycle
L
X
H
HIGH Z
I/O
H
Legend: L = Logic 0, H = Logic 1, X = Don’t Care
Note: Default active edge of CLK is the rising edge.
11.1 Requirements for Asynchronous ReadOperation (Non-Burst)
To read data from the memory array, the system must first assert a valid address on Amax–
A0(A22-A0 for WS128J and A21-A0 for WS064J), while driving AVD# and CE# to VIL. WE# should
remain at VIH. The rising edge of AVD# latches the address. The data will appear on DQ15–DQ0.
Since the memory array is divided into four banks, each bank remains enabled for read access
until the command register contents are altered.
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The
chip enable access time (tCE) is the delay from the stable addresses and stable CE# to valid data
at the outputs. The output enable access time (tOE) is the delay from the falling edge of OE# to
valid data at the output.
The internal state machine is set for reading array data in asynchronous mode upon device
power-up, or after a hardware reset. This ensures that no spurious alteration of the memory con-
tent occurs during the power transition.
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11.2 Requirements for Synchronous (Burst) Read Operation
The device is capable of continuous sequential burst operation and linear burst operation of a pre-
set length. When the device first powers up, it is enabled for asynchronous read operation.
Prior to entering burst mode, the system should determine how many wait states are desired for
the initial word (tIACC) of each burst access, what mode of burst operation is desired, which edge
of the clock will be the active clock edge, and how the RDY signal will transition with valid data.
The system would then write the configuration register command sequence. See “Set Configura-
tion Register Command Sequence” section on page 63 and “Command Definitions” section on
page 63 for further details.
Once the system has written the “Set Configuration Register” command sequence, the device is
enabled for synchronous reads only.
The initial word is output tIACC after the active edge of the first CLK cycle. Subsequent words are
output tBACC after the active edge of each successive clock cycle, which automatically increments
the internal address counter. Note that the device has a fixed internal address boundary that oc-
curs every 64 words, starting at address 00003Fh.
During the time the device is outputting data at this fixed internal address boundary (address
00003Fh, 00007Fh, 0000BFh, etc.), a two cycle latency (66MHz) or a three cycle latency(80MHz)
occurs before data appears for the next address (address 000040h, 000080h, 0000C0h, etc.).
Additionally, when the device is read from an odd address, one wait state is inserted when the
address pointer crosses the first boundary that occurs every 16 words. For instance, if the device
is read from 000011h, 000013h, … ,00001Fh (odd), one wait state is inserted before the data of
000020h is output. This wait is inserted only at the boundary of the first 16 words. Then, if the
device is read from the odd address within the last 16 words of 64 word boundary (address
000031h,000033h, … , 00003Fh), a three-cycle latency occurs before data appears for the next
address (address 000040h). During the boundary crossing condition, the system must assert an
additional wait state for WS128J model numbers 10 and 11.
The RDY output indicates this condition to the system by pulsing deactive (low). See
Figure 22.23, “Latency with Boundary Crossing,” on page 108.
The device will continue to output sequential burst data, wrapping around to address 000000h
after it reaches the highest addressable memory location, until the system drives CE# high, RE-
SET# low, or AVD# low in conjunction with a new address. See Table 11.1, “Device Bus
Operations,” on page 28.
If the host system crosses the bank boundary while reading in burst mode, and the device is not
programming or erasing, a two-cycle latency will occur as described above in the subsequent
bank. If the host system crosses the bank boundary while the device is programming or erasing,
the device will provide read status information. The clock will be ignored. After the host has com-
pleted status reads, or the device has completed the program or erase operation, the host can
restart a burst operation using a new address and AVD# pulse.
8-, 16-, and 32-Word Linear Burst with Wrap Around
The remaining three burst read modes are of the linear wrap around design, in which a fixed num-
ber of words are read from consecutive addresses. In each of these modes, the burst addresses
read are determined by the group within which the starting address falls. The groups are sized
according to the number of words read in a single burst sequence for a given mode (see
Table 11.2.)
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D a t a S h e e t
Table 11.2 Burst Address Groups
Mode
Group Size
Group Address Ranges
0-7h, 8-Fh, 10-17h,...
0-Fh, 10-1Fh, 20-2Fh,...
00-1Fh, 20-3Fh, 40-5Fh,...
8-word
16-word
32-word
8 words
16 words
32 words
As an example: if the starting address in the 8-word mode is 39h, the address range to be read
would be 38-3Fh, and the burst sequence would be 39-3A-3B-3C-3D-3E-3F-38h-etc. The burst
sequence begins with the starting address written to the device, but wraps back to the first ad-
dress in the selected group. In a similar fashion, the 16-word and 32-word Linear Wrap modes
begin their burst sequence on the starting address written to the device, and then wrap back to
the first address in the selected address group. Note that in these three burst read modes
the address pointer does not cross the boundary that occurs every 128 or 64 words;
thus, no wait states are inserted (except during the initial access).
The RDY pin indicates when data is valid on the bus.
11.3 Configuration Register
The device uses a configuration register to set the various burst parameters: number of wait
states, burst read mode, active clock edge, RDY configuration, and synchronous mode active.
11.4 Handshaking
The device is equipped with a handshaking feature that allows the host system to simply monitor
the RDY signal from the device to determine when the initial word of burst data is ready to be
read. The host system should use the programmable wait state configuration to set the number
of wait states for optimal burst mode operation. The initial word of burst data is indicated by the
active edge of RDY after OE# goes low.
For optimal burst mode performance, the host system must set the appropriate number of wait
states in the flash device depending on clock frequency. See “Set Configuration Register Com-
mand Sequence” section on page 63 for more information.
11.5 Simultaneous Read/Write Operations with Zero Latency
This device is capable of reading data from one bank of memory while programming or erasing
in another bank of memory. An erase operation may also be suspended to read from or program
to another location within the same bank (except the sector being erased). Figure 22.26, “Back-
to-Back Read/Write Cycle Timings,” on page 111 shows how read and write cycles may be initi-
ated for simultaneous operation with zero latency. Refer to the DC Characteristics table for read-
while-program and read-while-erase current specifications.
11.6 Writing Commands/Command Sequences
The device has the capability of performing an asynchronous or synchronous write operation.
While the device is configured in Asynchronous read mode, it is able to perform Asynchronous
write operations only. CLK is ignored in the Asynchronous programming mode. When in the Syn-
chronous read mode configuration, the device is able to perform both Asynchronous and
Synchronous write operations. CLK and WE# address latch is supported in the Synchronous pro-
gramming mode. During a synchronous write operation, to write a command or command
sequence (which includes programming data to the device and erasing sectors of memory), the
system must drive AVD# and CE# to VIL, and OE# to VIH when providing an address to the de-
vice, and drive WE# and CE# to VIL, and OE# to VIH. when writing commands or data. During an
asynchronous write operation, the system must drive CE# and WE# to VIL and OE# to VIH when
30
S29WS128J/064J
S29WS-J_M0_A4 June 24, 2005
D a t a S h e e t
providing an address, command, and data. Addresses are latched on the last falling edge of WE#
or CE#, while data is latched on the 1st rising edge of WE# or CE#. The asynchronous and syn-
chronous programing operation is independent of the Set Device Read Mode bit in the
Configuration Register (see Table 14.4, “Configuration Register,” on page 67).
The device features an Unlock Bypass mode to facilitate faster programming. Once the device en-
ters the Unlock Bypass mode, only two write cycles are required to program a word, instead of
four.
An erase operation can erase one sector, multiple sectors, or the entire device. Table 13.5,
“WS128J Sector Address Table,” on page 49 and Table 13.6, “WS064J Sector Address Table,” on
page 57 indicate the address space that each sector occupies. The device address space is divided
into four banks. A “bank address” is the address bits required to uniquely select a bank. Similarly,
a “sector address” is the address bits required to uniquely select a sector.
ICC2 in the “DC Characteristics” section on page 89 represents the active current specification for
the write mode. The AC Characteristics section contains timing specification tables and timing di-
agrams for write operations.
11.7 Accelerated Program Operation
The device offers accelerated program operations through the ACC function. ACC is primarily in-
tended to allow faster manufacturing throughput at the factory.
If the system asserts VHH on this input, the device automatically enters the aforementioned Un-
lock Bypass mode and uses the higher voltage on the input to reduce the time required for
program operations. The system would use a two-cycle program command sequence as required
by the Unlock Bypass mode. Removing VHH from the ACC input returns the device to normal op-
eration. Note that sectors must be unlocked prior to raising ACC to VHH. Note that the ACC pin
must not be at VHH for operations other than accelerated programming, or device damage may
result. In addition, the ACC pin must not be left floating or unconnected; inconsistent behavior of
the device may result.
When at VIL, ACC locks all sectors. ACC should be at VIH for all other conditions.
11.8 Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection ver-
ification, through identifier codes output from the internal register (which is separate from the
memory array) on DQ15–DQ0. This mode is primarily intended for programming equipment to
automatically match a device to be programmed with its corresponding programming algorithm.
However, the autoselect codes can also be accessed in-system through the command register.
When using programming equipment, the autoselect mode requires VID on address pin A9. Ad-
dress pins must be as shown in Table 11.3, “Autoselect Codes (High Voltage Method),” on
page 32. In addition, when verifying sector protection, the sector address must appear on the
appropriate highest order address bits (see Table , “,” on page 33 and Table , “,” on page 35).
Table 11.3 shows the remaining address bits that are don’t care. When all necessary bits have
been set as required, the programming equipment may then read the corresponding identifier
code on DQ15–DQ0. However, the autoselect codes can also be accessed in-system through the
command register, for instances when the device is erased or programmed in a system without
access to high voltage on the A9 pin. The command sequence is illustrated in Table 14.5, “Com-
mand Definitions,” on page 77. Note that if a Bank Address (BA) on address bits A22, A21, and
A20 for the WS128J (A21:A19 for the WS064J) is asserted during the third write cycle of the au-
toselect command, the host system can read autoselect data that bank and then immediately
read array data from the other bank, without exiting the autoselect mode.
June 24, 2005 S29WS-J_M0_A4
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D a t a S h e e t
To access the autoselect codes in-system, the host system can issue the autoselect command
via the command register, as shown in Table 14.5, “Command Definitions,” on page 77. This
method does not require VID. Autoselect mode may only be entered and used when in the asyn-
chronous read mode. Refer to the “Autoselect Command Sequence” section on page 68 for more
information.
Table 11.3 Autoselect Codes (High Voltage Method)
Amax A11
A5
to
to
to
DQ15
to DQ0
Description
CE# OE# WE# RESET#
A12
A10 A9 A8 A7 A6 A4 A3 A2 A1 A0
Manufacturer ID
Spansion
:
VID
VID
VID
L
L
L
L
L
L
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
L
L
L
L
L
X
L
L
L
L
L
L
L
L
L
H
L
0001h
227Eh
Read Cycle 1
Read Cycle 2
2218h (WS128J)
221Eh (WS064J)
H
H
H
2200h (WS128J)
2201h (WS064J)
Read Cycle 3
H
L
H
L
H
H
H
L
Sector Protection
Verification
0001h (protected),
0000h (unprotected)
SA
DQ15 - DQ8 = 0
DQ7 - Factory Lock Bit
1 = Locked, 0 = Not Locked
DQ6 -Customer Lock Bit
1 = Locked, 0 = Not Locked
DQ5 = Handshake Bit
1 = Reserved, 0 = Standard
Handshake
VID
Indicator Bits
L
L
L
L
H
H
H
H
X
X
X
X
X
X
X
L
X
L
L
L
L
L
H
H
H
L
DQ4 & DQ3 - Boot Code
DQ2 - DQ0 = 001
Hardware Sector Group
Protection
0001h (protected),
0000h (unprotected)
VID
SA
X
Legend: L = Logic Low = V , H = Logic High = V , BA = Bank Address, SA = Sector Address, X = Don’t care.
IL
IH
Notes:
1. The autoselect codes may also be accessed in-system via command sequences.
2. PPB Protection Status is shown on the data bus
11.9 Sector/Sector Block Protection and Unprotection
The hardware sector protection feature disables both programming and erase operations in any
sector. The hardware sector unprotection feature re-enables both program and erase operations
in previously protected sectors. Sector protection/unprotection can be implemented via two
methods.
(Note: For the following discussion, the term “sector” applies to both sectors and sector blocks.
A sector block consists of two or more adjacent sectors that are protected or unprotected at the
same time (see Table , “,” on page 33 and Table , “,” on page 35).)
32
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D a t a S h e e t
Table 11.4 S29WS128J/064J Boot Sector/Sector Block Addresses for Protection/Unprotection (Sheet 1 of 3)
Sector/
Sector
SA0
A22–A12
Sector Block Size
00000000000
00000000001
00000000010
00000000011
00000000100
00000000101
00000000110
00000000111
00000001XXX,
00000010XXX,
00000011XXX,
000001XXXXX
000010XXXXX
000011XXXXX
000100XXXXX
000101XXXXX
000110XXXXX
000111XXXXX
001000XXXXX
001001XXXXX
001010XXXXX
001011XXXXX
001100XXXXX
001101XXXXX
001110XXXXX
001111XXXXX
010000XXXXX
010001XXXXX
010010XXXXX
010011XXXXX
010100XXXXX
010101XXXXX
010110XXXXX
010111XXXXX
011000XXXXX
011001XXXXX
011010XXXXX
011011XXXXX
011100XXXXX
4 Kwords
SA1
4 Kwords
SA2
4 Kwords
SA3
4 Kwords
SA4
4 Kwords
SA5
4 Kwords
SA6
4 Kwords
SA7
4 Kwords
SA8
32 Kwords
SA9
32 Kwords
SA10
32 Kwords
SA11–SA14
SA15–SA18
SA19–SA22
SA23-SA26
SA27-SA30
SA31-SA34
SA35-SA38
SA39-SA42
SA43-SA46
SA47-SA50
SA51–SA54
SA55–SA58
SA59–SA62
SA63–SA66
SA67–SA70
SA71–SA74
SA75–SA78
SA79–SA82
SA83–SA86
SA87–SA90
SA91–SA94
SA95–SA98
SA99–SA102
SA103–SA106
SA107–SA110
SA111–SA114
SA115–SA118
SA119–SA122
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
June 24, 2005 S29WS-J_M0_A4
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33
D a t a S h e e t
Table 11.4 S29WS128J/064J Boot Sector/Sector Block Addresses for Protection/Unprotection (Sheet 2 of 3)
Sector/
Sector
A22–A12
Sector Block Size
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
32 Kwords
SA123–SA126
SA127–SA130
SA131-SA134
SA135-SA138
SA139-SA142
SA143-SA146
SA147-SA150
SA151–SA154
SA155–SA158
SA159–SA162
SA163–SA166
SA167–SA170
SA171–SA174
SA175–SA178
SA179–SA182
SA183–SA186
SA187–SA190
SA191–SA194
SA195–SA198
SA199–SA202
SA203–SA206
SA207–SA210
SA211–SA214
SA215–SA218
SA219–SA222
SA223–SA226
SA227–SA230
SA231–SA234
SA235–SA238
SA239–SA242
SA243–SA246
SA247–SA250
SA251–SA254
SA255–SA258
SA259
011101XXXXX
011110XXXXX
011111XXXXX
100000XXXXX
100001XXXXX
100010XXXXX
100011XXXXX
100100XXXXX
100101XXXXX
100110XXXXX
100111XXXXX
101000XXXXX
101001XXXXX
101010XXXXX
101011XXXXX
101100XXXXX
101101XXXXX
101110XXXXX
101111XXXXX
110000XXXXX
110001XXXXX
110010XXXXX
110011XXXXX
110100XXXXX
110101XXXXX
110110XXXXX
110111XXXXX
111000XXXXX
111001XXXXX
111010XXXXX
111011XXXXX
111100XXXXX
111101XXXXX
111110XXXXX
11111100XXX
11111101XXX
11111110XXX
11111111000
11111111001
SA260
32 Kwords
SA261
32 Kwords
SA262
4 Kwords
SA263
4 Kwords
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Table 11.4 S29WS128J/064J Boot Sector/Sector Block Addresses for Protection/Unprotection (Sheet 3 of 3)
Sector/
Sector
SA264
SA265
SA266
SA267
SA268
SA269
A22–A12
Sector Block Size
11111111010
11111111011
11111111100
11111111101
11111111110
11111111111
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
Table 11.5 S29WS064J Boot Sector/Sector Block Addresses for Protection/Unprotection (Sheet 1 of 2)
Sector/
Sector
SA0
A21–A12
Sector Block Size
0000000000
0000000001
0000000010
0000000011
0000000100
0000000101
0000000110
0000000111
0000001XXX
0000010XXX
0000011XXX
00001XXXXX
00010XXXXX
00011XXXXX
00100XXXXX
00101XXXXX
00110XXXXX
00111XXXXX
01000XXXXX
01001XXXXX
01010XXXXX
01011XXXXX
01100XXXXX
01101XXXXX
01110XXXXX
01111XXXXX
10000XXXXX
10001XXXXX
10010XXXXX
4 Kwords
SA1
4 Kwords
SA2
4 Kwords
SA3
4 Kwords
SA4
4 Kwords
SA5
4 Kwords
SA6
4 Kwords
SA7
4 Kwords
SA8
32 Kwords
SA9
32 Kwords
SA10
32 Kwords
SA11–SA14
SA15–SA18
SA19–SA22
SA23-SA26
SA27-SA30
SA31-SA34
SA35-SA38
SA39-SA42
SA43-SA46
SA47-SA50
SA51–SA54
SA55–SA58
SA59–SA62
SA63–SA66
SA67–SA70
SA71–SA74
SA75–SA78
SA79–SA82
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
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D a t a S h e e t
Table 11.5 S29WS064J Boot Sector/Sector Block Addresses for Protection/Unprotection (Sheet 2 of 2)
Sector/
Sector
SA83–SA86
SA87–SA90
SA91–SA94
SA95–SA98
SA99–SA102
SA103–SA106
SA107–SA110
SA111–SA114
SA115–SA118
SA119–SA122
SA123–SA126
SA127–SA130
SA131
A21–A12
Sector Block Size
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
32 Kwords
10011XXXXX
10100XXXXX
10101XXXXX
10110XXXXX
10111XXXXX
11000XXXXX
11001XXXXX
11010XXXXX
11011XXXXX
11100XXXXX
11101XXXXX
11110XXXXX
1111100XXX
1111101XXX
1111110XXX
1111111000
1111111001
1111111010
1111111011
1111111100
1111111101
1111111110
1111111111
SA132
32 Kwords
SA133
32 Kwords
SA134
4 Kwords
SA135
4 Kwords
SA136
4 Kwords
SA137
4 Kwords
SA138
4 Kwords
SA139
4 Kwords
SA140
4 Kwords
SA141
4 Kwords
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12 Advanced Sector Protection/Unprotection
The Advanced Sector Protection/Unprotection feature disables or enables programming or erase
operations in any or all sectors and can be implemented through software and/or hardware meth-
ods, which are independent of each other. This section describes the various methods of
protecting data stored in the memory array. An overview of these methods in shown in Figure
12.1.
Hardware Methods
Software Methods
Lock Register
(One Time Programmable)
ACC = V
IL
All sectors locked)
Persistent Method
Password Method
(
(DQ1)
(DQ2)
WP# = V
IL
(All boot
sectors locked)
64-bit Password
(One Time Protect)
1. Bit is volatile, and defaults to “1” on
reset.
PPB Lock Bit1,2,3
2. Programming to “0” locks all PPBs to
their current state.
0 = PPBs Locked
1 = PPBs Unlocked
3. Once programmed to “0”, requires
hardware reset to unlock.
Persistent
Protection Bit
(PPB)4,5
Dynamic
Protection Bit
(PPB)6,7,8
Memory Array
Sector 0
Sector 1
Sector 2
PPB 0
PPB 1
PPB 2
DYB 0
DYB 1
DYB 2
Sector N-2
Sector N-1
PPB N-2
PPB N-1
PPB N
DYB N-2
DYB N-1
DYB N
Sector N3
3. N = Highest Address Sector.
4. 0 = Sector Protected,
1 = Sector Unprotected.
6. 0 = Sector Protected,
1 = Sector Unprotected.
5. PPBs programmed individually,
but cleared collectively
7. Protect effective only if PPB Lock Bit
is unlocked and corresponding PPB
is “1” (unprotected).
8. Volatile Bits: defaults to user choice
upon power-up (see ordering
options).
Figure 12.1 Advanced Sector Protection/Unprotection
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12.1 Lock Register
As shipped from the factory, all devices default to the persistent mode when power is applied, and
all sectors are unprotected, unless otherwise chosen through the DYB ordering option. The device
programmer or host system must then choose which sector protection method to use. Program-
ming (setting to “0”) any one of the following two one-time programmable, non-volatile bits locks
the part permanently in that mode:
!
!
Lock Register Persistent Protection Mode Lock Bit (DQ1)
Lock Register Password Protection Mode Lock Bit (DQ2)
Table 12.1 Lock Register
Device
DQ15-05
DQ4
DQ3
DQ2
DQ1
DQ0
Password
Protection
Mode Lock Bit
Persistent
Protection
Mode Lock Bit
Customer
SecSi Sector
Protection Bit
S29WS256N
1
1
1
DYB Lock Boot Bit
0 = sectors
power up
PPB One-Time
Programmable Bit
0 = All PPB erase
command disabled
1 = All PPB Erase
command enabled
Password
Protection
Mode Lock Bit
Persistent
Protection
Mode Lock Bit
S29WS128N/
S29WS064N
SecSi Sector
Protection Bit
Undefined
protected
1 = sectors
power up
unprotected
Notes
1. If the password mode is chosen, the password must be programmed before setting the cor-
responding lock register bit.
2. After the Lock Register Bits Command Set Entry command sequence is written, reads and
writes for Bank 0 are disabled, while reads from other banks are allowed until exiting this
mode.
3. If both lock bits are selected to be programmed (to zeros) at the same time, the operation
aborts.
4. Once the Password Mode Lock Bit is programmed, the Persistent Mode Lock Bit is permanently
disabled, and no changes to the protection scheme are allowed. Similarly, if the Persistent
Mode Lock Bit is programmed, the Password Mode is permanently disabled.
After selecting a sector protection method, each sector can operate in any of the following three
states:
1. Constantly locked. The selected sectors are protected and can not be reprogrammed unless
PPB lock bit is cleared via a password, hardware reset, or power cycle.
2. Dynamically locked. The selected sectors are protected and can be altered via software com-
mands.
3. Unlocked. The sectors are unprotected and can be erased and/or programmed.
These states are controlled by the bit types described in Sections 12.2–12.6.
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12.2 Persistent Protection Bits
The Persistent Protection Bits are unique and nonvolatile for each sector and have the same en-
durances as the Flash memory. Preprogramming and verification prior to erasure are handled by
the device, and therefore do not require system monitoring.
Notes
1. Each PPB is individually programmed and all are erased in parallel.
2. While programming PPB for a sector, array data can be read from any other bank, except Bank
0 (used for Data# Polling) and the bank in which sector PPB is being programmed.
3. Entry command disables reads and writes for the bank selected.
4. Reads within that bank return the PPB status for that sector.
5. Reads from other banks are allowed while writes are not allowed.
6. All Reads must be performed using the Asynchronous mode.
7. The specific sector address (A23-A14 WS256N, A22-A14 WS128N, A21-A14 WS064N) are
written at the same time as the program command.
8. If the PPB Lock Bit is set, the PPB Program or erase command does not execute and times-
out without programming or erasing the PPB.
9. There are no means for individually erasing a specific PPB and no specific sector address is
required for this operation.
10.Exit command must be issued after the execution which resets the device to read mode and
re-enables reads and writes for Bank 0
11.The programming state of the PPB for a given sector can be verified by writing a PPB Status
Read Command to the device as described by the flow chart shown in Figure 12.2.
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D a t a S h e e t
Enter PPB
Command Set.
Addr = BA
Program PPB Bit.
Addr = SA
Read Byte Twice
Addr = SA0
No
DQ6 =
Toggle?
Yes
No
DQ5 = 1?
Yes
Wait 500 µs
Read Byte Twice
Addr = SA0
No
Read Byte.
Addr = SA
DQ6 =
Toggle?
Yes
DQ0 =
No
'1' (Erase)
'0' (Pgm.)?
FAIL
Yes
Issue Reset
Command
PASS
Exit PPB
Command Set
Figure 12.2 PPB Program/Erase Algorithm
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12.3 Dynamic Protection Bits
Dynamic Protection Bits are volatile and unique for each sector and can be individually modified.
DYBs only control the protection scheme for unprotected sectors that have their PPBs cleared
(erased to “1”). By issuing the DYB Set or Clear command sequences, the DYBs are set (pro-
grammed to “0”) or cleared (erased to “1”), thus placing each sector in the protected or
unprotected state respectively. This feature allows software to easily protect sectors against in-
advertent changes yet does not prevent the easy removal of protection when changes are
needed.
Notes
1. The DYBs can be set (programmed to “0”) or cleared (erased to “1”) as often as needed.
When the parts are first shipped, the PPBs are cleared (erased to “1”) and upon power up or reset,
the DYBs can be set or cleared depending upon the ordering option chosen.
2. If the option to clear the DYBs after power up is chosen, (erased to “1”), then the sectorsmay
be modified depending upon the PPB state of that sector (see Table 12.2).
3. The sectors would be in the protected state If the option to set the DYBs after power up is
chosen (programmed to “0”).
4. It is possible to have sectors that are persistently locked with sectors that are left in the dy-
namic state.
5. The DYB Set or Clear commands for the dynamic sectors signify protected or unprotected
state of the sectors respectively. However, if there is a need to change the status of the per-
sistently locked sectors, a few more steps are required. First, the PPB Lock Bit must be
cleared by either putting the device through a power-cycle, or hardware reset. The PPBs can
then be changed to reflect the desired settings. Setting the PPB Lock Bit once again locks the
PPBs, and the device operates normally again.
6. To achieve the best protection, it is recommended to execute the PPB Lock Bit Set command
early in the boot code and protect the boot code by holding WP# = VIL. Note that the PPB
and DYB bits have the same function when ACC = VHH as they do when ACC =VIH
.
12.4 Persistent Protection Bit Lock Bit
The Persistent Protection Bit Lock Bit is a global volatile bit for all sectors. When set (programmed
to “0”), it locks all PPBs and when cleared (programmed to “1”), allows the PPBs to be changed.
There is only one PPB Lock Bit per device.
Notes
1. No software command sequence unlocks this bit unless the device is in the password protec-
tion mode; only a hardware reset or a power-up clears this bit.
2. The PPB Lock Bit must be set (programmed to “0”) only after all PPBs are configured to the
desired settings.
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D a t a S h e e t
12.5 Password Protection Method
The Password Protection Method allows an even higher level of security than the Persistent Sector
Protection Mode by requiring a 64 bit password for unlocking the device PPB Lock Bit. In addition
to this password requirement, after power up and reset, the PPB Lock Bit is set “0” to maintain
the password mode of operation. Successful execution of the Password Unlock command by en-
tering the entire password clears the PPB Lock Bit, allowing for sector PPBs modifications.
Notes
1. There is no special addressing order required for programming the password. Once the Pass-
word is written and verified, the Password Mode Locking Bit must be set in order to prevent
access.
2. The Password Program Command is only capable of programming “0”s. Programming a “1”
after a cell is programmed as a “0” results in a time-out with the cell as a “0”.
3. The password is all “1”s when shipped from the factory.
4. All 64-bit password combinations are valid as a password.
5. There is no means to verify what the password is after it is set.
6. The Password Mode Lock Bit, once set, prevents reading the 64-bit password on the data bus
and further password programming.
7. The Password Mode Lock Bit is not erasable.
8. The lower two address bits (A1–A0) are valid during the Password Read, Password Program,
and Password Unlock.
9. The exact password must be entered in order for the unlocking function to occur.
10.The Password Unlock command cannot be issued any faster than 1 µs at a time to prevent a
hacker from running through all the 64-bit combinations in an attempt to correctly match a
password.
11.Approximately 1 µs is required for unlocking the device after the valid 64-bit password is
given to the device.
12.Password verification is only allowed during the password programming operation.
13.All further commands to the password region are disabled and all operations are ignored.
14.If the password is lost after setting the Password Mode Lock Bit, there is no way to clear the
PPB Lock Bit.
15.Entry command sequence must be issued prior to any of any operation and it disables reads
and writes for Bank 0. Reads and writes for other banks excluding Bank 0 are allowed.
16.If the user attempts to program or erase a protected sector, the device ignores the command
and returns to read mode.
17.A program or erase command to a protected sector enables status polling and returns to read
mode without having modified the contents of the protected sector.
18.The programming of the DYB, PPB, and PPB Lock for a given sector can be verified by writing
individual status read commands DYB Status, PPB Status, and PPB Lock Status to the device.
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Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write
Enter Lock Register Command:
Address 555h, Data 40h
XXXh = Address don’t care
* Not on future devices
Program Lock Register Data
Address XXXh, Data A0h
Address 77h*, Data PD
Program Data (PD): See text for Lock Register
definitions
Caution: Lock register can only be progammed
once.
Wait 4 µs
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Yes
Done?
No
No
DQ5 = 1?
Yes
Error condition (Exceeded Timing Limits)
PASS. Write Lock Register
Exit Command:
FAIL. Write rest command
to return to reading array.
Address XXXh, Data 90h
Address XXXh, Data 00h
Device returns to reading array.
Figure 12.3 Lock Register Program Algorithm
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D a t a S h e e t
12.6 Advanced Sector Protection Software Examples
Table 12.2 Sector Protection Schemes
Unique Device PPB Lock Bit
0 = locked
Sector PPB
0 = protected
1 = unprotected
Sector DYB
0 = protected
1 = unprotected
Sector Protection Status
1 = unlocked
Any Sector
Any Sector
Any Sector
Any Sector
Any Sector
Any Sector
Any Sector
Any Sector
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
x
x
1
0
x
x
0
1
Protected through PPB
Protected through PPB
Unprotected
Protected through DYB
Protected through PPB
Protected through PPB
Protected through DYB
Unprotected
Table 12.2 contains all possible combinations of the DYB, PPB, and PPB Lock Bit relating to the
status of the sector. In summary, if the PPB Lock Bit is locked (set to “0”), no changes to the PPBs
are allowed. The PPB Lock Bit can only be unlocked (reset to “1”) through a hardware reset or
power cycle. See also Figure 12.1 for an overview of the Advanced Sector Protection feature.
12.7 Hardware Data Protection Methods
The device offers two main types of data protection at the sector level via hardware control:
!
!
When WP# is at VIL, the four outermost sectors are locked (device specific).
When ACC is at VIL, all sectors are locked.
There are additional methods by which intended or accidental erasure of any sectors can be pre-
vented via hardware means. The following subsections describes these methods:
WP# Method
The Write Protect feature provides a hardware method of protecting the four outermost sectors.
This function is provided by the WP# pin and overrides the previously discussed Sector Protec-
tion/Unprotection method.
If the system asserts VIL on the WP# pin, the device disables program and erase functions in the
“outermost” boot sectors. The outermost boot sectors are the sectors containing both the lower
and upper set of sectors in a dual-boot-configured device.
If the system asserts VIH on the WP# pin, the device reverts to whether the boot sectors were
last set to be protected or unprotected. That is, sector protection or unprotection for these sectors
depends on whether they were last protected or unprotected.
Note that the WP# pin must not be left floating or unconnected as inconsistent behavior of the
device may result.
The WP# pin must be held stable during a command sequence execution
ACC Method
This method is similar to above, except it protects all sectors. Once ACC input is set to VIL, all
program and erase functions are disabled and hence all sectors are protected.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during
VCC power-up and power-down.
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The command register and all internal program/erase circuits are disabled, and the device resets
to reading array data. Subsequent writes are ignored until VCC is greater than VLKO. The system
must provide the proper signals to the control inputs to prevent unintentional writes when VCC is
greater than VLKO
.
Write Pulse “Glitch Protection”
Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Power-Up Write Inhibit
If WE# = CE# = RESET# = VIL and OE# = VIH during power up, the device does not accept com-
mands on the rising edge of WE#. The internal state machine is automatically reset to the read
mode on power-up.
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13 Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system software inter-
rogation handshake, which allows specific vendor-specified software algorithms to be used for
entire families of devices. Software support can then be device-independent, JEDEC ID-indepen-
dent, and forward- and backward-compatible for the specified flash device families. Flash vendors
can standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to
address 55h any time the device is ready to read array data. The system can read CFI information
at the addresses given in Tables 13.1-13.4. To terminate reading CFI data, the system must write
the reset command.
The system can also write the CFI query command when the device is in the autoselect mode.
The device enters the CFI query mode, and the system can read CFI data at the addresses given
in Tables 13.1-13.4. The system must write the reset command to return the device to the au-
toselect mode.
Table 13.1 CFI Query Identification String
Addresses
Data
Description
10h
11h
12h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
0002h
0000h
Primary OEM Command Set
15h
16h
0040h
0000h
Address for Primary Extended Table
17h
18h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
19h
1Ah
0000h
0000h
Address for Alternate OEM Extended Table (00h = none exists)
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Table 13.2 System Interface String
Addresses
Data
Description
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Bh
0017h
VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch
0019h
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
0000h
0000h
0003h
0000h
0009h
0000h
0004h
0000h
0004h
0000h
VPP Min. voltage (00h = no VPP pin present)
VPP Max. voltage (00h = no VPP pin present)
Typical timeout per single byte/word write 2N µs
Typical timeout for Min. size buffer write 2N
µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for byte/word write 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 13.3 Device Geometry Definition
Addresses
Data
Description
0018h (WS128J)
0017h (WS064J)
27h
Device Size = 2N byte
28h
29h
0001h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
0000h
0000h
Max. number of bytes in multi-byte write = 2N
(00h = not supported)
2Ch
0003h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
0007h
0000h
0020h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
00FDh (WS128J)
007Dh (WS064J)
31h
Erase Block Region 2 Information
32h
33h
34h
0000h
0000h
0001h
35h
36h
37h
38h
0007h
0000h
0020h
0000h
Erase Block Region 3 Information
Erase Block Region 4 Information
39h
3Ah
3Bh
3Ch
0000h
0000h
0000h
0000h
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D a t a S h e e t
Table 13.4 Primary Vendor-Specific Extended Query
Addresses
Data
Description
40h
41h
42h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
44h
0031h
0033h
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
45h
000Ch
Silicon Technology (Bits 5-2) 0011 = 0.13 µm
Erase Suspend
46h
47h
48h
49h
0002h
0001h
0001h
0007h
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
07 = Advanced Sector Protection
00E7h (WS128J)
0077h (WS064J)
Simultaneous Operation
Number of Sectors in all banks except boot block
4Ah
Burst Mode Type
00 = Not Supported, 01 = Supported
4Bh
4Ch
0001h
0000h
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page, 04 = 16 Word Page
ACC (Acceleration) Supply Minimum
4Dh
4Eh
4Fh
00B5h
00C5h
0001h
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
01h = Dual Boot Device, 02h = Bottom Boot Device, 03h = Top Boot Device
50h
57h
0000h
0004h
Program Suspend. 00h = not supported
Bank Organization: X = Number of banks
0027h (WS128J)
0017h (WS064J)
58h
59h
5Ah
5Bh
Bank A Region Information. X = Number of sectors in bank
Bank B Region Information. X = Number of sectors in bank
Bank C Region Information. X = Number of sectors in bank
Bank D Region Information. X = Number of sectors in bank
0060h (WS128J)
0030h (WS064J)
0060h (WS128J)
0030h (WS064J)
0027h (WS128J)
0017h (WS064J)
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D a t a S h e e t
Table 13.5 WS128J Sector Address Table (Sheet 1 of 8)
Bank
Sector
Sector Size
4 Kwords
(x16) Address Range
000000h-000FFFh
001000h-001FFFh
002000h-002FFFh
003000h-003FFFh
004000h-004FFFh
005000h-005FFFh
006000h-006FFFh
007000h-007FFFh
008000h-00FFFFh
010000h-017FFFh
018000h-01FFFFh
020000h-027FFFh
028000h-02FFFFh
030000h-037FFFh
038000h-03FFFFh
040000h-047FFFh
048000h-04FFFFh
050000h-057FFFh
058000h-05FFFFh
060000h-067FFFh
068000h-06FFFFh
070000h-077FFFh
078000h-07FFFFh
080000h-087FFFh
088000h-08FFFFh
090000h-097FFFh
098000h-09FFFFh
0A0000h-0A7FFFh
0A8000h-0AFFFFh
0B0000h-0B7FFFh
0B8000h-0BFFFFh
0C0000h-0C7FFFh
0C8000h-0CFFFFh
0D0000h-0D7FFFh
0D8000h-0DFFFFh
0E0000h-0E7FFFh
0E8000h-0EFFFFh
0F0000h-0F7FFFh
0F8000h-0FFFFFh
SA0
SA1
4 Kwords
SA2
4 Kwords
SA3
4 Kwords
SA4
4 Kwords
SA5
4 Kwords
SA6
4 Kwords
SA7
4 Kwords
SA8
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
Bank D
June 24, 2005 S29WS-J_M0_A4
S29WS128J/064J
49
D a t a S h e e t
Table 13.5 WS128J Sector Address Table (Sheet 2 of 8)
Bank
Sector
Sector Size
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
(x16) Address Range
100000h-107FFFh
108000h-10FFFFh
110000h-117FFFh
118000h-11FFFFh
120000h-127FFFh
128000h-12FFFFh
130000h-137FFFh
138000h-13FFFFh
140000h-147FFFh
148000h-14FFFFh
150000h-157FFFh
158000h-15FFFFh
160000h-167FFFh
168000h-16FFFFh
170000h-177FFFh
178000h-17FFFFh
180000h-187FFFh
188000h-18FFFFh
190000h-197FFFh
198000h-19FFFFh
1A0000h-1A7FFFh
1A8000h-1AFFFFh
1B0000h-1B7FFFh
1B8000h-1BFFFFh
1C0000h-1C7FFFh
1C8000h-1CFFFFh
1D0000h-1D7FFFh
1D8000h-1DFFFFh
1E0000h-1E7FFFh
1E8000h-1EFFFFh
1F0000h-1F7FFFh
1F8000h-1FFFFFh
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
Bank C
50
S29WS128J/064J
S29WS-J_M0_A4 June 24, 2005
D a t a S h e e t
Table 13.5 WS128J Sector Address Table (Sheet 3 of 8)
Bank
Sector
Sector Size
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
(x16) Address Range
200000h-207FFFh
208000h-20FFFFh
210000h-217FFFh
218000h-21FFFFh
220000h-227FFFh
228000h-22FFFFh
230000h-237FFFh
238000h-23FFFFh
240000h-247FFFh
248000h-24FFFFh
250000h-257FFFh
258000h-25FFFFh
260000h-267FFFh
268000h-26FFFFh
270000h-277FFFh
278000h-27FFFFh
280000h-287FFFh
288000h-28FFFFh
290000h-297FFFh
298000h-29FFFFh
2A0000h-2A7FFFh
2A8000h-2AFFFFh
2B0000h-2B7FFFh
2B8000h-2BFFFFh
2C0000h-2C7FFFh
2C8000h-2CFFFFh
2D0000h-2D7FFFh
2D8000h-2DFFFFh
2E0000h-2E7FFFh
2E8000h-2EFFFFh
2F0000h-2F7FFFh
2F8000h-2FFFFFh
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
Bank C
June 24, 2005 S29WS-J_M0_A4
S29WS128J/064J
51
D a t a S h e e t
Table 13.5 WS128J Sector Address Table (Sheet 4 of 8)
Bank
Sector
Sector Size
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
(x16) Address Range
300000h-307FFFh
308000h-30FFFFh
310000h-317FFFh
318000h-31FFFFh
320000h-327FFFh
328000h-32FFFFh
330000h-337FFFh
338000h-33FFFFh
340000h-347FFFh
348000h-34FFFFh
350000h-357FFFh
358000h-35FFFFh
360000h-367FFFh
368000h-36FFFFh
370000h-377FFFh
378000h-37FFFFh
380000h-387FFFh
388000h-38FFFFh
390000h-397FFFh
398000h-39FFFFh
3A0000h-3A7FFFh
3A8000h-3AFFFFh
3B0000h-3B7FFFh
3B8000h-3BFFFFh
3C0000h-3C7FFFh
3C8000h-3CFFFFh
3D0000h-3D7FFFh
3D8000h-3DFFFFh
3E0000h-3E7FFFh
3E8000h-3EFFFFh
3F0000h-3F7FFFh
3F8000h-3FFFFFh
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
Bank C
52
S29WS128J/064J
S29WS-J_M0_A4 June 24, 2005
D a t a S h e e t
Table 13.5 WS128J Sector Address Table (Sheet 5 of 8)
Bank
Sector
Sector Size
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
(x16) Address Range
400000h-407FFFh
408000h-40FFFFh
410000h-417FFFh
418000h-41FFFFh
420000h-427FFFh
428000h-42FFFFh
430000h-437FFFh
438000h-43FFFFh
440000h-447FFFh
448000h-44FFFFh
450000h-457FFFh
458000h-45FFFFh
460000h-467FFFh
468000h-46FFFFh
470000h-477FFFh
478000h-47FFFFh
480000h-487FFFh
488000h-48FFFFh
490000h-497FFFh
498000h-49FFFFh
4A0000h-4A7FFFh
4A8000h-4AFFFFh
4B0000h-4B7FFFh
4B8000h-4BFFFFh
4C0000h-4C7FFFh
4C8000h-4CFFFFh
4D0000h-4D7FFFh
4D8000h-4DFFFFh
4E0000h-4E7FFFh
4E8000h-4EFFFFh
4F0000h-4F7FFFh
4F8000h-4FFFFFh
SA135
SA136
SA137
SA138
SA139
SA140
SA141
SA142
SA143
SA144
SA145
SA146
SA147
SA148
SA149
SA150
SA151
SA152
SA153
SA154
SA155
SA156
SA157
SA158
SA159
SA160
SA161
SA162
SA163
SA164
SA165
SA166
Bank B
June 24, 2005 S29WS-J_M0_A4
S29WS128J/064J
53
D a t a S h e e t
Table 13.5 WS128J Sector Address Table (Sheet 6 of 8)
Bank
Sector
Sector Size
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
(x16) Address Range
500000h-507FFFh
508000h-50FFFFh
510000h-517FFFh
518000h-51FFFFh
520000h-527FFFh
528000h-52FFFFh
530000h-537FFFh
538000h-53FFFFh
540000h-547FFFh
548000h-54FFFFh
550000h-557FFFh
558000h-55FFFFh
560000h-567FFFh
568000h-56FFFFh
570000h-577FFFh
578000h-57FFFFh
580000h-587FFFh
588000h-58FFFFh
590000h-597FFFh
598000h-59FFFFh
5A0000h-5A7FFFh
5A8000h-5AFFFFh
5B0000h-5B7FFFh
5B8000h-5BFFFFh
5C0000h-5C7FFFh
5C8000h-5CFFFFh
5D0000h-5D7FFFh
5D8000h-5DFFFFh
5E0000h-5E7FFFh
5E8000h-5EFFFFh
5F0000h-5F7FFFh
5F8000h-5FFFFFh
SA167
SA168
SA169
SA170
SA171
SA172
SA173
SA174
SA175
SA176
SA177
SA178
SA179
SA180
SA181
SA182
SA183
SA184
SA185
SA186
SA187
SA188
SA189
SA190
SA191
SA192
SA193
SA194
SA195
SA196
SA197
SA198
Bank B
54
S29WS128J/064J
S29WS-J_M0_A4 June 24, 2005
D a t a S h e e t
Table 13.5 WS128J Sector Address Table (Sheet 7 of 8)
Bank
Sector
Sector Size
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
(x16) Address Range
600000h-607FFFh
608000h-60FFFFh
610000h-617FFFh
618000h-61FFFFh
620000h-627FFFh
628000h-62FFFFh
630000h-637FFFh
638000h-63FFFFh
640000h-647FFFh
648000h-64FFFFh
650000h-657FFFh
658000h-65FFFFh
660000h-667FFFh
668000h-66FFFFh
670000h-677FFFh
678000h-67FFFFh
680000h-687FFFh
688000h-68FFFFh
690000h-697FFFh
698000h-69FFFFh
6A0000h-6A7FFFh
6A8000h-6AFFFFh
6B0000h-6B7FFFh
6B8000h-6BFFFFh
6C0000h-6C7FFFh
6C8000h-6CFFFFh
6D0000h-6D7FFFh
6D8000h-6DFFFFh
6E0000h-6E7FFFh
6E8000h-6EFFFFh
6F0000h-6F7FFFh
6F8000h-6FFFFFh
SA199
SA200
SA201
SA202
SA203
SA204
SA205
SA206
SA207
SA208
SA209
SA210
SA211
SA212
SA213
SA214
SA215
SA216
SA217
SA218
SA219
SA220
SA221
SA222
SA223
SA224
SA225
SA226
SA227
SA228
SA229
SA230
Bank B
June 24, 2005 S29WS-J_M0_A4
S29WS128J/064J
55
D a t a S h e e t
Table 13.5 WS128J Sector Address Table (Sheet 8 of 8)
Bank
Sector
Sector Size
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
4 Kwords
(x16) Address Range
700000h-707FFFh
708000h-70FFFFh
710000h-717FFFh
718000h-71FFFFh
720000h-727FFFh
728000h-72FFFFh
730000h-737FFFh
738000h-73FFFFh
740000h-747FFFh
748000h-74FFFFh
750000h-757FFFh
758000h-75FFFFh
760000h-767FFFh
768000h-76FFFFh
770000h-777FFFh
778000h-77FFFFh
780000h-787FFFh
788000h-78FFFFh
790000h-797FFFh
798000h-79FFFFh
7A0000h-7A7FFFh
7A8000h-7AFFFFh
7B0000h-7B7FFFh
7B8000h-7BFFFFh
7C0000h-7C7FFFh
7C8000h-7CFFFFh
7D0000h-7D7FFFh
7D8000h-7DFFFFh
7E0000h-7E7FFFh
7E8000h-7EFFFFh
7F0000h-7F7FFFh
7F8000h-7F8FFFh
7F9000h-7F9FFFh
7FA000h-7FAFFFh
7FB000h-7FBFFFh
7FC000h-7FCFFFh
7FD000h-7FDFFFh
7FE000h-7FEFFFh
7FF000h-7FFFFFh
SA231
SA232
SA233
SA234
SA235
SA236
SA237
SA238
SA239
SA240
SA241
SA242
SA243
SA244
SA245
SA246
SA247
SA248
SA249
SA250
SA251
SA252
SA253
SA254
SA255
SA256
SA257
SA258
SA259
SA260
SA261
SA262
SA263
SA264
SA265
SA266
SA267
SA268
SA269
Bank A
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
56
S29WS128J/064J
S29WS-J_M0_A4 June 24, 2005
D a t a S h e e t
Table 13.6 WS064J Sector Address Table (Sheet 1 of 6)
Bank
Sector
Sector Size
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
(x16) Address Range
000000h-000FFFh
001000h-001FFFh
002000h-002FFFh
003000h-003FFFh
004000h-004FFFh
005000h-005FFFh
006000h-006FFFh
007000h-007FFFh
008000h-00FFFFh
010000h-017FFFh
018000h-01FFFFh
020000h-027FFFh
028000h-02FFFFh
030000h-037FFFh
038000h-03FFFFh
040000h-047FFFh
048000h-04FFFFh
050000h-057FFFh
058000h-05FFFFh
060000h-067FFFh
068000h-06FFFFh
070000h-077FFFh
078000h-07FFFFh
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
Bank D
June 24, 2005 S29WS-J_M0_A4
S29WS128J/064J
57
D a t a S h e e t
Table 13.6 WS064J Sector Address Table (Sheet 2 of 6)
Bank
Sector
Sector Size
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
(x16) Address Range
080000h-087FFFh
088000h-08FFFFh
090000h-097FFFh
098000h-09FFFFh
0A0000h-0A7FFFh
0A8000h-0AFFFFh
0B0000h-0B7FFFh
0B8000h-0BFFFFh
0C0000h-0C7FFFh
0C8000h-0CFFFFh
0D0000h-0D7FFFh
0D8000h-0DFFFFh
0E0000h-0E7FFFh
0E8000h-0EFFFFh
0F0000h-0F7FFFh
0F8000h-0FFFFFh
100000h-107FFFh
108000h-10FFFFh
110000h-117FFFh
118000h-11FFFFh
120000h-127FFFh
128000h-12FFFFh
130000h-137FFFh
138000h-13FFFFh
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
Bank C
58
S29WS128J/064J
S29WS-J_M0_A4 June 24, 2005
D a t a S h e e t
Table 13.6 WS064J Sector Address Table (Sheet 3 of 6)
Bank
Sector
Sector Size
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
(x16) Address Range
140000h-147FFFh
148000h-14FFFFh
150000h-157FFFh
158000h-15FFFFh
160000h-167FFFh
168000h-16FFFFh
170000h-177FFFh
178000h-17FFFFh
180000h-187FFFh
188000h-18FFFFh
190000h-197FFFh
198000h-19FFFFh
1A0000h-1A7FFFh
1A8000h-1AFFFFh
1B0000h-1B7FFFh
1B8000h-1BFFFFh
1C0000h-1C7FFFh
1C8000h-1CFFFFh
1D0000h-1D7FFFh
1D8000h-1DFFFFh
1E0000h-1E7FFFh
1E8000h-1EFFFFh
1F0000h-1F7FFFh
1F8000h-1FFFFFh
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
Bank C
June 24, 2005 S29WS-J_M0_A4
S29WS128J/064J
59
D a t a S h e e t
Table 13.6 WS064J Sector Address Table (Sheet 4 of 6)
Bank
Sector
Sector Size
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
(x16) Address Range
200000h-207FFFh
208000h-20FFFFh
210000h-217FFFh
218000h-21FFFFh
220000h-227FFFh
228000h-22FFFFh
230000h-237FFFh
238000h-23FFFFh
240000h-247FFFh
248000h-24FFFFh
250000h-257FFFh
258000h-25FFFFh
260000h-267FFFh
268000h-26FFFFh
270000h-277FFFh
278000h-27FFFFh
280000h-287FFFh
288000h-28FFFFh
290000h-297FFFh
298000h-29FFFFh
2A0000h-2A7FFFh
2A8000h-2AFFFFh
2B0000h-2B7FFFh
2B8000h-2BFFFFh
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
Bank B
60
S29WS128J/064J
S29WS-J_M0_A4 June 24, 2005
D a t a S h e e t
Table 13.6 WS064J Sector Address Table (Sheet 5 of 6)
Bank
Sector
Sector Size
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
(x16) Address Range
2C0000h-2C7FFFh
2C8000h-2CFFFFh
2D0000h-2D7FFFh
2D8000h-2DFFFFh
2E0000h-2E7FFFh
2E8000h-2EFFFFh
2F0000h-2F7FFFh
2F8000h-2FFFFFh
300000h-307FFFh
308000h-30FFFFh
310000h-317FFFh
318000h-31FFFFh
320000h-327FFFh
328000h-32FFFFh
330000h-337FFFh
338000h-33FFFFh
340000h-347FFFh
348000h-34FFFFh
350000h-357FFFh
358000h-35FFFFh
360000h-367FFFh
368000h-36FFFFh
370000h-377FFFh
378000h-37FFFFh
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
Bank B
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Table 13.6 WS064J Sector Address Table (Sheet 6 of 6)
Bank
Sector
Sector Size
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
(x16) Address Range
380000h-387FFFh
388000h-38FFFFh
390000h-397FFFh
398000h-39FFFFh
3A0000h-3A7FFFh
3A8000h-3AFFFFh
3B0000h-3B7FFFh
3B8000h-3BFFFFh
3C0000h-3C7FFFh
3C8000h-3CFFFFh
3D0000h-3D7FFFh
3D8000h-3DFFFFh
3E0000h-3E7FFFh
3E8000h-3EFFFFh
3F0000h-3F7FFFh
3F8000h-3F8FFFh
3F9000h-3F9FFFh
3FA000h-3FAFFFh
3FB000h-3FBFFFh
3FC000h-3FCFFFh
3FD000h-3FDFFFh
3FE000h-3FEFFFh
3FF000h-3FFFFFh
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
SA135
SA136
SA137
SA138
SA139
SA140
SA141
Bank A
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14 Command Definitions
Writing specific address and data commands or sequences into the command register initiates
device operations. Table 14.5, “Command Definitions,” on page 77 defines the valid register com-
mand sequences. Writing incorrect address and data values or writing them in the improper
sequence may place the device in an unknown state. The system must write the reset command
to return the device to reading array data. Refer to the AC Characteristics section for timing
diagrams.
14.1 Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are
required to retrieve data in asynchronous mode. Each bank is ready to read array data after com-
pleting an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the corresponding bank enters the erase-
suspend-read mode, after which the system can read data from any non-erase-suspended sector
within the same bank. After completing a programming operation in the Erase Suspend mode,
the system may once again read array data from any non-erase-suspended sector within the
same bank. See the “Erase Suspend/Erase Resume Commands” section on page 72 for more
information.
The system must issue the reset command to return a bank to the read (or erase-suspend-read)
mode if DQ5 goes high during an active program or erase operation, or if the bank is in the au-
toselect mode. See the “Reset Command” section on page 67 for more information.
See also “Requirements for Asynchronous ReadOperation (Non-Burst)” section on page 28 and
“Requirements for Synchronous (Burst) Read Operation” section on page 29 for more informa-
tion. The Asynchronous Read and Synchronous/Burst Read tables provide the read parameters,
and Figure 22.3, “CLK Synchronous Burst Mode Read (rising active CLK),” on page 93,
Figure 22.5, “Synchronous Burst Mode Read,” on page 94, and Figure 22.8, “Asynchronous Mode
Read with Latched Addresses,” on page 96 show the timings.
14.2 Set Configuration Register Command Sequence
The device uses a configuration register to set the various burst parameters: number of wait
states, burst read mode, active clock edge, RDY configuration, and synchronous mode active. The
configuration register must be set before the device will enter burst mode.
The configuration register is loaded with a three-cycle command sequence. The first two cycles
are standard unlock sequences. On the third cycle, the data should be C0h, address bits A11–A0
should be 555h, and address bits A19–A12 set the code to be latched. The device will power up
or after a hardware reset with the default setting, which is in asynchronous mode. The register
must be set before the device can enter synchronous mode. The configuration register can not
be changed during device operations (program, erase, or sector lock).
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Power-up/
Hardware Reset
Asynchronous Read
Mode Only
Set Burst Mode
Configuration Register
Command for
Set Burst Mode
Configuration Register
Command for
Synchronous Mode
(A19 = 0)
Asynchronous Mode
(A19 = 1)
Synchronous Read
Mode Only
Figure 14.1 Synchronous/Asynchronous State Diagram
14.2.1 Read Mode Setting
On power-up or hardware reset, the device is set to be in asynchronous read mode. This setting
allows the system to enable or disable burst mode during system operations. Address A19 deter-
mines this setting: “1’ for asynchronous mode, “0” for synchronous mode.
14.2.2 Programmable Wait State Configuration
The programmable wait state feature informs the device of the number of clock cycles that must
elapse after AVD# is driven active before data will be available. This value is determined by the
input frequency of the device. Address bits A14–A12 determine the setting (see Table 14.1, “Pro-
grammable Wait State Settings,” on page 65).
The wait state command sequence instructs the device to set a particular number of clock cycles
for the initial access in burst mode. The number of wait states that should be programmed into
the device is directly related to the clock frequency.
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Table 14.1 Programmable Wait State Settings
A14
0
A13
0
A12
0
Total Initial Access Cycles
2
0
0
1
3
0
1
0
4
5
0
1
1
1
0
0
6
1
0
1
7 (default)
Reserved
Reserved
1
1
0
1
1
1
Notes:
1. Upon power-up or hardware reset, the default setting is seven wait states.
2. RDY will default to being active with data when the Wait State Setting is set to a
total initial access cycle of 2.
It is recommended that the wait state command sequence be written, even if the default wait
state value is desired, to ensure the device is set as expected. A hardware reset will set the wait
state to the default setting.
14.2.3 Standard wait-state Handshaking Option
The host system must set the appropriate number of wait states in the flash device depending
upon the clock frequency. The host system should set address bits A14–A12 to 010 for a clock
frequency of 66/80 MHz for the system/device to execute at maximum speed.
Table 14.2 describes the recommended number of clock cycles (wait states) for various
conditions.
Table 14.2 Wait States for Standard wait-state Handshaking
Typical No. of Clock Cycles after AVD# Low
Burst Mode
8-Word or 16-Word or Continuous
32-Word
66 MHz
80 MHz
6 or 7
7
4
5
Notes:
1. In the 8-, 16- and 32-word burst read modes, the address pointer does not cross
64-word boundaries (addresses which are multiples of 3Fh).
2. For WS128J model numbers 10 and 11, an additional clock cycle is required for
boundary crossings while in Continuous read mode.
The host system must set the appropriate number of wait states in the flash device depending
upon the clock frequency. Note that the host system must set again the number of wait state
when the host system change the clock frequency. For example, the host system must set from
6 or 7 wait state to less than 5 wait states when the host system change the clock frequency from
80MHz to less than 80MHz. The autoselect function allows the host system to determine whether
the flash device is enabled for handshaking. See the “Autoselect Command Sequence” section on
page 68 for more information.
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14.2.4 Read Mode Configuration
The device supports four different read modes: continuous mode, and 8, 16, and 32 word linear
wrap around modes. A continuous sequence begins at the starting address and advances the ad-
dress pointer until the burst operation is complete. If the highest address in the device is reached
during the continuous burst read mode, the address pointer wraps around to the lowest address.
For example, an eight-word linear read with wrap around begins on the starting address written
to the device and then advances to the next 8 word boundary. The address pointer then returns
to the 1st word after the previous eight word boundary, wrapping through the starting location.
The sixteen- and thirty-two linear wrap around modes operate in a fashion similar to the eight-
word mode.
Table 14.3 shows the address bits and settings for the four read modes.
Table 14.3 Read Mode Settings
Address Bits
Burst Modes
A16
0
A15
0
Continuous
8-word linear wrap around
16-word linear wrap around
32-word linear wrap around
0
1
1
0
1
1
Note: Upon power-up or hardware reset the default setting is continuous.
14.2.5 Burst Active Clock Edge Configuration
By default, the device will deliver data on the rising edge of the clock after the initial synchronous
access time. Subsequent outputs will also be on the following rising edges, barring any delays.
The device can be set so that the falling clock edge is active for all synchronous accesses. Address
bit A17 determines this setting; “1” for rising active, “0” for falling active.
14.2.6 RDY Configuration
By default, the device is set so that the RDY pin will output VOH whenever there is valid data on
the outputs. The device can be set so that RDY goes active one data cycle before active data.
Address bit A18 determines this setting; “1” for RDY active with data, “0” for RDY active one clock
cycle before valid data. Only the combination of wait state 2 and RDY active one clock cycle before
data is not supported. In asynchronous mode, RDY is an open-drain output.
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14.3 Configuration Register
Table 14.4 shows the address bits that determine the configuration register settings for various
device functions.
Table 14.4 Configuration Register
Address Bit
Function
Settings (Binary)
Set Device
Read Mode
0 = Synchronous Read (Burst Mode) Enabled
1 = Asynchronous Mode (default)
A19
0 = RDY active one clock cycle before data
1 = RDY active with data (default)
A18
RDY
0 = Burst starts and data is output on the falling edge of CLK
1 = Burst starts and data is output on the rising edge of CLK (default)
A17
A16
Clock
Synchronous Mode
00 = Continuous (default)
Read Mode
01 = 8-word linear with wrap around
10 = 16-word linear with wrap around
11 = 32-word linear with wrap around
A15
A14
A13
000 = Data is valid on the 2nd active CLK edge after AVD# transition to VIH
001 = Data is valid on the 3rd active CLK edge after AVD# transition to VIH
010 = Data is valid on the 4th active CLK edge after AVD# transition to VIH
011 = Data is valid on the 5th active CLK edge after AVD# transition to VIH
100 = Data is valid on the 6th active CLK edge after AVD# transition to VIH
101 = Data is valid on the 7th active CLK edge after AVD# transition to VIH (default)
Programmable
Wait State
A12
110 = Reserved
111 = Reserved
Note: Device is in the default state upon power-up or hardware reset.
14.4 Reset Command
Writing the reset command resets the banks to the read or erase-suspend-read mode. Address
bits are don’t cares for this command.
The reset command may be written between the sequence cycles in an erase command sequence
before erasing begins. This resets the bank to which the system was writing to the read mode.
Once erasure begins, however, the device ignores reset commands until the operation is
complete.
The reset command may be written between the sequence cycles in a program command se-
quence before programming begins (prior to the third cycle). This resets the bank to which the
system was writing to the read mode. If the program command sequence is written to a bank that
is in the Erase Suspend mode, writing the reset command returns that bank to the erase-sus-
pend-read mode. Once programming begins, however, the device ignores reset commands until
the operation is complete.
The reset command may be written between the sequence cycles in an autoselect command se-
quence. Once in the autoselect mode, the reset command must be written to return to the read
mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset
command returns that bank to the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation, writing the reset command returns the
banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend).
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14.5 Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and device
codes, and determine whether or not a sector is protected. Table 14.5, “Command Definitions,”
on page 77 shows the address and data requirements. The autoselect command sequence may
be written to an address within a bank that is either in the read or erase-suspend-read mode. The
autoselect command may not be written while the device is actively programming or erasing in
the other bank.
The autoselect command sequence is initiated by first writing two unlock cycles. This is followed
by a third write cycle that contains the bank address and the autoselect command. The bank then
enters the autoselect mode. No subsequent data will be made available if the autoselect data is
read in synchronous mode. The system may read at any address within the same bank any num-
ber of times without initiating another autoselect command sequence. Read commands to other
banks will return data from the array. The following table describes the address requirements for
the various autoselect functions, and the resulting data. BA represents the bank address, and SA
represents the sector address. The device ID is read in three cycles.
Description
Manufacturer ID
Device ID, Word 1
Address
Read Data
0001h
(BA) + 00h
(BA) + 01h
227Eh
2218h (WS128J)
221Eh (WS064J)
Device ID, Word 2
Device ID, Word 3
(BA) + 0Eh
2200h (WS128J)
2201h (WS064J)
(BA) + 0Fh
(SA) + 02h
Sector Protection
Verification
0001 (locked),
0000 (unlocked)
DQ15 - DQ8 = 0
DQ7 - Factory Lock Bit
1 = Locked, 0 = Not Locked
DQ6 -Customer Lock Bit
1 = Locked, 0 = Not Locked
DQ5 - Handshake Bit
1 = Reserved,
Indicator Bits
(BA) + 03h
0 = Standard Handshake
DQ4 & DQ3 - Boot Code
00 = Dual Boot Sector,
01 = Top Boot Sector,
10 = Bottom Boot Sector
DQ2 - DQ0 = 001
The system must write the reset command to return to the read mode (or erase-suspend-read
mode if the bank was previously in Erase Suspend).
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14.6 Enter Secured Silicon Sector/Exit Secured Silicon Sector
Command Sequence
The Secured Silicon Sector region provides a secured data area containing a random, eight word
electronic serial number (ESN). The system can access the Secured Silicon Sector region by is-
suing the three-cycle Enter Secured Silicon Sector command sequence. The device continues to
access the Secured Silicon Sector region until the system issues the four-cycle Exit Secured Sili-
con Sector command sequence. The Exit Secured Silicon Sector command sequence returns the
device to normal operation. The Secured Silicon Sector is not accessible when the device is exe-
cuting an Embedded Program or embedded Erase algorithm. Table 14.5, “Command Definitions,”
on page 77 shows the address and data requirements for both command sequences.
The following commands are not allowed when the Secured Silicon is accessible.
!
!
!
!
!
!
CFI
Unlock Bypass Entry
Unlock Bypass Program
Unlock Bypass Reset
Erase Suspend/Resume
Chip Erase
14.7 Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writ-
ing two unlock write cycles, followed by the program set-up command. The program address and
data are written next, which in turn initiate the Embedded Program algorithm. The system is not
required to provide further controls or timings. The device automatically provides internally gen-
erated program pulses and verifies the programmed cell margin. Table 14.5, “Command
Definitions,” on page 77 shows the address and data requirements for the program command
sequence.
When the Embedded Program algorithm is complete, that bank then returns to the read mode
and addresses are no longer latched. The system can determine the status of the program oper-
ation by monitoring DQ7 or DQ6/DQ2. Refer to the “Write Operation Status” section on page 80
for information on these status bits.
Any commands written to the device during the Embedded Program Algorithm are ignored. Note
that a hardware reset immediately terminates the program operation. The program command se-
quence should be reinitiated once that bank has returned to the read mode, to ensure data
integrity.
Programming is allowed in any sequence and across sector boundaries. A bit cannot be pro-
grammed from “0” back to a “1.” Attempting to do so may cause that bank to set DQ5 = 1, or
cause the DQ7 and DQ6 status bit to indicate the operation was successful. However, a succeeding
read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.”
14.7.1 Unlock Bypass Command Sequence
The unlock bypass feature allows the system to primarily program to a array faster than using
the standard program command sequence. The unlock bypass command sequence is initiated by
first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass
command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass pro-
gram command sequence is all that is required to program in this mode. The first cycle in this
sequence contains the unlock bypass program command, A0h; the second cycle contains the pro-
gram address and data. Additional data is programmed in the same manner. This mode dispenses
with the initial two unlock cycles required in the standard program command sequence, resulting
in faster total programming time. The host system may also initiate the chip erase and sector
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erase sequences in the unlock bypass mode. The erase command sequences are four cycles in
length instead of six cycles. Table 14.5, “Command Definitions,” on page 77 shows the require-
ments for the unlock bypass command sequences.
During the unlock bypass mode, only the Read, Unlock Bypass Program, Unlock Bypass Sector
Erase, Unlock Bypass Chip Erase, and Unlock Bypass Reset commands are valid. To exit the unlock
bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The
first cycle must contain the bank address and the data 90h. The second cycle need only contain
the data 00h. The array then returns to the read mode.
The device offers accelerated program operations through the ACC input. When the system as-
serts VHH on this input, the device automatically enters the Unlock Bypass mode. The system may
then write the two-cycle Unlock Bypass program command sequence. The device uses the higher
voltage on the ACC input to accelerate the operation.
Figure 14.2, “Program Operation,” on page 70 illustrates the algorithm for the program opera-
tion. Refer to the Erase/Program Operations table in the AC Characteristics section for
parameters, and Figure 22.11, “Asynchronous Program Operation Timings: AVD# Latched Ad-
dresses,” on page 100 and Figure 22.13, “Synchronous Program Operation Timings: WE#
Latched Addresses,” on page 102 for timing diagrams.
START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
No
Yes
No
Increment Address
Last Address?
Yes
Programming
Completed
Note: See Table 14.5 for program command sequence.
Figure 14.2 Program Operation
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14.8 Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing
two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then
followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The
device does not require the system to preprogram prior to erase. The Embedded Erase algorithm
automatically preprograms and verifies the entire memory for an all zero data pattern prior to
electrical erase. The system is not required to provide any controls or timings during these oper-
ations. Table 14.5, “Command Definitions,” on page 77 shows the address and data requirements
for the chip erase command sequence.
When the Embedded Erase algorithm is complete, that bank returns to the read mode and ad-
dresses are no longer latched. The system can determine the status of the erase operation by
using DQ7 or DQ6/DQ2. Refer to the “Write Operation Status” section on page 80 for information
on these status bits.
Any commands written during the chip erase operation are ignored. However, note that a hard-
ware reset immediately terminates the erase operation. If that occurs, the chip erase command
sequence should be reinitiated once that bank has returned to reading array data, to ensure data
integrity.
The host system may also initiate the chip erase command sequence while the device is in the
unlock bypass mode. The command sequence is two cycles cycles in length instead of six cycles.
See Table 14.5, “Command Definitions,” on page 77 for details on the unlock bypass command
sequences.
Figure 14.3, “Erase Operation,” on page 73 illustrates the algorithm for the erase operation. Refer
to the Erase/Program Operations table in the AC Characteristics section for parameters and timing
diagrams.
14.9 Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writ-
ing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written,
and are then followed by the address of the sector to be erased, and the sector erase command.
Table 14.5, “Command Definitions,” on page 77 shows the address and data requirements for the
sector erase command sequence.
The device does not require the system to preprogram prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the entire memory for an all zero data pattern prior to
electrical erase. The system is not required to provide any controls or timings during these
operations.
After the command sequence is written, a sector erase time-out of no less than 50 µs occurs.
During the time-out period, additional sector addresses and sector erase commands may be writ-
ten. Loading the sector erase buffer may be done in any sequence, and the number of sectors
may be from one sector to all sectors. The time between these additional cycles must be less than
50 µs, otherwise erasure may begin. Any sector erase address and command following the ex-
ceeded time-out may or may not be accepted. It is recommended that processor interrupts be
disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled
after the last Sector Erase command is written. If any command other than 30h, B0h, F0h is input
during the time-out period, the normal operation will not be guaranteed.
The system can monitor DQ3 to determine if the sector erase timer has timed out (See “DQ3:
Sector Erase Timer” section on page 85.) The time-out begins from the rising edge of the final
WE# pulse in the command sequence.
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When the Embedded Erase algorithm is complete, the bank returns to reading array data and ad-
dresses are no longer latched. Note that while the Embedded Erase operation is in progress, the
system can read data from the non-erasing bank. The system can determine the status of the
erase operation by reading DQ7 or DQ6/DQ2 in the erasing bank. Refer to the “Write Operation
Status” section on page 80 for information on these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other
commands are ignored. However, note that a hardware reset immediately terminates the erase
operation. If that occurs, the sector erase command sequence should be reinitiated once that
bank has returned to reading array data, to ensure data integrity.
The host system may also initiate the sector erase command sequence while the device is in the
unlock bypass mode. The command sequence is four cycles cycles in length instead of six cycles.
Figure 14.3, “Erase Operation,” on page 73 illustrates the algorithm for the erase operation. Refer
to the Erase/Program Operations table in the AC Characteristics on page 91 for parameters and
timing diagrams.
14.10 Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and
then read data from, or program data to, any sector not selected for erasure. The bank address
is required when writing this command. This command is valid only during the sector erase op-
eration, including the minimum 50 µs time-out period during the sector erase command
sequence. The Erase Suspend command is ignored if written during the chip erase operation or
Embedded Program algorithm.
When the Erase Suspend command is written during the sector erase operation, the device re-
quires a maximum of 35 µs to suspend the erase operation. However, when the Erase Suspend
command is written during the sector erase time-out, the device immediately terminates the
time-out period and suspends the erase operation.
After the erase operation has been suspended, the bank enters the erase-suspend-read mode.
The system can read data from or program data to any sector not selected for erasure. (The de-
vice “erase suspends” all sectors selected for erasure.) Reading at any address within erase-
suspended sectors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6
and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the
Figure 15, “Write Operation Status,” on page 80 for information on these status bits.
After an erase-suspended program operation is complete, the bank returns to the erase-suspend-
read mode. The system can determine the status of the program operation using the DQ7 or DQ6
status bits, just as in the standard program operation. Refer to the “Write Operation Status” sec-
tion on page 80 for more information.
In the erase-suspend-read mode, the system can also issue the autoselect command sequence.
Refer to the “Autoselect Mode” section on page 31 and “Autoselect Command Sequence” section
on page 68 for details.
To resume the sector erase operation, the system must write the Erase Resume command. The
bank address of the erase-suspended bank is required when writing this command. Further writes
of the Resume command are ignored. Another Erase Suspend command can be written after the
chip has resumed erasing.
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START
Write Erase
Command Sequence
Data Poll
from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Table 14.5 for erase command sequence.
2. See the section on DQ3 for information on the sector erase timer
Figure 14.3 Erase Operation
14.11 Password Program Command
The Password Program Command permits programming the password that is used as part of the
hardware protection scheme. The actual password is 64-bits long. 4 Password Program com-
mands are required to program the password. The user must enter the unlock cycle, password
program command (38h) and the program address/data for each portion of the password when
programming. There are no provisions for entering the 2-cycle unlock cycle, the password pro-
gram command, and all the password data. There is no special addressing order required for
programming the password. Also, when the password is undergoing programming, Simultaneous
Operation is disabled. Read operations to any memory location will return the programming status
except DQ7. Once programming is complete, the user must issue a Read/Reset command to the
device to normal operation. Once the Password is written and verified, the Password Mode Locking
Bit must be set in order to prevent verification. The Password Program Command is only capable
of programming “0”s. Programming a “1” after a cell is programmed as a “0” results in a time-
out by the Embedded Program Algorithm™ with the cell remaining as a “0”. The password is all
F’s when shipped from the factory. All 64-bit password combinations are valid as a password.
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14.12 Password Verify Command
The Password Verify Command is used to verify the Password. The Password is verifiable only
when the Password Mode Locking Bit is not programmed. If the Password Mode Locking Bit is pro-
grammed and the user attempts to verify the Password, the device will always drive all F’s onto
the DQ data bus.
Also, the device will not operate in Simultaneous Operation when the Password Verify command
is executed. Only the password is returned regardless of the bank address. The lower two address
bits (A1–A0) are valid during the Password Verify. Writing the Secured Silicon Exit command re-
turns the device back to normal operation.
14.13 Password Protection Mode Locking Bit Program Command
The Password Protection Mode Locking Bit Program Command programs the Password Protection
Mode Locking Bit, which prevents further verifies or updates to the password. Once programmed,
the Password Protection Mode Locking Bit cannot be erased and the Persistent Protection Mode
Locking Bit program circuitry is disabled, thereby forcing the device to remain in the Password
Protection Mode. After issuing “PL/68h” at the fourth bus cycle, the device requires a time out
period of approximately 150 µs for programming the Password Protection Mode Locking Bit. Then
by writing “PL/48h” at the fifth bus cycle, the device outputs verify data at DQ0. If DQ0 = 1, then
the Password Protection Mode Locking Bit is programmed. If not, the system must repeat this
program sequence from the fourth cycle of “PL/68h”. Exiting the Password Protection Mode Lock-
ing Bit Program command is accomplished by writing the Secured Silicon Sector Exit command
or Read/Reset command.
14.14 Persistent Sector Protection Mode Locking Bit Program
Command
The Persistent Sector Protection Mode Locking Bit Program Command programs the Persistent
Sector Protection Mode Locking Bit, which prevents the Password Mode Locking Bit from ever
being programmed. By disabling the program circuitry of the Password Mode Locking Bit, the de-
vice is forced to remain in the Persistent Sector Protection mode of operation, once this bit is set.
After issuing “SL/68h” at the fourth bus cycle, the device requires a time out period of approxi-
mately 150 µs for programming the Persistent Protect ion Mode Locking Bit. Then by writ ing
“SMPL/48h” at the fifth bus cycle, the device outputs verify data at DQ0. If DQ0 = 1, then the
Persistent Protection Mode Locking Bit is programmed. If not, the system must repeat this pro-
gram sequence from the fourth cycle of “PL/68h”. Exiting the Persistent Protection Mode Locking
Bit Program command is accomplished by writing the Secured Silicon Sector Exit command or
Read/Reset command.
14.15 Secured Silicon Sector Protection Bit Program Command
To protect the Secured Silicon Sector, write the Secured Silicon Sector Protect command sequence
while in the Secured Silicon Sector mode. After issuing “OW/48h” at the fourth bus cycle, the de-
vice requires a time out period of approximately 150 µs to protect the Secured Silicon Sector.
Then, by writing “OPBP/48” at the fifth bus cycle, the device outputs verify data at DQ0. If DQ0
= 1, then the Secured Silicon Sector is protected. If not, then the system must repeat this pro-
gram sequence from the fourth cycle of “OPBP/48h”. Exiting the Secured Silicon Sector Protection
Mode Locking Bit Program command is accomplished by writing the Secured Silicon Sector Exit
command or Read/Reset command.
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14.16 PPB Lock Bit Set Command
The PPB Lock Bit Set command is used to set the PPB Lock bit if it is cleared either at reset or if
the Password Unlock command was successfully executed. There is no PPB Lock Bit Clear com-
mand. Once the PPB Lock Bit is set, it cannot be cleared unless the device is taken through a
power-on clear or the Password Unlock command is executed. Upon setting the PPB Lock Bit, the
PPBs are latched. If the Password Mode Locking Bit is set, the PPB Lock Bit status is reflected as
set, even after a power-on reset cycle. Exiting the PPB Lock Bit Set command is accomplished by
writing the Secured Silicon Exit command, only while in the Persistent Sector Protection Mode.
14.17 DPB Write/Erase/Status Command
The DPB Write command is used to set or clear a DPB for a given sector. The high order address
bits (Amax–A11) are issued at the same time as the code 01h or 00h on DQ7-DQ0. All other DQ
data bus pins are ignored during the data write cycle. The DPBs are modifiable at any time, re-
gardless of the state of the PPB or PPB Lock Bit. If the PPB is set, the sector is protected regardless
of the value of the DPB. If the PPB is cleared, setting the DPB to a 1 protects the sector from
programs or erases. Since this is a volatile bit, removing power or resetting the device will clear
the DPBs. The programming of the DPB for a given sector can be verified by writing a DPB Status
command to the device. Exiting the DPB Write/Erase command is accomplished by writing the
Read/Reset command. Exiting the DPB Status command is accomplished by writting the Secured
Silicon Sector Exit command
14.18 Password Unlock Command
The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs can be unlocked
for modification, thereby allowing the PPBs to become accessible for modification. The exact pass-
word must be entered in order for the unlocking function to occur. This command cannot be issued
any faster than 2 µs at a time to prevent a hacker from running through the all 64-bit combina-
tions in an attempt to correctly match a password. If the command is issued before the 2 µs
execution window for each portion of the unlock, the command will be ignored.
The Password Unlock function is accomplished by writing Password Unlock command and data to
the device to perform the clearing of the PPB Lock Bit. The password is 64 bits long, so the user
must write the Password Unlock command 4 times. A1 and A0 are used for matching. Writing the
Password Unlock command is not address order specific. The lower address A1–A0= 00, the next
Password Unlock command is to A1–A0= 01, then to A1–A0= 10, and finally to A1–A0= 11.
Once the Password Unlock command is entered for all four words, the RDY pin goes LOW indicat-
ing that the device is busy. Also, reading the Bank D results in the DQ6 pin toggling, indicating
that the Password Unlock function is in progress. Reading the other bank returns actual array
data. Approximately 1µs is required for each portion of the unlock. Once the first portion of the
password unlock completes (RDY is not driven and DQ6 does not toggle when read), the Password
Unlock command is issued again, only this time with the next part of the password. Four Password
Unlock commands are required to successfully clear the PPB Lock Bit. As with the first Password
Unlock command, the RDY signal goes LOW and reading the device results in the DQ6 pin toggling
on successive read operations until complete. It is the responsibility of the microprocessor to keep
track of the number of Password Unlock commands, the order, and when to read the PPB Lock bit
to confirm successful password unlock. In order to relock the device into the Password Mode, the
PPB Lock Bit Set command can be re-issued. Exiting the Password Unlock command is accom-
plished by writing the Secured Silicon Sector Exit command.
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14.19 PPB Program Command
The PPB Program command is used to program, or set, a given PPB. Each PPB is individually pro-
grammed (but is bulk erased with the other PPBs). The specific sector address (Amax–A12) are
written at the same time as the program command 60h with A6 = 0. If the PPB Lock Bit is set
and the corresponding PPB is set for the sector, the PPB Program command will not execute and
the command will time-out without programming the PPB.
After programming a PPB, two additional cycles are needed to determine whether the PPB has
been programmed with margin. After 4th cycle, the device requires approximately 150 µs time
out period for programming the PPB. And then after 5th cycle, the device outputs verify data at
DQ0.
The PPB Program command does not follow the Embedded Program algorithm. Writing the Se-
cured Silicon Sector Exit command or Read/Reset command return the device back to normal
operation.
14.20 All PPB Erase Command
The All PPB Erase command is used to erase all PPBs in bulk. There is no means for individually
erasing a specific PPB. Unlike the PPB program, no specific sector address is required. However,
when the PPB erase command is written (60h) and A6 = 1, all Sector PPBs are erased in parallel.
If the PPB Lock Bit is set the ALL PPB Erase command will not execute and the command will time-
out without erasing the PPBs.
After erasing the PPBs, two additional cycles are needed to determine whether the PPB has been
erased with margin. After 4th cycle, the device requires approximately 1.5 ms time out period for
erasing the PPB. And then after 5th cycle, the device outputs verify data at DQ0.
It is the responsibility of the user to preprogram all PPBs prior to issuing the All PPB Erase com-
mand. If the user attempts to erase a cleared PPB, over-erasure may occur making it difficult to
program the PPB at a later time. Also note that the total number of PPB program/erase cycles is
limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed. Writing the Secured
Silicon Sector Exit command or Read/Reset command return the device back to normal operation.
14.21 PPB Status Command
The programming of the PPB for a given sector can be verified by writing a PPB status verify com-
mand to the device. Writing the Secured Silicon Sector Exit command or Read/Reset command
return the device back to normal operation.
14.22 PPB Lock Bit Status Command
The programming of the PPB Lock Bit for a given sector can be verified by writing a PPB Lock Bit
status verify command to the device. Writing the Secured Silicon Sector Exit command or Read/
Reset command return the device back to normal operation.
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14.23 Command Definitions
Table 14.5 Command Definitions
Bus Cycles (Notes 1–6)
Command Sequence
First
Second
Third
Fourth
Fifth
Sixth
Seventh
(Note 1)
Addr Data Addr Data Addr Data Addr
Data
Addr Data Addr Data Addr Data
Asynchronous Read (Note 7)
Reset (Note 8)
1
1
RA
RD
F0
XXX
(BA)
555
(BA)
X00
Manufacturer ID
4
6
4
4
555
555
555
555
AA
AA
AA
AA
2AA
2AA
2AA
2AA
55
55
55
55
90
90
90
90
0001
227E
(BA)
555
(BA)
X01
(BA)X (Note (BA) (Not
Device ID (Note 10)
0E
10)
X0F e 10)
(SA)
555
(SA) 0000/
X02
Sector Lock Verify
(Note 11)
0001
(BA)
555
(BA)
X03
(Note
12)
Indicator Bits
Program
4
6
6
1
1
555
555
555
BA
AA
AA
AA
B0
30
2AA
2AA
2AA
55
55
55
555
555
555
A0
80
80
PA
Data
AA
Chip Erase
555
555
2AA
2AA
55
55
555
SA
10
30
Sector Erase
AA
Erase Suspend (Note 15)
Erase Resume (Note 16)
BA
(CR)
555
Set Configuration Register (Note 17)
3
555
AA
98
2AA
55
C0
20
CFI Query (Note 18)
1
55
Unlock Bypass Entry
3
555
AA 2AA 55
555
Unlock Bypass
Program (Notes 13,
14)
2
XX
A0
PA
SA
PD
30
Unlock Bypass
Unlock
Sector Erase (Notes
2
2
2
XX
XX
XX
80
80
90
Bypass
13, 14)
Mode
Unlock Bypass Erase
(Notes 13, 14)
XXX 10
XXX 00
Unlock Bypass Reset
(Notes 13, 14)
Sector Protection Command Definitions
Secured Silicon
Sector Entry
3
4
555
555
AA 2AA 55
AA 2AA 55
555
555
88
90
Secured Silicon
Sector Exit
Secured
XX
00
68
Silicon
Sector
Secured Silicon
Protection Bit
Program (Notes 19,
21)
RD
(0)
6
4
555
555
AA 2AA 55
AA 2AA 55
555
555
60
38
OW
OW
48
OW
XX0
XX1
XX2
XX3
XX0
XX1
XX2
XX3
PD0
PD1
PD2
PD3
PD0
PD1
PD2
PD3
Password Program
(Notes 23)
Password
Protection
Password Verify
4
7
555
555
AA 2AA 55
AA 2AA 55
555
555
C8
28
Password Unlock
(Note 23)
XX0
PD0 XX1 PD1 XX2 PD2 XX3 PD3
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D a t a S h e e t
Bus Cycles (Notes 1–6)
Fourth
Command Sequence
(Note 1)
First
Second
Third
Fifth
Sixth
Seventh
Addr Data Addr Data Addr Data Addr
Data
Addr Data Addr Data Addr Data
SBA
+ WP
RD
(0)
PPB Program (Notes
21)
SBA
6
6
555
555
AA 2AA 55
AA 2AA 55
555
555
60
68
48
40
XX
XX
+ WP
RD
(0)
PPB
All PPB Erase (Notes
Commands 22, 24)
60 WPE
60
SBA
WPE
SBA
555
SBA
90
RD
(0)
PPB Status (Note 25)
4
3
4
555
555
555
AA 2AA 55
AA 2AA 55
AA 2AA 55
+WP
PPB Lock Bit Set
555
78
PPB Lock
Bit
(BA)
555
RD
(1)
PPB Lock Bit Status
58
BA
DPB Write
DPB Erase
4
4
555
555
AA 2AA 55
AA 2AA 55
555
555
48
48
SA
SA
X1
X0
DPB
(BA)
555
RD
(0)
DPB Status
4
6
6
555
555
555
AA 2AA 55
AA 2AA 55
AA 2AA 55
58
60
60
SA
PL
SL
RD
(0)
Password Protection Mode
Locking Bit Program (Notes 21)
555
555
68
68
PL
SL
48
48
PL
SL
RD
(0)
Persistent Protection Mode
Locking Bit Program (Notes 21)
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the rising edge of the AVD# pulse or active edge of CLK which ever
comes first.
PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits Amax–A12 uniquely select any sector.
BA = Address of the bank (WS128J: A22, A21, A20, WS064J: A21, A20, A19) that is being switched to autoselect mode, is in bypass mode, or is
being erased.
SLA = Address of the sector to be locked. Set sector address (SA) and either A6 = 1 for unlocked or A6 = 0 for locked.
SBA = sector address block to be protected.
CR = Configuration Register address bits A19–A12.
OW = Address (A7–A0) is (00011010).
PD3–PD0 = Password Data. PD3–PD0 present four 16 bit combinations that represent the 64-bit Password
PWA = Password Address. Address bits A1 and A0 are used to select each 16-bit portion of the 64-bit entity.
PWD = Password Data.
PL = Address (A7-A0) is (00001010)
RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 1, if unprotected, DQ0 = 0.
RD(1) = DQ1 protection indicator bit. If protected, DQ1 = 1, if unprotected, DQ1 = 0.
SL = Address (A7-A0) is (00010010)
WD= Write Data. See “Configuration Register” definition for specific write data
WP = Address (A7-A0) is (00000010)
WPE = address(A7-A0) is (01000010)
Notes:
1. See Table 11.1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the following, all bus cycles are write cycle: read cycle, fourth through sixth cycles of the Autoselect commands, fourth cycle of
the configuration register verify and password verify commands, and any cycle reading at RD(0) and RD(1).
4. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD, PD, WD, PWD, and PD3-PD0.
5. Unless otherwise noted, address bits Amax–A12 are don’t cares.
6. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system
must write the reset command to return the device to reading array data.
7. No unlock or command cycles required when bank is reading array data.
8. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when a
bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information) or performing sector lock/unlock.
9. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address. See the Autoselect
Command Sequence section for more information.
10. (BA)X0Fh = 2200h (WS128J), (BA)X0Eh = 2218h (WS128J), (BA)X0Fh = 221Eh (WS064J), (BA)X0Eh = 2201h (WS064J)
11. The data is 0000h for an unlocked sector and 0001h for a locked sector
12. DQ15 - DQ8 = 0, DQ7 - Factory Lock Bit (1 = Locked, 0 = Not Locked), DQ6 -Customer Lock Bit (1 = Locked, 0 = Not Locked), DQ5 =
Handshake Bit (1 = Reserved, 0 = Standard Handshake)8, DQ4 & DQ3 - Boot Code (00= Dual Boot Sector, 01= Top Boot Sector, 10=
Bottom Boot Sector, 11=No Boot Sector), DQ2 - DQ0 = 001
13. The Unlock Bypass command sequence is required prior to this command sequence.
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D a t a S h e e t
14. The Unlock Bypass Reset command is required to return to reading array data.
15. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase
Suspend command is valid only during a sector erase operation, and requires the bank address.
16. The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address.
17. See “Set Configuration Register Command Sequence” for details.
18.Command is valid when device is ready to read array data or when device is in autoselect mode.
19. Regardless of CLK and AVD# interaction or Control Register bit 15 setting, command mode verifies are always asynchronous read
operations.
20. ACC must be at VHH during the entire operation of this command
21. The fourth cycle programs the addressed locking bit. The fifth and sixth cycles are used to validate whether the bit has been fully
programmed. If DQ0 (in the sixth cycle) reads 0, the program command must be issued and verified again.
22. The fourth cycle erases all PPBs. The fifth and sixth cycles are used to validate whether the bits have been fully erased. If DQ0 (in the sixth
cycle) reads 1, the erase command must be issued and verified again.
23. The entire four bus-cycle sequence must be entered for each portion of the password.
24. Before issuing the erase command, all PPBs should be programmed in order to prevent over-erasure of PPBs.
25. In the fourth cycle, 01h indicates PPB set; 00h indicates PPB not set.
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15 Write Operation Status
The device provides several bits to determine the status of a program or erase operation: DQ2,
DQ3, DQ5, DQ6, and DQ7. Table 15.2, “Write Operation Status,” on page 86 and the following
subsections describe the function of these bits. DQ7 and DQ6 each offers a method for determin-
ing whether a program or erase operation is complete or in progress.
15.1 DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase
algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is
valid after the rising edge of the final WE# pulse in the command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the
datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend.
When the Embedded Program algorithm is complete, the device outputs the datum programmed
to DQ7. The system must provide the program address to read valid status information on DQ7.
If a program address falls within a protected sector, Data# Polling on DQ7 is active for approxi-
mately 1 µs, then that bank returns to the read mode.
During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embed-
ded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling
produces a “1” on DQ7. The system must provide an address within any of the sectors selected
for erasure to read valid status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected,
Data# Polling on DQ7 is active for approximately 100 µs, then the bank returns to the read mode.
If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7
at an address within a protected sector, the status may not be valid.
Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asyn-
chronously with DQ6–DQ0 while Output Enable (OE#) is asserted low. That is, the device may
change from providing status information to valid data on DQ7. Depending on when the system
samples the DQ7 output, it may read the status or valid data. Even if the device has completed
the program or erase operation and DQ7 has valid data, the data outputs on DQ6-DQ0 may be
still invalid. Valid data on DQ7-D00 will appear on successive read cycles.
Table 15.2, “Write Operation Status,” on page 86 shows the outputs for Data# Polling on DQ7.
Figure 15.1, “Data# Polling Algorithm,” on page 81 shows the Data# Polling algorithm.
Figure 22.17, “Data# Polling Timings (During Embedded Algorithm),” on page 105 in the AC
Characteristics section shows the Data# Polling timing diagram.
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START
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
No
PASS
FAIL
Notes:
1. VA = Valid address for programming. During a sector erase operation, a valid
address is any sector address within the sector being erased. During chip erase,
a valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change
simultaneously with DQ5.
Figure 15.1 Data# Polling Algorithm
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15.2 RDY: Ready
The RDY is a dedicated output that, when the device is configured in the Synchronous mode, in-
dicates (when at logic low) the system should wait 1 clock cycle before expecting the next word
of data. The RDY pin is only controlled by CE#. Using the RDY Configuration Command Sequence,
RDY can be set so that a logic low indicates the system should wait 2 clock cycles before expecting
valid data.
The following conditions cause the RDY output to be low: during the initial access (in burst mode),
and after the boundary that occurs every 64 words beginning with the 64th address, 3Fh.
When the device is configured in Asynchronous Mode, the RDY is an open-drain output pin which
indicates whether an Embedded Algorithm is in progress or completed. The RDY status is valid
after the rising edge of the final WE# pulse in the command sequence.
If the output is low (Busy), the device is actively erasing or programming. (This includes program-
ming in the Erase Suspend mode.) If the output is in high impedance (Ready), the device is in
the read mode, the standby mode, or in the erase-suspend-read mode. Table 15.2, “Write Oper-
ation Status,” on page 86 shows the outputs for RDY.
15.3 DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or
complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read
at any address in the same bank, and is valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase operation), and during the sector erase time-
out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any ad-
dress cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6
toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors
are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or
is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm
is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops tog-
gling. However, the system must also use DQ2 to determine which sectors are erasing or erase-
suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling).
If a program address falls within a protected sector, DQ6 toggles for approximately 1 ms after the
program command sequence is written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embed-
ded Program algorithm is complete.
See the following for additional information: Figure 15.2, “Toggle Bit Algorithm,” on page 83,
DQ6: Toggle Bit I on page 82, Figure 22.18, “Toggle Bit Timings (During Embedded Algorithm),”
on page 106 (toggle bit timing diagram), and Table 15.1, “DQ6 and DQ2 Indications,” on
page 84.
Toggle Bit I on DQ6 requires either OE# or CE# to be deasserteed and reasserted to show the
change in state.
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START
Read Byte
(DQ0-DQ7)
Address = VA
Read Byte
(DQ0-DQ7)
Address = VA
No
DQ6 = Toggle?
Yes
No
DQ5 = 1?
Yes
Read Byte Twice
(DQ 0-DQ7)
Adrdess = VA
No
DQ6 = Toggle?
Yes
FAIL
PASS
Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5
changes to “1.” See the subsections on DQ6 and DQ2 for more information.
Figure 15.2 Toggle Bit Algorithm
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15.4 DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively
erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-
suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command
sequence.
DQ2 toggles when the system reads at addresses within those sectors that have been selected
for erasure. But DQ2 cannot distinguish whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase
Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are
required for sector and mode information. Refer to Table 15.1, “DQ6 and DQ2 Indications,” on
page 84 to compare outputs for DQ2 and DQ6.
See the following for additional information: Figure 15.2, “Toggle Bit Algorithm,” on page 83, See
DQ6: Toggle Bit I on page 82, Figure 22.18, “Toggle Bit Timings (During Embedded Algorithm),”
on page 106, and Table 15.1, “DQ6 and DQ2 Indications,” on page 84.
Table 15.1 DQ6 and DQ2 Indications
If device is
and the system reads
then DQ6
and DQ2
programming,
at any address,
toggles,
does not toggle.
at an address within a sector
selected for erasure,
toggles,
toggles,
also toggles.
does not toggle.
toggles.
actively erasing,
erase suspended,
at an address within sectors not
selected for erasure,
at an address within a sector
selected for erasure,
does not toggle,
returns array data,
toggles,
at an address within sectors not
returns array data. The system can read
from any sector not selected for erasure.
selected for erasure,
programming in
erase suspend
at any address,
is not applicable.
15.5 Reading Toggle Bits DQ6/DQ2
Refer to Figure 15.2, “Toggle Bit Algorithm,” on page 83 for the following discussion. Whenever
the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row
to determine whether a toggle bit is toggling. Typically, the system would note and store the value
of the toggle bit after the first read. After the second read, the system would compare the new
value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the
program or erase operation. The system can read array data on DQ7–DQ0 on the following read
cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still tog-
gling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If
it is, the system should then determine again whether the toggle bit is toggling, since the toggle
bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the
device has successfully completed the program or erase operation. If it is still toggling, the device
did not completed the operation successfully, and the system must write the reset command to
return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and
DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through suc-
cessive read cycles, determining the status as described in the previous paragraph. Alternatively,
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it may choose to perform other system tasks. In this case, the system must start at the beginning
of the algorithm when it returns to determine the status of the operation (Figure 15.2, “Toggle
Bit Algorithm,” on page 83).
15.6 DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count
limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was
not successfully completed.
The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was
previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this
condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 pro-
duces a “1.”
Under both these conditions, the system must write the reset command to return to the read
mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program
mode).
15.7 DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether
or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If
additional sectors are selected for erasure, the entire time-out also applies after each additional
sector erase command. When the time-out period is complete, DQ3 switches from a “0” to a “1.”
If the time between additional sector erase commands from the system can be assumed to be
less than 50 µs, the system need not monitor DQ3. See also Sector Erase Command Sequence
on page 71.
After the sector erase command is written, the system should read the status of DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and
then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all further commands
(except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device
will accept additional sector erase commands. To ensure the command has been accepted, the
system software should check the status of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status check, the last command might not have
been accepted.
Table 15.2 shows the status of DQ3 relative to the other status bits.
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Table 15.2 Write Operation Status
DQ7
(Note 2)
DQ5
(Note 1)
DQ2
(Note 2)
Status
DQ6
DQ3
RDY (Note 5)
No toggle
(Note 6)
Embedded Program Algorithm
DQ7#
Toggle
Toggle
0
0
0
N/A
1
0
Standard
Mode
Embedded Erase Algorithm
Erase
0
1
Toggle
Toggle
0
No toggle
(Note 6)
N/A
High Impedance
Suspended Sector
Erase-Suspend-
Read (Note 4)
Erase
Suspend
Mode
Non-Erase Suspended
Sector
Data
Data
Data
0
Data
N/A
Data
N/A
High Impedance
0
Erase-Suspend-Program
DQ7#
Toggle
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.
3. When reading write operation status bits, the system must always provide the bank address where the Embedded
Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank.
4. The system may read either asynchronously or synchronously (burst) while in erase suspend.
5. The RDY pin acts a dedicated output to indicate the status of an embedded erase or program operation is in progress. This
is available in the Asynchronous mode only.
6. When the device is set to Asynchronous mode, these status flags should be read by CE# toggle.
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16 Absolute Maximum Ratings
Storage Temperature, Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C
Voltage with Respect to Ground:
All Inputs and I/Os except as noted below (Note 1). . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
VCC (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +2.5 V
A9, RESET#, ACC (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +12.5 V
Output Short Circuit Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Notes:
1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs
or I/Os may undershoot V to –2.0 V for periods of up to 20 ns. See Figure 16.1.
SS
Maximum DC voltage on input or I/Os is V + 0.5 V. During voltage transitions
CC
outputs may overshoot to V + 2.0 V for periods up to 20 ns. See Figure 16.2.
CC
2. No more than one output may be shorted to ground at a time. Duration of the
short circuit should not be greater than one second.
3. Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this data sheet is not implied. Exposure of the device
to absolute maximum rating conditions for extended periods may affect device
reliability.
20 ns
20 ns
+0.8 V
–0.5 V
–2.0 V
20 ns
Figure 16.1 Maximum Negative Overshoot Waveform
20 ns
VCC
+2.0 V
VCC
+0.5 V
1.0 V
20 ns
20 ns
Figure 16.2 Maximum Positive Overshoot Waveform
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17 Operating Ranges
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Wireless (W) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25°C to +85°C
Supply Voltages
VCC Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.65 V to 1.95 V (66MHz)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.70 V to 1.95 V (80MHz)
Note: Operating ranges define those limits between which the functionality of the de-
vice is guaranteed.
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18 DC Characteristics
18.1 CMOS Compatible
Parameter Description
Test Conditions Notes: 1
Min
Typ
Max
±1
±1
30
Unit
µA
ILI
Input Load Current
VIN = VSS to VCC, VCC = VCCmax
VOUT = VSS to VCC, VCC = VCCmax
ILO
Output Leakage Current
µA
CE# = VIL, OE# = VIH
WE# = VIH, burst
length = 8
,
,
,
66 MHz
80 MHz
66 MHz
80 MHz
66 MHz
80 MHz
15
18
15
18
15
18
mA
36
30
36
30
36
mA
mA
mA
mA
mA
CE# = VIL, OE# = VIH
WE# = VIH, burst
length = 16
ICCB
VCC Active burst Read Current
VCC Non-active Output
CE# = VIL, OE# = VIH
WE# = VIH, burst
length = Continuous
IIO1
OE# = VIH
0.2
20
12
3.5
15
0.2
0.2
22
25
0.2
7
10
30
µA
mA
mA
mA
mA
µA
10 MHz
5 MHz
1 MHz
VCC Active Asynchronous Read
Current (Note 2)
CE# = VIL, OE# = VIH
,
ICC1
16
WE# = VIH
5
ICC2
ICC3
ICC4
VCC Active Write Current (Note 3) CE# = VIL, OE# = VIH, ACC = VIH
40
VCC Standby Current (Note 4)
VCC Reset Current
CE# = RESET# = VCC ± 0.2 V
RESET# = VIL, CLK = VIL
50
50
µA
66 MHz
54
mA
mA
µA
VCC Active Current
(Read While Write)
ICC5
ICC6
IACC
CE# = VIL, OE# = VIH
CE# = VIL, OE# = VIH
80 MHz
60
VCC Sleep Current
50
VACC
VCC
15
mA
mA
V
Accelerated Program Current
(Note 5)
CE# = VIL, OE# = VIH,
VACC = 12.0 ± 0.5 V
5
10
VIL
VIH
VOL
VOH
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
–0.5
0.4
VCC + 0.4
0.1
VCC – 0.4
IOL = 100 µA, VCC = VCC min = VIO
IOH = –100 µA, VCC = VCC min
V
V
VCC – 0.1
11.5
Voltage for Autoselect and
Temporary Sector Unprotect
VID
VCC = 1.8 V
12.5
V
VHH
Voltage for Accelerated Program
Low VCC Lock-out Voltage
11.5
1.0
12.5
1.4
V
V
VLKO
Notes:
1. Maximum I specifications are tested with V = V max.
CC
CC
CC
2. The I current listed is typically less than 2 mA/MHz, with OE# at V .
CC
IH
3. I active while Embedded Erase or Embedded Program is in progress.
CC
4. Device enters automatic sleep mode when addresses are stable for t
+ 60 ns. Typical sleep mode current is equal
ACC
to I
.
CC3
5. Total current during accelerated programming is the sum of V
6. 80 MHz applies only to the WS064J.
and V currents.
CC
ACC
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19 Test Conditions
Device
Under
Test
C
L
Figure 19.1 Test Setup
Table 19.1 Test Specifications
Test Condition
All Speed Options
Unit
Output Load Capacitance, CL
(including jig capacitance)
30
pF
Input Rise and Fall Times
2.5 - 3
ns
V
Input Pulse Levels
0.0–VCC
Input timing measurement reference levels
Output timing measurement reference levels
V
CC/2
V
VCC/2
V
20 Key to Switching Waveforms
Waveform
Inputs
Outputs
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
21 Switching Waveforms
VCC
All Inputs and Outputs
VCC/2
VCC/2
Input
Measurement Level
Output
0.0 V
Figure 21.1 Input Waveforms and Measurement Levels
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22 AC Characteristics
VCC Power-up
Parameter
Description
VCC Setup Time
Test Setup
Min
Speed
50
Unit
µs
tVCS
tRSTH
RESET# Low Hold Time
Min
50
µs
Notes:
1. VCC ramp rate is > 1V / 100µs
2. CC ramp rate <1V / 100µs, a Hardware Reset will be required.
V
tVCS
VCC
RESET#
Figure 22.1 VCC Power-up Diagram
22.1 CLK Characterization
80 MHz
(WaitState=6,7)
80 MHz
(WaitState less than 5)
Parameter
Description
66 MHz
Unit
Condition
Max
Min
66.0
80.0
66.0
66.0
18.2
MHz
continuous burst ,
CLK duty 50% +/-
10%
15.2
32.0
MHz
KHz
fCLK
CLK Frequency
8/16/32-word
burst,
CLK duty 50% +/-
10%
Min
-
32.0
Min
Min
Min
39.6
7
-
5
33.0
5
ns
ns
ns
continuous burst
tCLKH
CLK high time
8/16/32-word
burst
tCLKL
tCR
CLK Low Time
CLK Rise Time
CLK Fall Time
7.0
5.0
5.0
Max
3
2.5
2.5
ns
tCF
Note: 80 MHz applies only to the WS064J.
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t
CLK
t
t
CL
CH
CLK
t
t
CF
CR
Note: For WS128J (model numbers 10 and 11), and additional clock cycle is required during boundary crossing while
in continuous read mode.
Figure 22.2 CLK Characterization
22.2 Synchronous/Burst Read
Parameter
80 MHz
(WS064J only)
Description
66 MHz
Unit
JEDEC
Standard
Latency (Standard wait-state Handshake mode) for 8-Word and and
Continuous 16-Word Burst
tIACC
Max
56
71
ns
tIACC
tBACC
tACS
tACH
tBDH
tCR
Latency (Standard wait-state Handshake mode) for 32-Word Burst
Burst Access Time Valid Clock to Output Delay
Address Setup Time to CLK (Note 1)
Address Hold Time from CLK (Note 1)
Data Hold Time from Next Clock Cycle
Chip Enable to RDY Valid
Max
Max
Min
Min
Min
Max
Max
Max
Max
Min
Min
Max
Min
Min
Min
Min
Min
Max
Max
Max
Min
71
84
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11.2
9.1
4
5.5
2
11.2
11.2
9.1
9.1
8
tOE
Output Enable to Output Valid
Chip Enable to High Z
tCEZ
tOEZ
tCES
tRDYS
tRACC
tAAS
tAAH
tCAS
tAVC
tAVD
tACC
tCKA
tCKZ
tOES
Output Enable to High Z
8
CE# Setup Time to CLK
4
RDY Setup Time to CLK
4
Ready Access Time from CLK
Address Setup Time to AVD# (Note 1)
Address Hold Time to AVD# (Note 1)
CE# Setup Time to AVD#
11.2
9.1
4
5.5
0
AVD# Low to CLK
4
AVD# Pulse
10
55
9.1
8
Access Time
55
CLK to access resume
11.2
CLK to High Z
Output Enable Setup Time
4
Notes:
1. Addresses are latched on the first of either the active edge of CLK or the rising edge of AVD#.
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tCEZ
tCES
7 cycles for initial access shown.
CE#
CLK
1
2
3
4
5
6
7
tAVC
AVD#
tAVD
tACS
tBDH
Addresses
Data
Aa
tBACC
tACH
Hi-Z
tIACC
tACC
Da
Da + 1
Da + n
tOEZ
OE#
RDY
tCR
tRACC
tOE
Hi-Z
Hi-Z
tRDYS
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from
two cycles to seven cycles.
2. If any burst address occurs at a 64-word boundary, two additional clock cycle when wait state is set to less than 5 or
three additional clock cycle when wait state is set to 6 & 7 are inserted, and is indicated by RDY.
3. The device is in synchronous mode.
Figure 22.3 CLK Synchronous Burst Mode Read (rising active CLK)
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tCEZ
4 cycles for initial access shown.
tCES
CE#
CLK
1
2
3
4
5
tAVC
AVD#
tAVD
tACS
tBDH
Aa
Addresses
Data
tBACC
tACH
Hi-Z
tIACC
Da
Da + 1
Da + n
tACC
tOEZ
OE#
RDY
tRACC
tOE
tCR
Hi-Z
Hi-Z
tRDYS
Notes:
1. Figure shows total number of wait states set to four cycles. The total number of wait states can be programmed from two
cycles to seven cycles. Clock is set for active falling edge.
2. If any burst address occurs at a 64-word boundary, two additional clock cycle when wait state is set to less than 5 or
three additional clock cycle when wait state is set to 6 & 7 are inserted, clock cycle are inserted, and is indicated by RDY.
3. The device is in synchronous mode.
Figure 22.4 CLK Synchronous Burst Mode Read (Falling Active Clock)
tCEZ
7 cycles for initial access shown.
tCAS
CE#
CLK
1
2
3
4
5
6
7
tAVC
AVD#
tAVD
tAAS
Addresses
Data
Aa
tBACC
tAAH
Hi-Z
tIACC
Da
Da + 1
Da + n
tOEZ
tACC
tBDH
OE#
RDY
tRACC
tCR
tOE
Hi-Z
Hi-Z
tRDYS
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from
two cycles to seven cycles. Clock is set for active rising edge.
2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY.
3. The device is in synchronous mode.
Figure 22.5 Synchronous Burst Mode Read
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7 cycles for initial access shown.
tCES
CE#
CLK
1
2
3
4
5
6
7
tAVC
AVD#
tAVD
tACS
AC
Addresses
Data
tBACC
tACH
tIACC
DC
DD
DE
DF
D8
DB
tBDH
OE#
RDY
tCR
tRACC
tOE
tRACC
Hi-Z
tRDYS
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from
two cycles to seven cycles. Clock is set for active rising edge.
2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY.
3. The device is in synchronous mode with wrap around.
4. D0-D7 in data waveform indicates the order the data within a given 8-word address range, from lowest to highest.
Starting address in figure is the 4th address in range (AC)
Figure 22.6 8-word Linear Burst with Wrap Around
tCEZ
6 wait cycles for initial access shown.
tCES
CE#
1
2
3
4
5
6
CLK
tAVC
AVD#
tAVD
tACS
Aa
Addresses
Data
tBACC
tACH
Hi-Z
tIACC
Da
Da+1
Da+2
Da+3
Da + n
tBDH
tOEZ
tRACC
OE#
RDY
tCR
tOE
Hi-Z
Hi-Z
tRDYS
Notes:
1. Figure assumes 6 wait states for initial access and synchronous read.
2. The Set Configuration Register command sequence has been written with A18=0; device will output RDY one cycle before
valid data.
Figure 22.7 Linear Burst with RDY Set One Cycle Before Data
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22.3 Asynchronous Mode Read
Parameter
80 MHz
(WS064J only)
Description
66 MHz
Unit
JEDEC
Standard
tCE
Max
Max
Min
Min
55
55
55
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Access Time from CE# Low
Asynchronous Access Time
AVD# Low Time
tACC
tAVDP
tAAVDS
tAAVDH
tOE
10
Address Setup Time to Rising Edge of AVD
4
Address Hold Time from Rising Edge of AVD
Output Enable to Output Valid
Min
Max
Min
Min
Max
Min
5.5
11.2
9.1
Read
0
8
8
0
tOEH
Output Enable Hold Time
Toggle and Data# Polling
tOEZ
tCAS
Output Enable to High Z
CE# Setup Time to AVD#
CE#
OE#
tOE
tOEH
WE#
Data
tCE
tOEZ
Valid RD
tACC
RA
Addresses
AVD#
tAAVDH
tCAS
tAVDP
tAAVDS
Note: RA = Read Address, RD = Read Data.
Figure 22.8 Asynchronous Mode Read with Latched Addresses
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CE#
OE#
tOE
tOEH
WE#
Data
tCE
tOEZ
Valid RD
tACC
RA
Addresses
AVD#
Note: RA = Read Address, RD = Read Data.
Figure 22.9 Asynchronous Mode Read
22.4 Hardware Reset (RESET#)
Parameter
Description
All Speed Options
Unit
JEDEC
Std
RESET# Pin Low (During Embedded Algorithms)
tReady
Max
Max
35
µs
ns
to Read Mode (See Note)
RESET# Pin Low (NOT During Embedded Algorithms)
to Read Mode (See Note)
tReady
500
tRP
tRH
RESET# Pulse Width
Min
Min
Min
500
200
20
ns
ns
µs
Reset High Time Before Read (See Note)
RESET# Low to Standby Mode
tRPD
Note: Not 100% tested.
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CE#, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
CE#, OE#
RESET#
tReady
tRP
Figure 22.10 Reset Timings
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22.5 Erase/Program Operations
Parameter
80 MHz
(WS064J only)
Description
66 MHz
Unit
ns
JEDEC
tAVAV
Standard
tWC
Write Cycle Time (Note 1)
Min
Min
45
Synchronous
Asynchronous
Synchronous
Asynchronous
4
0
Address Setup Time (Notes 2,
3)
tAVWL
tAS
ns
5.5
20
10
20
0
tWLAX
tAH
Address Hold Time (Notes 2, 3)
Min
ns
tAVDP
tDS
AVD# Low Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Typ
Typ
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
tDVWH
tWHDX
tGHWL
Data Setup Time
tDH
Data Hold Time
tGHWL
tCAS
Read Recovery Time Before Write
CE# Setup Time to AVD#
CE# Hold Time
0
0
tWHEH
tWLWH
tWHWL
tCH
0
tWP
Write Pulse Width
20
20
0
tWPH
tSR/W
tWHWH1
tWHWH1
Write Pulse Width High
Latency Between Read and Write Operations
Programming Operation (Note 4)
Accelerated Programming Operation (Note 4)
Sector Erase Operation (Notes 4, 5)
Chip Erase Operation (Notes 4, 5)
VACC Rise and Fall Time
tWHWH1
tWHWH1
<7
<4
<0.2
<104
500
1
tWHWH2
tWHWH2
Typ
sec
tVID
tVIDS
tVCS
Min
Min
Min
Min
Min
Min
Min
Min
ns
µs
µs
ns
ns
ns
ns
ns
VACC Setup Time (During Accelerated Programming)
VCC Setup Time
50
0
tELWL
tCS
CE# Setup Time to WE#
tAVSW
tAVHW
tAVHC
tCSW
AVD# Setup Time to WE#
4
AVD# Hold Time to WE#
4
AVD# Hold Time to CLK
4
Clock Setup Time to WE#
5
Notes:
1. Not 100% tested.
2. Asynchronous mode allows both Asynchronous and Synchronous program operation. Synchronous mode allows both
Asynchronous and Synchronous program operation.
3. In asynchronous program operation timing, addresses are latched on the falling edge of WE# or rising edge of AVD#. In
synchronous program operation timing, addresses are latched on the first of either the rising edge of AVD# or the active
edge of CLK.
4. See the Erase and Programming Performance section for more information.
5. Does not include the preprogramming time.
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Program Command Sequence (last two cycles)
Read Status Data
V
IH
CLK
V
IL
tAVDP
AVD#
tAH
tAS
PA
VA
VA
Addresses
Data
555h
In
Complete
A0h
PD
tDS
tDH
Progress
CE#
tCH
OE#
WE#
tWP
tWHWH1
tCS
tWPH
tWC
tVCS
VCC
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. A22–A12 are don’t care during command sequence unlock cycles.
4. CLK can be either VIL or VIH
.
5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Configuration Register.
Figure 22.11 Asynchronous Program Operation Timings: AVD# Latched Addresses
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Program Command Sequence (last two cycles)
Read Status Data
CLK
tACS
tCSW
AVD#
tAVDP
555h
Addresses
Data
PA
VA
VA
In
Complete
A0h
PD
tDS
tDH
Progress
tCAS
tAVSW
CE#
tCH
OE#
WE#
tAH
tWP
tWHWH1
tWPH
tWC
tVCS
VCC
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. A22–A12 are don’t care during command sequence unlock cycles.
4. CLK can be either VIL or VIH
.
5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Configuration Register.
Figure 22.12 Asynchronous Program Operation Timings: WE# Latched Addresses
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Program Command Sequence (last two cycles)
tAVCH
Read Status Data
CLK
tACS
tCSW
AVD#
tAVDP
Addresses
Data
PA
VA
VA
555h
In
Complete
A0h
PD
tDS
tDH
Progress
tCAS
tAVSW
CE#
tCH
OE#
WE#
tAH
tWP
tWHWH1
tWPH
tWC
tVCS
VCC
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. A22–A12 are don’t care during command sequence unlock cycles.
4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK.
5. Either CE# or AVD# is required to go from low to high in between programming command sequences.
6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register. The
Configuration Register must be set to the Synchronous Read Mode.
Figure 22.13 Synchronous Program Operation Timings: WE# Latched Addresses
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Program Command Sequence (last two cycles)
tAVCH
Read Status Data
CLK
tAS
tAH
AVD#
tAVDP
Addresses
Data
PA
VA
VA
555h
In
Complete
A0h
PD
tDS
tDH
Progress
tCAS
CE#
tCH
OE#
WE#
tCSW
tWP
tWHWH1
tWPH
tWC
tVCS
VCC
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. A22–A12 are don’t care during command sequence unlock cycles.
4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK.
5. Either CE# or AVD# is required to go from low to high in between programming command sequences.
6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register. The
Configuration Register must be set to the Synchronous Read Mode.
Figure 22.14 Synchronous Program Operation Timings: CLK Latched Addresses
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Erase Command Sequence (last two cycles)
Read Status Data
V
IH
CLK
V
IL
tAVDP
AVD#
tAH
tAS
SA
555h for
chip erase
VA
VA
Addresses
Data
2AAh
10h for
chip erase
In
Complete
55h
30h
Progress
tDS
tDH
CE#
tCH
OE#
WE#
tWP
tWHWH2
tCS
tWPH
tWC
tVCS
VCC
Notes:
1. SA is the sector address for Sector Erase.
2. Address bits A22–A12 are don’t cares during unlock cycles in the command sequence.
Figure 22.15 Chip/Sector Erase Command Sequence
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CE#
AVD#
WE#
Addresses
Data
PA
Don't Care
A0h
Don't Care
PD
Don't Care
OE#
ACC
tVIDS
1 μs
V
V
ID
tVID
or V
IL
IH
Note: Use setup and hold times from conventional program operation.
Figure 22.16 Accelerated Unlock Bypass Programming Timing
AVD#
CE#
tCEZ
tCE
tOEZ
tCH
tOE
OE#
WE#
tOEH
tACC
Addresses
VA
VA
Status Data
Status Data
Data
Notes:
1. Status reads in figure are shown as asynchronous.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is
complete, and Data# Polling will output true data.
3. While in Asynchronous mode, RDY will be low while the device is in embedded erase or programming mode.
Figure 22.17 Data# Polling Timings (During Embedded Algorithm)
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AVD#
CE#
tCEZ
tCE
tOEZ
tCH
tOE
OE#
WE#
tOEH
tACC
VA
Addresses
Data
VA
Status Data
Status Data
Notes:
1. Status reads in figure are shown as asynchronous.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is
complete, the toggle bits will stop toggling.
3. While in Asynchronous mode, RDY will be low while the device is in embedded erase or programming mode.
Figure 22.18 Toggle Bit Timings (During Embedded Algorithm)
CE#
CLK
AVD#
Addresses
OE#
VA
VA
tIACC
tIACC
Data
Status Data
Status Data
RDY
Notes:
1. The timings are similar to synchronous read timings.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is
complete, the toggle bits will stop toggling.
3. RDY is active with data (A18 = 0 in the Configuration Register). When A18 = 1 in the Configuration Register, RDY is active
one clock cycle before data.
Figure 22.19 Synchronous Data Polling Timings/Toggle Bit Timings
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Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Erase
WE#
Erase
Erase Suspend
Suspend
Program
Complete
Read
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#
to toggle DQ2 and DQ6.
Figure 22.20 DQ2 vs. DQ6
22.6 Temporary Sector Unprotect
Parameter
JEDEC
Std
tVIDR
tVHH
Description
All Speed Options
Unit
ns
VID Rise and Fall Time (See Note)
VHH Rise and Fall Time (See Note)
Min
Min
500
250
ns
RESET# Setup Time for Temporary Sector
Unprotect
tRSP
Min
Min
4
4
µs
µs
RESET# Hold Time from RDY High for
Temporary Sector Unprotect
tRRB
Note: Not 100% tested.
VID
VID
RESET#
VIL or VIH
VIL or VIH
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
RDY
tRRB
tRSP
Figure 22.21 Temporary Sector Unprotect Timing Diagram
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D a t a S h e e t
VID
VIH
RESET#
SA, A6,
A1, A0
Valid*
Valid*
Valid*
Status
Sector Protect/Unprotect
Verify
40h
Data
60h
60h
Sector Protect: 150 µs
Sector Unprotect: 1.5 ms
1 µs
CE#
WE#
OE#
Note: For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 22.22 Sector/Sector Block Protect and Unprotect Timing Diagram
Address boundary occurs every 64 words, beginning at address
00003Fh: 00007Fh, 0000BFh, etc.) Address 000000h is also a boundary crossing.
C60
C61
3D
C62
3E
C63
3F
C63
3F
C63
3F
C63
3F
C64
40
C65
41
C66
42
CLK
3C
Address (hex)
(stays high)
AVD#
RDY(1)
RDY(2)
tRACC
tRACC
latency
tRACC
tRACC
latency
Data
D60
D61
D62
D63
D63
D64
D65
D66
OE#,
CE#f
(stays low)
Notes:
1. RDY active with data (A18 = 0 in the Configuration Register).
2. RDY active one clock cycle before data (A18 = 1 in the Configuration Register).
3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device not
crossing a bank in the process of performing an erase or program.
4. If the starting address latched in is either 3Eh or 3Fh (or some 64 multiple of either), there is no additional 2 cycle latency
at the boundary crossing.
Figure 22.23 Latency with Boundary Crossing
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Address boundary occurs every 64 words, beginning at address
00003Fh: (00007Fh, 0000BFh, etc.) Address 000000h is also a boundary crossing.
C60
C61
3D
C62
3E
C63
3F
C63
3F
C63
3F
C63
3F
C64
40
C65
41
C66
42
CLK
3C
Address (hex)
(stays high)
AVD#
RDY(1)
RDY(2)
tRACC
tRACC
latency
tRACC
tRACC
latency
Data
Invalid
Read Status
D63
D60
D61
D62
D63
OE#,
CE#
(stays low)
Notes:
1. RDY active with data (A18 = 0 in the Configuration Register).
2. RDY active one clock cycle before data (A18 = 1 in the Configuration Register).
3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device crossing
a bank in the process of performing an erase or program.
Figure 22.24 Latency with Boundary Crossing into Program/Erase Bank
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Data
D0
D1
Rising edge of next clock cycle
following last wait state triggers
next burst data
AVD#
OE#
total number of clock cycles
following AVD# falling edge
1
2
0
3
1
4
5
6
4
7
5
CLK
2
3
number of clock cycles
programmed
Wait State Decoding Addresses:
A14, A13, A12 = “111” ⇒ Reserved
A14, A13, A12 = “110” ⇒ Reserved
A14, A13, A12 = “101” ⇒ 5 programmed, 7 total
A14, A13, A12 = “100” ⇒ 4 programmed, 6 total
A14, A13, A12 = “011” ⇒ 3 programmed, 5 total
A14, A13, A12 = “010” ⇒ 2 programmed, 4 total
A14, A13, A12 = “001” ⇒ 1 programmed, 3 total
A14, A13, A12 = “000” ⇒ 0 programmed, 2 total
Note: Figure assumes address D0 is not at an address boundary, active clock edge is rising, and wait state is set to “101”.
Figure 22.25 Example of Wait States Insertion
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Last Cycle in
Program or
Sector Erase
Read status (at least two cycles) in same bank
and/or array data from other bank
Begin another
write or program
command sequence
Command Sequence
tWC
tRC
tRC
tWC
CE#
OE#
tOE
tGHWL
tOEH
WE#
Data
tWPH
tOEZ
tWP
tDS
tACC
tOEH
tDH
PD/30h
RD
RD
AAh
tSR/W
RA
Addresses
PA/SA
tAS
RA
555h
AVD#
tAH
Note: Breakpoints in waveforms indicate that system may alternately read array data from the “non-busy bank” while
checking the status of the program or erase operation in the “busy” bank. The system should read status twice to ensure
valid information.
Figure 22.26 Back-to-Back Read/Write Cycle Timings
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23 Erase and Programming Performance
Parameter
Typ (Note 1)
<0.4
Max (Note 2)
Unit
Comments
32 Kword
4 Kword
128J
<2
<2
Sector Erase Time
s
<0.2
Excludes 00h programming
prior to erasure (Note 4)
<103
Chip Erase Time
s
064J
<53
Excludes system level
overhead (Note 5)
Word Programming Time
<6
<100
<67
µs
µs
Accelerated Word Programming Time
<4
128J
<50.4
<25.2
<33
Chip Programming Time
(Note 3)
Excludes system level
overhead (Note 5)
s
s
064J
128J
Accelerated Chip
Programming Time
064J
<17
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 1.8 V VCC, 100K cycles. Additionally,
programming typicals assumes a checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 1.65 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed.
4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command.
See Table 14.5, “Command Definitions,” on page 77 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 100,000 cycles.
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24 Flash Revision Summary
24.1 Revision A0 (July 22, 2004)
Initial release.
24.2 Revision A1 (October 6, 2004)
Cosmetic changes.
24.3 Revision A2 (December 10, 2004)
Remove all in terms of 104 MHz speed bin.
Change statement of command during time-out period of sector erase.
Change exit command statement about password program command
Change exit command statement about password protection mode locking bit program command
Change exit command statement about persistentsector protection mode locking bit program
command
Change exit command statement about Secured Silicon sector protection bit program command
Change exit command statement about PPB program command
Change exit command statement about All PPB erase command
Change exit command statement about PPB/PPB lock bit status command
Change PPB command table.
Remove note 19 in command table.
Change waveform about boundary crossing.
Remove DC spec output disable status in synchronous read mode.
Change the word from SMPL to PL , from OPBP to OW.
Change the statement PPB Lock Bit Set Command.
Delete VIO pin
Added description at “RDY Configuration” in page56
Modified tAH in Asynchronous mode to 20ns in page89
24.4 Revision A3 (February 19, 2005)
Change "Secsi" to "Secured Silicon"
Add migration statement.
Modify "Sync Latency", "Asyn Access time" @80MHz
Update "Product Selector Guide" on tACC, tCE, tIACC@80MHz
Modify Table 15( "Wait States for Standard Wait-state Handshaking")
Change "Supply Voltage" to "1.70V to 1.95V for 80MHz parts
Modify "CLK Characterization" table
24.5 Revision A4 (June 24, 2005)
Added information for "Revision 1" for boundary crossing while in Continuous read mode
Removed all references to WS128J 80 MHz and WS064J Industrial grades
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113
CellularRAM Type 2
64 Megabit
Burst CellularRAM
ADVANCE
INFORMATION
Features
— Sixteen-word page size
!
Single device supports asynchronous, page,
and burst operations
— Interpage Read access: 70ns
— Intrapage Read access: 20ns
!
VCC, VCCQVoltages
!
!
Low-Power Consumption
— Asynchronous Read < 25 mA
— Intrapage Read < 15 mA
— 1.70 V–1.95 V VCC
— 1.70 V–3.30 V VCCQ
Random Access Time: 70 ns
!
!
— Initial access, burst Read < 35 mA
— Continuous burst Read < 15m A
— Standby: 120 µA
Burst Mode Write Access
— Continuous burst
!
!
Burst Mode Read Access
— 4, 8, or 16 words, or continuous burst
— Deep power-down < 10 µA
Low-Power Features
— Temperature Compensated Refresh (TCR)
— Partial Array Refresh (PAR)
Page Mode Read Access
— Deep Power-Down (DPD) Mode
General Description
CellularRAM™ products are High-speed, CMOS dynamic random access memories developed for low-
power, portable applications. These devices include an industry standard burst mode Flash interface that
dramatically increases Read/Write bandwidth compared with other low-power SRAM or Pseudo SRAM
offerings.
To operate seamlessly on a burst Flash bus, CellularRAM products incorporate a transparent self-refresh
mechanism. The hidden refresh requires no additional support from the system memory controller and
has no significant impact on device Read/Write performance.
Two user-accessible control registers define device operation. The bus configuration register (BCR) de-
fines how the CellularRAM device interacts with the system memory bus and is nearly identical to its
counterpart on burst mode Flash devices. The refresh configuration register (RCR) is used to control how
refresh is performed on the DRAM array. These registers are automatically loaded with default settings
during power-up and can be updated anytime during normal operation.
Special attention has been focused on standby current consumption during self refresh. CellularRAM prod-
ucts include three mechanisms to minimize standby current. Partial array refresh (PAR) enables the
system to limit refresh to only that part of the DRAM array that contains essential data. Temperature com-
pensated refresh (TCR) adjusts the refresh rate to match the device temperature—the refresh rate
decreases at lower temperatures to minimize current consumption during standby. Deep power-down
(DPD) enables the system to halt the refresh operation altogether when no vital information is stored in
the device. The system-configurable refresh mechanisms are accessed through the RCR.
Publication Number CellRam_03 Revision A Amendment 0 Issue Date March 9, 2005
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do
not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
A d v a n c e I n f o r m a t i o n
25 Functional Block Diagram
64M: A[21:0]
Address Decode
Logic
Input/
Output
MUX
and
Buffers
DQ[7:0]
DRAM
MEMORY
ARRAY
DQ[15:8]
Refresh Configuration
Register (RCR)
Bus Configuration
Register (BCR)
CE#
WE#
OE#
CLK
Control
Logic
ADV#
CRE
WAIT
LB#
UB#
Note: Functional block diagrams illustrate simplified device operation. See truth table, ball descriptions, and timing di-
agrams for detailed information.
Figure 25.1 Functional Block Diagram
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A d v a n c e I n f o r m a t i o n
Table 25.1 Signal Descriptions
Symbol
Type
Description
Address Inputs: Inputs for addresses during Read and Write operations. Addresses are
internally latched during Read and Write cycles. The address lines are also used to define
the value to be loaded into the BCR or the RCR.
64M: A[21:0]
Input
Clock: Synchronizes the memory to the system operating frequency during synchronous
operations. When configured for synchronous operation, the address is latched on the first
rising CLK edge when ADV# is active. CLK is static (High or Low) during asynchronous
access Read and Write operations and during Page Read Access operations.
CLK
Input
Input
Address Valid: Indicates that a valid address is present on the address inputs. Addresses
can be latched on the rising edge of ADV# during asynchronous Read and Write operations.
ADV# can be held Low during asynchronous Read and Write operations.
ADV#
CRE
CE#
Input
Input
Configuration Register Enable: When CRE is High, Write operations load the RCR or BCR.
Chip Enable: Activates the device when Low. When CE# is High, the device is disabled and
goes into standby or deep power-down mode.
Output Enable: Enables the output buffers when Low. When OE# is High, the output buffers
are disabled.
OE#
WE#
Input
Input
Write Enable: Determines if a given cycle is a Write cycle. If WE# is Low, the cycle is a Write
to either a configuration register or to the memory array.
LB#
UB#
Input
Input
Lower Byte Enable. DQ[7:0]
Upper Byte Enable. DQ[15:8]
Input/
Output
DQ[15:0]
Data Inputs/Outputs.
Wait: Provides data-valid feedback during burst Read and Write operations. The signal is
gated by CE#. Wait is used to arbitrate collisions between refresh and Read/Write
operations. Wait is asserted when a burst crosses a row boundary. Wait is also used to mask
the delay associated with opening a new internal page. Wait is asserted and should be
ignored during asynchronous and page mode operations. Wait is High-Z when CE# is High.
Wait
Output
VCC
VCCQ
VSS
Supply
Supply
Supply
Supply
Device Power Supply: (1.7V–1.95V) Power supply for device core operation.
I/O Power Supply: (1.7V–3.30V) Power supply for input/output buffers.
VSS must be connected to ground.
VSSQ
VSSQ must be connected to ground.
Note: The CLK and ADV# inputs can be tied to V if the device is always operating in asynchronous or page mode.
SS
Wait will be asserted but should be ignored during asynchronous and page mode operations.
March 9, 2005 CellRam_03_A0
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117
A d v a n c e I n f o r m a t i o n
Table 25.2 Bus Operations—Asynchronous Mode
CLK
(Note 1) ADV#
LB#/
UB#
Wait
(Note 2)
DQ[15:0]
(Note 3)
Mode
Read
Power
Active
Active
Standby
Idle
CE#
L
OE#
L
WE#
CRE
Notes
4
X
X
X
X
L
L
H
L
L
L
L
L
L
L
Low-Z
Low-Z
High-Z
Low-Z
Data-Out
Data-In
High-Z
X
Write
L
X
4
Standby
No Operation
X
X
H
X
X
X
X
X
5, 6
4, 6
L
X
Configuration
Register
Active
X
X
L
L
H
X
L
H
X
X
X
Low-Z
High-Z
High-Z
High-Z
Deep
Power-down
DPD
X
H
X
7
Notes:
1. CLK may be High or Low, but must be static during synchronous Read, synchronous Write, burst suspend, and DPD modes;
and to achieve standby power during standby and active modes.
2. The Wait polarity is configured through the bus configuration register (BCR[10]).
3. When LB# and UB# are in select mode (Low), DQ[15:0] are affected. When only LB# is in select mode, DQ[7:0] are
affected. When only UB# is in the select mode, DQ[15:8] are affected.
4. The device will consume active power in this mode whenever addresses are changed.
5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external
influence.
6. VIN = VCCQ or 0V; all device balls must be static (unswitched) to achieve standby current.
7. DPD is maintained until RCR is reconfigured.
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A d v a n c e I n f o r m a t i o n
Table 25.3 Bus Operations—Burst Mode
CLK
(Note 1) ADV#
LB#/
UB#
Wait
(Note 2)
DQ[15:0]
(Note 3)
Mode
Power
Active
Active
Standby
Idle
CE#
L
OE#
L
WE#
CRE
Notes
4
Async Read
Async Write
Standby
X
X
X
X
L
L
H
L
L
L
L
L
L
Low-Z
Low-Z
High-Z
Low-Z
Data-Out
Data-In
High-Z
X
L
X
L
4
X
X
H
X
X
X
X
5, 6
4, 6
No Operation
L
X
X
Initial Burst Read
Initial Burst Write
Active
Active
L
L
L
L
X
H
H
L
L
L
L
Low-Z
Low-Z
Data-Out
Data-In
4, 8
4, 8
X
Data-In or
Data-Out
Burst Continue
Burst Suspend
Active
Active
Active
H
X
L
L
L
L
X
H
H
X
X
L
L
L
X
X
X
Low-Z
Low-Z
Low-Z
4, 8
4, 8
8
X
X
High-Z
High-Z
Configuration
Register
H
Deep
Power-Down
DPD
X
H
X
X
X
X
High-Z
High-Z
7
Notes:
1. CLK may be High or Low, but must be static during asynchronous Read, synchronous Write, burst suspend, and DPD modes;
and to achieve standby power during standby and active modes.
2. The Wait polarity is configured through the bus configuration register (BCR[10]).
3. When LB# and UB# are in select mode (Low), DQ[15:0] are affected. When only LB# is in select mode, DQ[7:0] are
affected. When only UB# is in the select mode, DQ[15:8] are affected.
4. The device will consume active power in this mode whenever addresses are changed.
5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external
influence.
6. VIN = VCCQ or 0V; all device balls must be static (unswitched) to achieve standby current.
7. DPD is maintained until RCR is reconfigured.
8. Burst mode operation is initialized through the bus configuration register (BCR[15]).
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26 Functional Description
The CellularRAM bus interface supports both asynchronous and burst mode transfers. Page mode
accesses are also included as a bandwidth-enhancing extension to the asynchronous Read
protocol.
26.1 Power-Up Initialization
CellularRAM products include an on-chip voltage sensor used to launch the power-up initialization
process. Initialization will configure the BCR and the RCR with their default settings (see
Table 29.1 and Table 29.4). VCC and VCCQ must be applied simultaneously. When they reach a
stable level at or above 1.7V, the device will require 150 µs to complete its self-initialization pro-
cess. During the initialization period, CE# should remain High. When initialization is complete, the
device is Ready for normal operation.
>
PU
V
= 1.7 V
t
150 μs
CC
Device ready for
normal operation
V
CC
Device Initialization
V
Q
CC
Figure 26.1 Power-Up Initialization Timing
27 Bus Operating Modes
CellularRAM products incorporate a burst mode interface found on Flash products targeting low-
power, wireless applications. This bus interface supports asynchronous, page mode, and burst
mode Read and Write transfers. The specific interface supported is defined by the value loaded
into the BCR. Page mode is controlled by the refresh configuration register (RCR[7]).
27.1 Asynchronous Mode
CellularRAM products power up in the asynchronous operating mode. This mode uses the industry
standard SRAM control bus (CE#, OE#, WE#, LB#/ UB#). Read operations (Figure 27.1) are ini-
tiated by bringing CE#, OE#, and LB#/UB# Low while keeping WE# High. Valid data will be driven
out of the I/Os after the specified access time has elapsed. Write operations (Figure 27.2) occur
when CE#, WE#, and LB#/ UB# are driven Low. During asynchronous Write operations, the OE#
level is a don't care, and WE# will override OE#. The data to be written is latched on the rising
edge of CE#, WE#, or LB#/UB# (whichever occurs first). Asynchronous operations (page mode
disabled) can either use the ADV input to latch the address, or ADV can be driven Low during the
entire Read/Write operation.
During asynchronous operation, the CLK input must be held static (High or Low, no transitions).
Wait will be driven while the device is enabled and its state should be ignored. WE# low time must
be limited to tCEM
.
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CE#
OE#
WE#
ADDRESS
Address Valid
Data Valid
DATA
LB#/UB#
t
RC
= READ Cycle Time
Don't Care
Note: ADV must remain Low for page mode operation.
Figure 27.1 Read Operation (ADV# Low)
CE#
OE#
WE#
ADDRESS
Address Valid
Data Valid
DATA
LB#/UB#
t
= WRITE Cycle Time
WC
Don't Care
Figure 27.2 Write Operation (ADV# Low)
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27.2 Page Mode Read Operation
Page mode is a performance-enhancing extension to the legacy asynchronous Read operation. In
page mode-capable products, an initial asynchronous Read access is performed, then adjacent
addresses can be Read quickly by simply changing the low-order address. Addresses A[3:0] are
used to determine the members of the 16-address CellularRAM page. Addresses A[4] and higher
must remain fixed during the entire page mode access. Figure 27.3 shows the timing for a page
mode access. Page mode takes advantage of the fact that adjacent addresses can be Read in a
shorter period of time than random addresses. Write operations do not include comparable page
mode functionality.
During asynchronous page mode operation, the CLK input must be static (HIGH or LOW - no tran-
sitions). CE# must be driven High upon completion of a page mode access. WAIT is driven while
the device is enabled and its state should be ignored. Page mode is enabled by setting RCR[7] to
High. ADV must be driven Low during all page mode Read accesses. The CE# LOW time is limited
by refresh considerations. CE# must not stay LOW longer than tCEM
.
CE#
OE#
WE#
ADDRESS
ADD[0]
ADD[1] ADD[2] ADD[3]
t
AA
t
t
t
APA
APA
APA
D[0]
D[1]
D[2]
D[3]
DATA
LB#/UB#
Don't Care
Figure 27.3 Page Mode Read Operation (ADV# Low)
27.3 Burst Mode Operation
Burst mode operations enable High-speed synchronous Read and Write operations. Burst opera-
tions consist of a multi-clock sequence that must be performed in an ordered fashion. After CE#
goes Low, the address to access is latched on the rising edge of the next clock that ADV# is Low.
During this first clock rising edge, WE# indicates whether the operation is going to be a Read
(WE# = High, Figure 27.4) or Write (WE# = Low, Figure 27.5).
The size of a burst can be specified in the BCR either as a fixed length or continuous. Fixed-length
bursts consist of four, eight, or sixteen words. Continuous bursts have the ability to start at a
specified address and burst through the entire memory.
The latency count stored in the BCR defines the number of clock cycles that elapse before the
initial data value is transferred between the processor and CellularRAM device.
The WAIT output is asserted as soon as CE# goes LOW, and is de-asserted to indicate when data
is to be transferred into (or out of) the memory. WAIT is again asserted if the burst crosses the
boundary between 128-word rows. Once the CellularRAM device has restored the previous row's
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A d v a n c e I n f o r m a t i o n
data and accessed the next row, Wait will be deasserted and the burst can continue (see
Figure 33.9).
To access other devices on the same bus without the timing penalty of the initial latency for a new
burst, burst mode can be suspended. Bursts are suspended by stopping CLK. CLK can be stopped
High or Low. If another device will use the data bus while the burst is suspended, OE# should be
taken High to disable the CellularRAM outputs; otherwise, OE# can remain Low. Note that the
Wait output will continue to be active, and as a result no other devices should directly share the
Wait connection to the controller. To continue the burst sequence, OE# is taken Low, then CLK is
restarted after valid data is available on the bus.
The CE# low time is limited by refresh considerations. CE# must not stay low longer than tCEM
unless row boundaries are crossed at least every tCEM. If a burst suspension causes CE# to remain
Low for longer than tCEM, CE# should be taken High and the burst restarted with a new CE# Low/
ADV# low cycle.
CLK
Address
Valid
A[22:0]
ADV#
Latency Code 2 (3 clocks), variable
CE#
OE#
WE#
WAIT
DQ[15:0]
LB#/UB#
D[0]
D[1]
D[2]
D[3]
Legend:
READ Burst Identified
(WE# = HIGH)
Don't care
Undefined
Note: Non-default BCR settings: Variable latency; latency code two (three clocks); Wait active Low; Wait asserted dur-
ing delay.
Figure 27.4 Burst Mode Read (4-word burst)
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A d v a n c e I n f o r m a t i o n
CLK
A[22:0]
ADV#
Address
Valid
Latency Code 2 (3 clocks), variable
CE#
OE#
WE#
WAIT
DQ[15:0]
LB#/UB#
D[0]
D[1]
D[2]
D[3]
Legend:
Don't care
WRITE Burst Identified
(WE# = LOW)
Note: Non-default BCR settings: Variable latency; latency code two (three clocks); Wait active Low; Wait asserted dur-
ing delay.
Figure 27.5 Burst Mode Write (4-word burst)
27.4 Mixed-Mode Operation
The device can support a combination of synchronous Read and asynchronous Write operations
when the BCR is configured for synchronous operation. The asynchronous Write operation re-
quires that the clock (CLK) remain static (High or Low) during the entire sequence. The ADV#
signal can be used to latch the target address, or it can remain Low during the entire Write oper-
ation. CE# can remain Low when transitioning between mixed-mode operations with fixed latency
enabled. Note that the tCKA period is the same as a Read or Write cycle. This time is required to
ensure adequate refresh. Mixed-mode operation facilitates a seamless interface to legacy burst
mode Flash memory controllers. See Figure 33.17, Asynchronous Write Followed by Burst Read
(timing diagram).
27.5 Wait Operation
The Wait output on a CellularRAM device is typically connected to a shared, system-level Wait sig-
nal (Figure 27.6). The shared Wait signal is used by the processor to coordinate transactions with
multiple memories on the synchronous bus.
External
Pull-Up/
Pull-Down
Resistor
CellularRAM
WAIT
READY
WAIT
WAIT
Other
Other
Device
Device
Processor
Figure 27.6 Wired or Wait Configuration
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Once a Read or Write operation has been initiated, Wait goes active to indicate that the Cellular-
RAM device requires additional time before data can be transferred. For Read operations, Wait will
remain active until valid data is output from the device. For Write operations, Wait will indicate to
the memory controller when data will be accepted into the CellularRAM device. When Wait tran-
sitions to an inactive state, the data burst will progress on successive clock edges.
CE# must remain asserted during Wait cycles (Wait asserted and Wait configuration BCR[8] = 1).
Bringing CE# High during Wait cycles may cause data corruption. (Note that for BCR[8] = 0, the
actual Wait cycles end one cycle after Wait de-asserts, and for row boundary crossings, start one
cycle after the Wait signal asserts.)
The WAIT output also performs an arbitration role when a Read or Write operation is launched
while an on-chip refresh is in progress. If a collision occurs, the Wait pin is asserted for additional
clock cycles until the refresh has completed (Figure 27.7 and Figure 27.8). When the refresh op-
eration has completed, the Read or Write operation will continue normally.
Wait is also asserted when a continuous Read or Write burst crosses the boundary between 128-
word rows. The Wait assertion allows time for the new row to be accessed, and permits any pend-
ing refresh operations to be performed.
27.6 LB#/UB# Operation
The LB# enable and UB# enable signals support byte-wide data transfers. During Read opera-
tions, the enabled byte(s) are driven onto the DQs. The DQs associated with a disabled byte are
put into a High-Z state during a Read operation. During Write operations, any disabled bytes will
not be transferred to the RAM array and the internal value will remain unchanged. During an asyn-
chronous Write cycle, the data to be written is latched on the rising edge of CE#, WE#, LB#, or
UB#, whichever occurs first.
When both the LB# and UB# are disabled (High) during an operation, the device will disable the
data bus from receiving or transmitting data. Although the device will seem to be deselected, it
remains in an active mode as long as CE# remains Low.
V
V
IH
IL
CLK
A[22:0]
ADV#
V
V
IH
IL
Address
Valid
V
V
IH
IL
V
V
IH
IL
CE#
OE#
V
V
IH
IL
V
V
IH
IL
WE#
V
V
IH
IL
LB#/UB#
High-Z
V
V
OH
OL
WAIT
V
V
OH
OL
DQ[15:0]
D[0]
D[1]
D[2]
D[3]
Additional WAIT states inserted to allow refresh completion.
Legend:
Don't care
Undefined
Note: Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay.
Figure 27.7 Refresh Collision During Read Operation
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A d v a n c e I n f o r m a t i o n
V
V
IH
IL
CLK
A[22:0]
ADV#
V
V
IH
IL
Address
Valid
V
V
IH
IL
V
V
IH
IL
CE#
OE#
V
V
IH
IL
V
V
IH
IL
WE#
V
V
IH
IL
LB#/UB#
High-Z
V
V
OH
OL
WAIT
V
V
OH
OL
DQ[15:0]
D[0]
D[1]
D[2]
D[3]
Additional WAIT states inserted to allow refresh completion.
Legend:
Don't care
Note: Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay.
Figure 27.8 Refresh Collision During Write Operation
28 Low-Power Operation
28.1 Standby Mode Operation
During standby, the device current consumption is reduced to the level necessary to perform the
DRAM refresh operation. Standby operation occurs when CE# is High.
The device will enter a reduced power state upon completion of a Read or Write operation, or
when the address and control inputs remain static for an extended period of time. This mode will
continue until a change occurs to the address or control inputs.
28.2 Temperature Compensated Refresh
Temperature compensated refresh (TCR) is used to adjust the refresh rate depending on the de-
vice operating temperature. DRAM technology requires increasingly frequent refresh operation to
maintain data integrity as temperatures increase. More frequent refresh is required due to in-
creased leakage of the DRAM capacitive storage elements as temperatures rise. A decreased
refresh rate at lower temperatures will facilitate a savings in standby current.
TCR allows for adequate refresh at four different temperature thresholds (+15°C, +45°C, +70°C,
and +85°C). The setting selected must be for a temperature higher than the case temperature
of the CellularRAM device. For example, if the case temperature is 50°C, the system can minimize
self refresh current consumption by selecting the 70°C setting. The +15°C and +45°C settings
would result in inadequate refreshing and cause data corruption.
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28.3 Partial Array Refresh
Partial array refresh (PAR) restricts refresh operation to a portion of the total memory array. This
feature enables the device to reduce standby current by refreshing only that part of the memory
array required by the host system. The refresh options are full array, one-half array, one-quarter
array, three-quarter array, or none of the array. The mapping of these partitions can start at either
the beginning or the end of the address map (Table 29.5). Read and Write operations to address
ranges receiving refresh will not be affected. Data stored in addresses not receiving refresh will
become corrupted. When re-enabling additional portions of the array, the new portions are avail-
able immediately upon writing to the RCR.
28.4 Deep Power-Down Operation
Deep power-down (DPD) operation disables all refresh-related activity. This mode is used if the
system does not require the storage provided by the CellularRAM device. Any stored data will be-
come corrupted when DPD is enabled. When refresh activity has been re-enabled by rewriting the
RCR, the CellularRAM device will require 150µs to perform an initialization procedure before nor-
mal operations can resume. During this 150µs period, the current consumption will be higher than
the specified standby levels, but considerably lower than the active current specification.
DPD cannot be enabled or disabled by writing to the RCR using the software access sequence;
the RCR should be accessed using CRE instead.
29 Configuration Registers
Two user-accessible configuration registers define the device operation. The bus configuration
register (BCR) defines how the CellularRAM interacts with the system memory bus and is nearly
identical to its counterpart on burst mode Flash devices. The refresh configuration register (RCR)
is used to control how refresh is performed on the DRAM array. These registers are automatically
loaded with default settings during power-up, and can be updated any time the devices are op-
erating in a standby state.
29.1 Access Using CRE
The configuration registers are loaded using either a synchronous or an asynchronous operation
when the configuration register enable (CRE) input is High (see Figure 29.2). When CRE is Low,
a Read or Write operation will access the memory array. The register values are written via ad-
dress pins A[21:0]. In an asynchronous Write, the values are latched into the configuration
register on the rising edge of ADV#, CE#, or WE#, whichever occurs first; LB# and UB# are Don’t
Care. The BCR is accessed when A[19] is High; the RCR is accessed when A[19] is Low.
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CLK
A[21:0]
(except A19)
OPCODE
ADDRESS
ADDRESS
t
t
AVH
t
AVS
Select Control Register
A191
CRE
t
AVS
AVH
t
VPH
ADV#
CE#
t
VP
t
CBPH
Initiate Control Register Access
t
CW
OE#
t
WP
Write Address Bus Value
to Control Register
WE#
LB#/UB#
DQ[15:0]
DATA VALID
DON’T CARE
Note: A[19] = LOW to load RCR; A[19] = HIGH to load BCR.
Figure 29.1 Configuration Register WRITE in Asynchronous Mode Followed by READ
ARRAY Operation
CLK
Latch Control Register Value
A[21:0]
(except A19)
ADDRESS
ADDRESS
OPCODE
t
HD
t
Latch Control Register Address
SP
A192
CRE
t
SP
t
t
HD
t
SP
ADV#
HD
3
t
CBPH
t
CSP
CE#
OE#
t
SP
t
WE#
HD
LB#/UB#
t
CW
WAIT
High-Z
High-Z
Data
Valid
DQ[15:0]
DON’T CARE
Note: A[19] = Low to load RCR; A[19] = High to load BCR.
Figure 29.2 Configuration Register WRITE in Synchronous Mode Followed
by READ ARRAY Operation
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29.2 Software Access
Software access of the configuration registers uses a sequence of asynchronous READ and asyn-
chronous WRITE operations. The contents of the configuration registers can be read or modified
using the software sequence.
The configuration registers are loaded using a four step sequence consisting of two asynchronous
READ operations followed by two asynchronous WRITE operations (see Figure 29.3). The read se-
quence is virtually identical except that an asynchronous READ is performed during the fourth
operation (see Figure 29.4). Note that a third READ cycle cancels the access sequence.
The address used during all READ and WRITE operations is the highest address of the CellularRAM
device being accessed (3FFFFFh for 64Mb); the content at this address is changed by using this
sequence (note that this is a deviation from the CellularRAM specification).
The data value presented during the third operation (WRITE) in the sequence defines whether the
BCR or the RCR is to be accessed. If the data is 0000h, the sequence will access the RCR; if the
data is 0001h, the sequence will access the BCR. During the fourth operation, the data bus is used
to transfer data in to or out of the configuration registers.
The use of the software sequence does not affect the ability to perform the standard (CRE-con-
trolled) method of loading the configuration registers. However, the software nature of this access
mechanism eliminates the need for the control register enable (CRE) pin. If the software mecha-
nism is used, the CRE pin can simply be tied to VSS. The port line often used for CRE control
purposes is no longer required.
Software access of the RCR should not be used to enter or exit DPD.
READ
READ
WRIT1E
WRITE
ADDRESS
(MAX)
ADDRESS
(MAX)
ADDRESS
(MAX)
ADDRESS
(MAX)
ADDRESS
CE#
OE#
WE#
LB#/UB#
CRVALUE
IN
DATA
XXXXh
XXXXh
RCR0:000h
BCR0:001h
DON'TCARE
Notes:
1. The WRITE on the third cycle must be CE# controlled.
Figure 29.3 Load Configuration Register
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A d v a n c e I n f o r m a t i o n
READ
READ
WRITE 1
READ
ADDRESS
(MAX)
ADDRESS
(MAX)
ADDRESS
(MAX)
ADDRESS
(MAX)
ADDRESS
CE#
NOTE 2
OE#
WE#
LB#/UB#
CRValue
Out
DATA
XXXXh
XXXXh
RCR0:000h
BCR0:001h
DON'TCARE
Notes:
1. The WRITE on the third cycle must be CE# controlled.
2. CE# must be HIGH for 150ns before performing the cycle that reads a configura-
tion register.
Figure 29.4 Read Configuration Register
29.3 Bus Configuration Register
The BCR defines how the CellularRAM device interacts with the system memory bus. Page mode
operation is enabled by a bit contained in the RCR. Table 29.1 below describes the control bits in
the BCR. At power-up, the BCR is set to 9D4Fh.
The BCR is accessed using CRE and A[19] High, or through the configuration register software
sequence with DQ = 0001h on the third cycle.
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Table 29.1 Bus Configuration Register Definition
A[21:20]A19 A[18:16] A15
A14 A13A12A11 A10
A9
A8
A7
A6
A5
A4
A3
3
A2A1A0
21–20
19
18–16
15
14
13 12 11
10
9
8
7
6
5
4
2
1
0
Register
Select
Operating
Mode
Latency
Counter
WAIT
Polarity
WAIT
Configuration (WC)
Clock
Output
Burst
Burst
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Configuration (CC) Impedance
Wrap (BW)*Length (BL)*
Must be set to "0"
Must be set to "0"
Must be set to "0"
Must be set to "0"
Must be set to "0"
All must be set to "0"
BCR[13]BCR[12] BCR[11]
Latency Counter
Code 0–Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Code 1–Reserved
Code
Code
2
3
(Default)
Code 4–Reserved
Code 5–Reserved
Code 6–Reserved
Code 7–Reserved
BCR[3]
0
Burst Wrap (Note 1)
Burst wraps within the burst length
Burst no wrap (default)
1
BCR[10]
0
WAIT Polarity
Active LOW
1
Active HIGH (default)
Output Impedance
BCR[5]
Full Drive (default)
1/4 Drive
0
1
BCR[8]
WAIT Configuration
Asserted during delay
BCR[6]
0
1
Clock Configuration
Not supported
Rising edge (default)
Asserted one data cycle before delay (default)
0
1
BCR[15]
Operation Mode
0
1
Synchronous burst access mode
Asynchronous access mode (default)
Burst Length (Note 1)
BCR[2] BCR[1]BCR[0]
0
0
0
1
0
1
1
1
1
0
1
1
4
8
words
words
BCR[19]
Register Select
16 words
Continuous burst (default)
0
1
Select RCR
Select BCR
Note: All burs WRITEs are continuous.
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Table 29.2 Sequence and Burst Length
4-word
Burst
Starting
Burst Wrap
Address Length 8-word Burst Length
16-word Burst Length
Continuous Burst
BCR[3] Wrap (Decimal) Linear
Linear
Linear
Linear
0-1-2-3-4-5-6-…
1-2-3-4-5-6-7-…
2-3-4-5-6-7-8-…
3-4-5-6-7-8-9-…
4-5-6-7-8-9-10-…
5-6-7-8-9-10-11-…
6-7-8-9-10-11-12-…
7-8-9-10-11-12-13-…
…
0
1
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15
1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0
2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1
3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2
4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3
5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4
6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5
7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6
…
2
3
4
5
0
Yes
6
7
…
14
15
0
14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13
15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15
1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16
2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-17
3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18
4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-19
5-6-7-8-9-10-11-12-13-…-15-16-17-18-19-20
6-7-8-9-10-11-12-13-14-…-16-17-18-19-20-21
7-8-9-10-11-12-13-14-…-17-18-19-20-21-22
…
14-15-16-17-18-19-20-…
15-16-17-18-19-20-21…
0-1-2-3-4-5-6-…
1-2-3-4-5-6-7-…
2-3-4-5-6-7-8-…
3-4-5-6-7-8-9-…
4-5-6-7-8-9-10-…
5-6-7-8-9-10-11…
6-7-8-9-10-11-12…
7-8-9-10-11-12-13…
…
0-1-2-3
1-2-3-4
2-3-4-5
3-4-5-6
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-8
1
2
2-3-4-5-6-7-8-9
3
3-4-5-6-7-8-9-10
4-5-6-7-8-9-10-11
5-6-7-8-9-10-11-12
6-7-8-9-10-11-12-13
7-8-9-10-11-12-13-14
4
5
1
No
6
7
…
14
15
14-15-16-17-18-19-…-23-24-25-26-27-28-29
15-16-17-18-19-20-…-24-25-26-27-28-29-30
14-15-16-17-18-19-20-…
15-16-17-18-19-20-21-…
29.3.1 Burst Length (BCR[2:0]): Default = Continuous Burst
Burst lengths define the number of words the device outputs during burst Read operations. The
device supports a burst length of 4, 8, or 16 words. The device can also be set in continuous burst
mode where data is output sequentially without regard to address boundaries; the internal ad-
dress wraps to 000000h if the device is read past the last address. Write bursts are always
performed using continuous burst mode.
29.3.2 Burst Wrap (BCR[3]): Default = No Wrap
The burst-wrap option determines if a 4-, 8-, or 16-word Read burst wraps within the burst length
or steps through sequential addresses. If the wrap option is not enabled, the device accesses data
from sequential addresses without regard to burst boundaries; the internal address wraps to
000000h if the device is read past the last address.
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29.3.3 Output Impedance (BCR[5]): Default = Outputs Use Full Drive
Strength
The output driver strength can be altered to full, one-half, or one-quarter strength to adjust for
different data bus loading scenarios. The reduced-strength options are intended for stacked chip
(Flash + CellularRAM) environments when there is a dedicated memory bus. The reduced-drive-
strength option minimizes the noise generated on the data bus during Read operations. Normal
output drive strength should be selected when using a discrete CellularRAM device in a more
heavily loaded data bus environment. Outputs are configured at full drive strength during testing.
29.3.4 Wait Configuration (BCR[8]): Default = Wait Transitions One
Clock Before Data Valid/Invalid
The Wait configuration bit is used to determine when Wait transitions between the asserted and
the de-asserted state with respect to valid data presented on the data bus. The memory controller
will use the Wait signal to coordinate data transfer during synchronous Read and Write operations.
When BCR[8] = 0, data will be valid or invalid on the clock edge immediately after Wait transitions
to the de-asserted or asserted state, respectively (Figure 29.5 and Figure 29.7). When A8 = 1,
the Wait signal transitions one clock period prior to the data bus going valid or invalid
(Figure 29.6).
29.3.5 Wait Polarity (BCR[10]): Default = Wait Active High
The Wait polarity bit indicates whether an asserted Wait output should be High or Low. This bit
will determine whether the Wait signal requires a pull-up or pull-down resistor to maintain the de-
asserted state.
CLK
WAIT
High-Z
DQ[15:0]
Data[0]
Data[1]
Data immediately valid (or invalid)
Note: Data valid/invalid immediately after Wait transitions (BCR[8] = 0). See Figure 29.7.
Figure 29.5 Wait Configuration (BCR[8] = 0)
CLK
WAIT
High-Z
DQ[15:0]
Data[0]
Data valid (or invalid) after one clock delay
Note: Valid/invalid data delayed for one clock after Wait transitions (BCR[8] = 1). See Figure 29.7.
Figure 29.6 Wait Configuration (BCR[8] = 1)
March 9, 2005 CellRam_03_A0
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A d v a n c e I n f o r m a t i o n
CLK
BCR[8] = 0
DATA VALID IN CURRENT CYCLE
WAIT
BCR[8] = 1
DATA VALID IN NEXT CYCLE
WAIT
DQ[15:0]
D[0]
D[1]
D[2]
D[3]
D[4]
Legend:
Don't care
Note: Non-default BCR setting: Wait active Low.
Figure 29.7 Wait Configuration During Burst Operation
29.3.6 Latency Counter (BCR[13:11]): Default = Three-Clock Latency
The latency counter bits determine how many clocks occur between the beginning of a Read or
Write operation and the first data value transferred. Latency codes from two (three clocks) to six
(seven clocks) are allowed (see Table 29.3 and Figure 29.8 below).
Table 29.3 Variable Latency Configuration Codes
Max Input Clk Frequency (MHz)
Latency Configuration Code
2 (3 clocks)
70 ns/80 MHz
53 (18.75 ns)
80 (12.5 ns)
70 ns/66 MHz
44 (22.7 ns)
66 (15.2 ns)
3 (4 clocks)—default
Note: Clock rates below 50MHz are allowed as long as t
specifications are met.
CSP
V
IH
CLK
V
IL
V
IH
A[21:0]
Valid Address
V
IL
V
IH
ADV#
A/DQ[15:0]
A/DQ[15:0]
V
IL
Code 2
V
V
OH
OL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Code 3
(Default)
V
V
OH
OL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Legend:
Don't care
Undefined
Figure 29.8 Latency Counter (Variable Initial Latency, No Refresh Collision)
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29.3.7 Operating Mode (BCR[15]): Default = Asynchronous Operation
The operating mode bit selects either synchronous burst operation or the default asynchronous
mode of operation.
29.4 Refresh Configuration Register
The refresh configuration register (RCR) defines how the CellularRAM device performs its trans-
parent self refresh. Altering the refresh parameters can dramatically reduce current consumption
during standby mode. Page mode control is also embedded into the RCR. Table 29.4 below de-
scribes the control bits used in the RCR. At power-up, the RCR is set to 0070h. The RCR is
accessed using CRE and A[19] Low, or through the configuration register software access se-
quence with DQ = 0000h on the third cycle.
Table 29.4 Refresh Configuration Register Mapping
A[21:20]
A19
A[18:8]
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus
21–20
Reserved
19
18–8
Reserved
7
6
5
4
3
2
1
0
Read Configuration
Register
Register
Select
Page
TCR
DPD
Reserved
PAR
Must be set to "0"
All must be set to "0"
All must be set to "0"
RCR[19] Register Select
RCR[2] RCR[1] RCR[0] Refresh Coverage
0
1
Select RCR
Select BCR
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Full array (default)
Bottom 1/2 array
Bottom 1/4 array
Bottom 1/8 array
None of array
RCR[7]
Page Mode Enable/Disable
Page Mode Disabled (default)
Page Mode Enable
0
1
Top 1/2 array
Top 1/4 array
Maximum Case Temp
RCR[6]
RCR[5]
Top 3/4 array
1
1
0
1
0
+85ºC (default)
+70ºC
0
0
1
RCR[4]
Deep Power-Down
DPD Enable
+45ºC
0
1
+15ºC
DPD Disable (default)
29.4.1 Partial Array Refresh (RCR[2:0]): Default = Full Array Refresh
The PAR bits restrict refresh operation to a portion of the total memory array. This feature allows
the device to reduce standby current by refreshing only that part of the memory array required
by the host system. The refresh options are full array, one-half array, one-quarter array, three-
quarters array, or none of the array. The mapping of these partitions can start at either the be-
ginning or the end of the address map (see Table 29.5).
Table 29.5 64Mb Address Patterns for PAR (RCR[4] = 1)
RCR[2]
RCR[1]
RCR[0]
Active Section
Full die
Address Space
Size
Density
64Mb
32Mb
16Mb
8Mb
0
0
0
0
0
0
1
1
0
1
0
1
000000h–3FFFFFh
000000h–2FFFFFh
000000h–1FFFFFh
000000h–0FFFFFh
4 Meg x 16
2 Meg x 16
1 Meg x 16
512 K x 16
One-half of die
One-quarter of die
One-eighth of die
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A d v a n c e I n f o r m a t i o n
Table 29.5 64Mb Address Patterns for PAR (RCR[4] = 1) (Continued)
RCR[2]
RCR[1]
RCR[0]
Active Section
None of die
Address Space
0
Size
Density
0Mb
1
1
1
1
0
0
1
1
0
1
0
1
0 Meg x 16
2 Meg x 16
1 Meg x 16
512 K x 16
One-half of die
One-quarter of die
One-eighth of die
100000h–3FFFFFh
200000h–3FFFFFh
300000h–3FFFFFh
32Mb
16Mb
8Mb
29.4.2 Deep Power-Down (RCR[4]): Default = DPD Disabled
The deep power-down bit enables and disables all refresh-related activity. This mode is used if
the system does not require the storage provided by the CellularRAM device. Any stored data will
become corrupted when DPD is enabled. When refresh activity has been re-enabled, the Cellular-
RAM device will require 150µs to perform an initialization procedure before normal operations can
resume.
Deep power-down is enabled when RCR[4] = 0, and remains enabled until RCR[4] is set to 1.
29.4.3 Temperature Compensated Refresh (RCR[6:5]): Default = +85ºC
Operation
The TCR bits allow for adequate refresh at four different temperature thresholds (+15ºC, +45ºC,
+70ºC, and +85ºC). The setting selected must be for a temperature higher than the case tem-
perature of the CellurlarRAM device. If the case temperature is +50ºC, the system can minimize
self refresh current consumption by selecting the +70ºC setting. The +15ºC and +45ºC settings
would result in inadequate refreshing and cause data corruption.
29.4.4 Page Mode Operation (RCR[7]): Default = Disabled
The page mode operation bit determines whether page mode is enabled for asynchronous Read
operations. In the power-up default state, page mode is disabled.
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A d v a n c e I n f o r m a t i o n
30 Absolute Maximum Ratings
Voltage to Any Ball Except VCC, VCCQ Relative to VSS -0.50V to (4.0V or VCCQ
0.3V, whichever is less)
+
Voltage on VCC Supply Relative to VSS . . . . . . . . . . . . . . . . -0.2V to +2.45V
Voltage on VCCQ Supply Relative to VSS . . . . . . . . . . . . . . . . . -0.2V to +4.0V
Storage Temperature (plastic) . . . . . . . . . . . . . . . . . . . . . . -55ºC to +150ºC
Operating Temperature (case)
Wireless (See Note)-30ºC to +85ºC
Industrial-40°C to +85°C
Soldering Temperature and Time
10s (lead only)+260°C
Note: -30°C exceeds the CellularRAM Workgroup 1.0 specification of -25°C.
Stresses greater than those listed may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure to absolute max-
imum rating conditions for extended periods may affect reliability.
March 9, 2005 CellRam_03_A0
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A d v a n c e I n f o r m a t i o n
31 DC Characteristics
Table 31.1 Electrical Characteristics and Operating Conditions
Description
Conditions
Symbol
Min
1.70
Max
1.95
Units
V
Notes
Supply Voltage
VCC
I/O Supply Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage Current
VCC
VIH
VIL
Q
W: 1.8V
1.70
3.30
V
1.4
VCCQ + 0.2
0.4
V
2
3
4
4
-0.20
0.80 VCC
V
IOH = -0.2mA
IOL = +0.2mA
VOH
VOL
ILI
Q
V
0.20 VCC
Q
V
VIN = 0 to VCC
Q
1
µA
OE# = VIH or
Chip Disabled
Output Leakage Current
ILO
1
µA
Operating Current
-70
Asynchronous Random Read
Asynchronous Page Read
V
IN = VCCQ or 0V
Chip Enabled,
IOUT = 0
25
15
ICC1
mA
5
5
-70
80 MHz
66 MHz
80 MHz
66 MHz
80 MHz
66 MHz
35
30
18
15
35
30
Initial Access, Burst Read
Continuous Burst Read
Continuous Burst Write
VIN = VCCQ or 0V
Chip Enabled,
IOUT = 0
ICC
1
mA
VIN = VCCQ or 0V
Chip Enabled, IOUT = 0
ICC2
mA
µA
5
6
VIN = VCCQ or 0V
Standby Current
ISB
64 M
120
CE# = VCC
Q
Notes:
1. Wireless Temperature (-25ºC < TC < +85ºC); Industrial Temperature (-40ºC < TC < +85ºC).
2. Input signals may overshoot to VCCQ + 1.0V for periods less than 2ns during transitions.
3. Input signals may undershoot to VSS - 1.0V for periods less than 2ns during transitions.
4. BCR[5:4] = 00b.
5. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add the current
required to drive output capacitance expected in the actual system.
6. ISB (MAX) values measured with PAR set to FULL ARRAY and TCR set to +85°C. To achieve Low standby current, all inputs
must be driven to either VCCQ or VSS
.
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Table 31.2 Maximum Standby Currents for Applying PAR and TCR Settings
TCR
PAR
+15°C (RCR[6:5] = 10b)
+45°C (RCR[6:5] = 01b)
+85°C (RCR[6:5] = 11b)
Full Array
1/2 Array
1/4 Array
1/8 Array
70
65
60
57
50
120
115
110
105
70
85
80
75
70
55
0 Array
Notes:
1. For RCR[6:5] = 00b (default), refer to Figure 31.1 for typical values.
2. In order to achieve low standby current, all inputs must be driven to either VCCQ or VSS. ISB might be slightly higher for up
to 500ms after power-up, or after changes to the PAR array partition.
3. Values of TCR for 85 are 100% tested. Values of TCR for 15 and 45 are sampled only.
70
60
50
PAR = Full Array
PAR = 1/2 of Array
PAR = 1/4 of Array
PAR = 1/8 of Array
PAR = None of Array
40
30
20
10
0
-30
-20
-10
0
10
20
Temperature (°C)
Note: Typical ISB currents for each PAR setting with the appropriate TCR selected, or temperature sensor enabled.
30
40
50
60
70
80
90
Figure 31.1 Typical Refresh Current vs. Temperature (ITCR
)
Table 31.3 Deep Power-Down Specifications
Description
Conditions
Symbol
Typ
Units
Deep Power-down
VIN = VCCQ or 0V; +25°C
IZZ
10
µA
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A d v a n c e I n f o r m a t i o n
32 AC Characteristics
V
CC
Q
V
Q/2
VCC/2
Note 2
CC
Input
(Note 1)
Output
Test Points
(Note 3)
V
SS
Notes:
1. AC test inputs are driven at VCCQ for a logic 1 and VSS for a logic 0. Input rise and fall times (10% to 90%) < 1.6ns.
2. Input timing begins at VCC/2. Due to the possibility of a difference between VCC and VCCQ, the input test point may not be
shown to scale.
3. Output timing ends at VCCQ/2.
Figure 32.1 AC Input/Output Reference Waveform
Table 32.1 Capacitance
Description
Conditions
Symbol
CIN
Min
2.0
3.5
Max
6
Units
pF
Notes
Input Capacitance
1
1
TC = +25ºC; f = 1 MHz; VIN = 0V
Input/Output Capacitance (DQ)
CIO
6
pF
Notes:
1. These parameters are verified in device characterization and are not 100% tested.
V
Q
CC
R1
Test Point
DUT
30pF
R2
Note: All tests are performed with the outputs configured for full drive strength (BCR[5] = 0).
Figure 32.2 Output Load Circuit
Table 32.2 Output Load Circuit
VCCQ
R1/R2
1.8 V
2.5 V
3.0 V
2.7 K
3.7 K
4.5 K
Ω
Ω
Ω
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Table 32.3 Asynchronous Read Cycle Timing Requirements
70ns
Units
Notes
Parameter
Address Access Time
Symbol
tAA
Min
Max
70
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADV# Access Time
tAADV
tAPA
tAVH
tAVS
tBA
70
Page Access Time
20
Address Hold from ADV# High
Address Setup to ADV# High
LB#/UB# Access Time
5
10
70
8
LB#/UB# Disable to DQ High-Z Output
LB#/UB# Enable to Low-Z Output
Maximum CE# Pulse Width
CE# Low to Wait Valid
tBHZ
tBLZ
tCEM
tCEW
tCO
4
3
10
1
8
7.5
70
Chip Select Access Time
CE# Low to ADV# High
tCVS
tHZ
10
10
5
Chip Disable to DQ and Wait High-Z Output
Chip Enable to Low-Z Output
Output Enable to Valid Output
Output Hold from Address Change
Output Disable to DQ High-Z Output
Output Enable to Low-Z Output
Page Cycle Time
8
20
8
4
3
tLZ
tOE
tOH
tOHZ
tOLZ
tPC
4
3
5
20
70
10
10
Read Cycle Time
tRC
ADV# Pulse Width Low
tVP
ADV# Pulse Width High
tVPH
Notes:
1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0).
2. High-Z to Low-Z timings are tested with the circuit shown in Figure 32.2. The Low-Z timings measure a 100mV transition
away from the High-Z (VCCQ/2) level toward either VOH or VOL
.
3. Low-Z to High-Z timings are tested with the circuit shown in Figure 32.2. The High-Z timings measure a 100mV transition
from either VOH or VOL toward VCCQ/2.
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Table 32.4 Burst Read Cycle Timing Requirements
70ns/80 MHz
70ns/66 MHz
Parameter
Burst to Read Access Time (Variable Latency)
CLK to Output Delay
Symbol
tABA
tACLK
tBOE
tCBPH
tCEW
tCLK
tCSP
tHD
Min
Max
46.5
9
Min
Max
56
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
Notes
11
Burst OE# Low to Output Delay
CE# High between Subsequent Mixed-Mode Operations
CE# Low to Wait Valid
20
20
5
1
5
1
7.5
20
20
7.5
20
20
CLK Period
12.5
4.5
2
15
5
CE# Setup Time to Active CLK Edge
Hold Time from Active CLK Edge
Chip Disable to DQ and Wait High-Z Output
CLK Rise or Fall Time
2
tHZ
8
1.8
9
8
2.0
11
8
2
tKHKL
tKHTL
tKHZ
tKLZ
CLK to Wait Valid
CLK to DQ High-Z Output
3
2
2
4
8
3
2
2
5
CLK to Low-Z Output
5
5
Output Hold from CLK
tKOH
tKP
CLK High or Low Time
Output Disable to DQ High-Z Output
Output Enable to Low-Z Output
Setup Time to Active CLK Edge
tOHZ
tOLZ
tSP
8
8
8
8
2
3
5
3
5
3
Maximum CE# Pulse Width
tCBPH
2
Notes:
1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0).
2. Low-Z to High-Z timings are tested with the circuit shown in Figure 32.2. The High-Z timings measure a 100mV transition
from either VOH or VOL toward VCCQ/2.
3. High-Z to Low-Z timings are tested with the circuit shown in Figure 32.2. The Low-Z timings measure a 100mV transition
away from the High-Z (VCCQ/2) level toward either VOH or VOL
.
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Table 32.5 Asynchronous Write Cycle Timing Requirements
70 ns
Parameter
Address and ADV# Low Setup Time
Address Hold from ADV# Going High
Address Setup to ADV# Going High
Address Valid to End of Write
LB#/UB# Select to End of Write
CE# Low to Wait Valid
Symbol
tAS
Min
0
Max
7.5
8
Units
ns
Notes
tAVH
tAVS
tAW
5
ns
10
70
70
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tBW
tCEW
tCKA
tCVS
tCW
tDH
Async Address-to-Burst Transition Time
CE# Low to ADV# High
70
10
70
0
Chip Enable to End of Write
Data Hold from Write Time
Data Write Setup Time
tDW
tHZ
23
Chip Disable to Wait High-Z Output
Chip Enable to Low-Z Output
End Write to Low-Z Output
ADV# Pulse Width
tLZ
10
5
3
3
tOW
tVP
tVPH
tVS
10
10
70
70
ADV# Pulse Width High
ADV# Setup to End of Write
Write Cycle Time
tWC
tWHZ
tWP
Write to DQ High-Z Output
Write Pulse Width
8
2
46
10
0
Write Pulse Width High
tWPH
tWR
tCPH
Write Recovery Time
CE# High between subsequent asynchronous operations
5
Notes:
1. Low-Z to High-Z timings are tested with the circuit shown in Figure 32.2. The High-Z timings measure a 100mV transition
from either VOH or VOL toward VCCQ/2.
2. High-Z to Low-Z timings are tested with the circuit shown in Figure 32.2. The Low-Z timings measure a 100mV transition
away from the High-Z (VCCQ/2) level toward either VOH or VOL
.
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A d v a n c e I n f o r m a t i o n
Table 32.6 Burst Write Cycle Timing Requirements
70ns/80 MHz
70ns/66 MHz
Parameter
CE# High between Subsequent Mixed-Mode Operations
CE# Low to Wait Valid
Symbol
tCBPH
tCEW
tCLK
tCSP
tHD
Min
5
Max
Min
5
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
Notes
1
7.5
20
20
1
7.5
20
20
Clock Period
12.5
4.5
2
15
5
CE# Setup to CLK Active Edge
Hold Time from Active CLK Edge
Chip Disable to Wait High-Z Output
CLK Rise or Fall Time
2
tHZ
8
1.8
9
8
tKHKL
tKHTL
tKP
2.0
11
Clock to Wait Valid
CLK High or Low Time
4
3
5
3
Setup Time to Activate CLK Edge
tSP
Minimum CE# Pulse Width
tCEM
8
8
Notes:
1. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be provided every tCEM. A refresh
opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for greater than
15ns.
2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met.
144
CellularRAM Type 2
CellRam_03_A0 March 9, 2005
A d v a n c e I n f o r m a t i o n
33 Timing Diagrams
V
CC
(MIN)
V
, V Q = 1.7V
CC CC
t
PU
Device ready for
normal operation
Figure 33.1 Initialization Period
Table 33.1 Initialization Timing Parameters
70ns/80 MHz
85ns/66 MHz
Parameter
Symbol
Min
Max
Min
Max
Units
Notes
Initialization Period (required before normal operations)
tPU
150
150
µs
March 9, 2005 CellRam_03_A0
CellularRAM Type 2
145
A d v a n c e I n f o r m a t i o n
t
RC
V
V
IH
IL
VALID ADDRESS
A[22:0]
t
AA
V
V
IH
IL
ADV#
CE#
t
t
CBPH
HZ
V
V
IH
IL
t
CO
t
t
BHZ
BA
V
V
IH
IL
LB#/UB#
t
t
OHZ
OE
V
V
V
V
IH
IL
IH
IL
OE#
WE#
t
OLZ
t
BLZ
t
LZ
V
V
OH
OL
High-Z
DQ[15:0]
VALID OUTPUT
t
t
HZ
CEW
V
V
IH
IL
High-Z
High-Z
WAIT
Legend:
Don't Care
Undefined
Figure 33.2 Asynchronous Read
146
CellularRAM Type 2
CellRam_03_A0 March 9, 2005
A d v a n c e I n f o r m a t i o n
V
V
IH
IL
A[22:0]
VALID ADDRESS
t
AA
t
t
AVH
AVS
t
VPH
V
V
IH
IL
ADV#
t
AADV
t
VP
t
t
CVS
t
CBPH
HZ
V
V
IH
IL
CE#
t
CO
t
t
BHZ
BA
V
V
IH
IL
LB#/UB#
t
t
OHZ
OE
V
V
V
V
IH
IL
IH
IL
OE#
WE#
t
OLZ
t
BLZ
t
LZ
V
V
OH
OL
High-Z
DQ[15:0]
VALID OUTPUT
t
t
HZ
CEW
V
V
IH
IL
High-Z
High-Z
WAIT
Legend:
Don't Care
Undefined
Figure 33.3 Asynchronous Read Using ADV#
March 9, 2005 CellRam_03_A0
CellularRAM Type 2
147
A d v a n c e I n f o r m a t i o n
t
RC
V
V
IH
IL
A[22:0]
A[3:0]
VALID ADDRESS
V
V
IH
IL
VALID
VALID
VALID
ADDRESS
VALID ADDRESS
ADDRESS
ADDRESS
t
t
PC
AA
V
V
IH
IL
ADV#
t
t
CEM
CBPH
t
t
t
CBPH
CO
HZ
V
V
IH
IL
CE#
t
t
BHZ
BA
V
V
IH
IL
LB#/UB#
t
t
OHZ
OE
V
V
V
V
IH
IL
IH
IL
OE#
WE#
t
OLZ
t
t
APA
BLZ
t
t
OH
LZ
V
V
OH
OL
High-Z
t
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
DQ[15:0]
t
HZ
CEW
V
V
IH
IL
High-Z
High-Z
WAIT
Legend:
Don't Care
Undefined
Figure 33.4 Page Mode Read
148
CellularRAM Type 2
CellRam_03_A0 March 9, 2005
A d v a n c e I n f o r m a t i o n
t
t
KP
t
KP
CLK
V
V
IH
IL
CLK
t
KHKL
t
t
SP
HD
V
V
IH
IL
A[22:0]
ADV#
VALID ADDRESS
t
t
SP
HD
V
V
IH
IL
t
HD
t
t
HZ
t
ABA
CSP
V
V
IH
IL
CE#
OE#
t
t
OHZ
BOE
V
V
IH
IL
t
OLZ
t
t
SP
SP
HD
V
V
IH
IL
WE#
t
t
HD
V
V
IH
IL
LB#/UB#
t
CEW
t
KHTL
V
V
OH
OL
High-Z
High-Z
WAIT
t
t
KOH
ACLK
V
V
OH
OL
High-Z
DQ[15:0]
VALID OUTPUT
Legend:
Don't Care
Undefined
READ Burst Identified
(WE# = HIGH)
Note: Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay. Clock
rates below 50MHz (t
> 20ns) are allowed as long as t
specifications are met.
CLK
CSP
Figure 33.5 Single-Access Burst Read Operation—Variable Latency
March 9, 2005 CellRam_03_A0
CellularRAM Type 2
149
A d v a n c e I n f o r m a t i o n
t
CLK
t
t
t
KP
KHKL
KP
V
V
IH
IL
CLK
t
t
SP
HD
V
V
IH
IL
Valid
Address
A[22:0]
ADV#
CE#
t
t
SP
HD
V
V
IH
IL
t
t
t
t
HD
CSP
ABA
CBPH
V
V
IH
IL
t
HZ
t
t
OHZ
BOE
V
V
IH
IL
OE#
t
OLZ
t
t
t
SP
HD
HD
V
V
IH
IL
WE#
t
SP
V
V
IH
IL
LB#/UB#
t
t
CEW
KHTL
V
V
OH
OL
High-Z
High-Z
WAIT
t
KOH
t
ACLK
V
V
OH
OL
High-Z
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
DQ[15:0]
Legend:
READ Burst Identified
(WE# = HIGH)
Don't Care
Undefined
Note: Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay. Clock
rates below 50MHz (t
> 20ns) are allowed as long as t
specifications are met.
CLK
CSP
Figure 33.6 Four-word Burst Read Operation—Variable Latency
150
CellularRAM Type 2
CellRam_03_A0 March 9, 2005
A d v a n c e I n f o r m a t i o n
t
CLK
V
V
IH
IL
CLK
t
t
SP
HD
V
V
IH
IL
Valid
Address
A[22:0]
ADV#
CE#
t
t
SP
HD
V
V
IH
IL
t
t
t
HD
CSP
CBPH
V
V
IH
IL
t
HZ
t
t
OHZ
BOE
V
V
IH
IL
OE#
t
OLZ
t
t
t
SP
HD
HD
V
V
IH
IL
WE#
t
SP
V
V
IH
IL
LB#/UB#
t
t
CEW
KHTL
V
V
OH
OL
High-Z
High-Z
WAIT
t
KOH
t
ACLK
t
t
t
KHTL
KHTL
KHTL
V
V
OH
OL
High-Z
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
DQ[15:0]
High-Z
Legend:
READ Burst Identified
(WE# = HIGH)
Don't Care
Undefined
Note: Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay.
Figure 33.7 Four-word Burst Read Operation (with LB#/UB#)
March 9, 2005 CellRam_03_A0
CellularRAM Type 2
151
A d v a n c e I n f o r m a t i o n
t
CLK
V
V
IH
IL
CLK
t
t
SP
HD
V
V
IH
IL
Valid
Address
Valid
Address
A[22:0]
t
t
HD
SP
V
V
IH
IL
ADV#
t
CBPH
t
t
t
CSP
HZ
V
V
IH
IL
CE#
OE#
t
OHZ
OHZ
(Note 2)
V
V
IH
IL
t
t
t
SP
HD
HD
V
V
IH
IL
WE#
t
SP
V
V
IH
IL
LB#/UB#
t
t
CEW
BOE
t
OLZ
High-Z
V
V
High-Z
IH
IL
WAIT
t
KOH
t
BOE
t
ACLK
t
OLZ
V
V
OH
OL
High-Z
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
DQ[15:0]
Legend:
Don't Care
Undefined
Notes:
1. Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay.
2. OE# can stay Low during burst suspend. If OE# is Low, DQ[15:0] will continue to output valid data.
Figure 33.8 Refresh Collision During Write Operation
152
CellularRAM Type 2
CellRam_03_A0 March 9, 2005
A d v a n c e I n f o r m a t i o n
V
V
IH
IL
CLK
t
CLK
V
V
IH
IL
A[22:0]
ADV#
V
V
IH
IL
V
V
IH
IL
LB#/UB#
V
V
IH
IL
CE#
OE#
WE#
V
V
IH
IL
V
V
IH
IL
t
t
KHTL
KHTL
V
V
OH
OL
(Note 2)
WAIT
t
t
KOH
ACLK
V
V
OH
OL
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
DQ[15:0]
Legend:
Don't Care
Notes:
1. Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay.
2. Wait will assert LC + 1 or 2LC + 1 cycles for variable latency (depending upon refresh status).
Figure 33.9 Continuous Burst Read Showing an Output Delay with BCR[8] =
0 for End-of-Row Condition
March 9, 2005 CellRam_03_A0
CellularRAM Type 2
153
A d v a n c e I n f o r m a t i o n
t
AA
V
V
IH
IL
A[22:0]
VALID ADDRESS
t
AW
t
t
AS
WR
V
V
IH
IL
ADV#
t
CEM
t
CW
V
V
IH
IL
CE#
t
BW
V
V
IH
IL
LB#/UB#
OE#
V
V
IH
IL
t
t
WP
WPH
V
V
IH
IL
WE#
t
t
DH
DW
High-Z
V
V
IH
IL
DQ[15:0]
IN
VALID
INPUT
t
t
WHZ
LZ
V
V
OH
OL
DQ[15:0]
OUT
t
HZ
t
CEW
High-Z
V
V
IH
IL
High-Z
WAIT
Legend:
Don't Care
Figure 33.10 CE#-Controlled Asynchronous Write
154
CellularRAM Type 2
CellRam_03_A0 March 9, 2005
A d v a n c e I n f o r m a t i o n
t
WC
V
V
IH
IL
A[22:0]
VALID ADDRESS
t
AW
t
t
AS
WR
V
V
IH
IL
ADV#
t
CEM
t
CW
V
V
IH
IL
CE#
t
BW
V
V
IH
IL
LB#/UB#
OE#
V
V
IH
IL
t
t
WP
WPH
V
V
IH
IL
WE#
t
t
DH
DW
High-Z
V
V
IH
IL
DQ[15:0]
IN
VALID
INPUT
t
t
WHZ
LZ
V
V
OH
OL
DQ[15:0]
OUT
t
HZ
t
CEW
High-Z
V
V
IH
IL
High-Z
WAIT
Legend:
Don't Care
Figure 33.11 LB#/UB#-Controlled Asynchronous Write
March 9, 2005 CellRam_03_A0
CellularRAM Type 2
155
A d v a n c e I n f o r m a t i o n
t
WC
V
V
IH
IL
A[22:0]
VALID ADDRESS
t
AW
t
WR
V
V
IH
IL
ADV#
t
CEM
t
CW
V
V
IH
IL
CE#
t
BW
V
V
IH
IL
LB#/UB#
OE#
V
V
IH
IL
t
AS
t
t
WP
WPH
V
V
IH
IL
WE#
t
t
DH
DW
High-Z
V
V
IH
IL
DQ[15:0]
IN
VALID
INPUT
t
t
t
OW
LZ
WHZ
V
V
OH
OL
DQ[15:0]
OUT
t
t
CEW
HZ
V
V
IH
IL
High-Z
High-Z
WAIT
Legend:
Don't Care
Figure 33.12 WE#-Controlled Asynchronous Write
156
CellularRAM Type 2
CellRam_03_A0 March 9, 2005
A d v a n c e I n f o r m a t i o n
V
V
IH
IL
A[22:0]
VALID ADDRESS
t
t
AVH
AVS
t
VS
t
t
VP
VPH
t
AS
V
V
IH
IL
ADV#
t
AS
t
AW
t
CEM
t
CW
V
V
IH
IL
CE#
t
BW
V
V
IH
IL
LB#/UB#
OE#
V
V
IH
IL
t
t
WPH
WP
V
V
IH
IL
WE#
t
t
DH
DW
High-Z
V
V
IH
IL
DQ[15:0]
IN
VALID
INPUT
t
t
t
OW
LZ
WHZ
V
V
OH
OL
DQ[15:0]
OUT
t
t
CEW
HZ
V
V
IH
IL
High-Z
High-Z
WAIT
Legend:
Don't Care
Figure 33.13 Asynchronous Write Using ADV#
March 9, 2005 CellRam_03_A0
CellularRAM Type 2
157
A d v a n c e I n f o r m a t i o n
t
KHKL
t
t
KP
t
KP
CLK
V
V
IH
IL
CLK
t
t
SP
HD
V
V
IH
IL
Valid
Address
A[22:0]
ADV#
t
t
SP
HD
V
V
IH
IL
t
SP
t
HD
V
V
IH
IL
LB#/UB#
t
t
CSP
t
HD
CBPH
V
V
IH
IL
CE#
OE#
V
V
IH
IL
t
t
SP
HD
V
V
IH
IL
WE#
t
HZ
t
t
CEW
KHTL
High-Z
V
V
(Note 2)
IH
IL
High-Z
WAIT
t
t
HD
SP
V
V
OH
OL
DQ[15:0]
D[1]
D[2]
D[3]
D[0]
Legend:
READ Burst Identified
(WE# = LOW)
Don't Care
Notes:
1. Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay; burst length four;
burst wrap enabled.
Figure 33.14 Burst Write Operation
158
CellularRAM Type 2
CellRam_03_A0 March 9, 2005
A d v a n c e I n f o r m a t i o n
V
V
IH
IL
CLK
t
CLK
V
V
IH
IL
A[22:0]
ADV#
V
V
IH
IL
V
V
IH
IL
LB#/UB#
V
V
IH
IL
CE#
V
V
IH
IL
WE#
V
V
IH
IL
OE#
t
t
KHTL
KHTL
(Note 2)
V
V
OH
OL
WAIT
t
t
HD
SP
V
V
OH
OL
Valid Input
D[n+3]
Valid Input
D[n+2]
Valid Input Valid Input
DQ[15:0]
D[n]
D[n+1]
Legend:
Don't Care
END OF ROW
Notes:
1. Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay.
2. Wait will assert LC + 1 or 2LC + 1 cycles for variable latency (depending upon refresh status).
Figure 33.15 Continuous Burst Write Showing an Output Delay with BCR[8]
= 0 for End-of-Row Condition
March 9, 2005 CellRam_03_A0
CellularRAM Type 2
159
A d v a n c e I n f o r m a t i o n
t
CLK
V
V
IH
IL
CLK
t
t
t
t
t
t
HD
SP
SP
HD
V
V
IH
IL
Valid
Address
Valid
Address
A[22:0]
SP
t
t
HD
SP
HD
V
V
IH
IL
ADV#
t
t
HD
SP
V
V
IH
IL
LB#/UB#
CE#
t
t
t
HD
CSP
CBPH
V
V
IH
IL
(Note 2)
t
CSP
t
OHZ
V
V
IH
IL
OE#
t
SP
t
t
HD
t
SP
HD
V
V
IH
IL
WE#
t
BOE
V
V
High-Z
High-Z
OH
OL
WAIT
t
t
KOH
t
t
HD
ACLK
SP
V
V
V
High-Z
IH
IL
High-Z
OH
OL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
DQ[15:0]
D[0]
D[1]
D[2]
D[3]
V
Legend:
Don't Care
Undefined
Notes:
1. Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay.
2. To allow self-refresh operations to occur between transactions, CE# must remain High for at least 5ns (tCBPH) to schedule
the appropriate internal refresh operation. CE# can stay Low between burst Read and burst Write operations.
Figure 33.16 Burst Write Followed by Burst Read
160
CellularRAM Type 2
CellRam_03_A0 March 9, 2005
A d v a n c e I n f o r m a t i o n
t
CLK
V
V
IH
IL
CLK
t
t
t
t
t
HD
WC
WC
CKA
SP
V
V
IH
IL
Valid
Address
Valid
Address
Valid
Address
A[22:0]
t
t
t
t
WR
AVS
AVH
AW
t
t
HD
t
SP
VPH
V
V
IH
IL
ADV#
t
t
t
VP
VS
t
t
t
BW
SP
HD
CVS
V
V
IH
IL
LB#/UB#
CE#
t
t
t
CSP
CW
CBPH
V
V
IH
IL
(Note 2)
t
OHZ
V
V
IH
IL
OE#
t
WC
t
t
WP
t
AS
WPH
t
t
HD
SP
V
V
IH
IL
WE#
t
t
BOE
CEW
V
V
High-Z
OH
OL
WAIT
t
WHZ
t
ACLK
V
V
High-Z
V
V
High-Z
IH
IL
OH
OL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
DQ[15:0]
DATA
DATA
t
t
t
DH
DW
KOH
Legend:
Don't Care
Undefined
Notes:
1. Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay.
2. When transitioning between asynchronous and variable-latency burst operations, CE# must go High. If CE# goes High, it
must remain High for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation.
Figure 33.17 Asynchronous Write Followed by Burst Read
March 9, 2005 CellRam_03_A0
CellularRAM Type 2
161
A d v a n c e I n f o r m a t i o n
t
CLK
V
V
IH
IL
CLK
t
t
t
t
t
HD
WC
WC
CKA
SP
V
V
IH
IL
Valid
Address
Valid
Address
Valid
Address
A[22:0]
t
t
WR
AW
t
t
HD
SP
V
V
IH
IL
ADV#
t
t
SP
t
BW
HD
V
V
IH
IL
LB#/UB#
CE#
t
t
t
CSP
CW
CSP
V
V
IH
IL
(Note 2)
t
OHZ
V
V
IH
IL
OE#
t
WC
t
t
t
t
HD
WP
WPH
SP
V
V
IH
IL
WE#
t
t
BOE
CEW
V
V
High-Z
OH
OL
WAIT
t
t
WHZ
t
t
KOH
DW
ACLK
V
V
High-Z
V
V
High-Z
IH
IL
OH
OL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
DQ[15:0]
DATA
DATA
t
DH
Legend:
Don't Care
Undefined
Notes:
1. Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay.
2. When transitioning between asynchronous and variable-latency burst operations, CE# must go High. If CE# goes High, it
must remain High for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation.
Figure 33.18 Asynchronous Write (ADV# Low) Followed By Burst Read
162
CellularRAM Type 2
CellRam_03_A0 March 9, 2005
A d v a n c e I n f o r m a t i o n
t
CLK
V
V
IH
IL
CLK
t
t
t
WC
SP
HD
V
V
IH
IL
Valid
Address
Valid
Address
A[22:0]
t
t
AW
SP
t
WR
t
HD
V
V
IH
IL
ADV#
t
CBPH
t
t
CEM
HD
t
t
t
CSP
CW
HZ
V
V
IH
IL
CE#
OE#
(Note 2)
t
t
OHZ
BOE
V
V
IH
IL
t
AS
t
OLZ
t
t
t
t
t
WPH
SP
SP
HD
WP
V
V
IH
IL
WE#
t
t
BW
HD
V
V
IH
IL
LB#/UB#
t
t
CEW
CEW
t
t
KHTL
HZ
High-Z
V
V
High-Z
OH
OL
WAIT
t
DW
t
DH
t
t
KOH
ACLK
High-Z
V
V
IH
IL
Valid
Output
DQ[15:0]
Valid
Input
Legend:
Don't Care
Undefined
READ Burst Identified
(WE# = HIGH)
Notes:
1. Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay.
2. When transitioning between asynchronous and variable-latency burst operations, CE# must go High. If CE# goes High, it
must remain High for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation.
Figure 33.19 Burst Read Followed by Asynchronous Write (WE#-Controlled)
March 9, 2005 CellRam_03_A0
CellularRAM Type 2
163
A d v a n c e I n f o r m a t i o n
t
CLK
V
V
IH
IL
CLK
t
t
HD
SP
V
V
IH
IL
Valid
Address
Valid
Address
A[22:0]
t
t
AVS
AVH
t
t
t
VPH
VS
SP
t
t
HD
VP
V
V
IH
IL
ADV#
t
AW
t
t
AS
CBPH
t
t
CEM
HD
t
t
t
CSP
CW
HZ
V
V
IH
IL
CE#
OE#
(Note 2)
t
t
OHZ
BOE
V
V
IH
IL
t
AS
t
OLZ
t
t
t
t
t
WPH
SP
SP
HD
WP
V
V
IH
IL
WE#
t
t
BW
HD
V
V
IH
IL
LB#/UB#
t
t
CEW
CEW
t
t
KHTL
HZ
High-Z
V
V
High-Z
OH
OL
WAIT
t
DW
t
DH
t
t
KOH
ACLK
High-Z
V
V
OH
OL
Valid
Output
DQ[15:0]
Valid
Input
Legend:
Don't Care
Undefined
READ Burst Identified
(WE# = HIGH)
Notes:
1. Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay.
2. When transitioning between asynchronous and variable-latency burst operations, CE# must go High. If CE# goes High, it
must remain High for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation.
Figure 33.20 Burst Read Followed by Asynchronous Write Using ADV#
164
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A d v a n c e I n f o r m a t i o n
V
V
IH
IL
Valid
Address
Valid
Valid
Address
A[22:0]
ADV#
Address
t
t
t
AW
WR
AA
V
V
IH
IL
t
BHZ
t
t
BW
BLZ
V
V
IH
IL
LB#/UB#
CE#
t
t
CEM
t
CBPH
t
HZ
CW
V
V
IH
IL
(Note)
t
LZ
t
t
OHZ
OE
V
V
IH
IL
OE#
t
WC
t
t
WP
t
AS
WPH
V
V
IH
IL
WE#
t
t
HZ
HZ
V
V
OH
OL
WAIT
t
WHZ
t
OLZ
High-Z
High-Z
V
V
V
V
IH
IL
OH
OL
Valid
Output
DQ[15:0]
DATA
DATA
t
t
DW
DH
Legend:
Don't Care
Undefined
Note: CE# can stay Low when transitioning between asynchronous operations. If CE# goes High, it must remain High
for at least 5ns (t ) to schedule the appropriate internal refresh operation.
CBPH
Figure 33.21 Asynchronous Write Followed by Asynchronous Read—ADV#
Low
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165
A d v a n c e I n f o r m a t i o n
V
V
IH
IL
Valid
Address
Valid
Address
Valid
Address
A[22:0]
t
t
t
t
t
AA
AVS
AVH
AW
WR
t
t
t
VPH VP
VS
V
V
IH
IL
ADV#
t
t
t
BHZ
t
BW
BLZ
CVS
V
V
IH
IL
LB#/UB#
t
t
t
CBPH
CEM
t
HZ
CW
V
V
IH
IL
CE#
OE#
(Note)
t
t
LZ
AS
t
OHZ
V
V
IH
IL
t
WC
t
t
WP
t
AS
WPH
t
OLZ
V
V
IH
IL
WE#
V
V
OH
OL
WAIT
t
WHZ
t
OE
High-Z
High-Z
V
V
V
V
IH
IL
OH
OL
Valid
Output
DQ[15:0]
DATA
DATA
t
t
DW
DH
Legend:
Don't Care
Undefined
Note: CE# can stay Low when transitioning between asynchronous operations. If CE# goes High, it must remain High
for at least 5ns (t
) to schedule the appropriate internal refresh operation.
CBPH
Figure 33.22 Asynchronous Write Followed by Asynchronous Read
166
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A d v a n c e I n f o r m a t i o n
34 64M CellRAM Revision Summary
Revision A0 (March 9, 2005)
Initial release
March 9, 2005 CellRam_03_A0
CellularRAM Type 2
167
Aysnc/Page CellularRAM Type 2
1.8V 32/16 Megabit (2Mx16, 1 Mx16) Asynchronous/Page
CellularRAM
ADVANCE
INFORMATION
!
!
Low power consumption
Asynchronous READ < 20 mA
Intrapage READ < 15 mA
Standby: 110 µA (32 Mb), 80 µA (16 Mb)
Deep power-down < 10 µA (TYP @ 25° C)
Low-power features
Temperature compensated refresh (TCR)
On-chip temperature sensor
Features
!
!
!
Asynchronous and page mode interface
Random access time: 70 ns
, V voltages
V
CC
CCQ
1.70V–1.95V V
1.70V–3.30V V
CC
CCQ
!
Page mode read access
Partial array refresh (PAR)
Deep power-down (DPD) mode
Sixteen-word page size
Interpage read access: 70 ns
Intrapage read access: 20 ns
General Description
CellularRAM™ products are high-speed, CMOS PSRAM memories developed for low-power, por-
table applications. The 32-Mb part is a DRAM core device organized as 2 Meg x 16 bits, and the
16-Mb part is a DRAM core device organized as 1 Meg x 16 bits. These devices include the indus-
try-standard, asynchronous memory interface found on other low-power SRAM or Pseudo SRAM
offerings.
A user-accessible Configuration Register (CR) defines how the CellularRAM device performs on-
chip refresh and whether page mode read accesses are permitted. This register is automatically
loaded with a default setting during power-up and can be updated at any time during normal
operation.
To operate seamlessly on an asynchronous memory bus, CellularRAM products incorporate a
transparent self refresh mechanism. The hidden refresh requires no additional support from the
system memory controller and has no significant impact on device read/write performance.
Special attention has been focused on current consumption during self refresh. CellularRAM prod-
ucts include three system-accessible mechanisms to minimize refresh current. Temperature-
Compensated Refresh (TCR) uses an on-chip sensor to adjust the refresh rate to match the device
temperature. The refresh rate decreases at lower temperatures to minimize current consumption
during standby. TCR can also be set by the system for maximum device temperatures of +85° C,
+45° C, and +15° C. Setting sleep enable (ZZ#) to LOW enables one of two low-power modes:
Partial Array Refresh (PAR); or Deep Power-Down (DPD). PAR limits refresh to only that part of
the DRAM array that contains essential data. DPD halts refresh operation altogether and is used
when no vital information is stored in the device. These three refresh mechanisms are accessed
through the CR.
Publication Number CellRAM_05 Revision A Amendment 0 Issue Date August 25, 2005
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do
not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
A d v a n c e I n f o r m a t i o n
35 Functional Block Diagram
A[20:0]
(for 32Mb)
A[19:0]
Address Decode
Logic
Input/
Output
MUX
and
Buffers
2,048K x 16
(1,024K x 16)
DRAM
Memory
Array
DQ[7:0]
(for 16Mb)
DQ[15:8]
Configuration
Register (CR)
CE#
WE#
OE#
UB#
LB#
ZZ#
Control
Logic
Notes:Funtional block diagrams illustrate simplified device operation. See truth table, signal
descriptions, and timing diagrams for detailed information.
Figure 35.1 Functional Block Diagram 2 Meg x 16 and 1 Meg x 16
Table 35.1 Signal Descriptions
Symbol
Type
Description
Address Inputs: Inputs for the address accessed during READ or WRITE operations. The address
lines are also used to define the value to be loaded into the CR. On the 16-Mb device, A20 is
not internally connected.
A[20:0]
Input
Sleep Enable: When ZZ# is LOW, the CR can be loaded or the device can enter one of two low-
power modes (DPD or PAR).
ZZ#
CE#
OE#
Input
Input
Input
Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and
goes into standby power mode.
Output Enable: Enables the output buffers when LOW. When OE# is HIGH, the output buffers
are disabled.
WE#
LB#
Input
Input
Write Enable: Enables WRITE operations when LOW.
Lower Byte Enable. DQ[7:0]
Input/
Output
DQ[15:0]
Data Inputs/Outputs.
NC
VCC
Not internally connected.
Supply
Supply
Supply
Supply
Device Power Supply: (1.70V–1.95V) Power supply for device core operation.
I/O Power Supply: (1.70V–3.30V) Power supply for input/output buffers.
VSS must be connected to ground.
VCCQ
VSS
V
SSQ
VSSQ must be connected to ground.
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A d v a n c e I n f o r m a t i o n
Table 35.2 Bus Operations
LB#/
Mode
Standby
Power
CE#
WE#
OE#
ZZ#
DQ[15:0]1
Notes
UB#
Standby
Active
H
L
X
H
X
L
X
L
H
H
High-Z
(note 2),(note 5)
(note 1),(note 4)
Read
Data-Out
(note1),(note3),(note
4)
Write
Active
Idle
L
L
L
X
X
X
X
X
L
X
X
H
H
L
Data-In
X
No Operation
PAR
(note 4),(note 5)
(note 6)
Partial Array
Refresh
H
High-Z
Deep Power-
Down
DPD
H
L
X
L
X
X
X
X
L
L
High-Z
High-Z
(note 6)
Load
Configuration
Register
Active
Notes:
1. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When LB# only is in select mode, only DQ[7:0]
are affected. When UB# only is in the select mode, DQ[15:8] are affected.
2. When the device is in standby mode, control inputs (WE#, OE#), address inputs, and data inputs/outputs are internally
isolated from any external influence.
3. When WE# is invoked, the OE# input is internally disabled and has no effect on the I/Os.
4. The device consumes active power in this mode whenever addresses are changed.
5. VIN = VCCQ or 0V; all device balls must be static (unswitched) in order to achieve minimum standby current.
6. DPD is enabled when configuration register bit CR[4] is “0”; otherwise, PAR is enabled.
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A d v a n c e I n f o r m a t i o n
36 Functional Description
In general, the 32-Mb and 16-Mb CellularRAM Type 2 devices are high-density alternatives to
SRAM and Pseudo-SRAM products, popular in low-power, portable applications. The 32-Mb device
contains 33,554,432 bit DRAM core organized as 2,097,152 addresses by 16 bits. The 16-Mb de-
vice contains 16,777,216 bit DRAM core organized as 1,048,576 addresses by 16 bits. These
devices include the industry standard, asynchronous memory interface found on other low-power
SRAM or Pseudo-SRAM offerings. Page mode accesses are also included as a bandwidth-enhanc-
ing extension to the asynchronous read protocol.
36.1 Power-Up Initialization
CellularRAM products include an on-chip voltage sensor that is used to launch the power-up ini-
tialization process. Initialization loads the CR with its default setting. VCC and VCCQ must be
applied simultaneously. When they reach a stable level above 1.70V, the device requires 150 µs
to complete its self-initialization process (see Figure 36.1). During the initialization period, CE#
should remain HIGH. When initialization is complete, the device is ready for normal operation.
Vcc = 1.7V
t
>
PU 150μs
Device ready for
normal operation
Vcc
VccQ
Device Initialization
Figure 36.1 Power-Up Initialization Timing
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A d v a n c e I n f o r m a t i o n
37 Bus Operating Modes
These CellularRAM products incorporate the industry-standard, asynchronous interface found on
other low-power SRAM or Pseudo SRAM offerings. This bus interface supports asynchronous READ
and WRITE operations as well as the bandwidth-enhancing page mode READ operation. The spe-
cific interface that is supported is defined by the value loaded into the CR.
37.1 Asynchronous Mode
CellularRAM products power up in the asynchronous operating mode. This mode uses the indus-
try-standard SRAM control interface (CE#, OE#, WE#, LB#/UB#). READ operations (Figure 37.1)
are initiated by bringing CE#, OE#, and LB#/UB# LOW while keeping WE# HIGH. Valid data is
driven out of the I/Os after the specified access time has elapsed. WRITE operations (Figure 37.2)
occur when CE#, WE#, and LB#/UB# are driven LOW. During WRITE operations, the level of OE#
is a “Don't Care”; WE# overrides OE#. The data to be written is latched on the rising edge of CE#,
WE#, or LB#/UB# (whichever occurs first). WE# LOW time must be limited to tCEM
.
CE#
OE#
WE#
ADDRESS
ADDRESS VALID
DATA VALID
DATA
LB#/UB#
t
RC = READ Cycle Time
DON’T CARE
Figure 37.1 Asynchronous Mode READ Operation
CE#
OE#
t
<
CEM
WE#
ADDRESS
ADDRESS VALID
DATA VALID
DATA
LB#/UB#
t
WC = WRITE Cycle Time
DON’T CARE
Figure 37.2 Asynchronous Mode WRITE Operation
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A d v a n c e I n f o r m a t i o n
37.2 Page Mode Read Operation
Page mode is a performance-enhancing extension to the legacy asynchronous READ operation.
In page-mode-capable products, an initial asynchronous read access is performed, then adjacent
addresses can be quickly read by simply changing the low-order address. Addresses A[3:0] are
used to determine the members of the 16-address CellularRAM page. Any change in addresses
A[4] or higher initiates a new tAA access. Figure 37.3 shows the timing diagram for a page mode
access. Page mode takes advantage of the fact that adjacent addresses can be read in a shorter
period of time than random addresses. WRITE operations do not include comparable page mode
functionality. The CE# LOW time is limited by refresh considerations. CE# must not stay LOW
longer than tCEM
.
t
<
CEM
CE#
OE#
WE#
ADDRESS ADDRESS ADDRESS
[1] [2] [3]
ADDRESS[0]
ADDRESS
t
t
t
t
AA
APA APA APA
D[0]
D[1]
D[2]
D[3]
DATA
LB#/UB#
DON’T CARE
Figure 37.3 Page Mode READ Operation
37.3 LB#/UB# Operation
The Lower Byte (LB#) enable and Upper Byte (UB#) enable signals allow for byte-wide data
transfers. During READ operations, enabled bytes are driven onto the DQs. The DQs associated
with a disabled byte are put into a High-Z state during a READ operation. During WRITE opera-
tions, any disabled bytes are not transferred to the memory array; the internal value remains
unchanged. During a WRITE cycle, the data to be written is latched on the rising edge of CE#,
WE#, LB#, or UB#, whichever occurs first. When both the LB# and UB# are disabled (HIGH) dur-
ing an operation, the device disables the data bus from receiving or transmitting data. Although
the device seems to be deselected, the device remains in an active mode as long as CE# remains
LOW.
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A d v a n c e I n f o r m a t i o n
38 Low-Power Operation
38.1 Standby Mode Operation
During standby, the device current consumption is reduced to the level necessary to perform the
DRAM refresh operation on the full array. Standby operation occurs when CE# and ZZ# are HIGH.
The device enters a reduced power state during READ and WRITE operations where the address
and control inputs remain static for an extended period of time. This mode continues until a
change occurs to the address or control inputs.
38.2 Temperature Compensated Refresh
Temperature-Compensated Refresh (TCR) allows for adequate refresh at different temperatures.
This CellularRAM device includes an on-chip temperature sensor. When the sensor is enabled, it
continually adjusts the refresh rate according to the operating temperature. The on-chip sensor
is enabled by default.
Three fixed refresh rates are also available, corresponding to temperature thresholds of +15° C,
+45° C, and +85° C. The setting selected must be for a temperature higher than the case tem-
perature of the CellularRAM device. If the case temperature is +35° C, the system can minimize
self-refresh current consumption by selecting the +45° C setting. The +15° C setting may result
in inadequate refreshing and cause data corruption.
38.3 Partial Array Refresh
Partial Array Refresh (PAR) restricts refresh operation to a portion of the total memory array. This
feature enables the system to reduce refresh current by only refreshing that part of the memory
array that is absolutely necessary. The refresh options are full array, one-half array, one-quarter
array, one-eighth array, or none of the array. Data stored in addresses not receiving refresh be-
come corrupted. The mapping of these partitions can start at either the beginning or the end of
the address map (Table 39.1 and Table 39.2 on page 179). READ and WRITE operations are ig-
nored during PAR operation.
The device only enters PAR mode if the SLEEP bit in the CR has been set HIGH (CR[4] = 1). PAR
can be initiated by bring the ZZ# ball to the LOW state for longer than 10 µs. Returning ZZ# to
HIGH causes an exit from PAR and the entire array is immediately available for READ and WRITE
operations.
Alternatively, PAR can be initiated using the CR software access sequence (see Software Access
to the Configuration Register on page 176). PAR is enabled immediately upon setting CR[4] to
“1” using this method. However, using software access to write to the CR alters the function of
ZZ# so that ZZ# LOW no longer initiates PAR, although ZZ# continues to enable WRITEs to the
CR. This functional change persists until the next time the device is powered up (see Figure 38.1).
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A d v a n c e I n f o r m a t i o n
Power -Up
To enable P AR,
bring ZZ# LOW
for 10μs.
Software
LOAD
NO
executed?
YES
Change to ZZ#
functionality
.
PAR permanently
enabled,
independent of
ZZ# level.
Figure 38.1 Software Access PAR Functionality
38.4 Deep Power-Down Operation
Deep Power-Down (DPD) operation disables all refresh-related activity. This mode is used when
the system does not require the storage provided by the CellularRAM device. Any stored data be-
comes corrupted when DPD is entered. When refresh activity is re-enabled, the CellularRAM
device requires 150 µs to perform an initialization procedure before normal operations can re-
sume. READ and WRITE operations are ignored during DPD operation.
The device can only enter DPD if the SLEEP bit in the CR has been set LOW (CR[4] = 0). DPD is
initiated by bringing ZZ# to the LOW state for longer than 10 µs. Returning ZZ# to HIGH causes
the device to exit DPD and begin a 150-µs initialization process. During this 150−µs period, the
current consumption is higher than the specified standby levels, but considerably lower than the
active current specification.
Driving ZZ# LOW puts the device in the PAR mode if the SLEEP bit in the CR is set HIGH
(CR[4] = 1).
The device should not be put into DPD using CR software access.
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A d v a n c e I n f o r m a t i o n
39 Configuration Register Operation
The Configuration Register (CR) defines how the CellularRAM device performs its transparent self-
refresh. Altering the refresh parameters can dramatically reduce current consumption during
standby mode. Page mode control is also embedded into the CR. This register can be updated any
time while the device is operating in a standby state. Figure 39.4 on page 178 describes the con-
trol bits used in the CR. At power up, the CR is set to 0010h.
39.1 Access Using ZZ#
The CR can be loaded using a WRITE operation immediately after ZZ# makes a HIGH-to-LOW
transition (Figure 39.1). The values placed on addresses A[20:0] are latched into the CR on the
rising edge of CE# or WE#, whichever occurs first. LB#/UB# are “Don’t Care.” Access using ZZ#
is WRITE only.
ADDRESS
CE#
ADDRESS VALID
WE#
ZZ#
t < 500ns
Figure 39.1 Load Configuration Register Operation
39.2 Software Access to the Configuration Register
The contents of the CR can either be read or modified using a software sequence. The nature of
this access mechanism may eliminate the need for the ZZ# ball.
If the software mechanism is used, ZZ# can simply be tied to VCCQ. The port line typically used
for ZZ# control purposes is no longer required. However, ZZ# should not be tied to VCCQ if the
system uses DPD; DPD cannot be enabled or disabled using the software access sequence.
The CR is loaded using a four-step sequence consisting of two READ operations followed by two
WRITE operations (see Figure 39.2). The read sequence is virtually identical except that an asyn-
chronous READ is performed during the fourth operation (see Figure 39.3). Note that a third
READ cycle of the highest address cancels the access sequence until a different address is read.
The address used during all READ and WRITE operations is the highest address of the CellularRAM
device being accessed (1FFFFFh for 32 Mb and FFFFFh for 16 Mb); the content of this address is
changed by using this sequence (note that this is a deviation from the CellularRAM specification).
The data bus is used to transfer data into or out of bits 15–0 of the CR.
Writing to the CR using the software sequence modifies the function of the ZZ# ball. Once the
software sequence loads the CR, the level of the ZZ# ball no longer enables PAR operation. PAR
operation is updated whenever the software sequence loads a new value into the CR. This ZZ#
functionality continues until the next time the device is powered-up. The operation of the ZZ#
ball is not affected if the software sequence is only used to read the contents of the CR. The use
of the software sequence does not affect the ability to perform the standard (ZZ#-controlled)
method of loading the CR.
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A d v a n c e I n f o r m a t i o n
1
READ
READ
WRITE
WRITE
ADDRESS
(MAX)
ADDRESS
(MAX)
ADDRESS
(MAX)
ADDRESS
(MAX)
ADDRESS
CE#
OE#
WE#
LB#/UB#
CR VALUE
IN
DATA
XXXXh
XXXXh
0000h
DON'T CARE
Note:
1.The WRITE on the third cycle must be CE#-controlled.
Figure 39.2 Software Access Load Configuration Register
1
READ
READ
WRITE
READ
ADDRESS
(MAX)
ADDRESS
(MAX)
ADDRESS
(MAX)
ADDRESS
(MAX)
ADDRESS
CE#
NOTE2
OE#
WE#
LB#/UB#
CR VALUE
DATA
XXXXh
XXXXh
0000h
OUT
DON'T CARE
Notes:
1.The WRITE on the third cycle must be CE#-controlled.
2.CE# must be HIGH for 150 ns before performing the cycle that reads the configuration register.
Figure 39.3 Software Access Read Configuration Register
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A d v a n c e I n f o r m a t i o n
A[20:8]
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus
20–8
7
6
5
4
3
2
1
0
Configuration
Register
RESERVED
PAGE
TCR
SLEEP
RESERVED
PAR
All must be set to "0"
Must be set to "0"
CR[1] CR[0]
CR[2]
PAR Refresh Coverage
Full array (default)
Bottom 1/2 array
Bottom 1/4 array
Bottom 1/8 array
None of array
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
CR[7]
Page Mode Enable/Disable
0
1
Page Mode Disabled (default)
Page Mode Enabled
CR[6] CR[5]
Maximum Case Temp.
+85C
Top 1/2 array
1
1
0
Top 1/4 array
0
0
1
Internal sensor (default)
Top 1/8 array
1
+45C
+15C
0
Sleep Mode
DPD Enabled
PAR Enabled (default)
CR[4]
0
1
Figure 39.4 Configuration Register Bit Mapping
39.3 Partial Array Refresh (CR[2:0]) Default = Full Array Refresh
The PAR bits restrict refresh operation to a portion of the total memory array. This feature allows
the system to reduce current by only refreshing that part of the memory array required by the
host system. The refresh options are full array, one-half array, one-quarter array, one-eighth ar-
ray, or none of the array. The mapping of these partitions can start at either the beginning or the
end of the address map (see Table 39.1 and Table 39.2 on page 179).
39.4 Sleep Mode (CR[4]) Default = PAR Enabled, DPD Disabled
The sleep mode bit determines which low-power mode is to be entered when ZZ# is driven LOW.
If CR[4] = 1, PAR operation is enabled. If CR[4] = 0, DPD operation is enabled. PAR can also be
enabled directly by writing to the CR using the software access sequence. Note that this then dis-
ables ZZ# initiation of PAR. DPD cannot be enabled or disabled using the software access
sequence; this should only be done using ZZ# to access the CR.
DPD operation disables all refresh-related activity. This mode is used when the system does not
require the storage provided by the CellularRAM device. Any stored data becomes corrupted when
DPD is enabled. When refresh activity is re-enabled, the CellularRAM device requires 150 µs to
perform an initialization procedure before normal operation can resume. DPD should not be en-
abled using CR software access.
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39.5 Temperature Compensated Refresh (CR[6:5]) Default = On-Chip
Temperature Sensor
This CellularRAM device includes an on-chip temperature sensor that automatically adjusts the
refresh rate according to the operating temperature. The on-chip TCR is enabled by clearing both
of the TCR bits in the refresh configuration register (CR[6:5] = 00b). Any other TCR setting en-
ables a fixed refresh rate. When the on-chip temperature sensor is enabled, the device continually
adjusts the refresh rate according to the operating temperature.
The TCR bits also allow for adequate fixed-rate refresh at three different temperature thresholds
(+15° C, +45° C, and +85° C). The setting selected must be for a temperature higher than the
case temperature of the CellularRAM device. If the case temperature is +35° C, the system can
minimize self-refresh current consumption by selecting the +45° C setting. The +15° C setting
may result in inadequate refreshing and cause data corruption.
39.6 Page Mode READ Operation (CR[7]) Default = Disabled
The page mode operation bit determines whether page mode READ operations are enabled. In
the power-up default state, page mode is disabled.
Table 39.1 32-Mb Address Patterns for PAR (CR[4] = 1)
CR[2]
CR[1]
CR[0]
Active Section
Full die
Address Space
000000h–1FFFFFh
000000h–0FFFFFh
000000h–07FFFFh
000000h–03FFFFh
0
Size
Density
32Mb
16Mb
8Mb
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2 Meg x 16
1 Meg x 16
512K x 16
256K x 16
0 Meg x 16
1 Meg x 16
512K x 16
256K x 16
One-half of die
One-quarter of die
One-eighth of die
None of die
4Mb
0Mb
One-half of die
One-quarter of die
One-eighth of die
100000h–1FFFFFh
180000h–1FFFFFh
1C0000h–1FFFFFh
16Mb
8Mb
4Mb
Table 39.2 16-Mb Address Patterns for PAR (CR[4] = 1)
CR[2]
CR[1]
CR[0]
Active Section
Full die
Address Space
00000h–FFFFFh
00000h–7FFFFh
00000h–3FFFFh
00000h–1FFFFh
0
Size
Density
16Mb
8Mb
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1 Meg x 16
512K x 16
256K x 16
128K x 16
0 Meg x 16
512K x 16
256K x 16
128K x 16
One-half of die
One-quarter of die
One-eighth of die
None of die
4Mb
2Mb
0Mb
One-half of die
One-quarter of die
One-eighth of die
80000h–FFFFFh
C0000h–FFFFFh
E0000h–FFFFFh
8Mb
4Mb
2Mb
August 25, 2005 CellRAM_05_A0
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A d v a n c e I n f o r m a t i o n
40 Electrical Characteristics
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only, and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
Table 40.1 Absolute Maximum Ratings
Parameter
Voltage to Any Ball Except VCC, VCCQ relative to VSS
Voltage on VCC Supply Relative to VSS
Voltage on VCCQ Supply Relative to VSS
Storage Temperature
Rating
-0.50V to (4.0V or VCCQ + 0.3V, whichever is less)
-0.20V to 2.45V
-0.20V to 4.0V
-55°C to 150°C
Wireless Operating Temperature
-30°C to 85°C
Note:
-30° C exceeds the CellularRAM Workgroup 1.0 specification of -25° C.
Table 40.2 Electrical Characteristics and Operating Conditions
Description
Supply Voltage
Conditions
Symbol
Min
1.70
1.70
Max
1.95
3.30
Units
Notes
VCC
V
V
I/O Supply Voltage
VCCQ
(note
2),(note
3)
Input High Voltage
VIH
1.4
VCCQ + 0.2
+0.4
V
Input Low Voltage
VIL
VOH
VOL
ILI
-0.2
V
V
(note 4)
Output High Voltage
Output Low Voltage
Input Leakage Current
I
OH = -0.2mA
0.80 VCCQ
I
OL = 0.2mA
0.20 VCCQ
1
V
VIN = 0 to VCCQ
µA
OE# = VIH or Chip
Disabled
Output Leakage Current
ILO
1
µA
Operating Current
Asynchronous Random
READ/WRITE
ICC
1
20
15
mA
mA
(note 5)
(note 5)
V
IN = VCCQ or 0V Chip
Enabled, IOUT = 0
Asynchronous Page
READ
I
CC1P
32Mb
16Mb
110
80
V
IN = VCCQ or 0V
CE# = VCCQ
Standby Current
ISB
µA
(note 6)
Notes:
1. -30° C exceeds the CellularRAM Workgroup 1.0 specification of -25° C.
2. Input signals may overshoot to VCCQ + 1.0 V for periods less than 2ns during transitions.
3. VIH (MIN) value is not aligned with Cellular RAM Workgroup 1.0 specification of VCCQ - 0.4 V.
4. Input signals may undershoot to VSS - 1.0V for periods less than 2ns during transitions
5. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add the current
required to drive output capacitance expected in the actual system.
6. ISB (MAX) values measured with PAR set to FULL ARRAY and TCR set to +85° C. In order to achieve low standby current,
all inputs must be driven to VCCQ or VSS. ISB may be slightly higher for up to 500 ms after power-up or when entering
standby mode.
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40.1 Maximum and Typical Standby Currents
The following tables and figures refer to the maximum and typical standby currents for the de-
vices. The typical values shown in Figure 40.1 and Figure 40.2 are measured with the default on-
chip temperature sensor control enabled. The maximum values shown in Table 40.7, Table 40.8,
and Table 40.9 are measured with the relevant TCR bits set in the configuration register.
Table 40.3 Maximum Standby Currents for Applying PAR and TCR Settings – 32Mb
TCR
+15° C (CR[6:5] = 10b)
+45° C (CR[6:5] = 01b)
+85° C (CR[6:5] = 11b)
PAR
Full Array
1/2 Array
1/4 Array
1/8 Array
0 Array
70
60
57
55
50
80
65
60
57
55
110
105
95
95
70
Notes:
1. For CR[6:5] = 00b (default), refer to Figure 40.1 for typical values.
2. In order to achieve low standby current, all inputs must be driven to VCCQ or VSS. ISB may be slightly higher for up to
500ms after power-up or when entering standby mode.
3. TCR values for 85° C are 100 percent tested. TCR values for 15° C and 45° C are sampled only.
Table 40.4 Maximum Standby Currents for Applying PAR and TCR Settings – 16Mb
TCR
+15°C (CR[6:5] = 10b)
+45°C (CR[6:5] = 01b)
+85°C (CR[6:5] = 11b)
PAR
Full Array
1/2 Array
1/4 Array
1/8 Array
0 Array
40
38
38
38
35
50
55
55
55
40
80
70
70
70
65
Notes:
1. For CR[6:5] = 00b (default), refer to Figure 40.2, "Typical Refresh Current vs. Temperature (ITCR) – 16Mb" on page 182
for typical values.
2. In order to achieve low standby current, all inputs must be driven to VCCQ or VSS. ISB may be slightly higher for up to
500 ms after power-up or when entering standby mode.
3. TCR values for 85° C are 100 percent tested. TCR values for 15° C and 45° C are sampled only.
August 25, 2005 CellRAM_05_A0
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A d v a n c e I n f o r m a t i o n
75
65
55
45
35
25
15
PAR = Full and 1/2 Array
PAR = 1/4 Array
PAR = 1/8 Array
None
-3 0
- 20
-1 0
0
10
20
30
40
50
60
70
80
90
Temperature (°C)
Note: Typical ISB currents for each PAR setting with the appropriate TCR selected, or temperature
sensor enabled.
Figure 40.1 Typical Refresh Current vs. Temperature (ITCR) – 32Mb
60
55
50
PAR = Full Array
PAR = 1/2, 1/4, 1/8 Array
None
45
40
35
30
25
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
Temperature (°C)
Note: Typical ISB currents for each PAR setting with the appropriate TCR selected, or temperaturesen-
sor enabled.
Figure 40.2 Typical Refresh Current vs. Temperature (ITCR) – 16Mb
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Table 40.5 Deep Power-Down Specifications and Conditions
Description
Conditions
Symbol
Typ
Units
V
IN = VCCQ or 0V; +25°C; ZZ# = 0V;
CR[4] = 0
Deep Power-Down
IZZ
10
µA
Table 40.6 Capacitance Specifications and Conditions
Description
Conditions
Symbol
CIN
Min
2.0
3.0
Max
6.5
Units
pF
Notes
Input Capacitance
(note 1)
(note 1)
TC = +25ºC; f = 1 MHz; VIN = 0V
Input/Output Capacitance (DQ)
CIO
6.5
pF
Notes:
1. These parameters are verified in device characterization and are not 100-percent tested.
V
CCQ
Input 1
Output
V
CC/22
V
CCQ/23
Test Points
V
SSQ
Notes:
1. AC test inputs are driven at VCCQ for a logic 1 and VSSQ for a logic 0. Input rise and fall times (10% to 90%) < 1.6ns.
2. Input timing begins at VCC/2. Due to the possibility of a difference between VCC and VCCQ, the input test point may not
be shown to scale.
3. Output timing ends at VCCQ/2.
Figure 40.3 AC Input/Output Reference Waveform
VccQ
R1
Test Point
DUT
30pF
R2
Figure 40.4 Output Load Circuit
Table 40.7 Output Load Circuit
VCCQ
1.8V
2.5V
3.0V
R1/R2
2.7KΩ
3.7KΩ
4.5KΩ
August 25, 2005 CellRAM_05_A0
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A d v a n c e I n f o r m a t i o n
Table 40.8 READ Cycle Timing Requirements
Parameter
Symbol
Min
Max
70
20
70
8
Units
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Address Access Time
tAA
Page Access Time
tAPA
tBA
LB#/UB# Access Time
LB#/UB# Disable to High-Z Output
LB#/UB# Enable to Low-Z Output
Maximum CE# Pulse Width
Chip Select Access Time
Chip Disable to High-Z Output
Chip Enable to Low-Z Output
Output Enable to Valid Output
Output Hold from Address Change
Output Disable to High-Z Output
Output Enable to Low-Z Output
Page Cycle Time
tBHZ
tBLZ
tCEM
tCO
(note 2)
(note 1)
(note 3)
10
8
70
8
tHZ
(note 2)
(note 1)
tLZ
10
5
tOE
20
8
tOH
tOHZ
tOLZ
tPC
(note 2)
(note 1)
5
20
70
Read Cycle Time
tRC
Notes:
1. High-Z to Low-Z timings are tested with the circuit shown in Figure 40.4 on page 183. The Low-Z timings measure a 100-
mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL.
2. Low-Z to High-Z timings are tested with the circuit shown in Figure 40.4 on page 183. The High-Z timings measure a
100-mV transition from either VOH or VOL toward VCCQ/2.
3. Page mode enabled only.
Table 40.9 WRITE Cycle Timing Requirements
Parameter
Symbol
tAS
Min
0
Max
Units
ns
Notes
Address Setup Time
Address Valid to End of Write
Byte Select to End of Write
CE# HIGH Time During Write
Chip Enable to End of Write
Data Hold from Write Time
Data Write Setup Time
Chip Enable to Low-Z Output
End Write to Low-Z Output
Write Cycle Time
tAW
70
70
5
ns
tBW
ns
tCPH
tCW
ns
70
0
ns
tDH
ns
tDW
tLZ
tOW
tWC
tWHZ
tWP
tWPH
tWR
23
10
5
ns
ns
(note 1)
(note 1)
ns
70
ns
Write to High-Z Output
Write Pulse Width
8
ns
(note 2)
(note 3)
46
10
0
ns
Write Pulse Width HIGH
Write Recovery Time
ns
ns
Notes:
1. High-Z to Low-Z timings are tested with the circuit shown in Figure 40.4 on page 183. The Low-Z timings measure a 100-
mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL
.
2. Low-Z to High-Z timings are tested with the circuit shown in Figure 40.4 on page 183. The High-Z timings measure a
100-mV transition from either VOH or VOL toward VCCQ/2.
3. WE# LOW time must be limited to tCEM (8ìs).
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Table 40.10 Load Configuration Register Timing Requirements
Description
Symbol
tAS
Min
0
Max
Units
ns
Address Setup Time
Address Valid to End of Write
Chip Deselect to ZZ# LOW
Chip Enable to End of Write
Write Cycle Time
tAW
70
5
ns
tCDZZ
tCW
ns
70
70
40
0
ns
tWC
ns
Write Pulse Width
tWP
ns
Write Recovery Time
ZZ# LOW to WE# LOW
tWR
ns
tZZWE
10
500
ns
Table 40.11 Deep Power-Down Timing Requirements
Description
Symbol
tCDZZ
tR
Min
5
Max
Units
ns
Chip Deselect to ZZ# LOW
Deep Power-Down Recovery
Minimum ZZ# Pulse Width
150
10
µs
tZZMIN
µs
Vcc (MIN)
Vcc, VccQ = 1.7V
t
PU
Device ready for
normal operation
Figure 40.5 Power-Up Initialization Period
Table 40.12 Power-Up Initialization Timing Requirements
Description
Symbol
Min
Max
Units
Power-Up Initialization Period
tPU
150
µs
August 25, 2005 CellRAM_05_A0
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A d v a n c e I n f o r m a t i o n
tWC
ADDRESS
OPCODE
t
WR
tAW
t
CW
CE#
LB#/UB#
t
AS
tWP
WE#
OE#
t
CDZZ
tZZWE
ZZ#
DON’T CARE
Figure 40.6 Load Configuration Register
Table 40.13 Load Configuration Register Timing Requirements
Symbol
tAS
Min
0
Max
Units
ns
tAW
70
5
ns
tCDZZ
tCW
ns
70
70
40
0
ns
tWC
ns
tWP
ns
tWR
ns
tZZWE
10
500
ns
tCDZZ
tZZ (MIN)
ZZ#
CE#
t
R
Device ready for
normal operation
DON’T CARE
Figure 40.7 Deep Power-Down – Entry/Exit
Table 40.14 Deep Power-Down Timing Parameters
Symbol
tCDZZ
Min
5
Max
Units
ns
µs
µs
tR
150
10
tZZ (MIN)
186
Aysnc/Page CellularRAM Type 2
CellRAM_05_A0 August 25, 2005
A d v a n c e I n f o r m a t i o n
t
RC
ADDRESS VALID
ADDRESS
CE#
t
t
AA
HZ
t
CO
t
t
BA
BHZ
LB#/UB#
t
LZ
t
BLZ
t
OHZ
t
OE
OE#
t
OLZ
High-Z
High-Z
DATA VALID
DATA-OUT
DON’T CARE
UNDEFINED
Figure 40.8 Single READ Operation (WE# = VIH
)
Table 40.15 Single READ Timing Parameters
Symbol
tAA
Min
Max
70
70
8
Units
ns
tBA
ns
tBHZ
tBLZ
tCO
ns
10
10
ns
70
8
ns
tHZ
ns
tLZ
ns
tOE
20
8
ns
tOHZ
tOLZ
tRZ
ns
5
ns
70
ns
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A d v a n c e I n f o r m a t i o n
t
RC
ADDRESS
A[20:4]
ADDRESS VALID
ADDRESS
A[3:0]
t
t
PC
AA
t
t
HZ
CEM
CE#
t
CO
t
BHZ
t
BA
LB#/UB#
t
BLZ
t
LZ
t
OHZ
t
OE
OE#
t
APA
OH
t
OLZ
t
DATA
DATA
DATA
DATA
High-Z
High-Z
DATA-OUT
VALID
VALID
VALID
VALID
DON’T CARE
UNDEFINED
Figure 40.9 Page Mode READ Operation (WE# = VIH
)
Table 40.16 Page Mode READ Timing Parameters (WE# = VIH)
Symbol
tAA
Min
Max
70
20
70
8
Units
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAPA
tBA
tBHZ
tBLZ
tCEM
tCO
10
8
70
8
tHZ
tLZ
10
5
tOE
20
8
tOH
tOHZ
tOLZ
tPC
5
20
70
tRC
188
Aysnc/Page CellularRAM Type 2
CellRAM_05_A0 August 25, 2005
A d v a n c e I n f o r m a t i o n
t
WC
ADDRESS VALID
ADDRESS
t
t
WR
AW
t
CW
CE#
t
BW
LB#/UB#
t
t
t
WPH
AS
WP
WE#
OE#
t
t
DH
DW
DATA VALID
t
DATA-IN
t
WHZ
OW
High-Z
DATA-OUT
DON’T CARE
Figure 40.10 WRITE Cycle (WE# Control)
Table 40.17 WRITE Cycle Timing Parameters (WE# Control)
Symbol
tAS
Min
0
Max
Units
ns
tAW
70
70
70
0
ns
tBW
ns
tCW
ns
tDH
ns
tDW
23
5
ns
tOW
tWC
tWHZ
tWP
tWPH
tWR
ns
70
ns
8
ns
46
10
0
ns
ns
ns
August 25, 2005 CellRAM_05_A0
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A d v a n c e I n f o r m a t i o n
t
WC
ADDRESS VALID
ADDRESS
t
t
AW
WR
t
t
CW
CPH
CE#
t
AS
t
BW
LB#/UB#
t
WP
WE#
OE#
t
t
DH
DW
DATA VALID
High-Z
DATA-IN
t
LZ
t
WHZ
DATA-OUT
DON’T CARE
Figure 40.11 WRITE Cycle (CE# Control)
Table 40.18 WRITE Cycle Timing Parameters (CE# Control)
Symbol
tAS
Min
0
Max
Units
ns
tAW
70
70
5
ns
tBW
ns
tCPH
tCW
ns
70
0
ns
tDH
ns
tDW
tLZ
23
10
70
ns
ns
tWC
ns
tWHZ
tWP
8
ns
46
0
ns
tWR
ns
190
Aysnc/Page CellularRAM Type 2
CellRAM_05_A0 August 25, 2005
A d v a n c e I n f o r m a t i o n
t
WC
ADDRESS VALID
ADDRESS
t
t
AW
WR
t
CW
CE#
t
t
AS
BW
LB#/UB#
WE#
OE#
t
t
DW
DH
DATA-IN
DATA VALID
t
LZ
t
WHZ
High-Z
DATA-OUT
DON’T CARE
Figure 40.12 WRITE Cycle (LB#/UB# Control)
Table 40.19 WRITE Cycle Timing Parameters (LB#/UB# Control)
Symbol
tAS
Min
0
Max
Units
ns
tAW
70
70
70
0
ns
tBW
ns
tCW
ns
tDH
ns
tDW
tLZ
23
10
70
ns
ns
tWC
8
8
ns
tWHZ
tWR
ns
0
ns
August 25, 2005 CellRAM_05_A0
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A d v a n c e I n f o r m a t i o n
41 32/16M CellRAM Revision Summary
Revision A (August 25, 2005)
Initial release.
192
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CellRAM_05_A0 August 25, 2005
A d v a n c e I n f o r m a t i o n
42 MCP Revision Summary
42.1 Revision A0 (October 14, 2004)
Initial release.
42.2 Revision A1 (June 15, 2005)
Added two 80-ball pinouts
Added new TLC080 package drawing
Swapped 128/64/32 module with CellularRAM 16/32/64.
42.3 Revision A2 (October 28, 2005)
Global: added Package on Package (PoP) information
Updated the Ordering Information table
Added a valid combinations table for the 64/16 device
Added two 128-ball pinouts
Added new ALG128 package drawing
42.4 Revision A3 (November 28, 2005)
Replaced CellRAM modules with the 64M CellularRAM Type 2 and 32/16M Aysnc/Page CellularRAM
Type 2
Updated the Flash Module with latest version data sheet
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary
industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that
includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal
injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and
artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-
mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels
and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on ex-
port under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the
prior authorization by the respective government entity will be required for export of those products.
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S71WS-J Based MCPs
S71WS-J_03_A3 November 28, 2005
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SI9130DB
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