S71WS128JB0BAWTY3 [SPANSION]
Stacked Multi-Chip Product (MCP); 堆叠式多芯片产品（ MCP ）
| 型号： | S71WS128JB0BAWTY3 |
| 厂家： | 
SPANSION |
| 描述： | Stacked Multi-Chip Product (MCP) |
| 文件： | 总186页 (文件大小：4364K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S71WS-J Based MCPs
Stacked Multi-Chip Product (MCP)
128/64 Megabit (8M/4M x 16-bit) CMOS 1.8 Volt-only,
Simultaneous Read/Write, Burst Mode Flash Memory
with CosmoRAM
PRELIMINARY
Data Sheet
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Publication Number S71WS-J_04 Revision A Amendment 2 Issue Date August 19, 2005
P r e l i m i n a r y
Notice On Data Sheet Designations
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S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
S71WS-J Based MCPs
Stacked Multi-Chip Product (MCP)
128/64 Megabit (8M/4M x 16-bit) CMOS 1.8 Volt-only,
Simultaneous Read/Write, Burst Mode Flash Memory
with CosmoRAM
Data Sheet
PRELIMINARY
Distinctive Characteristics
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General Description
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Flash Memory Density
256Mb
128Mb
64Mb
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Publication Number S71WS-J_04 Revision A Amendment 2 Issue Date August 19, 2005
P r e l i m i n a r y
Product Selector Guide
pSRAM
Speed
(MHz/ns)
Flash Speed
(MHz)
Device-Model#
Flash Density
pSRAM Density
Supplier
Package
Availability Status
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S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Persistent Protection Bit Lock .......................................................................38
Standby Mode ......................................................................................................39
Automatic Sleep Mode .....................................................................................39
RESET#: Hardware Reset Input ................................................................39
Output Disable Mode ...................................................................................40
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Secured Silicon Sector Protection Bit ......................................................43
Hardware Data Protection .........................................................................43
S71WS-J Based MCPs
Notice On Data Sheet Designations . . . . . . . . . . . ii
Advance Information .......................................................................................ii
Preliminary ..........................................................................................................ii
Combination .......................................................................................................ii
Full Production (No Designation on Document) ...................................ii
MCP Features ........................................................................................................ 1
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 2
MCP Block Diagram .............................................................................................6
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 7
Lookahead Connection Diagram . . . . . . . . . . . . 10
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 11
Ordering Information . . . . . . . . . . . . . . . . . . . . . . 12
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 14
TLA084—84-ball Fine-Pitch Ball Grid Array (FBGA)
8 x 11.6 mm Package ........................................................................................... 14
FTA084—84-ball Fine-Pitch Ball Grid Array
(FBGA) 8 x 11.6 mm Package ............................................................................15
TLC080—80-ball Fine-Pitch Ball Grid Array
(FBGA) 7 x 9 mm Package ............................................................................... 16
TSC080 - Fine-Pitch Ball Grid Array (FBGA) 7 x 9 mm Package .........17
Write Protect (WP#) .......................................................................................44
Low V Write Inhibit .................................................................................44
CC
Write Pulse “Glitch” Protection ...............................................................44
Logical Inhibit ...................................................................................................44
Power-Up Write Inhibit ...............................................................................44
Common Flash Memory Interface (CFI) . . . . . . . 45
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7DEOHꢀꢈꢑꢃꢀ:6ꢍꢉꢊ-ꢀ6HFWRUꢀ$GGUHVVꢀ7DEOHꢀ ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ ꢏꢉ
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 62
Reading Array Data ...........................................................................................62
Set Configuration Register Command Sequence .....................................62
)LJXUHꢀꢑꢃꢀ6\QFKURQRXVꢒ$V\QFKURQRXVꢀ6WDWHꢀ'LDJUDPꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ ꢀꢉꢑ
Read Mode Setting .........................................................................................63
Programmable Wait State Configuration ...............................................63
7DEOHꢀꢈꢊꢃꢀ3URJUDPPDEOHꢀ:DLWꢀ6WDWHꢀ6HWWLQJVꢀꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ ꢉꢊ
Standard wait-state Handshaking Option ...............................................64
7DEOHꢀꢈꢏꢃꢀ:DLWꢀ6WDWHVꢀIRUꢀ6WDQGDUGꢀZDLWꢅVWDWHꢀ+DQGVKDNLQJꢀꢀꢃꢃꢃꢃ ꢉꢊ
Read Mode Configuration ...........................................................................64
7DEOHꢀꢈꢉꢃꢀ5HDGꢀ0RGHꢀ6HWWLQJVꢀ ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ ꢉꢏ
Burst Active Clock Edge Configuration ..................................................65
RDY Configuration ........................................................................................65
7DEOHꢀꢈꢋꢃꢀ&RQILJXUDWLRQꢀ5HJLVWHUꢀꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ ꢉꢉ
Reset Command .................................................................................................66
Autoselect Command Sequence ....................................................................67
Enter/Exit Secured Silicon Sector Command Sequence .........................67
Program Command Sequence ........................................................................68
Unlock Bypass Command Sequence ........................................................68
)LJXUHꢀꢊꢃꢀ3URJUDPꢀ2SHUDWLRQ ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ ꢀꢉꢌ
Chip Erase Command Sequence ...................................................................69
Sector Erase Command Sequence ................................................................70
Erase Suspend/Erase Resume Commands ...................................................71
)LJXUHꢀꢏꢃꢀ(UDVHꢀ2SHUDWLRQ ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ ꢀꢋꢎ
Password Program Command .......................................................................72
Password Verify Command ............................................................................. 73
Password Protection Mode Locking Bit Program Command .............. 73
Persistent Sector Protection Mode Locking Bit
S29WS128/064J
General Description . . . . . . . . . . . . . . . . . . . . . . . .20
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .22
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Block Diagram of Simultaneous
Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . .23
Input/Output Descriptions . . . . . . . . . . . . . . . . . . .24
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .25
7DEOHꢀꢈꢃꢀ'HYLFHꢀ%XVꢀ2SHUDWLRQVꢀꢀꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ ꢎꢏ
VersatileIO™ (V ) Control .............................................................................25
IO
Requirements for Asynchronous Read Operation (Non-Burst) ..........25
Requirements for Synchronous (Burst) Read Operation ...................... 26
8-, 16-, and 32-Word Linear Burst with Wrap Around ......................27
7DEOHꢀꢎꢃꢀ%XUVWꢀ$GGUHVVꢀ*URXSVꢀ ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ ꢎꢋ
Configuration Register ......................................................................................27
Handshaking ..........................................................................................................27
Simultaneous Read/Write Operations with Zero Latency ................... 28
Writing Commands/Command Sequences ................................................ 28
Accelerated Program Operation .................................................................. 28
Autoselect Mode ................................................................................................ 29
7DEOHꢀꢑꢃꢀ$XWRVHOHFWꢀ&RGHVꢀꢁ+LJKꢀ9ROWDJHꢀ0HWKRGꢂꢀꢀ ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ ꢑꢍ
Sector/Sector Block Protection and Unprotection ................................. 30
7DEOHꢀꢊꢃꢀ6ꢎꢌ:6ꢈꢎꢇꢒꢍꢉꢊ-B0&3ꢀ%RRWꢀ6HFWRUꢒ6HFWRU
%ORFNꢀ$GGUHVVHVꢀIRUꢀ3URWHFWLRQꢒ8QSURWHFWLRQꢀ ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ ꢑꢍ
7DEOHꢀꢏꢃꢀ6ꢎꢌ:6ꢍꢉꢊ-ꢀ%RRWꢀ6HFWRUꢒ6HFWRUꢀ%ORFNꢀ$GGUHVVHVꢀIRUꢀ
3URWHFWLRQꢒ8QSURWHFWLRQꢀ ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ ꢑꢎ
Sector Protection ...........................................................................................34
Persistent Sector Protection ...........................................................................34
Persistent Protection Bit (PPB) ..................................................................35
Persistent Protection Bit Lock (PPB Lock) .............................................35
Dynamic Protection Bit (DYB) ...................................................................35
7DEOHꢀꢉꢃꢀ6HFWRUꢀ3URWHFWLRQꢀ6FKHPHVꢀꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ ꢑꢉ
Persistent Sector Protection Mode Locking Bit ........................................37
Password Protection Mode .............................................................................37
Password and Password Mode Locking Bit ................................................37
64-bit Password ...................................................................................................38
Program Command ........................................................................................... 73
Secured Silicon Sector Protection Bit Program Command .................. 73
PPB Lock Bit Set Command ............................................................................74
DPB Write/Erase/Status Command .............................................................74
Password Unlock Command ..........................................................................74
PPB Program Command .................................................................................. 75
All PPB Erase Command .................................................................................. 75
PPB Status Command ....................................................................................... 75
PPB Lock Bit Status Command ...................................................................... 75
Command Definitions .......................................................................................76
7DEOHꢀꢈꢇꢃꢀ&RPPDQGꢀ'HILQLWLRQVꢀꢀ ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ ꢋꢉ
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
3
P r e l i m i n a r y
%DQNꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ ꢀꢈꢈꢍ
)LJXUHꢀꢑꢉꢃꢀ([DPSOHꢀRIꢀ:DLWꢀ6WDWHVꢀ,QVHUWLRQꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ ꢀꢈꢈꢈ
)LJXUHꢀꢑꢋꢃꢀ%DFNꢅWRꢅ%DFNꢀ5HDGꢒ:ULWHꢀ&\FOHꢀ7LPLQJV ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ ꢀꢈꢈꢎ
Write Operation Status . . . . . . . . . . . . . . . . . . . . .79
DQ7: Data# Polling ............................................................................................79
)LJXUHꢀꢉꢃꢀ'DWDꢓꢀ3ROOLQJꢀ$OJRULWKPꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢀꢇꢍ
DQ6: Toggle Bit I ................................................................................................ 81
)LJXUHꢀꢋꢃꢀ7RJJOHꢀ%LWꢀ$OJRULWKPꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢀꢇꢎ
DQ2: Toggle Bit II .............................................................................................. 82
7DEOHꢀꢈꢌꢃꢀ'4ꢉꢀDQGꢀ'4ꢎꢀ,QGLFDWLRQVꢀ ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ ꢇꢑ
Reading Toggle Bits DQ6/DQ2 ......................................................................83
DQ5: Exceeded Timing Limits .......................................................................84
DQ3: Sector Erase Timer ................................................................................84
7DEOHꢀꢎꢍꢃꢀ:ULWHꢀ2SHUDWLRQꢀ6WDWXVꢀꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ ꢇꢏ
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 85
)LJXUHꢀꢇꢃꢀ0D[LPXPꢀ1HJDWLYHꢀ2YHUVKRRWꢀ:DYHIRUPꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢀꢇꢉ
)LJXUHꢀꢌꢃꢀ0D[LPXPꢀ3RVLWLYHꢀ2YHUVKRRWꢀ:DYHIRUP ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢀꢇꢉ
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 86
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .87
CosmoRAM
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Pin Description (32M) . . . . . . . . . . . . . . . . . . . . . . 114
Functional Description . . . . . . . . . . . . . . . . . . . . . 115
Asynchronous Operation (Page Mode) .......................................................115
Functional Description . . . . . . . . . . . . . . . . . . . . . 116
Synchronous Operation (Burst Mode) ........................................................116
State Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Initial/Standby State ............................................................................................117
)LJXUHꢀꢑꢇꢃꢀ,QLWLDOꢀ6WDQGE\ꢀ6WDWHꢀ'LDJUDP ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ ꢀꢈꢈꢋ
Asynchronous Operation State .....................................................................117
)LJXUHꢀꢑꢌꢃꢀ$V\QFKURQRXVꢀ2SHUDWLRQꢀ6WDWHꢀ'LDJUDPꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ ꢀꢈꢈꢋ
Synchronous Operation State ........................................................................118
)LJXUHꢀꢊꢍꢃꢀ6\QFKURQRXVꢀ2SHUDWLRQꢀ'LDJUDP ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ ꢀꢈꢈꢇ
Functional Description . . . . . . . . . . . . . . . . . . . . . 118
Power-up ...............................................................................................................118
Configuration Register ......................................................................................118
CR Set Sequence ................................................................................................118
Power Down ........................................................................................................121
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
)LJXUHꢀꢈꢍꢃꢀ7HVWꢀ6HWXS ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢀꢇꢇ
7DEOHꢀꢎꢈꢃꢀ7HVWꢀ6SHFLILFDWLRQVꢀꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ ꢇꢇ
Key to Switching Waveforms . . . . . . . . . . . . . . . 88
Switching Waveforms . . . . . . . . . . . . . . . . . . . . . 89
)LJXUHꢀꢈꢈꢃꢀ,QSXWꢀ:DYHIRUPVꢀDQGꢀ0HDVXUHPHQWꢀ/HYHOVꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢀꢇꢌ
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 89
V
Power-up .....................................................................................................89
CC
)LJXUHꢀꢈꢎꢃꢀ9 ꢀ3RZHUꢅXSꢀ'LDJUDP ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢀꢇꢌ
Burst Read/Write Operation ..........................................................................121
)LJXUHꢀꢊꢈꢃꢀ%XUVWꢀ5HDGꢀ2SHUDWLRQꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ ꢀꢈꢎꢎ
)LJXUHꢀꢊꢎꢃꢀ%XUVWꢀ:ULWHꢀ2SHUDWLRQ ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ ꢀꢈꢎꢎ
CLK Input Function ..........................................................................................122
&&
CLK Characterization .......................................................................................90
)LJXUHꢀꢈꢑꢃꢀ&/.ꢀ&KDUDFWHUL]DWLRQ ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢀꢌꢍ
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 91
ADV# Input Function .......................................................................................123
WAIT# Output Function ................................................................................123
)LJXUHꢀꢊꢑꢃꢀ5HDGꢀ/DWHQF\ꢀ'LDJUDP ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ ꢀꢈꢎꢊ
Address Latch by ADV# .................................................................................125
Burst Length ........................................................................................................125
Single Write .........................................................................................................125
Write Control ....................................................................................................126
)LJXUHꢀꢊꢊꢃꢀ:ULWHꢀ&RQWUROVꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ ꢀꢈꢎꢉ
Burst Read Suspend ..........................................................................................126
)LJXUHꢀꢊꢏꢃꢀ%XUVWꢀ5HDGꢀ6XVSHQGꢀ'LDJUDPꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ ꢀꢈꢎꢋ
Burst Write Suspend ........................................................................................127
)LJXUHꢀꢊꢉꢃꢀ%XUVWꢀ:ULWHꢀ6XVSHQGꢀ'LDJUDP ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ ꢀꢈꢎꢋ
Burst Read Termination ..................................................................................127
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Burst Write Termination ................................................................................128
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Absolute Maximum Ratings . . . . . . . . . . . . . . . . 129
Recommended Operating Conditions (See
Warning Below) . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Package Pin Capacitance . . . . . . . . . . . . . . . . . . . 129
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 130
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 131
Read Operation ..................................................................................................131
Write Operation ...............................................................................................133
Synchronous Operation - Clock Input (Burst Mode) ............................134
Synchronous Operation - Address Latch (Burst Mode) .......................134
Synchronous Read Operation (Burst Mode) ............................................135
Synchronous Write Operation (Burst Mode) ..........................................136
Power Down Parameters ...............................................................................137
Other Timing Parameters ...............................................................................137
AC Test Conditions .........................................................................................137
AC Measurement Output Load Circuit .....................................................138
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Synchronous/Burst Read @ V = 1.8 V ...................................................... 91
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Asynchronous Mode Read @ V = 1.8 V ..................................................95
IO
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Erase/Program Operations @ V = 1.8 V .................................................98
IO
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Temporary Sector Unprotect .......................................................................107
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4
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
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Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 139
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COSMORAM Type 1 – 1.8 V, 16 Mb
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
General Description . . . . . . . . . . . . . . . . . . . . . . . 169
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Function Truth Table . . . . . . . . . . . . . . . . . . . . . . 171
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 171
Recommended Operating Conditions . . . . . . . . 171
Package Pin Capacitance . . . . . . . . . . . . . . . . . . . 172
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 172
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 172
Read Operation .................................................................................................172
Write Operation ..............................................................................................173
Power Down Parameters ...............................................................................174
Other Timing Parameters ...............................................................................174
AC Test Conditions .........................................................................................174
AC Measurement Output Load Circuit .....................................................174
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 175
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6LQJOHꢀ:ULWHꢂ ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢀꢈꢏꢌ
)LJXUHꢀꢇꢍꢃꢀꢑꢎ0ꢀ6\QFKURQRXVꢀ5HDGꢀWRꢀ:ULWHꢀ7LPLQJꢀꢓꢈꢁ&(ꢈꢓꢀ
&RQWUROꢂ ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢀꢈꢉꢍ
)LJXUHꢀꢇꢈꢃꢀꢑꢎ0ꢀ6\QFKURQRXVꢀ5HDGꢀWRꢀ:ULWHꢀ7LPLQJꢀꢓꢎꢁ$'9ꢓꢀ
&RQWUROꢂ ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢀꢈꢉꢈ
)LJXUHꢀꢇꢎꢃꢀꢉꢊ0ꢀ6\QFKURQRXVꢀ5HDGꢀWRꢀ:ULWHꢀ7LPLQJꢀꢓꢈꢁ&(ꢈꢓꢀ
&RQWUROꢂ ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢀꢈꢉꢎ
)LJXUHꢀꢇꢑꢃꢀꢉꢊ0ꢀ6\QFKURQRXVꢀ5HDGꢀWRꢀ:ULWHꢀ7LPLQJꢀꢓꢎꢁ$'9ꢓꢀ
&RQWUROꢂ ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢀꢈꢉꢑ
)LJXUHꢀꢇꢊꢃꢀ6\QFKURQRXVꢀ:ULWHꢀWRꢀ5HDGꢀ7LPLQJꢀꢓꢈꢀ
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 183
ꢁ&(ꢈꢓꢀ&RQWUROꢂ ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢀꢈꢉꢊ
Revision Summary
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
5
P r e l i m i n a r y
MCP Block Diagram
F-VCC
Flash-only Address
Shared Address
V
V
ID
CC
DQ15 to DQ0
CLK
WP#
A22
16
DQ15 to DQ0
CLK
F-WP#
F-ACC
(Note 3) F1-CE#
OE#
ACC
CE#
OE#
WE#
Flash 1
Flash 2
(Note 4)
WE#
F-RST#
AVD#
RESET#
AVD#
RDY
RDY
(Note 3) F2-CE#
V
SS
R-V
CC
A22
V
V
CCQ
CC
WAIT#
(Note 5)
CLK
16
R-CE1#
CE#
WE#
OE#
I/O15 to I/O0
pSRAM
R-UB#
R-LB#
UB#
LB#
V
SSQ
(Note 1) R-CE2
(Note 5)
AVD#
(Note 2) R-CRE
1RWHVꢀ
ꢀꢁ 5ꢂ&5(ꢃLVꢃRQO\ꢃSUHVHQWꢃLQꢃ&HOOXODU5$0ꢂFRPSDWLEOHꢃS65$0ꢁ
ꢄꢁ 5ꢂ&(ꢄꢃLVꢃRQO\ꢃSUHVHQWꢃLQꢃ&RVPR5$0ꢂFRPSDWLEOHꢃS65$0ꢁ
ꢅꢁ )RUꢃꢀꢃ)ODVKꢃ ꢃS65$0ꢆꢃ)ꢀꢂ&(!ꢃ ꢃ&(!ꢁꢃ)RUꢃꢄꢃ)ODVKꢃꢇꢃS65$0ꢆꢃ&(!ꢃ ꢃ)ꢀꢂ&(!ꢃDQGꢃ)ꢄꢂ&(!ꢃLVꢃWKHꢃFKLSꢂHQDEOHꢃSLQꢃIRUꢃWKHꢃVHFRQGꢃ)ODVKꢁ
ꢈꢁ 2QO\ꢃQHHGHGꢃIRUꢃ6ꢉꢀ:6ꢄꢊꢋ-&ꢌꢆꢃDQGꢃ6ꢉꢌ:6ꢄꢊꢋ-ꢌꢌꢁ
ꢊꢁ &/.ꢃDQGꢃ$9'!ꢃQRWꢃDSSOLFDEOHꢃIRUꢃꢀꢋ0EꢃS65$0ꢁ
6
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Connection Diagrams
(CosmoRAM Type-based)
ꢊꢋꢌEDOOꢀ)LQHꢌ3LWFKꢀ%DOOꢀ*ULGꢀ$UUD\
&RVPR5$0ꢅEDVHGꢀ3LQRXWꢀꢁ7RSꢀ9LHZꢄꢀ%DOOVꢀ
)DFLQJꢀ'RZQꢂ
A1
NC
A10
NC
Legend
Shared
B2
B3
B4
B5
B6
B7
B8
B9
AVD#
RFU
CLK
F2-CE#
RFU
RFU
RFU
RFU
C2
C3
A7
C4
LB#s
D4
C5
ACC
D5
C6
WE#
D6
C7
A8
C8
A11
D9
C9
RFU
D10
A15
E9
WP#
D2
1st Flash only
2nd Flash only
1st RAM only
D3
A6
D7
A3
UB#s RESET#
CE2s
E6
A19
E7
A12
E8
E2
A2
E3
E4
A18
F4
E5
RDY
F5
A5
A20
F6
A9
A13
F8
A21
F9
F2
F3
F7
RFU
A23
A1
A4
A17
G4
A10
G7
A14
G8
A22
G9
G2
G3
VSS
H3
G5
RFU
H5
G6
RFU
H6
A0
DQ1
H4
DQ6
H7
RFU
H8
A16
Reserved for
Future Use
H2
H9
RFU
J9
CE1#f
J2
OE#
J3
DQ9
J4
DQ3
J5
DQ4
J6
DQ13
J7
DQ15
J8
CE1#s
K2
DQ0
K3
DQ10
K4
VCCf
K5
VCCs
K6
DQ12
K7
DQ7
K8
VSS
K9
RFU
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
RFU
L5
L2
L3
L4
L6
L7
L8
L9
RFU
RFU
RFU
VCCf
RFU
RFU
RFU
RFU
M1
NC
M10
NC
1RWHVꢀ
ꢀꢁ ,Qꢃ0&3¶VꢃEDVHGꢃRQꢃDꢃVLQJOHꢃ6ꢄꢍ:6[[[-ꢃꢎ6ꢉꢀ:6[[[-ꢏꢆꢃEDOOꢃ%ꢊꢃLVꢃ5)8ꢁꢃ,Qꢃ0&3¶VꢃEDVHGꢃRQꢃWZRꢃ6ꢄꢍ:6[[[-ꢃꢎ6ꢉꢀ:6ꢄꢊꢋ-ꢏꢆꢃEDOOꢃ%ꢊꢃLVꢃ&(!IꢄꢃRUꢃ
)ꢄꢂ&(!ꢁ
ꢄꢁ $GGUHVVHVꢃDUHꢃVKDUHGꢃEWZHHQꢃ)ODVKꢃDQGꢃ5$0ꢃGHSHQGLQJꢃRQꢃWKHꢃGHQVLW\ꢃRIꢃWKHꢃS65$0ꢁ
MCP
Flash-only Addresses
$ꢎꢈꢅ$ꢎꢍ
$ꢎꢈ
Shared Addresses
$ꢈꢌꢅ$ꢍ
6ꢋꢈ:6ꢍꢉꢊ-$ꢍ
6ꢋꢈ:6ꢍꢉꢊ-%ꢍ
6ꢋꢈ:6ꢈꢎꢇ-$ꢍ
6ꢋꢈ:6ꢈꢎꢇ-%ꢍ
6ꢋꢈ:6ꢈꢎꢇ-&ꢍ
$ꢎꢍꢅ$ꢍ
$ꢎꢎꢅ$ꢎꢍ
$ꢎꢎꢅ$ꢎꢈ
$ꢎꢎ
$ꢈꢌꢅ$ꢍ
$ꢈꢌꢅ$ꢍ
$ꢎꢈꢅ$ꢍ
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
7
P r e l i m i n a r y
MCP
Flash-only Addresses
Shared Addresses
$ꢎꢈꢅ$ꢍ
6ꢋꢈ:6ꢎꢏꢉ-&ꢍ
$ꢎꢎ
6SHFLDOꢀ+DQGOLQJꢀ,QVWUXFWLRQVꢀ)RUꢀ)%*$ꢀ3DFNDJH
6SHFLDOꢀKDQGOLQJꢀLVꢀUHTXLUHGꢀIRUꢀ)ODVKꢀ0HPRU\ꢀSURGXFWVꢀLQꢀ)%*$ꢀSDFNDJHVꢃ
)ODVKꢀPHPRU\ꢀGHYLFHVꢀLQꢀ)%*$ꢀSDFNDJHVꢀPD\ꢀEHꢀGDPDJHGꢀLIꢀH[SRVHGꢀWRꢀXOWUDVRQLFꢀFOHDQLQJꢀPHWKꢅ
RGVꢃꢀ7KHꢀSDFNDJHꢀDQGꢒRUꢀGDWDꢀLQWHJULW\ꢀPD\ꢀEHꢀFRPSURPLVHGꢀLIꢀWKHꢀSDFNDJHꢀERG\ꢀLVꢀH[SRVHGꢀWRꢀ
WHPSHUDWXUHVꢀDERYHꢀꢈꢏꢍ°&ꢀIRUꢀSURORQJHGꢀSHULRGVꢀRIꢀWLPHꢃ
(CosmoRAM Type-based)
ꢊꢍꢌEDOOꢀ)LQHꢌ3LWFKꢀ%DOOꢀ*ULGꢀ$UUD\
&RVPR5$0ꢅEDVHGꢀ3LQRXWꢀꢁ7RSꢀ9LHZꢄꢀ%DOOVꢀ
Legend
A1
A2
A3
A4
A5
A6
A7
A8
AVD#
RFU
CLK
F2-CE#
RFU
RFU
RFU
RFU
Shared
B1
B2
A7
B3
LB#s
C3
B4
ACC
C4
B5
WE#
C5
B6
A8
B7
A11
C7
B8
RFU
C8
WP#
C1
1st Flash only
C2
C6
A3
A6
UB#s RESET#
CE2s
D5
A19
D6
A12
D7
A15
D8
D1
A2
D2
A5
D3
A18
E3
D4
RDY
E4
2nd Flash only
1st RAM only
A20
E5
A9
A13
E7
A21
E8
E1
E2
E6
RFU
A23
A1
A4
A17
F3
A10
F6
A14
F7
A22
F8
F1
F2
F4
RFU
G4
F5
RFU
G5
A0
VSS
G2
OE#
H2
DQ1
G3
DQ6
G6
RFU
G7
A16
Reserved for
Future Use
G1
G8
RFU
H8
CE1#f
H1
DQ9
H3
DQ3
H4
DQ4
H5
DQ13
H6
DQ15
H7
CE1#s
J1
DQ0
J2
DQ10
J3
VCCf
J4
VCCs
J5
DQ12
J6
DQ7
J7
VSS
J8
RFU
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
RFU
K4
K1
K2
K3
K5
K6
K7
K8
RFU
RFU
RFU
VCCf
RFU
RFU
RFU
RFU
1RWHVꢀ
ꢀꢁ ,Qꢃ0&3¶VꢃEDVHGꢃRQꢃDꢃVLQJOHꢃ6ꢄꢍ:6[[[-ꢃꢎ6ꢉꢀ:6[[[-ꢏꢆꢃEDOOꢃ%ꢊꢃLVꢃ5)8ꢁꢃ,Qꢃ0&3¶VꢃEDVHGꢃRQꢃWZRꢃ6ꢄꢍ:6[[[-ꢃꢎ6ꢉꢀ:6ꢄꢊꢋ-ꢏꢆꢃEDOOꢃ%ꢊꢃLVꢃ&(!IꢄꢃRUꢃ
)ꢄꢂ&(!ꢁ
ꢄꢁ $GGUHVVHVꢃDUHꢃVKDUHGꢃEWZHHQꢃ)ODVKꢃDQGꢃ5$0ꢃGHSHQGLQJꢃRQꢃWKHꢃGHQVLW\ꢃRIꢃWKHꢃS65$0ꢁ
ꢅꢁ 7KHꢃꢐꢌꢂEDOOꢃSLQRXWꢃLVꢃDSSOLFDEOHꢃRQO\ꢃWRꢃWKRVHꢃ0&3VꢃZLWKꢃ)ODVKꢃGHQVLW\ꢃRIꢃꢋꢈ0EꢃRUꢃꢅꢄ0Eꢁꢃ)RUꢃDOOꢃWKHꢃRWKHUꢃ0&3VꢃLQFOXGHGꢃLQꢃWKLVꢃGDWDVKHHWꢆꢃ
SOHDVHꢃXVHꢃWKHꢃꢐꢈꢂEDOOꢃSLQRXWꢃIRUꢃGHVLJQꢁ
MCP
6ꢋꢈ:6ꢍꢉꢊ-$ꢍ
6ꢋꢈ:6ꢍꢉꢊ-%ꢍ
Flash-only Addresses
$ꢎꢈꢅ$ꢎꢍ
Shared Addresses
$ꢈꢌꢅ$ꢍ
$ꢎꢈ
$ꢎꢍꢅ$ꢍ
8
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
MCP
Flash-only Addresses
Shared Addresses
$ꢈꢌꢅ$ꢍ
6ꢋꢈ:6ꢈꢎꢇ-$ꢍ
6ꢋꢈ:6ꢈꢎꢇ-%ꢍ
6ꢋꢈ:6ꢈꢎꢇ-&ꢍ
6ꢋꢈ:6ꢎꢏꢉ-&ꢍ
$ꢎꢎꢅ$ꢎꢍ
$ꢎꢎꢅ$ꢎꢈ
$ꢎꢎ
$ꢈꢌꢅ$ꢍ
$ꢎꢈꢅ$ꢍ
$ꢎꢎ
$ꢎꢈꢅ$ꢍ
6SHFLDOꢀ+DQGOLQJꢀ,QVWUXFWLRQVꢀ)RUꢀ)%*$ꢀ3DFNDJH
6SHFLDOꢀKDQGOLQJꢀLVꢀUHTXLUHGꢀIRUꢀ)ODVKꢀ0HPRU\ꢀSURGXFWVꢀLQꢀ)%*$ꢀSDFNDJHVꢃ
)ODVKꢀPHPRU\ꢀGHYLFHVꢀLQꢀ)%*$ꢀSDFNDJHVꢀPD\ꢀEHꢀGDPDJHGꢀLIꢀH[SRVHGꢀWRꢀXOWUDVRQLFꢀFOHDQLQJꢀPHWKꢅ
RGVꢃꢀ7KHꢀSDFNDJHꢀDQGꢒRUꢀGDWDꢀLQWHJULW\ꢀPD\ꢀEHꢀFRPSURPLVHGꢀLIꢀWKHꢀSDFNDJHꢀERG\ꢀLVꢀH[SRVHGꢀWRꢀ
WHPSHUDWXUHVꢀDERYHꢀꢈꢏꢍ°&ꢀIRUꢀSURORQJHGꢀSHULRGVꢀRIꢀWLPHꢃ
9
S71WS-J_04A2 August 19, 2005
P r e l i m i n a r y
Lookahead Connection Diagram
Legend:
A9
A2
A10
A1
DNU
DNU
DNU
Shared
or DNU
(Do Not Use)
DNU
B9
B1
B2
B10
DNU
DNU
DNU
DNU
MirrorBit Data-storage Only
Flash/Data Shared Only
C4
CC55
C6
C7
C8
C9
C2
C3
AVD#
VSS
CLK
F2-CE#
F-VCC
F-CLK
R-OE# F2-OE#
D2
D3
A7
D6
D7
A8
D8
D9
D4
D5
F-WP#
R-LB# WP#/ACC WE#
E5 E6
R-UB# F-RST# R1-CE2
A11
F3-CE#
E2
A3
E3
A6
E7
E8
E9
E4
1st Flash Only
Flash Only
A19
A12
A15
F2
A2
F3
A5
F4
F5
F6
F7
A9
F8
F9
A18
RDY
A20
A13
A21
G2
A1
G3
A4
G4
GG55
G6
G7
G8
G9
A17
R2-CE1
A23
A10
A14
A22
1st RAM Only
2nd RAM Only
xRAM Shared Only
H2
A0
H3
H4
HH55
H6
H7
H8
H9
VSS
DQ1
R2-VCC R2-CE2
DQ6
A24
A16
J2
J3
J4
J5
J6
J7
J8
J2
DQ9
DQ3
DQ4
DQ13
DQ15
DNU
F1-CE#
OE#
K2
K3
K4
KK55
K6
K7
K8
K9
DQ12
VSS
R1-CE1#
DQ0
DQ10
F-VCC
R1-VCC
DQ7
L2
L4
L5
L6
L7
L8
L9
L3
DQ2
DQ11
A25
DQ5
DQ14 WP#/ACC
R-VCC
DQ8
M2
M3
M4
M5
M6
M7
M8
M9
R-CLK
A27
A26
VSS
F-VCC
F4-CE# R-VCCQ F-VCCQ
N9
N1
N2
N10
DNU
F-DQS-1
F-DQS0
DNU
P1
P9
P2
P10
DNU
DNU
DNU
DNU
1RWHVꢀ
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10
P r e l i m i n a r y
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S71WS-J Based MCPs
11
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12
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
S71WS064JB0 Valid Combinations (WS064J Flash + 32Mb pSRAM)
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
13
P r e l i m i n a r y
Physical Dimensions
TLA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm Package
A
D1
D
eD
0.15
(2X)
C
10
9
8
SE
7
7
6
E
B
E1
5
4
3
2
1
eE
J
H
G
F
E
D
C
B
A
M
L K
INDEX MARK
10
PIN A1
CORNER
PIN A1
CORNER
7
SD
0.15
(2X)
C
TOP VIEW
BOTTOM VIEW
0.20
C
C
A2
A
0.08
C
A1
SIDE VIEW
6
84X
b
0.15
0.08
M
C
C
A
B
M
NOTES:
PACKAGE
JEDEC
TLA 084
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
11.60 mm x 8.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
---
NOM
---
MAX
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
1.20
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.17
0.81
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
0.97
BODY THICKNESS
BODY SIZE
D
11.60 BSC.
8.00 BSC.
8.80 BSC.
7.20 BSC.
12
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
E1
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
10
84
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
Ø b
eE
0.35
0.40
0.45
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
0.80 BSC.
0.80 BSC
0.40 BSC.
BALL PITCH
eD
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SD / SE
SOLDER BALL PLACEMENT
A2,A3,A4,A5,A6,A7,A8,A9
B1,B10,C1,C10,D1,D10,
E1,E10,F1,F10,G1,G10,
H1,H10,J1,J10,K1,K10,L1,L10,
M2,M3,M4,M5,M6,M7,M8,M9
DEPOPULATED SOLDER BALLS
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3372-2 \ 16-038.22a
14
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
FTA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm Package
A
D1
D
eD
0.15
(2X)
C
10
9
8
SE
7
7
6
E
B
E1
5
4
3
2
1
eE
J
H
G
F
E
D
C
B
A
M
L K
INDEX MARK
10
PIN A1
CORNER
PIN A1
CORNER
7
SD
0.15
(2X)
C
TOP VIEW
BOTTOM VIEW
0.20
0.08
C
C
A2
A
C
A1
SIDE VIEW
6
84X
b
0.15
M
C
C
A
B
0.08
M
NOTES:
PACKAGE
JEDEC
FTA 084
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
11.60 mm x 8.00 mm
PACKAGE
NOTE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
---
NOM
---
MAX
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
1.40
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.17
1.02
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
1.17
BODY THICKNESS
BODY SIZE
D
11.60 BSC.
8.00 BSC.
8.80 BSC.
7.20 BSC.
12
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
E1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
10
84
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
φb
0.35
0.40
0.45
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
eE
0.80 BSC.
0.80 BSC
0.40 BSC.
BALL PITCH
eD
SD / SE
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SOLDER BALL PLACEMENT
A2,A3,A4,A5,A6,A7,A8,A9
B1,B10,C1,C10,D1,D10,E1,E10
F1,F10,G1,G10,H1,H10
DEPOPULATED SOLDER BALLS
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
J1,J10,K1,K10,L1,L10
M2,M3,M4,M5,M6,M7,M8,M9
3388 \ 16-038.21a
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
15
P r e l i m i n a r y
TLC080—80-ball Fine-Pitch Ball Grid Array (FBGA) 7 x 9 mm Package
D1
A
D
eD
0.15
(2X)
C
8
7
SE
7
6
5
4
3
2
E
B
E1
eE
1
K
J
H
G
F
E
D
C
B
A
INDEX MARK
10
PIN A1
CORNER
PIN A1
CORNER
7
SD
0.15
(2X)
C
TOP VIEW
BOTTOM VIEW
0.20
0.08
C
A2
A
C
C
A1
SIDE VIEW
6
80X
b
0.15
0.08
M
M
C
C
A
B
NOTES:
PACKAGE
JEDEC
TLC 080
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
9.00 mm x 7.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
NOM
---
MAX
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
---
1.20
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.17
0.81
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
0.97
BODY THICKNESS
BODY SIZE
D
9.00 BSC.
7.00 BSC.
7.20 BSC.
5.60 BSC.
10
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
E1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
8
80
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
φb
0.35
0.40
0.45
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
eE
0.80 BSC.
0.80 BSC
0.40 BSC.
BALL PITCH
eD
SD / SE
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3430 \ 16-038.22 \ 10.15.04
16
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
TSC080 - Fine-Pitch Ball Grid Array (FBGA) 7 x 9 mm Package
D1
A
D
eD
0.15
(2X)
C
8
7
SE
7
6
5
4
3
2
E
B
E1
eE
1
K
J
H
G
F
E
D
C
B
A
INDEX MARK
9
PIN A1
CORNER
PIN A1
CORNER
7
SD
0.15
(2X)
C
TOP VIEW
BOTTOM VIEW
0.20
0.08
C
C
A2
A
C
A1
SIDE VIEW
6
80X
b
0.15
M
C
C
A
B
0.08
M
NOTES:
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
PACKAGE
JEDEC
TSC 080
N/A
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
9.00 mm x 7.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3,
SPP-010.
SYMBOL
MIN
---
NOM
---
MAX
1.20
---
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.17
0.81
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
0.97
BODY THICKNESS
BODY SIZE
D
9.00 BSC.
7.00 BSC.
7.20 BSC.
5.60 BSC.
10
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
E1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
8
80
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
Øb
eE
0.35
0.40
0.45
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
0.80 BSC.
0.80 BSC
0.40 BSC.
BALL PITCH
eD
SD / SE
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3496 \ 16-038.22 \ 5.20.05
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
17
S29WS128/064J
Flash Family for Multi-Chip Products (MCP)
128/64 Megabit (8/4 M x 16-Bit) CMOS 1.8 Volt-only
Simultaneous Read/Write, Burst Mode Flash Memory
PRELIMINARY
Distinctive Characteristics
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Publication Number S71WS-J_04 Revision A Amendment 2 Issue Date August 19, 2005
P r e l i m i n a r y
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
19
P r e l i m i n a r y
General Description
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S71WS-J_04_A2 August 19, 2005
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S71WS-J Based MCPs
21
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S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
23
P r e l i m i n a r y
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S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
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S71WS-J Based MCPs
25
P r e l i m i n a r y
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S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
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WKHꢀVWDUWLQJꢀDGGUHVVꢀIDOOVꢃꢀ7KHꢀJURXSVꢀDUHꢀVL]HGꢀDFFRUGLQJꢀWRꢀWKHꢀQXPEHUꢀRIꢀZRUGVꢀ
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Table 2. Burst Address Groups
0RGH
ꢇꢅZRUG
ꢈꢉꢅZRUG
ꢑꢎꢅZRUG
*URXSꢀ6L]H
ꢇꢀZRUGV
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ꢈꢉꢀZRUGV
ꢑꢎꢀZRUGV
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ꢍꢍꢅꢈ)Kꢄꢀꢎꢍꢅꢑ)Kꢄꢀꢊꢍꢅꢏ)Kꢄꢃꢃꢃ
$VꢀDQꢀH[DPSOHꢆꢀLIꢀWKHꢀVWDUWLQJꢀDGGUHVVꢀLQꢀWKHꢀꢇꢅZRUGꢀPRGHꢀLVꢀꢑꢌKꢄꢀWKHꢀDGGUHVVꢀ
UDQJHꢀWRꢀEHꢀUHDGꢀZRXOGꢀEHꢀꢑꢇꢅꢑ)KꢄꢀDQGꢀWKHꢀEXUVWꢀVHTXHQFHꢀZRXOGꢀEHꢀꢑꢌꢅꢑ$ꢅꢑ%ꢅ
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VHTXHQFHꢀRQꢀWKHꢀVWDUWLQJꢀDGGUHVVꢀZULWWHQꢀWRꢀWKHꢀGHYLFHꢄꢀDQGꢀWKHQꢀZUDSꢀEDFNꢀWRꢀ
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UHDGꢀPRGHVꢀWKHꢀDGGUHVVꢀSRLQWHUꢀGRHVꢀQRWꢀFURVVꢀWKHꢀERXQGDU\ꢀWKDWꢀRFFXUVꢀ
HYHU\ꢀꢄꢐꢊꢀRUꢀꢉꢋꢀZRUGVꢓꢀWKXVꢎꢀQRꢀZDLWꢀVWDWHVꢀDUHꢀLQVHUWHGꢀꢂH[FHSWꢀGXULQJꢀ
WKHꢀLQLWLDOꢀDFFHVVꢃꢅ
7KHꢀ5'<ꢀSLQꢀLQGLFDWHVꢀZKHQꢀGDWDꢀLVꢀYDOLGꢀRQꢀWKHꢀEXVꢃꢀ
Configuration Register
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QXPEHUꢀRIꢀZDLWꢀVWDWHVꢄꢀEXUVWꢀUHDGꢀPRGHꢄꢀDFWLYHꢀFORFNꢀHGJHꢄꢀ5'<ꢀFRQILJXUDWLRQꢄꢀ
DQGꢀV\QFKURQRXVꢀPRGHꢀDFWLYHꢃꢀ
Handshaking
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WRꢀVLPSO\ꢀPRQLWRUꢀWKHꢀ5'<ꢀVLJQDOꢀIURPꢀWKHꢀGHYLFHꢀWRꢀGHWHUPLQHꢀZKHQꢀWKHꢀLQLWLDOꢀ
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PDEOHꢀZDLWꢀVWDWHꢀFRQILJXUDWLRQꢀWRꢀVHWꢀWKHꢀQXPEHUꢀRIꢀZDLWꢀVWDWHVꢀIRUꢀRSWLPDOꢀEXUVWꢀ
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5'<ꢀDIWHUꢀ2(ꢓꢀJRHVꢀORZꢃꢀ
)RUꢀRSWLPDOꢀEXUVWꢀPRGHꢀSHUIRUPDQFHꢄꢀWKHꢀKRVWꢀV\VWHPꢀPXVWꢀVHWꢀWKHꢀDSSURSULDWHꢀ
QXPEHUꢀRIꢀZDLWꢀVWDWHVꢀLQꢀWKHꢀIODVKꢀGHYLFHꢀGHSHQGLQJꢀRQꢀFORFNꢀIUHTXHQF\ꢃꢀ6HHꢀ³6HWꢀ
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
27
P r e l i m i n a r y
Simultaneous Read/Write Operations with Zero Latency
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7LPLQJVꢄ´ꢀRQꢀSDJHꢀꢈꢈꢎꢀVKRZVꢀKRZꢀUHDGꢀDQGꢀZULWHꢀF\FOHVꢀPD\ꢀEHꢀLQLWLDWHGꢀIRUꢀVLꢅ
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Writing Commands/Command Sequences
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28
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
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Autoselect Mode
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LVꢀHUDVHGꢀRUꢀSURJUDPPHGꢀLQꢀDꢀV\VWHPꢀZLWKRXWꢀDFFHVVꢀWRꢀKLJKꢀYROWDJHꢀRQꢀWKHꢀ$ꢌꢀ
SLQꢃꢀ7KHꢀFRPPDQGꢀVHTXHQFHꢀLVꢀLOOXVWUDWHGꢀLQꢀ7DEOHꢀꢈꢇꢄꢀ³&RPPDQGꢀ'HILQLWLRQVꢄ´ꢀ
RQꢀSDJHꢀꢋꢉꢃꢀ1RWHꢃWKDWꢃLIꢃDꢃ%DQNꢃ$GGUHVVꢃꢎ%$ꢏꢃRQꢃDGGUHVVꢃELWVꢃ$ꢄꢄꢆꢃ$ꢄꢀꢆꢃDQGꢃ$ꢄꢌꢃ
IRUꢃWKHꢃ:6ꢀꢄꢐ-ꢃꢎ$ꢄꢀꢓ$ꢀꢍꢃIRUꢃWKHꢃ:6ꢌꢋꢈ-ꢏꢃLVꢃDVVHUWHGꢃGXULQJꢃWKHꢃWKLUGꢃZULWHꢃ
F\FOHꢃRIꢃWKHꢃDXWRVHOHFWꢃFRPPDQGꢆꢃWKHꢃKRVWꢃV\VWHPꢃFDQꢃUHDGꢃDXWRVHOHFWꢃGDWDꢃWKDWꢃ
EDQNꢃDQGꢃWKHQꢃLPPHGLDWHO\ꢃUHDGꢃDUUD\ꢃGDWDꢃIURPꢃWKHꢃRWKHUꢃEDQNꢆꢃZLWKRXWꢃH[LWLQJꢃ
WKHꢃDXWRVHOHFWꢃPRGHꢁ
7RꢀDFFHVVꢀWKHꢀDXWRVHOHFWꢀFRGHVꢀLQꢅV\VWHPꢄꢀWKHꢀKRVWꢀV\VWHPꢀFDQꢀLVVXHꢀWKHꢀDXWRVHꢅ
OHFWꢀFRPPDQGꢀYLDꢀWKHꢀFRPPDQGꢀUHJLVWHUꢄꢀDVꢀVKRZQꢀLQꢀ7DEOHꢀꢈꢇꢄꢀ³&RPPDQGꢀ
'HILQLWLRQVꢄ´ꢀRQꢀSDJHꢀꢋꢉꢃꢀ7KLVꢀPHWKRGꢀGRHVꢀQRWꢀUHTXLUHꢀ9,'ꢃꢀ$XWRVHOHFWꢀPRGHꢀ
PD\ꢀRQO\ꢀEHꢀHQWHUHGꢀDQGꢀXVHGꢀZKHQꢀLQꢀWKHꢀDV\QFKURQRXVꢀUHDGꢀPRGHꢃꢀ5HIHUꢀWRꢀ
WKHꢀ³$XWRVHOHFWꢀ&RPPDQGꢀ6HTXHQFH´ꢀVHFWLRQꢀRQꢀSDJHꢀꢉꢋꢀIRUꢀPRUHꢀLQIRUPDWLRQꢃ
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
29
P r e l i m i n a r y
Table 3. Autoselect Codes (High Voltage Method)
$PD
[
WRꢀ
$ꢄꢄꢀ
WRꢀ
$ꢈ
WR
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ꢒ
'4ꢄꢈ
WRꢀ'4ꢍ
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&(ꢒ 2(ꢒ
5(6(7ꢒ $ꢄꢐ $ꢄꢍ $ꢇ $ꢊ $ꢆ $ꢉ $ꢋ $ꢑ $ꢐ $ꢄ $ꢍ
0DQXIDFWXUHUꢀ,'ꢁꢀ
)$6/
9,'
9,'
9,'
/
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/
/
+
+
+
+
+
+
;
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;
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;
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/
/
/
/
/
;
/
/
/
/
/
/
/
/
/
+
/
ꢍꢍꢍꢈK
ꢎꢎꢋ(K
5HDGꢀ&\FOHꢀꢈ
5HDGꢀ&\FOHꢀꢎ
ꢎꢎꢈꢇKꢀꢁ:6ꢈꢎꢇ-ꢂ
ꢎꢎꢈ(Kꢀꢁ:6ꢍꢉꢊ-ꢂ
+
+
+
ꢎꢎꢍꢍKꢀꢁ:6ꢈꢎꢇ-ꢂ
ꢎꢎꢍꢈKꢀꢁ:6ꢍꢉꢊ-ꢂ
5HDGꢀ&\FOHꢀꢑ
+
/
+
/
+
+
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6HFWRUꢀ3URWHFWLRQꢀ
9HULILFDWLRQ
ꢍꢍꢍꢈKꢀꢁSURWHFWHGꢂꢄ
ꢍꢍꢍꢍKꢀꢁXQSURWHFWHGꢂ
6$
'4ꢈꢏꢀꢅꢀ'4ꢇꢀ ꢀꢍ
'4ꢋꢀꢅꢀ)DFWRU\ꢀ/RFNꢀ%LW
ꢈꢀ ꢀ/RFNHGꢄꢀꢍꢀ ꢀ1RWꢀ/RFNHG
'4ꢉꢀꢅ&XVWRPHUꢀ/RFNꢀ%LW
ꢈꢀ ꢀ/RFNHGꢄꢀꢍꢀ ꢀ1RWꢀ/RFNHG
'4ꢏꢀ ꢀ+DQGVKDNHꢀ%LW
ꢈꢀ ꢀ5HVHUYHGꢄꢀꢍꢀ ꢀ6WDQGDUGꢀ
+DQGVKDNH
9,'
,QGLFDWRUꢀ%LWV
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+
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'4ꢊꢀꢔꢀ'4ꢑꢀꢅꢀ%RRWꢀ&RGH
'4ꢎꢀꢅꢀ'4ꢍꢀ ꢀꢍꢍꢈ
+DUGZDUHꢀ6HFWRUꢀ
*URXSꢀ3URWHFWLRQ
ꢍꢍꢍꢈKꢀꢁSURWHFWHGꢂꢄ
ꢍꢍꢍꢍKꢀꢁXQSURWHFWHGꢂ
9,'
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6$
;
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/HJHQGꢀꢃ/ꢃ ꢃ/RJLFꢃ/RZꢃ ꢃ9 ꢆꢃ+ꢃ ꢃ/RJLFꢃ+LJKꢃ ꢃ9 ꢆꢃꢃ%$ꢃ ꢃ%DQNꢃ$GGUHVVꢆꢃ6$ꢃ ꢃ6HFWRUꢃ$GGUHVVꢆꢃ;ꢃ ꢃ'RQ¶WꢃFDUHꢁ
,/
,+
1RWHVꢀ
ꢀꢁ 7KHꢃDXWRVHOHFWꢃFRGHVꢃPD\ꢃDOVRꢃEHꢃDFFHVVHGꢃLQꢂV\VWHPꢃYLDꢃFRPPDQGꢃVHTXHQFHVꢁ
ꢄꢁ 33%ꢃ3URWHFWLRQꢃ6WDWXVꢃLVꢃVKRZQꢃRQꢃWKHꢃGDWDꢃEXV
Sector/Sector Block Protection and Unprotection
7KHꢀKDUGZDUHꢀVHFWRUꢀSURWHFWLRQꢀIHDWXUHꢀGLVDEOHVꢀERWKꢀSURJUDPPLQJꢀDQGꢀHUDVHꢀRSꢅ
HUDWLRQVꢀLQꢀDQ\ꢀVHFWRUꢃꢀ7KHꢀKDUGZDUHꢀVHFWRUꢀXQSURWHFWLRQꢀIHDWXUHꢀUHꢅHQDEOHVꢀERWKꢀ
SURJUDPꢀDQGꢀHUDVHꢀRSHUDWLRQVꢀLQꢀSUHYLRXVO\ꢀSURWHFWHGꢀVHFWRUVꢃꢀ6HFWRUꢀSURWHFWLRQꢒ
XQSURWHFWLRQꢀFDQꢀEHꢀLPSOHPHQWHGꢀYLDꢀWZRꢀPHWKRGVꢃ
ꢁ1RWHꢆꢀ)RUꢀWKHꢀIROORZLQJꢀGLVFXVVLRQꢄꢀWKHꢀWHUPꢀ³VHFWRU´ꢀDSSOLHVꢀWRꢀERWKꢀVHFWRUVꢀDQGꢀ
VHFWRUꢀEORFNVꢃꢀ$ꢀVHFWRUꢀEORFNꢀFRQVLVWVꢀRIꢀWZRꢀRUꢀPRUHꢀDGMDFHQWꢀVHFWRUVꢀWKDWꢀDUHꢀ
SURWHFWHGꢀRUꢀXQSURWHFWHGꢀDWꢀWKHꢀVDPHꢀWLPHꢀꢁVHHꢀ7DEOHꢀꢊꢄꢀ³6ꢎꢌ:6ꢈꢎꢇꢒꢍꢉꢊ-B0&3
%RRWꢀ6HFWRUꢒ6HFWRUꢀ%ORFNꢀ$GGUHVVHVꢀIRUꢀ3URWHFWLRQꢒ8QSURWHFWLRQꢄ´ꢀRQꢀSDJHꢀꢑꢍꢀDQGꢀ
7DEOHꢀꢏꢄꢀ³6ꢎꢌ:6ꢍꢉꢊ-ꢀ%RRWꢀ6HFWRUꢒ6HFWRUꢀ%ORFNꢀ$GGUHVVHVꢀIRUꢀ3URWHFWLRQꢒ8QSURꢅ
WHFWLRQꢄ´ꢀRQꢀSDJHꢀꢑꢎꢂꢃꢂ
Table 4. S29WS128/064J_MCP Boot Sector/Sector Block Addresses for Protection/Unprotection
6HFWRUꢏ
6HFWRU
6$ꢍ
$ꢐꢐ±$ꢄꢐ
6HFWRUꢀ%ORFNꢀ6L]H
ꢍꢍꢍꢍꢍꢍꢍꢍꢍꢍꢍ
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ꢍꢍꢍꢍꢍꢍꢍꢍꢍꢈꢍ
ꢍꢍꢍꢍꢍꢍꢍꢍꢍꢈꢈ
ꢍꢍꢍꢍꢍꢍꢍꢍꢈꢍꢍ
ꢍꢍꢍꢍꢍꢍꢍꢍꢈꢍꢈ
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6$ꢈ
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6$ꢎ
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6$ꢑ
ꢊꢀ.ZRUGV
6$ꢊ
ꢊꢀ.ZRUGV
6$ꢏ
ꢊꢀ.ZRUGV
30
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
6HFWRUꢏ
6HFWRU
6$ꢉ
$ꢐꢐ±$ꢄꢐ
6HFWRUꢀ%ORFNꢀ6L]H
ꢍꢍꢍꢍꢍꢍꢍꢍꢈꢈꢍ
ꢍꢍꢍꢍꢍꢍꢍꢍꢈꢈꢈ
ꢍꢍꢍꢍꢍꢍꢍꢈ;;;ꢄ
ꢍꢍꢍꢍꢍꢍꢈꢍ;;;ꢄ
ꢍꢍꢍꢍꢍꢍꢈꢈ;;;ꢄ
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ꢍꢍꢈꢍꢈꢈ;;;;;
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ꢍꢈꢈꢈꢈꢍ;;;;;
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ꢈꢍꢍꢍꢍꢈ;;;;;
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ꢊꢀ.ZRUGV
6$ꢋ
ꢊꢀ.ZRUGV
6$ꢇ
ꢑꢎꢀ.ZRUGV
6$ꢌ
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6$ꢈꢍ
ꢑꢎꢀ.ZRUGV
6$ꢈꢈ±6$ꢈꢊ
6$ꢈꢏ±6$ꢈꢇ
6$ꢈꢌ±6$ꢎꢎ
6$ꢎꢑꢅ6$ꢎꢉ
6$ꢎꢋꢅ6$ꢑꢍ
6$ꢑꢈꢅ6$ꢑꢊ
6$ꢑꢏꢅ6$ꢑꢇ
6$ꢑꢌꢅ6$ꢊꢎ
6$ꢊꢑꢅ6$ꢊꢉ
6$ꢊꢋꢅ6$ꢏꢍ
6$ꢏꢈ±6$ꢏꢊ
6$ꢏꢏ±6$ꢏꢇ
6$ꢏꢌ±6$ꢉꢎ
6$ꢉꢑ±6$ꢉꢉ
6$ꢉꢋ±6$ꢋꢍ
6$ꢋꢈ±6$ꢋꢊ
6$ꢋꢏ±6$ꢋꢇ
6$ꢋꢌ±6$ꢇꢎ
6$ꢇꢑ±6$ꢇꢉ
6$ꢇꢋ±6$ꢌꢍ
6$ꢌꢈ±6$ꢌꢊ
6$ꢌꢏ±6$ꢌꢇ
6$ꢌꢌ±6$ꢈꢍꢎ
6$ꢈꢍꢑ±6$ꢈꢍꢉ
6$ꢈꢍꢋ±6$ꢈꢈꢍ
6$ꢈꢈꢈ±6$ꢈꢈꢊ
6$ꢈꢈꢏ±6$ꢈꢈꢇ
6$ꢈꢈꢌ±6$ꢈꢎꢎ
6$ꢈꢎꢑ±6$ꢈꢎꢉ
6$ꢈꢎꢋ±6$ꢈꢑꢍ
6$ꢈꢑꢈꢅ6$ꢈꢑꢊ
6$ꢈꢑꢏꢅ6$ꢈꢑꢇ
6$ꢈꢑꢌꢅ6$ꢈꢊꢎ
6$ꢈꢊꢑꢅ6$ꢈꢊꢉ
6$ꢈꢊꢋꢅ6$ꢈꢏꢍ
6$ꢈꢏꢈ±6$ꢈꢏꢊ
6$ꢈꢏꢏ±6$ꢈꢏꢇ
6$ꢈꢏꢌ±6$ꢈꢉꢎ
6$ꢈꢉꢑ±6$ꢈꢉꢉ
6$ꢈꢉꢋ±6$ꢈꢋꢍ
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
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ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
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ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
31
P r e l i m i n a r y
6HFWRUꢏ
6HFWRU
6$ꢈꢋꢈ±6$ꢈꢋꢊ
6$ꢈꢋꢏ±6$ꢈꢋꢇ
6$ꢈꢋꢌ±6$ꢈꢇꢎ
6$ꢈꢇꢑ±6$ꢈꢇꢉ
6$ꢈꢇꢋ±6$ꢈꢌꢍ
6$ꢈꢌꢈ±6$ꢈꢌꢊ
6$ꢈꢌꢏ±6$ꢈꢌꢇ
6$ꢈꢌꢌ±6$ꢎꢍꢎ
6$ꢎꢍꢑ±6$ꢎꢍꢉ
6$ꢎꢍꢋ±6$ꢎꢈꢍ
6$ꢎꢈꢈ±6$ꢎꢈꢊ
6$ꢎꢈꢏ±6$ꢎꢈꢇ
6$ꢎꢈꢌ±6$ꢎꢎꢎ
6$ꢎꢎꢑ±6$ꢎꢎꢉ
6$ꢎꢎꢋ±6$ꢎꢑꢍ
6$ꢎꢑꢈ±6$ꢎꢑꢊ
6$ꢎꢑꢏ±6$ꢎꢑꢇ
6$ꢎꢑꢌ±6$ꢎꢊꢎ
6$ꢎꢊꢑ±6$ꢎꢊꢉ
6$ꢎꢊꢋ±6$ꢎꢏꢍ
6$ꢎꢏꢈ±6$ꢎꢏꢊ
6$ꢎꢏꢏ±6$ꢎꢏꢇ
6$ꢎꢏꢌ
$ꢐꢐ±$ꢄꢐ
6HFWRUꢀ%ORFNꢀ6L]H
ꢈꢍꢈꢍꢍꢈ;;;;;
ꢈꢍꢈꢍꢈꢍ;;;;;
ꢈꢍꢈꢍꢈꢈ;;;;;
ꢈꢍꢈꢈꢍꢍ;;;;;
ꢈꢍꢈꢈꢍꢈ;;;;;
ꢈꢍꢈꢈꢈꢍ;;;;;
ꢈꢍꢈꢈꢈꢈ;;;;;
ꢈꢈꢍꢍꢍꢍ;;;;;
ꢈꢈꢍꢍꢍꢈ;;;;;
ꢈꢈꢍꢍꢈꢍ;;;;;
ꢈꢈꢍꢍꢈꢈ;;;;;
ꢈꢈꢍꢈꢍꢍ;;;;;
ꢈꢈꢍꢈꢍꢈ;;;;;
ꢈꢈꢍꢈꢈꢍ;;;;;
ꢈꢈꢍꢈꢈꢈ;;;;;
ꢈꢈꢈꢍꢍꢍ;;;;;
ꢈꢈꢈꢍꢍꢈ;;;;;
ꢈꢈꢈꢍꢈꢍ;;;;;
ꢈꢈꢈꢍꢈꢈ;;;;;
ꢈꢈꢈꢈꢍꢍ;;;;;
ꢈꢈꢈꢈꢍꢈ;;;;;
ꢈꢈꢈꢈꢈꢍ;;;;;
ꢈꢈꢈꢈꢈꢈꢍꢍ;;;
ꢈꢈꢈꢈꢈꢈꢍꢈ;;;
ꢈꢈꢈꢈꢈꢈꢈꢍ;;;
ꢈꢈꢈꢈꢈꢈꢈꢈꢍꢍꢍ
ꢈꢈꢈꢈꢈꢈꢈꢈꢍꢍꢈ
ꢈꢈꢈꢈꢈꢈꢈꢈꢍꢈꢍ
ꢈꢈꢈꢈꢈꢈꢈꢈꢍꢈꢈ
ꢈꢈꢈꢈꢈꢈꢈꢈꢈꢍꢍ
ꢈꢈꢈꢈꢈꢈꢈꢈꢈꢍꢈ
ꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢍ
ꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈ
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
6$ꢎꢉꢍ
ꢑꢎꢀ.ZRUGV
6$ꢎꢉꢈ
ꢑꢎꢀ.ZRUGV
6$ꢎꢉꢎ
ꢊꢀ.ZRUGV
6$ꢎꢉꢑ
ꢊꢀ.ZRUGV
6$ꢎꢉꢊ
ꢊꢀ.ZRUGV
6$ꢎꢉꢏ
ꢊꢀ.ZRUGV
6$ꢎꢉꢉ
ꢊꢀ.ZRUGV
6$ꢎꢉꢋ
ꢊꢀ.ZRUGV
6$ꢎꢉꢇ
ꢊꢀ.ZRUGV
6$ꢎꢉꢌ
ꢊꢀ.ZRUGV
Table 5. S29WS064J Boot Sector/Sector Block Addresses for Protection/Unprotection
6HFWRUꢏ
6HFWRU
6$ꢍ
6$ꢈ
6$ꢎ
6$ꢑ
6$ꢊ
6$ꢏ
6$ꢉ
6$ꢋ
6$ꢇ
$ꢐꢄ±$ꢄꢐ
ꢍꢍꢍꢍꢍꢍꢍꢍꢍꢍ
ꢍꢍꢍꢍꢍꢍꢍꢍꢍꢈ
ꢍꢍꢍꢍꢍꢍꢍꢍꢈꢍ
ꢍꢍꢍꢍꢍꢍꢍꢍꢈꢈ
ꢍꢍꢍꢍꢍꢍꢍꢈꢍꢍ
ꢍꢍꢍꢍꢍꢍꢍꢈꢍꢈ
ꢍꢍꢍꢍꢍꢍꢍꢈꢈꢍ
ꢍꢍꢍꢍꢍꢍꢍꢈꢈꢈ
ꢍꢍꢍꢍꢍꢍꢈ;;;
6HFWRUꢀ%ORFNꢀ6L]H
ꢊꢀ.ZRUGV
ꢊꢀ.ZRUGV
ꢊꢀ.ZRUGV
ꢊꢀ.ZRUGV
ꢊꢀ.ZRUGV
ꢊꢀ.ZRUGV
ꢊꢀ.ZRUGV
ꢊꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
32
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
6HFWRUꢏ
6HFWRU
6$ꢌ
$ꢐꢄ±$ꢄꢐ
6HFWRUꢀ%ORFNꢀ6L]H
ꢍꢍꢍꢍꢍꢈꢍ;;;
ꢍꢍꢍꢍꢍꢈꢈ;;;
ꢍꢍꢍꢍꢈ;;;;;
ꢍꢍꢍꢈꢍ;;;;;
ꢍꢍꢍꢈꢈ;;;;;
ꢍꢍꢈꢍꢍ;;;;;
ꢍꢍꢈꢍꢈ;;;;;
ꢍꢍꢈꢈꢍ;;;;;
ꢍꢍꢈꢈꢈ;;;;;
ꢍꢈꢍꢍꢍ;;;;;
ꢍꢈꢍꢍꢈ;;;;;
ꢍꢈꢍꢈꢍ;;;;;
ꢍꢈꢍꢈꢈ;;;;;
ꢍꢈꢈꢍꢍ;;;;;
ꢍꢈꢈꢍꢈ;;;;;
ꢍꢈꢈꢈꢍ;;;;;
ꢍꢈꢈꢈꢈ;;;;;
ꢈꢍꢍꢍꢍ;;;;;
ꢈꢍꢍꢍꢈ;;;;;
ꢈꢍꢍꢈꢍ;;;;;
ꢈꢍꢍꢈꢈ;;;;;
ꢈꢍꢈꢍꢍ;;;;;
ꢈꢍꢈꢍꢈ;;;;;
ꢈꢍꢈꢈꢍ;;;;;
ꢈꢍꢈꢈꢈ;;;;;
ꢈꢈꢍꢍꢍ;;;;;
ꢈꢈꢍꢍꢈ;;;;;
ꢈꢈꢍꢈꢍ;;;;;
ꢈꢈꢍꢈꢈ;;;;;
ꢈꢈꢈꢍꢍ;;;;;
ꢈꢈꢈꢍꢈ;;;;;
ꢈꢈꢈꢈꢍ;;;;;
ꢈꢈꢈꢈꢈꢍꢍ;;;
ꢈꢈꢈꢈꢈꢍꢈ;;;
ꢈꢈꢈꢈꢈꢈꢍ;;;
ꢈꢈꢈꢈꢈꢈꢈꢍꢍꢍ
ꢈꢈꢈꢈꢈꢈꢈꢍꢍꢈ
ꢈꢈꢈꢈꢈꢈꢈꢍꢈꢍ
ꢈꢈꢈꢈꢈꢈꢈꢍꢈꢈ
ꢈꢈꢈꢈꢈꢈꢈꢈꢍꢍ
ꢈꢈꢈꢈꢈꢈꢈꢈꢍꢈ
ꢈꢈꢈꢈꢈꢈꢈꢈꢈꢍ
ꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈ
ꢑꢎꢀ.ZRUGV
6$ꢈꢍ
ꢑꢎꢀ.ZRUGV
6$ꢈꢈ±6$ꢈꢊ
6$ꢈꢏ±6$ꢈꢇ
6$ꢈꢌ±6$ꢎꢎ
6$ꢎꢑꢅ6$ꢎꢉ
6$ꢎꢋꢅ6$ꢑꢍ
6$ꢑꢈꢅ6$ꢑꢊ
6$ꢑꢏꢅ6$ꢑꢇ
6$ꢑꢌꢅ6$ꢊꢎ
6$ꢊꢑꢅ6$ꢊꢉ
6$ꢊꢋꢅ6$ꢏꢍ
6$ꢏꢈ±6$ꢏꢊ
6$ꢏꢏ±6$ꢏꢇ
6$ꢏꢌ±6$ꢉꢎ
6$ꢉꢑ±6$ꢉꢉ
6$ꢉꢋ±6$ꢋꢍ
6$ꢋꢈ±6$ꢋꢊ
6$ꢋꢏ±6$ꢋꢇ
6$ꢋꢌ±6$ꢇꢎ
6$ꢇꢑ±6$ꢇꢉ
6$ꢇꢋ±6$ꢌꢍ
6$ꢌꢈ±6$ꢌꢊ
6$ꢌꢏ±6$ꢌꢇ
6$ꢌꢌ±6$ꢈꢍꢎ
6$ꢈꢍꢑ±6$ꢈꢍꢉ
6$ꢈꢍꢋ±6$ꢈꢈꢍ
6$ꢈꢈꢈ±6$ꢈꢈꢊ
6$ꢈꢈꢏ±6$ꢈꢈꢇ
6$ꢈꢈꢌ±6$ꢈꢎꢎ
6$ꢈꢎꢑ±6$ꢈꢎꢉ
6$ꢈꢎꢋ±6$ꢈꢑꢍ
6$ꢈꢑꢈ
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢈꢎꢇꢀꢁꢊ[ꢑꢎꢂꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
6$ꢈꢑꢎ
ꢑꢎꢀ.ZRUGV
6$ꢈꢑꢑ
ꢑꢎꢀ.ZRUGV
6$ꢈꢑꢊ
ꢊꢀ.ZRUGV
6$ꢈꢑꢏ
ꢊꢀ.ZRUGV
6$ꢈꢑꢉ
ꢊꢀ.ZRUGV
6$ꢈꢑꢋ
ꢊꢀ.ZRUGV
6$ꢈꢑꢇ
ꢊꢀ.ZRUGV
6$ꢈꢑꢌ
ꢊꢀ.ZRUGV
6$ꢈꢊꢍ
ꢊꢀ.ZRUGV
6$ꢈꢊꢈ
ꢊꢀ.ZRUGV
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
33
P r e l i m i n a r y
6HFWRUꢀ3URWHFWLRQ
7KHꢀGHYLFHꢀIHDWXUHVꢀVHYHUDOꢀOHYHOVꢀRIꢀVHFWRUꢀSURWHFWLRQꢄꢀZKLFKꢀFDQꢀGLVDEOHꢀERWKꢀWKHꢀ
SURJUDPꢀDQGꢀHUDVHꢀRSHUDWLRQVꢀLQꢀFHUWDLQꢀVHFWRUVꢀRUꢀVHFWRUꢀJURXSVꢆ
3HUVLVWHQWꢁ6HFWRUꢁ3URWHFWLRQ
$ꢀFRPPDQGꢀVHFWRUꢀSURWHFWLRQꢀPHWKRGꢀWKDWꢀUHSODFHVꢀWKHꢀROGꢀꢈꢎꢀ9ꢀFRQWUROOHGꢀSURꢅ
WHFWLRQꢀPHWKRGꢃ
3DVVZRUGꢁ6HFWRUꢁ3URWHFWLRQ
$ꢀKLJKO\ꢀVRSKLVWLFDWHGꢀSURWHFWLRQꢀPHWKRGꢀWKDWꢀUHTXLUHVꢀDꢀSDVVZRUGꢀEHIRUHꢀ
FKDQJHVꢀWRꢀFHUWDLQꢀVHFWRUVꢀRUꢀVHFWRUꢀJURXSVꢀDUHꢀSHUPLWWHG
:3ꢂꢁ+DUGZDUHꢁ3URWHFWLRQ
$ꢀZULWHꢀSURWHFWꢀSLQꢀWKDWꢀFDQꢀSUHYHQWꢀSURJUDPꢀRUꢀHUDVHꢀRSHUDWLRQVꢀLQꢀWKHꢀRXWHUꢅ
PRVWꢀVHFWRUVꢃ
$OOꢀSDUWVꢀGHIDXOWꢀWRꢀRSHUDWHꢀLQꢀWKHꢀ3HUVLVWHQWꢀ6HFWRUꢀ3URWHFWLRQꢀPRGHꢃꢀ7KHꢀFXVꢅ
WRPHUꢀPXVWꢀWKHQꢀFKRRVHꢀLIꢀWKHꢀ3HUVLVWHQWꢀRUꢀ3DVVZRUGꢀ3URWHFWLRQꢀPHWKRGꢀLVꢀPRVWꢀ
GHVLUDEOHꢃꢀ7KHUHꢀDUHꢀWZRꢀRQHꢅWLPHꢀSURJUDPPDEOHꢀQRQꢅYRODWLOHꢀELWVꢀWKDWꢀGHILQHꢀ
ZKLFKꢀVHFWRUꢀSURWHFWLRQꢀPHWKRGꢀZLOOꢀEHꢀXVHGꢃꢀ,IꢀWKHꢀFXVWRPHUꢀGHFLGHVꢀWRꢀFRQWLQXHꢀ
XVLQJꢀWKHꢀ3HUVLVWHQWꢀ6HFWRUꢀ3URWHFWLRQꢀPHWKRGꢄꢀWKH\ꢀPXVWꢀVHWꢀWKHꢀ3HUVLVWHQWꢀ
6HFWRUꢀ3URWHFWLRQꢀ0RGHꢀ/RFNLQJꢀ%LWꢃꢀ7KLVꢀZLOOꢀSHUPDQHQWO\ꢀVHWꢀWKHꢀSDUWꢀWRꢀRSꢅ
HUDWHꢀRQO\ꢀXVLQJꢀ3HUVLVWHQWꢀ6HFWRUꢀ3URWHFWLRQꢃꢀ,IꢀWKHꢀFXVWRPHUꢀGHFLGHVꢀWRꢀXVHꢀWKHꢀ
SDVVZRUGꢀPHWKRGꢄꢀWKH\ꢀPXVWꢀVHWꢀWKHꢀ3DVVZRUGꢀ0RGHꢀ/RFNLQJꢀ%LWꢃꢀ7KLVꢀZLOOꢀ
SHUPDQHQWO\ꢀVHWꢀWKHꢀSDUWꢀWRꢀRSHUDWHꢀRQO\ꢀXVLQJꢀSDVVZRUGꢀVHFWRUꢀSURWHFWLRQꢃ
,WꢀLVꢀLPSRUWDQWꢀWRꢀUHPHPEHUꢀWKDWꢀVHWWLQJꢀHLWKHUꢀWKHꢀ3HUVLVWHQWꢀ6HFWRUꢀ3URWHFꢌ
WLRQꢀ0RGHꢀ/RFNLQJꢀ%LWꢀRUꢀWKHꢀ3DVVZRUGꢀ0RGHꢀ/RFNLQJꢀ%LWꢀSHUPDQHQWO\ꢀ
VHOHFWVꢀWKHꢀSURWHFWLRQꢀPRGHꢃꢀ,WꢀLVꢀQRWꢀSRVVLEOHꢀWRꢀVZLWFKꢀEHWZHHQꢀWKHꢀWZRꢀPHWKꢅ
RGVꢀRQFHꢀDꢀORFNLQJꢀELWꢀKDVꢀEHHQꢀVHWꢃꢀ,WꢀLVꢀLPSRUWDQWꢀWKDWꢀRQHꢀPRGHꢀLVꢀ
H[SOLFLWO\ꢀVHOHFWHGꢀZKHQꢀWKHꢀGHYLFHꢀLVꢀILUVWꢀSURJUDPPHGꢎꢀUDWKHUꢀWKDQꢀUHꢌ
O\LQJꢀRQꢀWKHꢀGHIDXOWꢀPRGHꢀDORQHꢅꢀ7KLVꢀLVꢀVRꢀWKDWꢀLWꢀLVꢀQRWꢀSRVVLEOHꢀIRUꢀDꢀV\VWHPꢀ
SURJUDPꢀRUꢀYLUXVꢀWRꢀODWHUꢀVHWꢀWKHꢀ3DVVZRUGꢀ0RGHꢀ/RFNLQJꢀ%LWꢄꢀZKLFKꢀZRXOGꢀFDXVHꢀ
DQꢀXQH[SHFWHGꢀVKLIWꢀIURPꢀWKHꢀGHIDXOWꢀ3HUVLVWHQWꢀ6HFWRUꢀ3URWHFWLRQꢀ0RGHꢀLQWRꢀWKHꢀ
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JUDPPLQJꢀVHUYLFHVꢀHQDEOHꢀSURJUDPPLQJꢀDQGꢀSURWHFWLQJꢀVHFWRUVꢀDWꢀWKHꢀIDFWRU\ꢀ
SULRUꢀWRꢀVKLSSLQJꢀWKHꢀGHYLFHꢃꢀ&RQWDFWꢀ\RXUꢀORFDOꢀVDOHVꢀRIILFHꢀIRUꢀ'HWDLOVꢃ
,WꢀLVꢀSRVVLEOHꢀWRꢀGHWHUPLQHꢀZKHWKHUꢀDꢀVHFWRUꢀLVꢀSURWHFWHGꢀRUꢀXQSURWHFWHGꢃꢀ6HHꢀ
³$XWRVHOHFWꢀ&RPPDQGꢀ6HTXHQFH´ꢀVHFWLRQꢀRQꢀSDJHꢀꢉꢋꢀIRUꢀGHWDLOVꢃ
Persistent Sector Protection
7KHꢀ3HUVLVWHQWꢀ6HFWRUꢀ3URWHFWLRQꢀPHWKRGꢀUHSODFHVꢀWKHꢀROGꢀꢈꢎꢀ9ꢀFRQWUROOHGꢀSURWHFꢅ
WLRQꢀPHWKRGꢀZKLOHꢀDWꢀWKHꢀVDPHꢀWLPHꢀHQKDQFLQJꢀIOH[LELOLW\ꢀE\ꢀSURYLGLQJꢀWKUHHꢀ
GLIIHUHQWꢀVHFWRUꢀSURWHFWLRQꢀVWDWHVꢆ
3HUVLVWHQWO\ꢀ/RFNHG²$ꢀVHFWRUꢀLVꢀSURWHFWHGꢀDQGꢀFDQQRWꢀEHꢀFKDQJHGꢃ
'\QDPLFDOO\ꢀ/RFNHG²7KHꢀVHFWRUꢀLVꢀSURWHFWHGꢀDQGꢀFDQꢀEHꢀFKDQJHGꢀE\ꢀDꢀVLPꢅ
SOHꢀFRPPDQG
8QORFNHG²7KHꢀVHFWRUꢀLVꢀXQSURWHFWHGꢀDQGꢀFDQꢀEHꢀFKDQJHGꢀE\ꢀDꢀVLPSOHꢀFRPꢅ
PDQG
,QꢀRUGHUꢀWRꢀDFKLHYHꢀWKHVHꢀVWDWHVꢄꢀWKUHHꢀW\SHVꢀRIꢀ³ELWV´ꢀDUHꢀJRLQJꢀWRꢀEHꢀXVHGꢆ
34
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
3HUVLVWHQWꢀ3URWHFWLRQꢀ%LWꢀꢂ33%ꢃ
$ꢀVLQJOHꢀ3HUVLVWHQWꢀꢁQRQꢅYRODWLOHꢂꢀ3URWHFWLRQꢀ%LWꢀLVꢀDVVLJQHGꢀWRꢀDꢀPD[LPXPꢀRIꢀIRXUꢀ
VHFWRUVꢀꢁ³6ꢎꢌ:6ꢈꢎꢇꢒꢍꢉꢊ-B0&3ꢀ%RRWꢀ6HFWRUꢒ6HFWRUꢀ%ORFNꢀ$GGUHVVHVꢀIRUꢀ3URWHFꢅ
WLRQꢒ8QSURWHFWLRQ´ꢀVHFWLRQꢀRQꢀSDJHꢀꢑꢍꢄꢀ³6ꢎꢌ:6ꢍꢉꢊ-ꢀ%RRWꢀ6HFWRUꢒ6HFWRUꢀ%ORFNꢀ
$GGUHVVHVꢀIRUꢀ3URWHFWLRQꢒ8QSURWHFWLRQ´ꢀVHFWLRQꢀRQꢀSDJHꢀꢑꢎꢂꢃꢀ$OOꢀꢊꢀ.E\WHꢀERRWꢅ
EORFNꢀVHFWRUVꢀKDYHꢀLQGLYLGXDOꢀVHFWRUꢀ3HUVLVWHQWꢀ3URWHFWLRQꢀ%LWVꢀꢁ33%VꢂꢀIRUꢀJUHDWHUꢀ
IOH[LELOLW\ꢃꢀ(DFKꢀ33%ꢀLVꢀLQGLYLGXDOO\ꢀPRGLILDEOHꢀWKURXJKꢀWKHꢀ33%ꢀ3URJUDPꢀ
&RPPDQGꢃ
1RWHꢆꢀ,IꢀDꢀ33%ꢀUHTXLUHVꢀHUDVXUHꢄꢀDOOꢀRIꢀWKHꢀVHFWRUꢀ33%VꢀPXVWꢀILUVWꢀEHꢀSUHSURꢅ
JUDPPHGꢀSULRUꢀWRꢀ33%ꢀHUDVLQJꢃꢀ$OOꢀ33%VꢀHUDVHꢀLQꢀSDUDOOHOꢄꢀXQOLNHꢀSURJUDPPLQJꢀ
ZKHUHꢀLQGLYLGXDOꢀ33%VꢀDUHꢀSURJUDPPDEOHꢃꢀ,WꢀLVꢀWKHꢀUHVSRQVLELOLW\ꢀRIꢀWKHꢀXVHUꢀWRꢀ
SHUIRUPꢀWKHꢀSUHSURJUDPPLQJꢀRSHUDWLRQꢃꢀ2WKHUZLVHꢄꢀDQꢀDOUHDG\ꢀHUDVHGꢀVHFWRUꢀ
33%VꢀKDVꢀWKHꢀSRWHQWLDOꢀRIꢀEHLQJꢀRYHUꢅHUDVHGꢃꢀ7KHUHꢀLVꢀQRꢀKDUGZDUHꢀPHFKDQLVPꢀWRꢀ
SUHYHQWꢀVHFWRUꢀ33%VꢀRYHUꢅHUDVXUHꢃ
3HUVLVWHQWꢀ3URWHFWLRQꢀ%LWꢀ/RFNꢀꢂ33%ꢀ/RFNꢃ
$ꢀJOREDOꢀYRODWLOHꢀELWꢃꢀ:KHQꢀVHWꢀWRꢀ³ꢈ´ꢄꢀWKHꢀ33%VꢀFDQQRWꢀEHꢀFKDQJHGꢃꢀ:KHQꢀFOHDUHGꢀ
ꢁ³ꢍ´ꢂꢄꢀWKHꢀ33%VꢀDUHꢀFKDQJHDEOHꢃꢀ7KHUHꢀLVꢀRQO\ꢀRQHꢀ33%ꢀ/RFNꢀELWꢀSHUꢀGHYLFHꢃꢀ7KHꢀ
33%ꢀ/RFNꢀLVꢀFOHDUHGꢀDIWHUꢀSRZHUꢅXSꢀRUꢀKDUGZDUHꢀUHVHWꢃꢀ7KHUHꢀLVꢀQRꢀFRPPDQGꢀVHꢅ
TXHQFHꢀWRꢀXQORFNꢀWKHꢀ33%ꢀ/RFNꢃ
'\QDPLFꢀ3URWHFWLRQꢀ%LWꢀꢂ'<%ꢃ
$ꢀYRODWLOHꢀSURWHFWLRQꢀELWꢀLVꢀDVVLJQHGꢀIRUꢀHDFKꢀVHFWRUꢃꢀ$IWHUꢀSRZHUꢅXSꢀRUꢀKDUGZDUHꢀ
UHVHWꢄꢀWKHꢀFRQWHQWVꢀRIꢀDOOꢀ'<%VꢀLVꢀ³ꢍ´ꢃꢀ(DFKꢀ'<%ꢀLVꢀLQGLYLGXDOO\ꢀPRGLILDEOHꢀWKURXJKꢀ
WKHꢀ'3%ꢀ:ULWHꢀ&RPPDQGꢃ
:KHQꢀWKHꢀSDUWVꢀDUHꢀILUVWꢀVKLSSHGꢄꢀWKHꢀ33%VꢀDUHꢀFOHDUHGꢀꢁ³ꢍ´ꢂꢃꢀ7KHꢀ'3%VꢀDQGꢀ33%ꢀ
/RFNꢀDUHꢀGHIDXOWHGꢀWRꢀSRZHUꢀXSꢀLQꢀWKHꢀFOHDUHGꢀVWDWHꢀ±ꢀPHDQLQJꢀWKHꢀ33%VꢀDUHꢀ
FKDQJHDEOHꢃ
:KHQꢀWKHꢀGHYLFHꢀLVꢀILUVWꢀSRZHUHGꢀRQꢄꢀWKHꢀ'<%VꢀSRZHUꢀXSꢀLQꢀWKHꢀFOHDUHGꢀVWDWHꢀ
ꢁVHFWRUVꢀQRWꢀSURWHFWHGꢂꢃꢀ7KHꢀ3URWHFWLRQꢀ6WDWHꢀIRUꢀHDFKꢀVHFWRUꢀLVꢀGHWHUPLQHGꢀE\ꢀ
WKHꢀORJLFDOꢀ25ꢀRIꢀWKHꢀ33%ꢀDQGꢀWKHꢀ'3%ꢀUHODWHGꢀWRꢀWKDWꢀVHFWRUꢃꢀ)RUꢀWKHꢀVHFWRUVꢀWKDWꢀ
KDYHꢀWKHꢀ33%VꢀFOHDUHGꢄꢀWKHꢀ'3%VꢀFRQWUROꢀZKHWKHUꢀRUꢀQRWꢀWKHꢀVHFWRUꢀLVꢀSURWHFWHGꢀ
RUꢀXQSURWHFWHGꢃꢀ%\ꢀLVVXLQJꢀWKHꢀ'3%ꢀ:ULWHꢀFRPPDQGꢀVHTXHQFHVꢄꢀWKHꢀ'3%VꢀZLOOꢀEHꢀ
VHWꢀRUꢀFOHDUHGꢄꢀWKXVꢀSODFLQJꢀHDFKꢀVHFWRUꢀLQꢀWKHꢀSURWHFWHGꢀRUꢀXQSURWHFWHGꢀVWDWHꢃꢀ
7KHVHꢀDUHꢀWKHꢀVRꢅFDOOHGꢀ'\QDPLFꢀ/RFNHGꢀRUꢀ8QORFNHGꢀVWDWHVꢃꢀ7KH\ꢀDUHꢀFDOOHGꢀ
G\QDPLFꢀVWDWHVꢀEHFDXVHꢀLWꢀLVꢀYHU\ꢀHDV\ꢀWRꢀVZLWFKꢀEDFNꢀDQGꢀIRUWKꢀEHWZHHQꢀWKHꢀ
SURWHFWHGꢀDQGꢀXQSURWHFWHGꢀFRQGLWLRQVꢃꢀ7KLVꢀDOORZVꢀVRIWZDUHꢀWRꢀHDVLO\ꢀSURWHFWꢀVHFꢅ
WRUVꢀDJDLQVWꢀLQDGYHUWHQWꢀFKDQJHVꢀ\HWꢀGRHVꢀQRWꢀSUHYHQWꢀWKHꢀHDV\ꢀUHPRYDOꢀRIꢀ
SURWHFWLRQꢀZKHQꢀFKDQJHVꢀDUHꢀQHHGHGꢃꢀ7KHꢀ'3%VꢀPD\EHꢀVHWꢀRUꢀFOHDUHGꢀDVꢀRIWHQꢀ
DVꢀQHHGHGꢃ
7KHꢀ33%VꢀDOORZꢀIRUꢀDꢀPRUHꢀVWDWLFꢄꢀDQGꢀGLIILFXOWꢀWRꢀFKDQJHꢄꢀOHYHOꢀRIꢀSURWHFWLRQꢃꢀ7KHꢀ
33%VꢀUHWDLQꢀWKHLUꢀVWDWHꢀDFURVVꢀSRZHUꢀF\FOHVꢀEHFDXVHꢀWKH\ꢀDUHꢀ1RQꢅ9RODWLOHꢃꢀ,QGLꢅ
YLGXDOꢀ33%VꢀDUHꢀVHWꢀZLWKꢀDꢀFRPPDQGꢀEXWꢀPXVWꢀDOOꢀEHꢀFOHDUHGꢀDVꢀDꢀJURXSꢀWKURXJKꢀ
DꢀFRPSOH[ꢀVHTXHQFHꢀRIꢀSURJUDPꢀDQGꢀHUDVLQJꢀFRPPDQGVꢃꢀ7KHꢀ33%VꢀDUHꢀDOVRꢀOLPꢅ
LWHGꢀWRꢀꢈꢍꢍꢀHUDVHꢀF\FOHVꢃꢀ
7KHꢀ3%%ꢀ/RFNꢀELWꢀDGGVꢀDQꢀDGGLWLRQDOꢀOHYHOꢀRIꢀSURWHFWLRQꢃꢀ2QFHꢀDOOꢀ33%VꢀDUHꢀSURꢅ
JUDPPHGꢀWRꢀWKHꢀGHVLUHGꢀVHWWLQJVꢄꢀWKHꢀ33%ꢀ/RFNꢀPD\ꢀEHꢀVHWꢀWRꢀ³ꢈ´ꢃꢀ6HWWLQJꢀWKHꢀ
33%ꢀ/RFNꢀGLVDEOHVꢀDOOꢀSURJUDPꢀDQGꢀHUDVHꢀFRPPDQGVꢀWRꢀWKHꢀ1RQꢅ9RODWLOHꢀ33%Vꢃꢀ,Qꢀ
HIIHFWꢄꢀWKHꢀ33%ꢀ/RFNꢀ%LWꢀORFNVꢀWKHꢀ33%VꢀLQWRꢀWKHLUꢀFXUUHQWꢀVWDWHꢃꢀ7KHꢀRQO\ꢀZD\ꢀWRꢀ
FOHDUꢀWKHꢀ33%ꢀ/RFNꢀLVꢀWRꢀJRꢀWKURXJKꢀDꢀSRZHUꢀF\FOHꢃꢀ6\VWHPꢀERRWꢀFRGHꢀFDQꢀGHWHUꢅ
PLQHꢀLIꢀDQ\ꢀFKDQJHVꢀWRꢀWKHꢀ33%ꢀDUHꢀQHHGHGꢀHꢃJꢃꢀWRꢀDOORZꢀQHZꢀV\VWHPꢀFRGHꢀWRꢀEHꢀ
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
35
P r e l i m i n a r y
GRZQORDGHGꢃꢀ,IꢀQRꢀFKDQJHVꢀDUHꢀQHHGHGꢀWKHQꢀWKHꢀERRWꢀFRGHꢀFDQꢀVHWꢀWKHꢀ33%ꢀ/RFNꢀ
WRꢀGLVDEOHꢀDQ\ꢀIXUWKHUꢀFKDQJHVꢀWRꢀWKHꢀ33%VꢀGXULQJꢀV\VWHPꢀRSHUDWLRQꢃ
7KHꢀ:3ꢓꢀZULWHꢀSURWHFWꢀSLQꢀDGGVꢀDꢀILQDOꢀOHYHOꢀRIꢀKDUGZDUHꢀSURWHFWLRQꢀWRꢀWKHꢀIRXUꢀ
RXWHUPRVWꢀꢊꢀ.E\WHVꢀVHFWRUVꢀꢁ6$ꢍꢀꢅꢀ6$ꢑꢀIRUꢀDꢀERWWRPꢀERRWꢄꢀ:6ꢈꢎꢇ-ꢆꢀ6$ꢎꢉꢉꢀꢅꢀ
6$ꢎꢉꢌꢄꢀ:6ꢍꢉꢊ-ꢆꢀ6$ꢈꢑꢇꢀꢅꢀ6$ꢈꢊꢈꢄꢀRUꢀ6$ꢍꢀꢅꢀ6$ꢑꢀꢔꢀ:6ꢈꢎꢇ-ꢆꢀ6$ꢎꢉꢉꢀꢅꢀ6$ꢎꢉꢌꢄꢀ
:6ꢍꢉꢊ-ꢆꢀ6$ꢈꢑꢇꢀꢅꢀ6$ꢈꢊꢈꢀIRUꢀDꢀGXDOꢀERRWꢂꢃꢀ:KHQꢀWKLVꢀSLQꢀLVꢀORZꢀLWꢀLVꢀQRWꢀSRVVLEOHꢀ
WRꢀFKDQJHꢀWKHꢀFRQWHQWVꢀRIꢀWKHVHꢀIRXUꢀVHFWRUVꢃꢀ7KHVHꢀVHFWRUVꢀJHQHUDOO\ꢀKROGꢀV\Vꢅ
WHPꢀERRWꢀFRGHꢃꢀ6RꢄꢀWKHꢀ:3ꢓꢀSLQꢀFDQꢀSUHYHQWꢀDQ\ꢀFKDQJHVꢀWRꢀWKHꢀERRWꢀFRGHꢀWKDWꢀ
FRXOGꢀRYHUULGHꢀWKHꢀFKRLFHVꢀPDGHꢀZKLOHꢀVHWWLQJꢀXSꢀVHFWRUꢀSURWHFWLRQꢀGXULQJꢀV\Vꢅ
WHPꢀLQLWLDOL]DWLRQꢃꢀ
,WꢀLVꢀSRVVLEOHꢀWRꢀKDYHꢀVHFWRUVꢀWKDWꢀKDYHꢀEHHQꢀSHUVLVWHQWO\ꢀORFNHGꢄꢀDQGꢀVHFWRUVꢀ
WKDWꢀDUHꢀOHIWꢀLQꢀWKHꢀG\QDPLFꢀVWDWHꢃꢀ7KHꢀVHFWRUVꢀLQꢀWKHꢀG\QDPLFꢀVWDWHꢀDUHꢀDOOꢀXQꢅ
SURWHFWHGꢃꢀ,IꢀWKHUHꢀLVꢀDꢀQHHGꢀWRꢀSURWHFWꢀVRPHꢀRIꢀWKHPꢄꢀDꢀVLPSOHꢀ'3%ꢀ:ULWHꢀ
FRPPDQGꢀVHTXHQFHꢀLVꢀDOOꢀWKDWꢀLVꢀQHFHVVDU\ꢃꢀ7KHꢀ'3%ꢀZULWHꢀFRPPDQGꢀIRUꢀWKHꢀG\ꢅ
QDPLFꢀVHFWRUVꢀVZLWFKꢀWKHꢀ'3%VꢀWRꢀVLJQLI\ꢀSURWHFWHGꢀDQGꢀXQSURWHFWHGꢄꢀ
UHVSHFWLYHO\ꢃꢀ,IꢀWKHUHꢀLVꢀDꢀQHHGꢀWRꢀFKDQJHꢀWKHꢀVWDWXVꢀRIꢀWKHꢀSHUVLVWHQWO\ꢀORFNHGꢀ
VHFWRUVꢄꢀDꢀIHZꢀPRUHꢀVWHSVꢀDUHꢀUHTXLUHGꢃꢀ)LUVWꢄꢀWKHꢀ33%ꢀ/RFNꢀELWꢀPXVWꢀEHꢀGLVDEOHGꢀ
E\ꢀHLWKHUꢀSXWWLQJꢀWKHꢀGHYLFHꢀWKURXJKꢀDꢀSRZHUꢅF\FOHꢄꢀRUꢀKDUGZDUHꢀUHVHWꢃꢀ7KHꢀ33%Vꢀ
FDQꢀWKHQꢀEHꢀFKDQJHGꢀWRꢀUHIOHFWꢀWKHꢀGHVLUHGꢀVHWWLQJVꢃꢀ6HWWLQJꢀWKHꢀ33%ꢀORFNꢀELWꢀRQFHꢀ
DJDLQꢀZLOOꢀORFNꢀWKHꢀ33%VꢄꢀDQGꢀWKHꢀGHYLFHꢀRSHUDWHVꢀQRUPDOO\ꢀDJDLQꢃ
1RWHꢆꢀWRꢀDFKLHYHꢀWKHꢀEHVWꢀSURWHFWLRQꢄꢀLW¶VꢀUHFRPPHQGHGꢀWRꢀH[HFXWHꢀWKHꢀ33%ꢀORFNꢀ
ELWꢀVHWꢀFRPPDQGꢀHDUO\ꢀLQꢀWKHꢀERRWꢀFRGHꢄꢀDQGꢀSURWHFWꢀWKHꢀERRWꢀFRGHꢀE\ꢀKROGLQJꢀ
:3ꢓꢀ ꢀ9,/ꢃ
Table 6. Sector Protection Schemes
'3%
33%
33%ꢀ/RFN
6HFWRUꢀ6WDWH
ꢍ
ꢈ
ꢍ
ꢈ
ꢍ
ꢍ
ꢈ
ꢈ
ꢍ
ꢍ
ꢍ
ꢍ
8QSURWHFWHG²33%ꢀDQGꢀ'3%ꢀDUHꢀFKDQJHDEOH
3URWHFWHG²33%ꢀDQGꢀ'3%ꢀDUHꢀFKDQJHDEOH
3URWHFWHG²33%ꢀDQGꢀ'3%ꢀDUHꢀFKDQJHDEOH
3URWHFWHG²33%ꢀDQGꢀ'3%ꢀDUHꢀFKDQJHDEOH
8QSURWHFWHG²33%ꢀQRWꢀFKDQJHDEOHꢄꢀ'3%ꢀLVꢀ
FKDQJHDEOH
ꢍ
ꢈ
ꢍ
ꢈ
ꢍ
ꢍ
ꢈ
ꢈ
ꢈ
ꢈ
ꢈ
ꢈ
3URWHFWHG²33%ꢀQRWꢀFKDQJHDEOHꢄꢀ'3%ꢀLVꢀ
FKDQJHDEOH
3URWHFWHG²33%ꢀQRWꢀFKDQJHDEOHꢄꢀ'3%ꢀLVꢀ
FKDQJHDEOH
3URWHFWHG²33%ꢀQRWꢀFKDQJHDEOHꢄꢀ'3%ꢀLVꢀ
FKDQJHDEOH
7DEOHꢀꢉꢀFRQWDLQVꢀDOOꢀSRVVLEOHꢀFRPELQDWLRQVꢀRIꢀWKHꢀ'3%ꢄꢀ33%ꢄꢀDQGꢀ33%ꢀORFNꢀUHODWLQJꢀ
WRꢀWKHꢀVWDWXVꢀRIꢀWKHꢀVHFWRUꢃ
,QꢀVXPPDU\ꢄꢀLIꢀWKHꢀ33%ꢀLVꢀVHWꢄꢀDQGꢀWKHꢀ33%ꢀORFNꢀLVꢀVHWꢄꢀWKHꢀVHFWRUꢀLVꢀSURWHFWHGꢀDQGꢀ
WKHꢀSURWHFWLRQꢀFDQꢀQRWꢀEHꢀUHPRYHGꢀXQWLOꢀWKHꢀQH[WꢀSRZHUꢀF\FOHꢀFOHDUVꢀWKHꢀ33%ꢀ
ORFNꢃꢀ,IꢀWKHꢀ33%ꢀLVꢀFOHDUHGꢄꢀWKHꢀVHFWRUꢀFDQꢀEHꢀG\QDPLFDOO\ꢀORFNHGꢀRUꢀXQORFNHGꢃꢀ7KHꢀ
'3%ꢀWKHQꢀFRQWUROVꢀZKHWKHUꢀRUꢀQRWꢀWKHꢀVHFWRUꢀLVꢀSURWHFWHGꢀRUꢀXQSURWHFWHGꢃ
36
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
,IꢀWKHꢀXVHUꢀDWWHPSWVꢀWRꢀSURJUDPꢀRUꢀHUDVHꢀDꢀSURWHFWHGꢀVHFWRUꢄꢀWKHꢀGHYLFHꢀLJQRUHVꢀ
WKHꢀFRPPDQGꢀDQGꢀUHWXUQVꢀWRꢀUHDGꢀPRGHꢃꢀ$ꢀSURJUDPꢀFRPPDQGꢀWRꢀDꢀSURWHFWHGꢀ
VHFWRUꢀHQDEOHVꢀVWDWXVꢀSROOLQJꢀIRUꢀDSSUR[LPDWHO\ꢀꢈꢀVꢀEHIRUHꢀWKHꢀGHYLFHꢀUHWXUQVꢀWRꢀ
UHDGꢀPRGHꢀZLWKRXWꢀKDYLQJꢀPRGLILHGꢀWKHꢀFRQWHQWVꢀRIꢀWKHꢀSURWHFWHGꢀVHFWRUꢃꢀ$Qꢀ
HUDVHꢀFRPPDQGꢀWRꢀDꢀSURWHFWHGꢀVHFWRUꢀHQDEOHVꢀVWDWXVꢀSROOLQJꢀIRUꢀDSSUR[LPDWHO\ꢀ
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
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S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
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(PEHGGHGꢀ$OJRULWKPVꢂꢃꢀ7KHꢀV\VWHPꢀFDQꢀUHDGꢀGDWDꢀW5+ꢀDIWHUꢀ5(6(7ꢓꢀUHWXUQVꢀWRꢀ
9,+
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WRꢀ)LJXUHꢀꢎꢈꢄꢀ³5HVHWꢀ7LPLQJVꢄ´ꢀRQꢀSDJHꢀꢌꢋꢀIRUꢀWKHꢀWLPLQJꢀGLDJUDPꢃ
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
39
P r e l i m i n a r y
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67$57
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ꢀꢁ $OOꢃSURWHFWHGꢃVHFWRUVꢃXQSURWHFWHGꢃꢎ,Iꢃ:3!ꢃ ꢃ9 ꢆꢃRXWHUPRVWꢃERRWꢃVHFWRUVꢃZLOOꢃUHPDLQꢃSURWHFWHGꢏꢁ
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ꢄꢁ $OOꢃSUHYLRXVO\ꢃSURWHFWHGꢃVHFWRUVꢃDUHꢃSURWHFWHGꢃRQFHꢃDJDLQꢁ
Figure 1. Temporary Sector Unprotect Operation
40
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
START
START
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
PLSCNT = 1
PLSCNT = 1
RESET# = VID
RESET# = VID
unprotected sectors
prior to issuing the
first sector
Wait 1 μs
Wait 1 μs
unprotect address
No
First Write
Cycle = 60h?
No
First Write
Cycle = 60h?
Temporary Sector
Unprotect Mode
Temporary Sector
Unprotect Mode
Yes
Yes
Set up sector
address
No
All sectors
protected?
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Yes
Set up first sector
address
Sector Unprotect:
Wait 150 µs
Write 60h to sector
address with
A7:A0 =
Verify Sector
Protect: Write 40h
to sector address
with A7:A0 =
01000010
Reset
PLSCNT = 1
Increment
PLSCNT
Wait 1.5 ms
00000010
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Read from
sector address
with A6 = 1,
Data = 01h?
Yes
A1 = 1, A0 = 0
No
Yes
Set up
next sector
address
Yes
No
PLSCNT
= 1000?
Protect another
sector?
Data = 00h?
Yes
Device failed
No
Yes
Remove VID
from RESET#
No
Last sector
verified?
Device failed
Write reset
command
Yes
Remove VID
Sector Unprotect
Algorithm
from RESET#
Sector Protect
Algorithm
Sector Protect
complete
Write reset
command
Sector Unprotect
complete
Figure 2. In-System Sector Protection/Sector Unprotection Algorithms
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
41
P r e l i m i n a r y
Secured Silicon Sector Flash Memory Region
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Table 7. Secured Silicon Sector Addresses
6HFWRU
&XVWRPHU
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ꢉꢊꢀZRUGV
$GGUHVVꢀ5DQJH
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ꢉꢊꢀZRUGV
42
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
43
P r e l i m i n a r y
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Write Protect (WP#)
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S71WS-J_04_A2 August 19, 2005
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Common Flash Memory Interface (CFI)
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Table 8. CFI Query Identification String
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S71WS-J Based MCPs
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P r e l i m i n a r y
Table 9. System Interface String
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Table 10. Device Geometry Definition
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46
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Table 11. Primary Vendor-Specific Extended Query
$GGUHVVHV
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6HFWRUꢀ7HPSRUDU\ꢀ8QSURWHFW
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6HFWRUꢀ3URWHFWꢒ8QSURWHFWꢀVFKHPHꢀ
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%DQNꢀ'ꢀ5HJLRQꢀ,QIRUPDWLRQꢃꢀ;ꢀ ꢀ1XPEHUꢀRIꢀVHFWRUVꢀLQꢀEDQNꢀ
ꢍꢍꢉꢍKꢀꢁ:6ꢈꢎꢇ-ꢂ
ꢍꢍꢑꢍKꢀꢁ:6ꢍꢉꢊ-ꢂ
ꢍꢍꢉꢍKꢀꢁ:6ꢈꢎꢇ-ꢂ
ꢍꢍꢑꢍKꢀꢁ:6ꢍꢉꢊ-ꢂ
ꢍꢍꢎꢋKꢀꢁ:6ꢈꢎꢇ-ꢂ
ꢍꢍꢈꢋKꢀꢁ:6ꢍꢉꢊ-ꢂ
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
47
P r e l i m i n a r y
Table 12. WS128J Sector Address Table
%DQN
6HFWRU
6$ꢍ
6HFWRUꢀ6L]H
ꢊꢀ.ZRUGV
ꢂ[ꢄꢉꢃꢀ$GGUHVVꢀ5DQJH
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ꢍꢍꢈꢍꢍꢍKꢅꢍꢍꢈ)))K
ꢍꢍꢎꢍꢍꢍKꢅꢍꢍꢎ)))K
ꢍꢍꢑꢍꢍꢍKꢅꢍꢍꢑ)))K
ꢍꢍꢊꢍꢍꢍKꢅꢍꢍꢊ)))K
ꢍꢍꢏꢍꢍꢍKꢅꢍꢍꢏ)))K
ꢍꢍꢉꢍꢍꢍKꢅꢍꢍꢉ)))K
ꢍꢍꢋꢍꢍꢍKꢅꢍꢍꢋ)))K
ꢍꢍꢇꢍꢍꢍKꢅꢍꢍ))))K
ꢍꢈꢍꢍꢍꢍKꢅꢍꢈꢋ)))K
ꢍꢈꢇꢍꢍꢍKꢅꢍꢈ))))K
ꢍꢎꢍꢍꢍꢍKꢅꢍꢎꢋ)))K
ꢍꢎꢇꢍꢍꢍKꢅꢍꢎ))))K
ꢍꢑꢍꢍꢍꢍKꢅꢍꢑꢋ)))K
ꢍꢑꢇꢍꢍꢍKꢅꢍꢑ))))K
ꢍꢊꢍꢍꢍꢍKꢅꢍꢊꢋ)))K
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ꢍ'ꢍꢍꢍꢍKꢅꢍ'ꢋ)))K
ꢍ'ꢇꢍꢍꢍKꢅꢍ'))))K
ꢍ(ꢍꢍꢍꢍKꢅꢍ(ꢋ)))K
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ꢍ)ꢍꢍꢍꢍKꢅꢍ)ꢋ)))K
ꢍ)ꢇꢍꢍꢍKꢅꢍ)))))K
6$ꢈ
ꢊꢀ.ZRUGV
6$ꢎ
ꢊꢀ.ZRUGV
6$ꢑ
ꢊꢀ.ZRUGV
6$ꢊ
ꢊꢀ.ZRUGV
6$ꢏ
ꢊꢀ.ZRUGV
6$ꢉ
ꢊꢀ.ZRUGV
6$ꢋ
ꢊꢀ.ZRUGV
6$ꢇ
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
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ꢑꢎꢀ.ZRUGV
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ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
6$ꢌ
6$ꢈꢍ
6$ꢈꢈ
6$ꢈꢎ
6$ꢈꢑ
6$ꢈꢊ
6$ꢈꢏ
6$ꢈꢉ
6$ꢈꢋ
6$ꢈꢇ
6$ꢈꢌ
6$ꢎꢍ
6$ꢎꢈ
6$ꢎꢎ
6$ꢎꢑ
6$ꢎꢊ
6$ꢎꢏ
6$ꢎꢉ
6$ꢎꢋ
6$ꢎꢇ
6$ꢎꢌ
6$ꢑꢍ
6$ꢑꢈ
6$ꢑꢎ
6$ꢑꢑ
6$ꢑꢊ
6$ꢑꢏ
6$ꢑꢉ
6$ꢑꢋ
6$ꢑꢇ
ꢀ%DQNꢀ'
48
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Table 12. WS128J Sector Address Table
%DQN
6HFWRU
6$ꢑꢌ
6$ꢊꢍ
6$ꢊꢈ
6$ꢊꢎ
6$ꢊꢑ
6$ꢊꢊ
6$ꢊꢏ
6$ꢊꢉ
6$ꢊꢋ
6$ꢊꢇ
6$ꢊꢌ
6$ꢏꢍ
6$ꢏꢈ
6$ꢏꢎ
6$ꢏꢑ
6$ꢏꢊ
6$ꢏꢏ
6$ꢏꢉ
6$ꢏꢋ
6$ꢏꢇ
6$ꢏꢌ
6$ꢉꢍ
6$ꢉꢈ
6$ꢉꢎ
6$ꢉꢑ
6$ꢉꢊ
6$ꢉꢏ
6$ꢉꢉ
6$ꢉꢋ
6$ꢉꢇ
6$ꢉꢌ
6$ꢋꢍ
6HFWRUꢀ6L]H
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
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ꢑꢎꢀ.ZRUGV
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ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
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ꢑꢎꢀ.ZRUGV
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ꢑꢎꢀ.ZRUGV
ꢂ[ꢄꢉꢃꢀ$GGUHVVꢀ5DQJH
ꢈꢍꢍꢍꢍꢍKꢅꢈꢍꢋ)))K
ꢈꢍꢇꢍꢍꢍKꢅꢈꢍ))))K
ꢈꢈꢍꢍꢍꢍKꢅꢈꢈꢋ)))K
ꢈꢈꢇꢍꢍꢍKꢅꢈꢈ))))K
ꢈꢎꢍꢍꢍꢍKꢅꢈꢎꢋ)))K
ꢈꢎꢇꢍꢍꢍKꢅꢈꢎ))))K
ꢈꢑꢍꢍꢍꢍKꢅꢈꢑꢋ)))K
ꢈꢑꢇꢍꢍꢍKꢅꢈꢑ))))K
ꢈꢊꢍꢍꢍꢍKꢅꢈꢊꢋ)))K
ꢈꢊꢇꢍꢍꢍKꢅꢈꢊ))))K
ꢈꢏꢍꢍꢍꢍKꢅꢈꢏꢋ)))K
ꢈꢏꢇꢍꢍꢍKꢅꢈꢏ))))K
ꢈꢉꢍꢍꢍꢍKꢅꢈꢉꢋ)))K
ꢈꢉꢇꢍꢍꢍKꢅꢈꢉ))))K
ꢈꢋꢍꢍꢍꢍKꢅꢈꢋꢋ)))K
ꢈꢋꢇꢍꢍꢍKꢅꢈꢋ))))K
ꢈꢇꢍꢍꢍꢍKꢅꢈꢇꢋ)))K
ꢈꢇꢇꢍꢍꢍKꢅꢈꢇ))))K
ꢈꢌꢍꢍꢍꢍKꢅꢈꢌꢋ)))K
ꢈꢌꢇꢍꢍꢍKꢅꢈꢌ))))K
ꢈ$ꢍꢍꢍꢍKꢅꢈ$ꢋ)))K
ꢈ$ꢇꢍꢍꢍKꢅꢈ$))))K
ꢈ%ꢍꢍꢍꢍKꢅꢈ%ꢋ)))K
ꢈ%ꢇꢍꢍꢍKꢅꢈ%))))K
ꢈ&ꢍꢍꢍꢍKꢅꢈ&ꢋ)))K
ꢈ&ꢇꢍꢍꢍKꢅꢈ&))))K
ꢈ'ꢍꢍꢍꢍKꢅꢈ'ꢋ)))K
ꢈ'ꢇꢍꢍꢍKꢅꢈ'))))K
ꢈ(ꢍꢍꢍꢍKꢅꢈ(ꢋ)))K
ꢈ(ꢇꢍꢍꢍKꢅꢈ())))K
ꢈ)ꢍꢍꢍꢍKꢅꢈ)ꢋ)))K
ꢈ)ꢇꢍꢍꢍKꢅꢈ)))))K
%DQNꢀ&
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
49
P r e l i m i n a r y
Table 12. WS128J Sector Address Table
%DQN
6HFWRU
6$ꢋꢈ
6$ꢋꢎ
6$ꢋꢑ
6$ꢋꢊ
6$ꢋꢏ
6$ꢋꢉ
6$ꢋꢋ
6$ꢋꢇ
6$ꢋꢌ
6$ꢇꢍ
6$ꢇꢈ
6$ꢇꢎ
6$ꢇꢑ
6$ꢇꢊ
6$ꢇꢏ
6$ꢇꢉ
6$ꢇꢋ
6$ꢇꢇ
6$ꢇꢌ
6$ꢌꢍ
6$ꢌꢈ
6$ꢌꢎ
6$ꢌꢑ
6$ꢌꢊ
6$ꢌꢏ
6$ꢌꢉ
6$ꢌꢋ
6$ꢌꢇ
6$ꢌꢌ
6$ꢈꢍꢍ
6$ꢈꢍꢈ
6$ꢈꢍꢎ
6HFWRUꢀ6L]H
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
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ꢎ$ꢇꢍꢍꢍKꢅꢎ$))))K
ꢎ%ꢍꢍꢍꢍKꢅꢎ%ꢋ)))K
ꢎ%ꢇꢍꢍꢍKꢅꢎ%))))K
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ꢎ'ꢇꢍꢍꢍKꢅꢎ'))))K
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ꢎ)ꢇꢍꢍꢍKꢅꢎ)))))K
%DQNꢀ&
50
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Table 12. WS128J Sector Address Table
%DQN
6HFWRU
6$ꢈꢍꢑ
6$ꢈꢍꢊ
6$ꢈꢍꢏ
6$ꢈꢍꢉ
6$ꢈꢍꢋ
6$ꢈꢍꢇ
6$ꢈꢍꢌ
6$ꢈꢈꢍ
6$ꢈꢈꢈ
6$ꢈꢈꢎ
6$ꢈꢈꢑ
6$ꢈꢈꢊ
6$ꢈꢈꢏ
6$ꢈꢈꢉ
6$ꢈꢈꢋ
6$ꢈꢈꢇ
6$ꢈꢈꢌ
6$ꢈꢎꢍ
6$ꢈꢎꢈ
6$ꢈꢎꢎ
6$ꢈꢎꢑ
6$ꢈꢎꢊ
6$ꢈꢎꢏ
6$ꢈꢎꢉ
6$ꢈꢎꢋ
6$ꢈꢎꢇ
6$ꢈꢎꢌ
6$ꢈꢑꢍ
6$ꢈꢑꢈ
6$ꢈꢑꢎ
6$ꢈꢑꢑ
6$ꢈꢑꢊ
6HFWRUꢀ6L]H
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ꢑꢎꢀ.ZRUGV
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ꢑꢎꢀ.ZRUGV
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ꢑꢎꢀ.ZRUGV
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ꢑꢊꢍꢍꢍꢍKꢅꢑꢊꢋ)))K
ꢑꢊꢇꢍꢍꢍKꢅꢑꢊ))))K
ꢑꢏꢍꢍꢍꢍKꢅꢑꢏꢋ)))K
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ꢑꢌꢇꢍꢍꢍKꢅꢑꢌ))))K
ꢑ$ꢍꢍꢍꢍKꢅꢑ$ꢋ)))K
ꢑ$ꢇꢍꢍꢍKꢅꢑ$))))K
ꢑ%ꢍꢍꢍꢍKꢅꢑ%ꢋ)))K
ꢑ%ꢇꢍꢍꢍKꢅꢑ%))))K
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ꢑ(ꢇꢍꢍꢍKꢅꢑ())))K
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%DQNꢀ&
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
51
P r e l i m i n a r y
Table 12. WS128J Sector Address Table
%DQN
6HFWRU
6$ꢈꢑꢏ
6$ꢈꢑꢉ
6$ꢈꢑꢋ
6$ꢈꢑꢇ
6$ꢈꢑꢌ
6$ꢈꢊꢍ
6$ꢈꢊꢈ
6$ꢈꢊꢎ
6$ꢈꢊꢑ
6$ꢈꢊꢊ
6$ꢈꢊꢏ
6$ꢈꢊꢉ
6$ꢈꢊꢋ
6$ꢈꢊꢇ
6$ꢈꢊꢌ
6$ꢈꢏꢍ
6$ꢈꢏꢈ
6$ꢈꢏꢎ
6$ꢈꢏꢑ
6$ꢈꢏꢊ
6$ꢈꢏꢏ
6$ꢈꢏꢉ
6$ꢈꢏꢋ
6$ꢈꢏꢇ
6$ꢈꢏꢌ
6$ꢈꢉꢍ
6$ꢈꢉꢈ
6$ꢈꢉꢎ
6$ꢈꢉꢑ
6$ꢈꢉꢊ
6$ꢈꢉꢏ
6$ꢈꢉꢉ
6HFWRUꢀ6L]H
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ꢑꢎꢀ.ZRUGV
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ꢑꢎꢀ.ZRUGV
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ꢊꢇꢇꢍꢍꢍKꢅꢊꢇ))))K
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ꢊ$ꢇꢍꢍꢍKꢅꢊ$))))K
ꢊ%ꢍꢍꢍꢍKꢅꢊ%ꢋ)))K
ꢊ%ꢇꢍꢍꢍKꢅꢊ%))))K
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%DQNꢀ%
52
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Table 12. WS128J Sector Address Table
%DQN
6HFWRU
6$ꢈꢉꢋ
6$ꢈꢉꢇ
6$ꢈꢉꢌ
6$ꢈꢋꢍ
6$ꢈꢋꢈ
6$ꢈꢋꢎ
6$ꢈꢋꢑ
6$ꢈꢋꢊ
6$ꢈꢋꢏ
6$ꢈꢋꢉ
6$ꢈꢋꢋ
6$ꢈꢋꢇ
6$ꢈꢋꢌ
6$ꢈꢇꢍ
6$ꢈꢇꢈ
6$ꢈꢇꢎ
6$ꢈꢇꢑ
6$ꢈꢇꢊ
6$ꢈꢇꢏ
6$ꢈꢇꢉ
6$ꢈꢇꢋ
6$ꢈꢇꢇ
6$ꢈꢇꢌ
6$ꢈꢌꢍ
6$ꢈꢌꢈ
6$ꢈꢌꢎ
6$ꢈꢌꢑ
6$ꢈꢌꢊ
6$ꢈꢌꢏ
6$ꢈꢌꢉ
6$ꢈꢌꢋ
6$ꢈꢌꢇ
6HFWRUꢀ6L]H
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
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ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
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ꢏꢈꢇꢍꢍꢍKꢅꢏꢈ))))K
ꢏꢎꢍꢍꢍꢍKꢅꢏꢎꢋ)))K
ꢏꢎꢇꢍꢍꢍKꢅꢏꢎ))))K
ꢏꢑꢍꢍꢍꢍKꢅꢏꢑꢋ)))K
ꢏꢑꢇꢍꢍꢍKꢅꢏꢑ))))K
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ꢏ$ꢇꢍꢍꢍKꢅꢏ$))))K
ꢏ%ꢍꢍꢍꢍKꢅꢏ%ꢋ)))K
ꢏ%ꢇꢍꢍꢍKꢅꢏ%))))K
ꢏ&ꢍꢍꢍꢍKꢅꢏ&ꢋ)))K
ꢏ&ꢇꢍꢍꢍKꢅꢏ&))))K
ꢏ'ꢍꢍꢍꢍKꢅꢏ'ꢋ)))K
ꢏ'ꢇꢍꢍꢍKꢅꢏ'))))K
ꢏ(ꢍꢍꢍꢍKꢅꢏ(ꢋ)))K
ꢏ(ꢇꢍꢍꢍKꢅꢏ())))K
ꢏ)ꢍꢍꢍꢍKꢅꢏ)ꢋ)))K
ꢏ)ꢇꢍꢍꢍKꢅꢏ)))))K
%DQNꢀ%
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
53
P r e l i m i n a r y
Table 12. WS128J Sector Address Table
%DQN
6HFWRU
6$ꢈꢌꢌ
6$ꢎꢍꢍ
6$ꢎꢍꢈ
6$ꢎꢍꢎ
6$ꢎꢍꢑ
6$ꢎꢍꢊ
6$ꢎꢍꢏ
6$ꢎꢍꢉ
6$ꢎꢍꢋ
6$ꢎꢍꢇ
6$ꢎꢍꢌ
6$ꢎꢈꢍ
6$ꢎꢈꢈ
6$ꢎꢈꢎ
6$ꢎꢈꢑ
6$ꢎꢈꢊ
6$ꢎꢈꢏ
6$ꢎꢈꢉ
6$ꢎꢈꢋ
6$ꢎꢈꢇ
6$ꢎꢈꢌ
6$ꢎꢎꢍ
6$ꢎꢎꢈ
6$ꢎꢎꢎ
6$ꢎꢎꢑ
6$ꢎꢎꢊ
6$ꢎꢎꢏ
6$ꢎꢎꢉ
6$ꢎꢎꢋ
6$ꢎꢎꢇ
6$ꢎꢎꢌ
6$ꢎꢑꢍ
6HFWRUꢀ6L]H
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢂ[ꢄꢉꢃꢀ$GGUHVVꢀ5DQJH
ꢉꢍꢍꢍꢍꢍKꢅꢉꢍꢋ)))K
ꢉꢍꢇꢍꢍꢍKꢅꢉꢍ))))K
ꢉꢈꢍꢍꢍꢍKꢅꢉꢈꢋ)))K
ꢉꢈꢇꢍꢍꢍKꢅꢉꢈ))))K
ꢉꢎꢍꢍꢍꢍKꢅꢉꢎꢋ)))K
ꢉꢎꢇꢍꢍꢍKꢅꢉꢎ))))K
ꢉꢑꢍꢍꢍꢍKꢅꢉꢑꢋ)))K
ꢉꢑꢇꢍꢍꢍKꢅꢉꢑ))))K
ꢉꢊꢍꢍꢍꢍKꢅꢉꢊꢋ)))K
ꢉꢊꢇꢍꢍꢍKꢅꢉꢊ))))K
ꢉꢏꢍꢍꢍꢍKꢅꢉꢏꢋ)))K
ꢉꢏꢇꢍꢍꢍKꢅꢉꢏ))))K
ꢉꢉꢍꢍꢍꢍKꢅꢉꢉꢋ)))K
ꢉꢉꢇꢍꢍꢍKꢅꢉꢉ))))K
ꢉꢋꢍꢍꢍꢍKꢅꢉꢋꢋ)))K
ꢉꢋꢇꢍꢍꢍKꢅꢉꢋ))))K
ꢉꢇꢍꢍꢍꢍKꢅꢉꢇꢋ)))K
ꢉꢇꢇꢍꢍꢍKꢅꢉꢇ))))K
ꢉꢌꢍꢍꢍꢍKꢅꢉꢌꢋ)))K
ꢉꢌꢇꢍꢍꢍKꢅꢉꢌ))))K
ꢉ$ꢍꢍꢍꢍKꢅꢉ$ꢋ)))K
ꢉ$ꢇꢍꢍꢍKꢅꢉ$))))K
ꢉ%ꢍꢍꢍꢍKꢅꢉ%ꢋ)))K
ꢉ%ꢇꢍꢍꢍKꢅꢉ%))))K
ꢉ&ꢍꢍꢍꢍKꢅꢉ&ꢋ)))K
ꢉ&ꢇꢍꢍꢍKꢅꢉ&))))K
ꢉ'ꢍꢍꢍꢍKꢅꢉ'ꢋ)))K
ꢉ'ꢇꢍꢍꢍKꢅꢉ'))))K
ꢉ(ꢍꢍꢍꢍKꢅꢉ(ꢋ)))K
ꢉ(ꢇꢍꢍꢍKꢅꢉ())))K
ꢉ)ꢍꢍꢍꢍKꢅꢉ)ꢋ)))K
ꢉ)ꢇꢍꢍꢍKꢅꢉ)))))K
%DQNꢀ%
54
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Table 12. WS128J Sector Address Table
%DQN
6HFWRU
6$ꢎꢑꢈ
6$ꢎꢑꢎ
6$ꢎꢑꢑ
6$ꢎꢑꢊ
6$ꢎꢑꢏ
6$ꢎꢑꢉ
6$ꢎꢑꢋ
6$ꢎꢑꢇ
6$ꢎꢑꢌ
6$ꢎꢊꢍ
6$ꢎꢊꢈ
6$ꢎꢊꢎ
6$ꢎꢊꢑ
6$ꢎꢊꢊ
6$ꢎꢊꢏ
6$ꢎꢊꢉ
6$ꢎꢊꢋ
6$ꢎꢊꢇ
6$ꢎꢊꢌ
6$ꢎꢏꢍ
6$ꢎꢏꢈ
6$ꢎꢏꢎ
6$ꢎꢏꢑ
6$ꢎꢏꢊ
6$ꢎꢏꢏ
6$ꢎꢏꢉ
6$ꢎꢏꢋ
6$ꢎꢏꢇ
6$ꢎꢏꢌ
6$ꢎꢉꢍ
6$ꢎꢉꢈ
6$ꢎꢉꢎ
6$ꢎꢉꢑ
6$ꢎꢉꢊ
6$ꢎꢉꢏ
6$ꢎꢉꢉ
6$ꢎꢉꢋ
6$ꢎꢉꢇ
6$ꢎꢉꢌ
6HFWRUꢀ6L]H
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢊꢀ.ZRUGV
ꢂ[ꢄꢉꢃꢀ$GGUHVVꢀ5DQJH
ꢋꢍꢍꢍꢍꢍKꢅꢋꢍꢋ)))K
ꢋꢍꢇꢍꢍꢍKꢅꢋꢍ))))K
ꢋꢈꢍꢍꢍꢍKꢅꢋꢈꢋ)))K
ꢋꢈꢇꢍꢍꢍKꢅꢋꢈ))))K
ꢋꢎꢍꢍꢍꢍKꢅꢋꢎꢋ)))K
ꢋꢎꢇꢍꢍꢍKꢅꢋꢎ))))K
ꢋꢑꢍꢍꢍꢍKꢅꢋꢑꢋ)))K
ꢋꢑꢇꢍꢍꢍKꢅꢋꢑ))))K
ꢋꢊꢍꢍꢍꢍKꢅꢋꢊꢋ)))K
ꢋꢊꢇꢍꢍꢍKꢅꢋꢊ))))K
ꢋꢏꢍꢍꢍꢍKꢅꢋꢏꢋ)))K
ꢋꢏꢇꢍꢍꢍKꢅꢋꢏ))))K
ꢋꢉꢍꢍꢍꢍKꢅꢋꢉꢋ)))K
ꢋꢉꢇꢍꢍꢍKꢅꢋꢉ))))K
ꢋꢋꢍꢍꢍꢍKꢅꢋꢋꢋ)))K
ꢋꢋꢇꢍꢍꢍKꢅꢋꢋ))))K
ꢋꢇꢍꢍꢍꢍKꢅꢋꢇꢋ)))K
ꢋꢇꢇꢍꢍꢍKꢅꢋꢇ))))K
ꢋꢌꢍꢍꢍꢍKꢅꢋꢌꢋ)))K
ꢋꢌꢇꢍꢍꢍKꢅꢋꢌ))))K
ꢋ$ꢍꢍꢍꢍKꢅꢋ$ꢋ)))K
ꢋ$ꢇꢍꢍꢍKꢅꢋ$))))K
ꢋ%ꢍꢍꢍꢍKꢅꢋ%ꢋ)))K
ꢋ%ꢇꢍꢍꢍKꢅꢋ%))))K
ꢋ&ꢍꢍꢍꢍKꢅꢋ&ꢋ)))K
ꢋ&ꢇꢍꢍꢍKꢅꢋ&))))K
ꢋ'ꢍꢍꢍꢍKꢅꢋ'ꢋ)))K
ꢋ'ꢇꢍꢍꢍKꢅꢋ'))))K
ꢋ(ꢍꢍꢍꢍKꢅꢋ(ꢋ)))K
ꢋ(ꢇꢍꢍꢍKꢅꢋ())))K
ꢋ)ꢍꢍꢍꢍKꢅꢋ)ꢋ)))K
ꢋ)ꢇꢍꢍꢍKꢅꢋ)ꢇ)))K
ꢋ)ꢌꢍꢍꢍKꢅꢋ)ꢌ)))K
ꢋ)$ꢍꢍꢍKꢅꢋ)$)))K
ꢋ)%ꢍꢍꢍKꢅꢋ)%)))K
ꢋ)&ꢍꢍꢍKꢅꢋ)&)))K
ꢋ)'ꢍꢍꢍKꢅꢋ)')))K
ꢋ)(ꢍꢍꢍKꢅꢋ)()))K
ꢋ))ꢍꢍꢍKꢅꢋ)))))K
%DQNꢀ$
ꢊꢀ.ZRUGV
ꢊꢀ.ZRUGV
ꢊꢀ.ZRUGV
ꢊꢀ.ZRUGV
ꢊꢀ.ZRUGV
ꢊꢀ.ZRUGV
ꢊꢀ.ZRUGV
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
55
P r e l i m i n a r y
Table 13. WS064J Sector Address Table
%DQN
6HFWRU
6$ꢍ
6HFWRUꢀ6L]H
ꢊꢀ.ZRUGV
ꢊꢀ.ZRUGV
ꢊꢀ.ZRUGV
ꢊꢀ.ZRUGV
ꢊꢀ.ZRUGV
ꢊꢀ.ZRUGV
ꢊꢀ.ZRUGV
ꢊꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
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ꢂ[ꢄꢉꢃꢀ$GGUHVVꢀ5DQJH
ꢍꢍꢍꢍꢍꢍKꢅꢍꢍꢍ)))K
ꢍꢍꢈꢍꢍꢍKꢅꢍꢍꢈ)))K
ꢍꢍꢎꢍꢍꢍKꢅꢍꢍꢎ)))K
ꢍꢍꢑꢍꢍꢍKꢅꢍꢍꢑ)))K
ꢍꢍꢊꢍꢍꢍKꢅꢍꢍꢊ)))K
ꢍꢍꢏꢍꢍꢍKꢅꢍꢍꢏ)))K
ꢍꢍꢉꢍꢍꢍKꢅꢍꢍꢉ)))K
ꢍꢍꢋꢍꢍꢍKꢅꢍꢍꢋ)))K
ꢍꢍꢇꢍꢍꢍKꢅꢍꢍ))))K
ꢍꢈꢍꢍꢍꢍKꢅꢍꢈꢋ)))K
ꢍꢈꢇꢍꢍꢍKꢅꢍꢈ))))K
ꢍꢎꢍꢍꢍꢍKꢅꢍꢎꢋ)))K
ꢍꢎꢇꢍꢍꢍKꢅꢍꢎ))))K
ꢍꢑꢍꢍꢍꢍKꢅꢍꢑꢋ)))K
ꢍꢑꢇꢍꢍꢍKꢅꢍꢑ))))K
ꢍꢊꢍꢍꢍꢍKꢅꢍꢊꢋ)))K
ꢍꢊꢇꢍꢍꢍKꢅꢍꢊ))))K
ꢍꢏꢍꢍꢍꢍKꢅꢍꢏꢋ)))K
ꢍꢏꢇꢍꢍꢍKꢅꢍꢏ))))K
ꢍꢉꢍꢍꢍꢍKꢅꢍꢉꢋ)))K
ꢍꢉꢇꢍꢍꢍKꢅꢍꢉ))))K
ꢍꢋꢍꢍꢍꢍKꢅꢍꢋꢋ)))K
ꢍꢋꢇꢍꢍꢍKꢅꢍꢋ))))K
6$ꢈ
6$ꢎ
6$ꢑ
6$ꢊ
6$ꢏ
6$ꢉ
6$ꢋ
6$ꢇ
6$ꢌ
6$ꢈꢍ
6$ꢈꢈ
6$ꢈꢎ
6$ꢈꢑ
6$ꢈꢊ
6$ꢈꢏ
6$ꢈꢉ
6$ꢈꢋ
6$ꢈꢇ
6$ꢈꢌ
6$ꢎꢍ
6$ꢎꢈ
6$ꢎꢎ
ꢀ%DQNꢀ'
56
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Table 13. WS064J Sector Address Table
%DQN
6HFWRU
6$ꢎꢑ
6$ꢎꢊ
6$ꢎꢏ
6$ꢎꢉ
6$ꢎꢋ
6$ꢎꢇ
6$ꢎꢌ
6$ꢑꢍ
6$ꢑꢈ
6$ꢑꢎ
6$ꢑꢑ
6$ꢑꢊ
6$ꢑꢏ
6$ꢑꢉ
6$ꢑꢋ
6$ꢑꢇ
6$ꢑꢌ
6$ꢊꢍ
6$ꢊꢈ
6$ꢊꢎ
6$ꢊꢑ
6$ꢊꢊ
6$ꢊꢏ
6$ꢊꢉ
6HFWRUꢀ6L]H
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
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ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
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ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
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ꢍꢇꢇꢍꢍꢍKꢅꢍꢇ))))K
ꢍꢌꢍꢍꢍꢍKꢅꢍꢌꢋ)))K
ꢍꢌꢇꢍꢍꢍKꢅꢍꢌ))))K
ꢍ$ꢍꢍꢍꢍKꢅꢍ$ꢋ)))K
ꢍ$ꢇꢍꢍꢍKꢅꢍ$))))K
ꢍ%ꢍꢍꢍꢍKꢅꢍ%ꢋ)))K
ꢍ%ꢇꢍꢍꢍKꢅꢍ%))))K
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ꢍ&ꢇꢍꢍꢍKꢅꢍ&))))K
ꢍ'ꢍꢍꢍꢍKꢅꢍ'ꢋ)))K
ꢍ'ꢇꢍꢍꢍKꢅꢍ'))))K
ꢍ(ꢍꢍꢍꢍKꢅꢍ(ꢋ)))K
ꢍ(ꢇꢍꢍꢍKꢅꢍ())))K
ꢍ)ꢍꢍꢍꢍKꢅꢍ)ꢋ)))K
ꢍ)ꢇꢍꢍꢍKꢅꢍ)))))K
ꢈꢍꢍꢍꢍꢍKꢅꢈꢍꢋ)))K
ꢈꢍꢇꢍꢍꢍKꢅꢈꢍ))))K
ꢈꢈꢍꢍꢍꢍKꢅꢈꢈꢋ)))K
ꢈꢈꢇꢍꢍꢍKꢅꢈꢈ))))K
ꢈꢎꢍꢍꢍꢍKꢅꢈꢎꢋ)))K
ꢈꢎꢇꢍꢍꢍKꢅꢈꢎ))))K
ꢈꢑꢍꢍꢍꢍKꢅꢈꢑꢋ)))K
ꢈꢑꢇꢍꢍꢍKꢅꢈꢑ))))K
%DQNꢀ&
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
57
P r e l i m i n a r y
Table 13. WS064J Sector Address Table
%DQN
6HFWRU
6$ꢊꢋ
6$ꢊꢇ
6$ꢊꢌ
6$ꢏꢍ
6$ꢏꢈ
6$ꢏꢎ
6$ꢏꢑ
6$ꢏꢊ
6$ꢏꢏ
6$ꢏꢉ
6$ꢏꢋ
6$ꢏꢇ
6$ꢏꢌ
6$ꢉꢍ
6$ꢉꢈ
6$ꢉꢎ
6$ꢉꢑ
6$ꢉꢊ
6$ꢉꢏ
6$ꢉꢉ
6$ꢉꢋ
6$ꢉꢇ
6$ꢉꢌ
6$ꢋꢍ
6HFWRUꢀ6L]H
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ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
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ꢂ[ꢄꢉꢃꢀ$GGUHVVꢀ5DQJH
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ꢈꢊꢇꢍꢍꢍKꢅꢈꢊ))))K
ꢈꢏꢍꢍꢍꢍKꢅꢈꢏꢋ)))K
ꢈꢏꢇꢍꢍꢍKꢅꢈꢏ))))K
ꢈꢉꢍꢍꢍꢍKꢅꢈꢉꢋ)))K
ꢈꢉꢇꢍꢍꢍKꢅꢈꢉ))))K
ꢈꢋꢍꢍꢍꢍKꢅꢈꢋꢋ)))K
ꢈꢋꢇꢍꢍꢍKꢅꢈꢋ))))K
ꢈꢇꢍꢍꢍꢍKꢅꢈꢇꢋ)))K
ꢈꢇꢇꢍꢍꢍKꢅꢈꢇ))))K
ꢈꢌꢍꢍꢍꢍKꢅꢈꢌꢋ)))K
ꢈꢌꢇꢍꢍꢍKꢅꢈꢌ))))K
ꢈ$ꢍꢍꢍꢍKꢅꢈ$ꢋ)))K
ꢈ$ꢇꢍꢍꢍKꢅꢈ$))))K
ꢈ%ꢍꢍꢍꢍKꢅꢈ%ꢋ)))K
ꢈ%ꢇꢍꢍꢍKꢅꢈ%))))K
ꢈ&ꢍꢍꢍꢍKꢅꢈ&ꢋ)))K
ꢈ&ꢇꢍꢍꢍKꢅꢈ&))))K
ꢈ'ꢍꢍꢍꢍKꢅꢈ'ꢋ)))K
ꢈ'ꢇꢍꢍꢍKꢅꢈ'))))K
ꢈ(ꢍꢍꢍꢍKꢅꢈ(ꢋ)))K
ꢈ(ꢇꢍꢍꢍKꢅꢈ())))K
ꢈ)ꢍꢍꢍꢍKꢅꢈ)ꢋ)))K
ꢈ)ꢇꢍꢍꢍKꢅꢈ)))))K
%DQNꢀ&
58
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Table 13. WS064J Sector Address Table
%DQN
6HFWRU
6$ꢋꢈ
6$ꢋꢎ
6$ꢋꢑ
6$ꢋꢊ
6$ꢋꢏ
6$ꢋꢉ
6$ꢋꢋ
6$ꢋꢇ
6$ꢋꢌ
6$ꢇꢍ
6$ꢇꢈ
6$ꢇꢎ
6$ꢇꢑ
6$ꢇꢊ
6$ꢇꢏ
6$ꢇꢉ
6$ꢇꢋ
6$ꢇꢇ
6$ꢇꢌ
6$ꢌꢍ
6$ꢌꢈ
6$ꢌꢎ
6$ꢌꢑ
6$ꢌꢊ
6HFWRUꢀ6L]H
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢂ[ꢄꢉꢃꢀ$GGUHVVꢀ5DQJH
ꢎꢍꢍꢍꢍꢍKꢅꢎꢍꢋ)))K
ꢎꢍꢇꢍꢍꢍKꢅꢎꢍ))))K
ꢎꢈꢍꢍꢍꢍKꢅꢎꢈꢋ)))K
ꢎꢈꢇꢍꢍꢍKꢅꢎꢈ))))K
ꢎꢎꢍꢍꢍꢍKꢅꢎꢎꢋ)))K
ꢎꢎꢇꢍꢍꢍKꢅꢎꢎ))))K
ꢎꢑꢍꢍꢍꢍKꢅꢎꢑꢋ)))K
ꢎꢑꢇꢍꢍꢍKꢅꢎꢑ))))K
ꢎꢊꢍꢍꢍꢍKꢅꢎꢊꢋ)))K
ꢎꢊꢇꢍꢍꢍKꢅꢎꢊ))))K
ꢎꢏꢍꢍꢍꢍKꢅꢎꢏꢋ)))K
ꢎꢏꢇꢍꢍꢍKꢅꢎꢏ))))K
ꢎꢉꢍꢍꢍꢍKꢅꢎꢉꢋ)))K
ꢎꢉꢇꢍꢍꢍKꢅꢎꢉ))))K
ꢎꢋꢍꢍꢍꢍKꢅꢎꢋꢋ)))K
ꢎꢋꢇꢍꢍꢍKꢅꢎꢋ))))K
ꢎꢇꢍꢍꢍꢍKꢅꢎꢇꢋ)))K
ꢎꢇꢇꢍꢍꢍKꢅꢎꢇ))))K
ꢎꢌꢍꢍꢍꢍKꢅꢎꢌꢋ)))K
ꢎꢌꢇꢍꢍꢍKꢅꢎꢌ))))K
ꢎ$ꢍꢍꢍꢍKꢅꢎ$ꢋ)))K
ꢎ$ꢇꢍꢍꢍKꢅꢎ$))))K
ꢎ%ꢍꢍꢍꢍKꢅꢎ%ꢋ)))K
ꢎ%ꢇꢍꢍꢍKꢅꢎ%))))K
%DQNꢀ%
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
59
P r e l i m i n a r y
Table 13. WS064J Sector Address Table
%DQN
6HFWRU
6$ꢌꢏ
6HFWRUꢀ6L]H
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢂ[ꢄꢉꢃꢀ$GGUHVVꢀ5DQJH
ꢎ&ꢍꢍꢍꢍKꢅꢎ&ꢋ)))K
ꢎ&ꢇꢍꢍꢍKꢅꢎ&))))K
ꢎ'ꢍꢍꢍꢍKꢅꢎ'ꢋ)))K
ꢎ'ꢇꢍꢍꢍKꢅꢎ'))))K
ꢎ(ꢍꢍꢍꢍKꢅꢎ(ꢋ)))K
ꢎ(ꢇꢍꢍꢍKꢅꢎ())))K
ꢎ)ꢍꢍꢍꢍKꢅꢎ)ꢋ)))K
ꢎ)ꢇꢍꢍꢍKꢅꢎ)))))K
ꢑꢍꢍꢍꢍꢍKꢅꢑꢍꢋ)))K
ꢑꢍꢇꢍꢍꢍKꢅꢑꢍ))))K
ꢑꢈꢍꢍꢍꢍKꢅꢑꢈꢋ)))K
ꢑꢈꢇꢍꢍꢍKꢅꢑꢈ))))K
ꢑꢎꢍꢍꢍꢍKꢅꢑꢎꢋ)))K
ꢑꢎꢇꢍꢍꢍKꢅꢑꢎ))))K
ꢑꢑꢍꢍꢍꢍKꢅꢑꢑꢋ)))K
ꢑꢑꢇꢍꢍꢍKꢅꢑꢑ))))K
ꢑꢊꢍꢍꢍꢍKꢅꢑꢊꢋ)))K
ꢑꢊꢇꢍꢍꢍKꢅꢑꢊ))))K
ꢑꢏꢍꢍꢍꢍKꢅꢑꢏꢋ)))K
ꢑꢏꢇꢍꢍꢍKꢅꢑꢏ))))K
ꢑꢉꢍꢍꢍꢍKꢅꢑꢉꢋ)))K
ꢑꢉꢇꢍꢍꢍKꢅꢑꢉ))))K
ꢑꢋꢍꢍꢍꢍKꢅꢑꢋꢋ)))K
ꢑꢋꢇꢍꢍꢍKꢅꢑꢋ))))K
6$ꢌꢉ
6$ꢌꢋ
6$ꢌꢇ
6$ꢌꢌ
6$ꢈꢍꢍ
6$ꢈꢍꢈ
6$ꢈꢍꢎ
6$ꢈꢍꢑ
6$ꢈꢍꢊ
6$ꢈꢍꢏ
6$ꢈꢍꢉ
6$ꢈꢍꢋ
6$ꢈꢍꢇ
6$ꢈꢍꢌ
6$ꢈꢈꢍ
6$ꢈꢈꢈ
6$ꢈꢈꢎ
6$ꢈꢈꢑ
6$ꢈꢈꢊ
6$ꢈꢈꢏ
6$ꢈꢈꢉ
6$ꢈꢈꢋ
6$ꢈꢈꢇ
%DQNꢀ%
60
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Table 13. WS064J Sector Address Table
%DQN
6HFWRU
6$ꢈꢈꢌ
6$ꢈꢎꢍ
6$ꢈꢎꢈ
6$ꢈꢎꢎ
6$ꢈꢎꢑ
6$ꢈꢎꢊ
6$ꢈꢎꢏ
6$ꢈꢎꢉ
6$ꢈꢎꢋ
6$ꢈꢎꢇ
6$ꢈꢎꢌ
6$ꢈꢑꢍ
6$ꢈꢑꢈ
6$ꢈꢑꢎ
6$ꢈꢑꢑ
6$ꢈꢑꢊ
6$ꢈꢑꢏ
6$ꢈꢑꢉ
6$ꢈꢑꢋ
6$ꢈꢑꢇ
6$ꢈꢑꢌ
6$ꢈꢊꢍ
6$ꢈꢊꢈ
6HFWRUꢀ6L]H
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢑꢎꢀ.ZRUGV
ꢊꢀ.ZRUGV
ꢊꢀ.ZRUGV
ꢊꢀ.ZRUGV
ꢊꢀ.ZRUGV
ꢊꢀ.ZRUGV
ꢊꢀ.ZRUGV
ꢊꢀ.ZRUGV
ꢊꢀ.ZRUGV
ꢂ[ꢄꢉꢃꢀ$GGUHVVꢀ5DQJH
ꢑꢇꢍꢍꢍꢍKꢅꢑꢇꢋ)))K
ꢑꢇꢇꢍꢍꢍKꢅꢑꢇ))))K
ꢑꢌꢍꢍꢍꢍKꢅꢑꢌꢋ)))K
ꢑꢌꢇꢍꢍꢍKꢅꢑꢌ))))K
ꢑ$ꢍꢍꢍꢍKꢅꢑ$ꢋ)))K
ꢑ$ꢇꢍꢍꢍKꢅꢑ$))))K
ꢑ%ꢍꢍꢍꢍKꢅꢑ%ꢋ)))K
ꢑ%ꢇꢍꢍꢍKꢅꢑ%))))K
ꢑ&ꢍꢍꢍꢍKꢅꢑ&ꢋ)))K
ꢑ&ꢇꢍꢍꢍKꢅꢑ&))))K
ꢑ'ꢍꢍꢍꢍKꢅꢑ'ꢋ)))K
ꢑ'ꢇꢍꢍꢍKꢅꢑ'))))K
ꢑ(ꢍꢍꢍꢍKꢅꢑ(ꢋ)))K
ꢑ(ꢇꢍꢍꢍKꢅꢑ())))K
ꢑ)ꢍꢍꢍꢍKꢅꢑ)ꢋ)))K
ꢑ)ꢇꢍꢍꢍKꢅꢑ)ꢇ)))K
ꢑ)ꢌꢍꢍꢍKꢅꢑ)ꢌ)))K
ꢑ)$ꢍꢍꢍKꢅꢑ)$)))K
ꢑ)%ꢍꢍꢍKꢅꢑ)%)))K
ꢑ)&ꢍꢍꢍKꢅꢑ)&)))K
ꢑ)'ꢍꢍꢍKꢅꢑ)')))K
ꢑ)(ꢍꢍꢍKꢅꢑ)()))K
ꢑ))ꢍꢍꢍKꢅꢑ)))))K
%DQNꢀ$
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
61
P r e l i m i n a r y
Command Definitions
:ULWLQJꢀVSHFLILFꢀDGGUHVVꢀDQGꢀGDWDꢀFRPPDQGVꢀRUꢀVHTXHQFHVꢀLQWRꢀWKHꢀFRPPDQGꢀ
UHJLVWHUꢀLQLWLDWHVꢀGHYLFHꢀRSHUDWLRQVꢃꢀ7DEOHꢀꢈꢇꢄꢀ³&RPPDQGꢀ'HILQLWLRQVꢄ´ꢀRQꢀSDJHꢀꢋꢉ
GHILQHVꢀWKHꢀYDOLGꢀUHJLVWHUꢀFRPPDQGꢀVHTXHQFHVꢃꢀ:ULWLQJꢀLQFRUUHFWꢀDGGUHVVꢀDQGꢀ
GDWDꢀYDOXHVꢀRUꢀZULWLQJꢀWKHPꢀLQꢀWKHꢀLPSURSHUꢀVHTXHQFHꢀPD\ꢀSODFHꢀWKHꢀGHYLFHꢀLQꢀDQꢀ
XQNQRZQꢀVWDWHꢃꢀ7KHꢀV\VWHPꢀPXVWꢀZULWHꢀWKHꢀUHVHWꢀFRPPDQGꢀWRꢀUHWXUQꢀWKHꢀGHYLFHꢀ
WRꢀUHDGLQJꢀDUUD\ꢀGDWDꢃꢀ5HIHUꢀWRꢀWKHꢀ$&ꢀ&KDUDFWHULVWLFVꢀVHFWLRQꢀIRUꢀWLPLQJꢀGLDJUDPVꢃ
Reading Array Data
7KHꢀGHYLFHꢀLVꢀDXWRPDWLFDOO\ꢀVHWꢀWRꢀUHDGLQJꢀDUUD\ꢀGDWDꢀDIWHUꢀGHYLFHꢀSRZHUꢅXSꢃꢀ1Rꢀ
FRPPDQGVꢀDUHꢀUHTXLUHGꢀWRꢀUHWULHYHꢀGDWDꢀLQꢀDV\QFKURQRXVꢀPRGHꢃꢀ(DFKꢀEDQNꢀLVꢀ
UHDG\ꢀWRꢀUHDGꢀDUUD\ꢀGDWDꢀDIWHUꢀFRPSOHWLQJꢀDQꢀ(PEHGGHGꢀ3URJUDPꢀRUꢀ(PEHGGHGꢀ
(UDVHꢀDOJRULWKPꢃ
$IWHUꢀWKHꢀGHYLFHꢀDFFHSWVꢀDQꢀ(UDVHꢀ6XVSHQGꢀFRPPDQGꢄꢀWKHꢀFRUUHVSRQGLQJꢀEDQNꢀ
HQWHUVꢀWKHꢀHUDVHꢅVXVSHQGꢅUHDGꢀPRGHꢄꢀDIWHUꢀZKLFKꢀWKHꢀV\VWHPꢀFDQꢀUHDGꢀGDWDꢀIURPꢀ
DQ\ꢀQRQꢅHUDVHꢅVXVSHQGHGꢀVHFWRUꢀZLWKLQꢀWKHꢀVDPHꢀEDQNꢃꢀ$IWHUꢀFRPSOHWLQJꢀDꢀSURꢅ
JUDPPLQJꢀRSHUDWLRQꢀLQꢀWKHꢀ(UDVHꢀ6XVSHQGꢀPRGHꢄꢀWKHꢀV\VWHPꢀPD\ꢀRQFHꢀDJDLQꢀ
UHDGꢀDUUD\ꢀGDWDꢀIURPꢀDQ\ꢀQRQꢅHUDVHꢅVXVSHQGHGꢀVHFWRUꢀZLWKLQꢀWKHꢀVDPHꢀEDQNꢃꢀ6HHꢀ
WKHꢀ³(UDVHꢀ6XVSHQGꢒ(UDVHꢀ5HVXPHꢀ&RPPDQGV´ꢀVHFWLRQꢀRQꢀSDJHꢀꢋꢈꢀIRUꢀPRUHꢀ
LQIRUPDWLRQꢃ
7KHꢀV\VWHPꢀPXVWꢀLVVXHꢀWKHꢀUHVHWꢀFRPPDQGꢀWRꢀUHWXUQꢀDꢀEDQNꢀWRꢀWKHꢀUHDGꢀꢁRUꢀHUDVHꢅ
VXVSHQGꢅUHDGꢂꢀPRGHꢀLIꢀ'4ꢏꢀJRHVꢀKLJKꢀGXULQJꢀDQꢀDFWLYHꢀSURJUDPꢀRUꢀHUDVHꢀRSHUDꢅ
WLRQꢄꢀRUꢀLIꢀWKHꢀEDQNꢀLVꢀLQꢀWKHꢀDXWRVHOHFWꢀPRGHꢃꢀ6HHꢀWKHꢀ³5HVHWꢀ&RPPDQG´ꢀVHFWLRQꢀ
RQꢀSDJHꢀꢉꢉꢀIRUꢀPRUHꢀLQIRUPDWLRQꢃ
6HHꢀDOVRꢀ³5HTXLUHPHQWVꢀIRUꢀ$V\QFKURQRXVꢀ5HDGꢀ2SHUDWLRQꢀꢁ1RQꢅ%XUVWꢂ´ꢀVHFWLRQꢀ
RQꢀSDJHꢀꢎꢏꢀDQGꢀ³5HTXLUHPHQWVꢀIRUꢀ6\QFKURQRXVꢀꢁ%XUVWꢂꢀ5HDGꢀ2SHUDWLRQ´ꢀVHFWLRQꢀ
RQꢀSDJHꢀꢎꢉꢀIRUꢀPRUHꢀLQIRUPDWLRQꢃꢀ7KHꢀ$V\QFKURQRXVꢀ5HDGꢀDQGꢀ6\QFKURQRXVꢒ
%XUVWꢀ5HDGꢀWDEOHVꢀSURYLGHꢀWKHꢀUHDGꢀSDUDPHWHUVꢄꢀDQGꢀ)LJXUHꢀꢈꢊꢄꢀ³&/.ꢀ6\QFKURQRXVꢀ
%XUVWꢀ0RGHꢀ5HDGꢀꢁULVLQJꢀDFWLYHꢀ&/.ꢂꢄ´ꢀRQꢀSDJHꢀꢌꢎꢄꢀ)LJXUHꢀꢈꢉꢄꢀ³6\QFKURQRXVꢀ%XUVWꢀ
0RGHꢀ5HDGꢄ´ꢀRQꢀSDJHꢀꢌꢑꢄꢀDQGꢀ)LJXUHꢀꢈꢌꢄꢀ³$V\QFKURQRXVꢀ0RGHꢀ5HDGꢀZLWKꢀ/DWFKHGꢀ
$GGUHVVHVꢄ´ꢀRQꢀSDJHꢀꢌꢉꢀVKRZꢀWKHꢀWLPLQJVꢃ
Set Configuration Register Command Sequence
7KHꢀGHYLFHꢀXVHVꢀDꢀFRQILJXUDWLRQꢀUHJLVWHUꢀWRꢀVHWꢀWKHꢀYDULRXVꢀEXUVWꢀSDUDPHWHUVꢆꢀ
QXPEHUꢀRIꢀZDLWꢀVWDWHVꢄꢀEXUVWꢀUHDGꢀPRGHꢄꢀDFWLYHꢀFORFNꢀHGJHꢄꢀ5'<ꢀFRQILJXUDWLRQꢄꢀ
DQGꢀV\QFKURQRXVꢀPRGHꢀDFWLYHꢃꢀ7KHꢀFRQILJXUDWLRQꢀUHJLVWHUꢀPXVWꢀEHꢀVHWꢀEHIRUHꢀWKHꢀ
GHYLFHꢀZLOOꢀHQWHUꢀEXUVWꢀPRGHꢃ
7KHꢀFRQILJXUDWLRQꢀUHJLVWHUꢀLVꢀORDGHGꢀZLWKꢀDꢀWKUHHꢅF\FOHꢀFRPPDQGꢀVHTXHQFHꢃꢀ7KHꢀ
ILUVWꢀWZRꢀF\FOHVꢀDUHꢀVWDQGDUGꢀXQORFNꢀVHTXHQFHVꢃꢀ2QꢀWKHꢀWKLUGꢀF\FOHꢄꢀWKHꢀGDWDꢀ
VKRXOGꢀEHꢀ&ꢍKꢄꢀDGGUHVVꢀELWVꢀ$ꢈꢈ±$ꢍꢀVKRXOGꢀEHꢀꢏꢏꢏKꢄꢀDQGꢀDGGUHVVꢀELWVꢀ$ꢈꢌ±$ꢈꢎꢀ
VHWꢀWKHꢀFRGHꢀWRꢀEHꢀODWFKHGꢃꢀ7KHꢀGHYLFHꢀZLOOꢀSRZHUꢀXSꢀRUꢀDIWHUꢀDꢀKDUGZDUHꢀUHVHWꢀ
ZLWKꢀWKHꢀGHIDXOWꢀVHWWLQJꢄꢀZKLFKꢀLVꢀLQꢀDV\QFKURQRXVꢀPRGHꢃꢀ7KHꢀUHJLVWHUꢀPXVWꢀEHꢀVHWꢀ
EHIRUHꢀWKHꢀGHYLFHꢀFDQꢀHQWHUꢀV\QFKURQRXVꢀPRGHꢃꢀ7KHꢀFRQILJXUDWLRQꢀUHJLVWHUꢀFDQꢀ
QRWꢀEHꢀFKDQJHGꢀGXULQJꢀGHYLFHꢀRSHUDWLRQVꢀꢁSURJUDPꢄꢀHUDVHꢄꢀRUꢀVHFWRUꢀORFNꢂꢃ
62
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Power-up/
Hardware Reset
Asynchronous Read
Mode Only
Set Burst Mode
Configuration Register
Command for
Set Burst Mode
Configuration Register
Command for
Synchronous Mode
(D15 = 0)
Asynchronous Mode
(D15 = 1)
Synchronous Read
Mode Only
Figure 3. Synchronous/Asynchronous State Diagram
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
63
P r e l i m i n a r y
Table 14. Programmable Wait State Settings
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Table 15. Wait States for Standard wait-state Handshaking
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64
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S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
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Table 16. Read Mode Settings
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DV\QFKURQRXVꢀPRGHꢄꢀ5'<ꢀLVꢀDQꢀRSHQꢅGUDLQꢀRXWSXWꢃ
Configuration Register
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
65
P r e l i m i n a r y
Table 17. Configuration Register
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Reset Command
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66
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Autoselect Command Sequence
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Enter/Exit Secured Silicon Sector Command Sequence
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
67
P r e l i m i n a r y
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Program Command Sequence
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68
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
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START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
No
Yes
No
Increment Address
Last Address?
Yes
Programming
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Chip Erase Command Sequence
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
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S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
71
P r e l i m i n a r y
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Password Program Command
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72
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Password Verify Command
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Password Protection Mode Locking Bit Program Command
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
73
P r e l i m i n a r y
PPB Lock Bit Set Command
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Password Unlock Command
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JRHVꢀ/2:ꢀLQGLFDWLQJꢀWKDWꢀWKHꢀGHYLFHꢀLVꢀEXV\ꢃꢀ$OVRꢄꢀUHDGLQJꢀWKHꢀ%DQNꢀ'ꢀUHVXOWVꢀLQꢀ
WKHꢀ'4ꢉꢀSLQꢀWRJJOLQJꢄꢀLQGLFDWLQJꢀWKDWꢀWKHꢀ3DVVZRUGꢀ8QORFNꢀIXQFWLRQꢀLVꢀLQꢀ
SURJUHVVꢃꢀ5HDGLQJꢀWKHꢀRWKHUꢀEDQNꢀUHWXUQVꢀDFWXDOꢀDUUD\ꢀGDWDꢃꢀ$SSUR[LPDWHO\ꢀꢈVꢀ
LVꢀUHTXLUHGꢀIRUꢀHDFKꢀSRUWLRQꢀRIꢀWKHꢀXQORFNꢃꢀ2QFHꢀWKHꢀILUVWꢀSRUWLRQꢀRIꢀWKHꢀSDVVZRUGꢀ
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3DVVZRUGꢀ8QORFNꢀFRPPDQGꢀLVꢀLVVXHGꢀDJDLQꢄꢀRQO\ꢀWKLVꢀWLPHꢀZLWKꢀWKHꢀQH[WꢀSDUWꢀRIꢀ
WKHꢀSDVVZRUGꢃꢀ)RXUꢀ3DVVZRUGꢀ8QORFNꢀFRPPDQGVꢀDUHꢀUHTXLUHGꢀWRꢀVXFFHVVIXOO\ꢀ
FOHDUꢀWKHꢀ33%ꢀ/RFNꢀ%LWꢃꢀ$VꢀZLWKꢀWKHꢀILUVWꢀ3DVVZRUGꢀ8QORFNꢀFRPPDQGꢄꢀWKHꢀ5'<ꢀVLJꢅ
QDOꢀJRHVꢀ/2:ꢀDQGꢀUHDGLQJꢀWKHꢀGHYLFHꢀUHVXOWVꢀLQꢀWKHꢀ'4ꢉꢀSLQꢀWRJJOLQJꢀRQꢀ
VXFFHVVLYHꢀUHDGꢀRSHUDWLRQVꢀXQWLOꢀFRPSOHWHꢃꢀ,WꢀLVꢀWKHꢀUHVSRQVLELOLW\ꢀRIꢀWKHꢀPLFURꢅ
74
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
SURFHVVRUꢀWRꢀNHHSꢀWUDFNꢀRIꢀWKHꢀQXPEHUꢀRIꢀ3DVVZRUGꢀ8QORFNꢀFRPPDQGVꢄꢀWKHꢀRUGHUꢄꢀ
DQGꢀZKHQꢀWRꢀUHDGꢀWKHꢀ33%ꢀ/RFNꢀELWꢀWRꢀFRQILUPꢀVXFFHVVIXOꢀSDVVZRUGꢀXQORFNꢃꢀ,Qꢀ
RUGHUꢀWRꢀUHꢀORFNꢀWKHꢀGHYLFHꢀLQWRꢀWKHꢀ3DVVZRUGꢀ0RGHꢄꢀWKHꢀ33%ꢀ/RFNꢀ%LWꢀ6HWꢀFRPꢅ
PDQGꢀFDQꢀEHꢀUHꢅLVVXHGꢃ
PPB Program Command
7KHꢀ33%ꢀ3URJUDPꢀFRPPDQGꢀLVꢀXVHGꢀWRꢀSURJUDPꢄꢀRUꢀVHWꢄꢀDꢀJLYHQꢀ33%ꢃꢀ(DFKꢀ33%ꢀLVꢀ
LQGLYLGXDOO\ꢀSURJUDPPHGꢀꢁEXWꢀLVꢀEXONꢀHUDVHGꢀZLWKꢀWKHꢀRWKHUꢀ33%Vꢂꢃꢀ7KHꢀVSHFLILFꢀ
VHFWRUꢀDGGUHVVꢀꢁ$PD[±$ꢈꢎꢂꢀDUHꢀZULWWHQꢀDWꢀWKHꢀVDPHꢀWLPHꢀDVꢀWKHꢀSURJUDPꢀFRPꢅ
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WLPHꢅRXWꢀZLWKRXWꢀSURJUDPPLQJꢀWKHꢀ33%ꢃꢀ
$IWHUꢀSURJUDPPLQJꢀDꢀ33%ꢄꢀWZRꢀDGGLWLRQDOꢀF\FOHVꢀDUHꢀQHHGHGꢀWRꢀGHWHUPLQHꢀZKHWKHUꢀ
WKHꢀ33%ꢀKDVꢀEHHQꢀSURJUDPPHGꢀZLWKꢀPDUJLQꢃꢀ$IWHUꢀꢊWKꢀF\FOHꢄꢀWKHꢀGHYLFHꢀUHTXLUHVꢀ
DSSUR[LPDWHO\ꢀꢈꢏꢍꢀVꢀWLPHꢀRXWꢀSHULRGꢀIRUꢀSURJUDPPLQJꢀWKHꢀ33%ꢃꢀ$QGꢀWKHQꢀDIWHUꢀ
ꢏWKꢀF\FOHꢄꢀWKHꢀGHYLFHꢀRXWSXWVꢀYHULI\ꢀGDWDꢀDWꢀ'4ꢍꢃ
7KHꢀ33%ꢀ3URJUDPꢀFRPPDQGꢀGRHVꢀQRWꢀIROORZꢀWKHꢀ(PEHGGHGꢀ3URJUDPꢀDOJRULWKPꢃꢀ
:ULWLQJꢀWKHꢀ6HFXUHGꢀ6LOLFRQꢀ6HFWRUꢀ([LWꢀFRPPDQGꢀUHWXUQVꢀWKHꢀGHYLFHꢀEDFNꢀWRꢀQRUꢅ
PDOꢀRSHUDWLRQꢃ
All PPB Erase Command
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IRUꢀLQGLYLGXDOO\ꢀHUDVLQJꢀDꢀVSHFLILFꢀ33%ꢃꢀ8QOLNHꢀWKHꢀ33%ꢀSURJUDPꢄꢀQRꢀVSHFLILFꢀVHFWRUꢀ
DGGUHVVꢀLVꢀUHTXLUHGꢃꢀ+RZHYHUꢄꢀZKHQꢀWKHꢀ33%ꢀHUDVHꢀFRPPDQGꢀLVꢀZULWWHQꢀꢁꢉꢍKꢂꢀ
DQGꢀ$ꢉꢀ ꢀꢈꢄꢀDOOꢀ6HFWRUꢀ33%VꢀDUHꢀHUDVHGꢀLQꢀSDUDOOHOꢃꢀ,IꢀWKHꢀ33%ꢀ/RFNꢀ%LWꢀLVꢀVHWꢀWKHꢀ
$//ꢀ33%ꢀ(UDVHꢀFRPPDQGꢀZLOOꢀQRWꢀH[HFXWHꢀDQGꢀWKHꢀFRPPDQGꢀZLOOꢀWLPHꢅRXWꢀZLWKꢅ
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$IWHUꢀHUDVLQJꢀWKHꢀ33%VꢄꢀWZRꢀDGGLWLRQDOꢀF\FOHVꢀDUHꢀQHHGHGꢀWRꢀGHWHUPLQHꢀZKHWKHUꢀ
WKHꢀ33%ꢀKDVꢀEHHQꢀHUDVHGꢀZLWKꢀPDUJLQꢃꢀ$IWHUꢀꢊWKꢀF\FOHꢄꢀWKHꢀGHYLFHꢀUHTXLUHVꢀDSꢅ
SUR[LPDWHO\ꢀꢈꢃꢏꢀPVꢀWLPHꢀRXWꢀSHULRGꢀIRUꢀHUDVLQJꢀWKHꢀ33%ꢃꢀ$QGꢀWKHQꢀDIWHUꢀꢏWKꢀ
F\FOHꢄꢀWKHꢀGHYLFHꢀRXWSXWVꢀYHULI\ꢀGDWDꢀDWꢀ'4ꢍꢃ
,WꢀLVꢀWKHꢀUHVSRQVLELOLW\ꢀRIꢀWKHꢀXVHUꢀWRꢀSUHSURJUDPꢀDOOꢀ33%VꢀSULRUꢀWRꢀLVVXLQJꢀWKHꢀ$OOꢀ
33%ꢀ(UDVHꢀFRPPDQGꢃꢀ,IꢀWKHꢀXVHUꢀDWWHPSWVꢀWRꢀHUDVHꢀDꢀFOHDUHGꢀ33%ꢄꢀRYHUꢅHUDVXUHꢀ
PD\ꢀRFFXUꢀPDNLQJꢀLWꢀGLIILFXOWꢀWRꢀSURJUDPꢀWKHꢀ33%ꢀDWꢀDꢀODWHUꢀWLPHꢃꢀ$OVRꢀQRWHꢀWKDWꢀ
WKHꢀWRWDOꢀQXPEHUꢀRIꢀ33%ꢀSURJUDPꢒHUDVHꢀF\FOHVꢀLVꢀOLPLWHGꢀWRꢀꢈꢍꢍꢀF\FOHVꢃꢀ&\FOLQJꢀ
WKHꢀ33%VꢀEH\RQGꢀꢈꢍꢍꢀF\FOHVꢀLVꢀQRWꢀJXDUDQWHHGꢃꢀ:ULWLQJꢀWKHꢀ6HFXUHGꢀ6LOLFRQꢀ6HFꢅ
WRUꢀ([LWꢀFRPPDQGꢀUHWXUQVꢀWKHꢀGHYLFHꢀEDFNꢀWRꢀQRUPDOꢀRSHUDWLRQꢃ
PPB Status Command
7KHꢀSURJUDPPLQJꢀRIꢀWKHꢀ33%ꢀIRUꢀDꢀJLYHQꢀVHFWRUꢀFDQꢀEHꢀYHULILHGꢀE\ꢀZULWLQJꢀDꢀ33%ꢀ
VWDWXVꢀYHULI\ꢀFRPPDQGꢀWRꢀWKHꢀGHYLFHꢃ
PPB Lock Bit Status Command
7KHꢀSURJUDPPLQJꢀRIꢀWKHꢀ33%ꢀ/RFNꢀ%LWꢀIRUꢀDꢀJLYHQꢀVHFWRUꢀFDQꢀEHꢀYHULILHGꢀE\ꢀZULWꢅ
LQJꢀDꢀ33%ꢀ/RFNꢀ%LWꢀVWDWXVꢀYHULI\ꢀFRPPDQGꢀWRꢀWKHꢀGHYLFHꢃ
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
75
P r e l i m i n a r y
Command Definitions
Table 18. Command Definitions
%XVꢀ&\FOHVꢀꢂ1RWHVꢀꢄ±ꢉꢃ
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76
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
%XVꢀ&\FOHVꢀꢂ1RWHVꢀꢄ±ꢉꢃ
7KLUGꢀ )RXUWK )LIWK
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S71WS-J Based MCPs
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S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
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EDQNꢀUHWXUQVꢀWRꢀWKHꢀUHDGꢀPRGHꢃꢀ,IꢀQRWꢀDOOꢀVHOHFWHGꢀVHFWRUVꢀDUHꢀSURWHFWHGꢄꢀWKHꢀ(Pꢅ
EHGGHGꢀ(UDVHꢀDOJRULWKPꢀHUDVHVꢀWKHꢀXQSURWHFWHGꢀVHFWRUVꢄꢀDQGꢀLJQRUHVꢀWKHꢀVHOHFWHGꢀ
VHFWRUVꢀWKDWꢀDUHꢀSURWHFWHGꢃꢀ+RZHYHUꢄꢀLIꢀWKHꢀV\VWHPꢀUHDGVꢀ'4ꢋꢀDWꢀDQꢀDGGUHVVꢀZLWKLQꢀ
DꢀSURWHFWHGꢀVHFWRUꢄꢀWKHꢀVWDWXVꢀPD\ꢀQRWꢀEHꢀYDOLGꢃ
-XVWꢀSULRUꢀWRꢀWKHꢀFRPSOHWLRQꢀRIꢀDQꢀ(PEHGGHGꢀ3URJUDPꢀRUꢀ(UDVHꢀRSHUDWLRQꢄꢀ'4ꢋꢀ
PD\ꢀFKDQJHꢀDV\QFKURQRXVO\ꢀZLWKꢀ'4ꢉ±'4ꢍꢀZKLOHꢀ2XWSXWꢀ(QDEOHꢀꢁ2(ꢓꢂꢀLVꢀDVꢅ
VHUWHGꢀORZꢃꢀ7KDWꢀLVꢄꢀWKHꢀGHYLFHꢀPD\ꢀFKDQJHꢀIURPꢀSURYLGLQJꢀVWDWXVꢀLQIRUPDWLRQꢀWRꢀ
YDOLGꢀGDWDꢀRQꢀ'4ꢋꢃꢀ'HSHQGLQJꢀRQꢀZKHQꢀWKHꢀV\VWHPꢀVDPSOHVꢀWKHꢀ'4ꢋꢀRXWSXWꢄꢀLWꢀ
PD\ꢀUHDGꢀWKHꢀVWDWXVꢀRUꢀYDOLGꢀGDWDꢃꢀ(YHQꢀLIꢀWKHꢀGHYLFHꢀKDVꢀFRPSOHWHGꢀWKHꢀSURJUDPꢀ
RUꢀHUDVHꢀRSHUDWLRQꢀDQGꢀ'4ꢋꢀKDVꢀYDOLGꢀGDWDꢄꢀWKHꢀGDWDꢀRXWSXWVꢀRQꢀ'4ꢉꢅ'4ꢍꢀPD\ꢀ
EHꢀVWLOOꢀLQYDOLGꢃꢀ9DOLGꢀGDWDꢀRQꢀ'4ꢋꢅ'ꢍꢍꢀZLOOꢀDSSHDUꢀRQꢀVXFFHVVLYHꢀUHDGꢀF\FOHVꢃ
7DEOHꢀꢎꢍꢄꢀ³:ULWHꢀ2SHUDWLRQꢀ6WDWXVꢄ´ꢀRQꢀSDJHꢀꢇꢏꢀVKRZVꢀWKHꢀRXWSXWVꢀIRUꢀ'DWDꢓꢀ3ROOꢅ
LQJꢀRQꢀ'4ꢋꢃꢀ)LJXUHꢀꢉꢄꢀ³'DWDꢓꢀ3ROOLQJꢀ$OJRULWKPꢄ´ꢀRQꢀSDJHꢀꢇꢍꢀVKRZVꢀWKHꢀ'DWDꢓꢀ
3ROOLQJꢀ
DOJRULWKPꢃꢀ
)LJXUHꢀꢎꢇꢄꢀ
³'DWDꢓꢀ
3ROOLQJꢀ
7LPLQJVꢀ
ꢁ'XULQJꢀ(PEHGGHGꢀ$OJRULWKPꢂꢄ´ꢀRQꢀSDJHꢀꢈꢍꢏꢀLQꢀWKHꢀ$&ꢀ&KDUDFWHULVWLFVꢀVHFWLRQꢀ
VKRZVꢀWKHꢀ'DWDꢓꢀ3ROOLQJꢀWLPLQJꢀGLDJUDPꢃ
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
79
P r e l i m i n a r y
START
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
No
PASS
FAIL
1RWHVꢀ
ꢀꢁ 9$ꢃ ꢃ9DOLGꢃDGGUHVVꢃIRUꢃSURJUDPPLQJꢁꢃ'XULQJꢃDꢃVHFWRUꢃHUDVHꢃRSHUDWLRQꢆꢃDꢃYDOLGꢃDGGUHVVꢃLVꢃDQ\ꢃVHFWRUꢃDGGUHVVꢃZLWKLQꢃ
WKHꢃVHFWRUꢃEHLQJꢃHUDVHGꢁꢃ'XULQJꢃFKLSꢃHUDVHꢆꢃDꢃYDOLGꢃDGGUHVVꢃLVꢃDQ\ꢃQRQꢂSURWHFWHGꢃVHFWRUꢃDGGUHVVꢁ
ꢄꢁ '4ꢉꢃVKRXOGꢃEHꢃUHFKHFNHGꢃHYHQꢃLIꢃ'4ꢊꢃ ꢃ³ꢀ´ꢃEHFDXVHꢃ'4ꢉꢃPD\ꢃFKDQJHꢃVLPXOWDQHRXVO\ꢃZLWKꢃ'4ꢊꢁ
Figure 6. Data# Polling Algorithm
80
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
RDY: Ready
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QRXVꢀPRGHꢄꢀLQGLFDWHVꢀꢁZKHQꢀDWꢀORJLFꢀORZꢂꢀWKHꢀV\VWHPꢀVKRXOGꢀZDLWꢀꢈꢀFORFNꢀF\FOHꢀ
EHIRUHꢀH[SHFWLQJꢀWKHꢀQH[WꢀZRUGꢀRIꢀGDWDꢃꢀ7KHꢀ5'<ꢀSLQꢀLVꢀRQO\ꢀFRQWUROOHGꢀE\ꢀ&(ꢓꢃꢀ
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ORZꢀLQGLFDWHVꢀWKHꢀV\VWHPꢀVKRXOGꢀZDLWꢀꢎꢀFORFNꢀF\FOHVꢀEHIRUHꢀH[SHFWLQJꢀYDOLGꢀGDWDꢃ
7KHꢀIROORZLQJꢀFRQGLWLRQVꢀFDXVHꢀWKHꢀ5'<ꢀRXWSXWꢀWRꢀEHꢀORZꢆꢀGXULQJꢀWKHꢀLQLWLDOꢀDFFHVVꢀ
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:KHQꢀWKHꢀGHYLFHꢀLVꢀFRQILJXUHGꢀLQꢀ$V\QFKURQRXVꢀ0RGHꢄꢀWKHꢀ5'<ꢀLVꢀDQꢀRSHQꢅGUDLQꢀ
RXWSXWꢀSLQꢀZKLFKꢀLQGLFDWHVꢀZKHWKHUꢀDQꢀ(PEHGGHGꢀ$OJRULWKPꢀLVꢀLQꢀSURJUHVVꢀRUꢀ
FRPSOHWHGꢃꢀ7KHꢀ5'<ꢀVWDWXVꢀLVꢀYDOLGꢀDIWHUꢀWKHꢀULVLQJꢀHGJHꢀRIꢀWKHꢀILQDOꢀ:(ꢓꢀSXOVHꢀLQꢀ
WKHꢀFRPPDQGꢀVHTXHQFHꢃꢀ
,IꢀWKHꢀRXWSXWꢀLVꢀORZꢀꢁ%XV\ꢂꢄꢀWKHꢀGHYLFHꢀLVꢀDFWLYHO\ꢀHUDVLQJꢀRUꢀSURJUDPPLQJꢃꢀꢁ7KLVꢀ
LQFOXGHVꢀSURJUDPPLQJꢀLQꢀWKHꢀ(UDVHꢀ6XVSHQGꢀPRGHꢃꢂꢀ,IꢀWKHꢀRXWSXWꢀLVꢀLQꢀKLJKꢀLPꢅ
SHGDQFHꢀꢁ5HDG\ꢂꢄꢀWKHꢀGHYLFHꢀLVꢀLQꢀWKHꢀUHDGꢀPRGHꢄꢀWKHꢀVWDQGE\ꢀPRGHꢄꢀRUꢀLQꢀWKHꢀ
HUDVHꢅVXVSHQGꢅUHDGꢀPRGHꢃꢀ7DEOHꢀꢎꢍꢄꢀ³:ULWHꢀ2SHUDWLRQꢀ6WDWXVꢄ´ꢀRQꢀSDJHꢀꢇꢏꢀVKRZVꢀ
WKHꢀRXWSXWVꢀIRUꢀ5'<ꢃ
DQ6: Toggle Bit I
7RJJOHꢀ%LWꢀ,ꢀRQꢀ'4ꢉꢀLQGLFDWHVꢀZKHWKHUꢀDQꢀ(PEHGGHGꢀ3URJUDPꢀRUꢀ(UDVHꢀDOJRULWKPꢀ
LVꢀLQꢀSURJUHVVꢀRUꢀFRPSOHWHꢄꢀRUꢀZKHWKHUꢀWKHꢀGHYLFHꢀKDVꢀHQWHUHGꢀWKHꢀ(UDVHꢀ6XVSHQGꢀ
PRGHꢃꢀ7RJJOHꢀ%LWꢀ,ꢀPD\ꢀEHꢀUHDGꢀDWꢀDQ\ꢀDGGUHVVꢀLQꢀWKHꢀVDPHꢀEDQNꢄꢀDQGꢀLVꢀYDOLGꢀ
DIWHUꢀWKHꢀULVLQJꢀHGJHꢀRIꢀWKHꢀILQDOꢀ:(ꢓꢀSXOVHꢀLQꢀWKHꢀFRPPDQGꢀVHTXHQFHꢀꢁSULRUꢀWRꢀ
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FOHVꢀWRꢀDQ\ꢀDGGUHVVꢀFDXVHꢀ'4ꢉꢀWRꢀWRJJOHꢃꢀ:KHQꢀWKHꢀRSHUDWLRQꢀLVꢀFRPSOHWHꢄꢀ'4ꢉꢀ
VWRSVꢀWRJJOLQJꢃ
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DUHꢀSURWHFWHGꢄꢀ'4ꢉꢀWRJJOHVꢀIRUꢀDSSUR[LPDWHO\ꢀꢈꢍꢍꢀVꢄꢀWKHQꢀUHWXUQVꢀWRꢀUHDGLQJꢀ
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SURWHFWHGꢃꢀ
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WLYHO\ꢀHUDVLQJꢀRUꢀLVꢀHUDVHꢅVXVSHQGHGꢃꢀ:KHQꢀWKHꢀGHYLFHꢀLVꢀDFWLYHO\ꢀHUDVLQJꢀꢁWKDWꢀLVꢄꢀ
WKHꢀ(PEHGGHGꢀ(UDVHꢀDOJRULWKPꢀLVꢀLQꢀSURJUHVVꢂꢄꢀ'4ꢉꢀWRJJOHVꢃꢀ:KHQꢀWKHꢀGHYLFHꢀHQꢅ
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PDWHO\ꢀꢈꢀPVꢀDIWHUꢀWKHꢀSURJUDPꢀFRPPDQGꢀVHTXHQFHꢀLVꢀZULWWHQꢄꢀWKHQꢀUHWXUQVꢀWRꢀ
UHDGLQJꢀDUUD\ꢀGDWDꢃ
'4ꢉꢀDOVRꢀWRJJOHVꢀGXULQJꢀWKHꢀHUDVHꢅVXVSHQGꢅSURJUDPꢀPRGHꢄꢀDQGꢀVWRSVꢀWRJJOLQJꢀ
RQFHꢀWKHꢀ(PEHGGHGꢀ3URJUDPꢀDOJRULWKPꢀLVꢀFRPSOHWHꢃ
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SDJHꢀꢇꢎꢄꢀ³'4ꢉꢆꢀ7RJJOHꢀ%LWꢀ,´ꢀRQꢀSDJHꢀꢇꢈꢄꢀ)LJXUHꢀꢎꢌꢄꢀ³7RJJOHꢀ%LWꢀ7LPLQJVꢀ
ꢁ'XULQJꢀ(PEHGGHGꢀ$OJRULWKPꢂꢄ´ꢀRQꢀSDJHꢀꢈꢍꢏꢀꢁWRJJOHꢀELWꢀWLPLQJꢀGLDJUDPꢂꢄꢀDQGꢀ
7DEOHꢀꢈꢌꢄꢀ³'4ꢉꢀDQGꢀ'4ꢎꢀ,QGLFDWLRQVꢄ´ꢀRQꢀSDJHꢀꢇꢑꢃꢀ
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
81
P r e l i m i n a r y
7RJJOHꢀ%LWꢀ,ꢀRQꢀ'4ꢉꢀUHTXLUHVꢀHLWKHUꢀ2(ꢓꢀRUꢀ&(ꢓꢀWRꢀEHꢀGHDVVHUWHHGꢀDQGꢀUHDVVHUWHGꢀ
WRꢀVKRZꢀWKHꢀFKDQJHꢀLQꢀVWDWHꢃ
START
Read Byte
(DQ0-DQ7)
Address = VA
Read Byte
(DQ0-DQ7)
Address = VA
No
DQ6 = Toggle?
Yes
No
DQ5 = 1?
Yes
Read Byte Twice
(DQ 0-DQ7)
Adrdess = VA
No
DQ6 = Toggle?
Yes
FAIL
PASS
1RWHꢀꢁ7KHꢃV\VWHPꢃVKRXOGꢃUHFKHFNꢃWKHꢃWRJJOHꢃELWꢃHYHQꢃLIꢃ'4ꢊꢃ ꢃ³ꢀ´ꢃEHFDXVHꢃWKHꢃWRJJOHꢃELWꢃPD\ꢃVWRSꢃWRJJOLQJꢃDVꢃ'4ꢊꢃFKDQJHVꢃWRꢃ
³ꢀꢁ´ꢃ6HHꢃWKHꢃVXEVHFWLRQVꢃRQꢃ'4ꢋꢃDQGꢃ'4ꢄꢃIRUꢃPRUHꢃLQIRUPDWLRQꢁ
Figure 7. Toggle Bit Algorithm
DQ2: Toggle Bit II
7KHꢀ³7RJJOHꢀ%LWꢀ,,´ꢀRQꢀ'4ꢎꢄꢀZKHQꢀXVHGꢀZLWKꢀ'4ꢉꢄꢀLQGLFDWHVꢀZKHWKHUꢀDꢀSDUWLFXODUꢀ
VHFWRUꢀLVꢀDFWLYHO\ꢀHUDVLQJꢀꢁWKDWꢀLVꢄꢀWKHꢀ(PEHGGHGꢀ(UDVHꢀDOJRULWKPꢀLVꢀLQꢀSURJUHVVꢂꢄꢀ
RUꢀZKHWKHUꢀWKDWꢀVHFWRUꢀLVꢀHUDVHꢅVXVSHQGHGꢃꢀ7RJJOHꢀ%LWꢀ,,ꢀLVꢀYDOLGꢀDIWHUꢀWKHꢀULVLQJꢀ
HGJHꢀRIꢀWKHꢀILQDOꢀ:(ꢓꢀSXOVHꢀLQꢀWKHꢀFRPPDQGꢀVHTXHQFHꢃ
82
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
'4ꢎꢀWRJJOHVꢀZKHQꢀWKHꢀV\VWHPꢀUHDGVꢀDWꢀDGGUHVVHVꢀZLWKLQꢀWKRVHꢀVHFWRUVꢀWKDWꢀKDYHꢀ
EHHQꢀVHOHFWHGꢀIRUꢀHUDVXUHꢃꢀ%XWꢀ'4ꢎꢀFDQQRWꢀGLVWLQJXLVKꢀZKHWKHUꢀWKHꢀVHFWRUꢀLVꢀDFꢅ
WLYHO\ꢀHUDVLQJꢀRUꢀLVꢀHUDVHꢅVXVSHQGHGꢃꢀ'4ꢉꢄꢀE\ꢀFRPSDULVRQꢄꢀLQGLFDWHVꢀZKHWKHUꢀWKHꢀ
GHYLFHꢀLVꢀDFWLYHO\ꢀHUDVLQJꢄꢀRUꢀLVꢀLQꢀ(UDVHꢀ6XVSHQGꢄꢀEXWꢀFDQQRWꢀGLVWLQJXLVKꢀZKLFKꢀ
VHFWRUVꢀDUHꢀVHOHFWHGꢀIRUꢀHUDVXUHꢃꢀ7KXVꢄꢀERWKꢀVWDWXVꢀELWVꢀDUHꢀUHTXLUHGꢀIRUꢀVHFWRUꢀDQGꢀ
PRGHꢀLQIRUPDWLRQꢃꢀ5HIHUꢀWRꢀ7DEOHꢀꢈꢌꢄꢀ³'4ꢉꢀDQGꢀ'4ꢎꢀ,QGLFDWLRQVꢄ´ꢀRQꢀSDJHꢀꢇꢑꢀWRꢀ
FRPSDUHꢀRXWSXWVꢀIRUꢀ'4ꢎꢀDQGꢀ'4ꢉꢃꢀ
6HHꢀWKHꢀIROORZLQJꢀIRUꢀDGGLWLRQDOꢀLQIRUPDWLRQꢆꢀ)LJXUHꢀꢋꢄꢀ³7RJJOHꢀ%LWꢀ$OJRULWKPꢄ´ꢀRQꢀ
SDJHꢀꢇꢎꢄꢀ³'4ꢉꢆꢀ7RJJOHꢀ%LWꢀ,´ꢀRQꢀSDJHꢀꢇꢈꢄꢀ)LJXUHꢀꢎꢌꢄꢀ³7RJJOHꢀ%LWꢀ7LPLQJVꢀ
ꢁ'XULQJꢀ(PEHGGHGꢀ$OJRULWKPꢂꢄ´ꢀRQꢀSDJHꢀꢈꢍꢏꢄꢀDQGꢀ7DEOHꢀꢈꢌꢄꢀ³'4ꢉꢀDQGꢀ'4ꢎꢀ,QGLꢅ
FDWLRQVꢄ´ꢀRQꢀSDJHꢀꢇꢑꢃꢀ
Table 19. DQ6 and DQ2 Indications
,IꢀGHYLFHꢀLV
DQGꢀWKHꢀV\VWHPꢀUHDGV
WKHQꢀ'4ꢉ
DQGꢀ'4ꢐ
SURJUDPPLQJꢄ
DWꢀDQ\ꢀDGGUHVVꢄ
WRJJOHVꢄ
GRHVꢀQRWꢀWRJJOHꢃ
DWꢀDQꢀDGGUHVVꢀZLWKLQꢀDꢀVHFWRUꢀ
VHOHFWHGꢀIRUꢀHUDVXUHꢄ
WRJJOHVꢄ
WRJJOHVꢄ
DOVRꢀWRJJOHVꢃ
GRHVꢀQRWꢀWRJJOHꢃ
WRJJOHVꢃ
DFWLYHO\ꢀHUDVLQJꢄ
HUDVHꢀVXVSHQGHGꢄ
DWꢀDQꢀDGGUHVVꢀZLWKLQꢀVHFWRUVꢀQRWꢀ
VHOHFWHGꢀIRUꢀHUDVXUHꢄ
DWꢀDQꢀDGGUHVVꢀZLWKLQꢀDꢀVHFWRUꢀ
VHOHFWHGꢀIRUꢀHUDVXUHꢄ
GRHVꢀQRWꢀWRJJOHꢄ
UHWXUQVꢀDUUD\ꢀGDWDꢄ
WRJJOHVꢄ
DWꢀDQꢀDGGUHVVꢀZLWKLQꢀVHFWRUVꢀQRWꢀ
UHWXUQVꢀDUUD\ꢀGDWDꢃꢀ7KHꢀV\VWHPꢀFDQꢀUHDGꢀ
IURPꢀDQ\ꢀVHFWRUꢀQRWꢀVHOHFWHGꢀIRUꢀHUDVXUHꢃ
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Reading Toggle Bits DQ6/DQ2
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LVꢀWRJJOLQJꢀDQGꢀ'4ꢏꢀKDVꢀQRWꢀJRQHꢀKLJKꢃꢀ7KHꢀV\VWHPꢀPD\ꢀFRQWLQXHꢀWRꢀPRQLWRUꢀWKHꢀ
WRJJOHꢀELWꢀDQGꢀ'4ꢏꢀWKURXJKꢀVXFFHVVLYHꢀUHDGꢀF\FOHVꢄꢀGHWHUPLQLQJꢀWKHꢀVWDWXVꢀDVꢀGHꢅ
VFULEHGꢀLQꢀWKHꢀSUHYLRXVꢀSDUDJUDSKꢃꢀ$OWHUQDWLYHO\ꢄꢀLWꢀPD\ꢀFKRRVHꢀWRꢀSHUIRUPꢀRWKHUꢀ
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
83
P r e l i m i n a r y
V\VWHPꢀWDVNVꢃꢀ,QꢀWKLVꢀFDVHꢄꢀWKHꢀV\VWHPꢀPXVWꢀVWDUWꢀDWꢀWKHꢀEHJLQQLQJꢀRIꢀWKHꢀDOJRꢅ
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DQ5: Exceeded Timing Limits
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84
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Table 20. Write Operation Status
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Absolute Maximum Ratings
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9&&ꢀꢁ1RWHꢀꢈꢂ ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ ±ꢍꢃꢏꢀ9ꢀWRꢀꢐꢎꢃꢏꢀ9
9
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66
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S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Switching Waveforms
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AC Characteristics
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
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S71WS-J Based MCPs
91
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ꢅꢁ 7KHꢃGHYLFHꢃLVꢃLQꢃV\QFKURQRXVꢃPRGHꢁ
Figure 14. CLK Synchronous Burst Mode Read (rising active CLK)
tCEZ
4 cycles for initial access shown.
tCES
CE#
1
2
3
4
5
CLK
tAVC
AVD#
tAVD
tACS
tBDH
Aa
Addresses
Data
tBACC
tACH
Hi-Z
tIACC
Da
Da + 1
Da + n
tACC
tOEZ
OE#
RDY
tRACC
tOE
tCR
Hi-Z
Hi-Z
tRDYS
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Figure 15. CLK Synchronous Burst Mode Read (Falling Active Clock)
92
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
AC Characteristics
tCEZ
7 cycles for initial access shown.
tCAS
CE#
CLK
1
2
3
4
5
6
7
tAVC
AVD#
tAVD
tAAS
Addresses
Data
Aa
tBACC
tAAH
Hi-Z
tIACC
Da
Da + 1
Da + n
tACC
tBDH
tOEZ
OE#
RDY
tRACC
tCR
tOE
Hi-Z
Hi-Z
tRDYS
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Figure 16. Synchronous Burst Mode Read
7 cycles for initial access shown.
tCES
CE#
1
2
3
4
5
6
7
CLK
tAVC
AVD#
tAVD
tACS
AC
Addresses
Data
tBACC
tACH
tIACC
DC
DD
DE
DF
D8
DB
tBDH
OE#
RDY
tCR
tRACC
tOE
tRACC
Hi-Z
tRDYS
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Figure 17. 8-word Linear Burst with Wrap Around
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
93
P r e l i m i n a r y
AC Characteristics
tCEZ
6 wait cycles for initial access shown.
tCES
CE#
1
2
3
4
5
6
CLK
tAVC
AVD#
tAVD
tACS
Aa
Addresses
Data
tBACC
tACH
Hi-Z
tIACC
Da
Da+1
Da+2
Da+3
Da + n
tBDH
tOEZ
tRACC
OE#
RDY
tCR
tOE
Hi-Z
Hi-Z
tRDYS
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Figure 18. Linear Burst with RDY Set One Cycle Before Data
94
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
AC Characteristics
Asynchronous Mode Read @ VIO = 1.8 V
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
95
P r e l i m i n a r y
AC Characteristics
CE#
tOE
OE#
tOEH
WE#
Data
tCE
tOEZ
Valid RD
tACC
RA
Addresses
AVD#
tAAVDH
tCAS
tAVDP
tAAVDS
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CE#
OE#
tOE
tOEH
WE#
Data
tCE
tOEZ
Valid RD
tACC
RA
Addresses
AVD#
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Figure 20. Asynchronous Mode Read
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S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
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Hardware Reset (RESET#)
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tRH
RESET#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
CE#, OE#
tReady
RESET#
tRP
ꢃ
Figure 21. Reset Timings
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
97
P r e l i m i n a r y
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S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
AC Characteristics
Program Command Sequence (last two cycles)
Read Status Data
V
IH
CLK
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IL
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AVD#
tAH
tAS
PA
VA
VA
Addresses
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Figure 22. Asynchronous Program Operation Timings: AVD# Latched Addresses
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
99
P r e l i m i n a r y
AC Characteristics
Program Command Sequence (last two cycles)
Read Status Data
CLK
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Addresses
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Figure 23. Asynchronous Program Operation Timings: WE# Latched Addresses
100
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
AC Characteristics
Program Command Sequence (last two cycles)
tAVCH
Read Status Data
CLK
tACS
tCSW
AVD#
tAVDP
Addresses
555h
PA
VA
VA
In
Data
tCAS
Complete
A0h
PD
tDS
tDH
Progress
tAVSW
CE#
tCH
OE#
tAH
tWP
WE#
tWHWH1
tWPH
tWC
tVCS
VCC
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Figure 24. Synchronous Program Operation Timings: WE# Latched Addresses
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
101
P r e l i m i n a r y
AC Characteristics
Program Command Sequence (last two cycles)
tAVCH
Read Status Data
CLK
tAS
tAH
tAVSC
AVD#
tAVDP
Addresses
555h
PA
VA
VA
In
Data
Complete
A0h
PD
tDS
tDH
Progress
tCAS
CE#
tCH
OE#
WE#
tCSW
tWP
tWHWH1
tWPH
tWC
tVCS
VCC
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Figure 25. Synchronous Program Operation Timings: CLK Latched Addresses
102
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
AC Characteristics
Erase Command Sequence (last two cycles)
Read Status Data
V
IH
CLK
V
IL
tAVDP
AVD#
tAH
tAS
SA
555h for
chip erase
VA
VA
Addresses
Data
2AAh
10h for
chip erase
In
Complete
55h
30h
Progress
tDS
tDH
CE#
tCH
OE#
WE#
tWP
tWHWH2
tCS
tWPH
tWC
tVCS
VCC
Figure 26. Chip/Sector Erase Command Sequence
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
103
P r e l i m i n a r y
AC Characteristics
CE#
AVD#
WE#
Addresses
Data
PA
Don't Care
A0h
Don't Care
PD
Don't Care
OE#
tVIDS
1 μs
V
V
ID
ACC
tVID
or V
IL
IH
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Figure 27. Accelerated Unlock Bypass Programming Timing
104
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
AC Characteristics
AVD#
tCEZ
tCE
CE#
tOEZ
tCH
tOE
OE#
tOEH
WE#
tACC
VA
Addresses
VA
Status Data
Status Data
Data
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Figure 28. Data# Polling Timings (During Embedded Algorithm)
AVD#
tCEZ
tCE
CE#
tOEZ
tCH
tOE
OE#
WE#
tOEH
tACC
Addresses
Data
VA
VA
Status Data
Status Data
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Figure 29. Toggle Bit Timings (During Embedded Algorithm)
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
105
P r e l i m i n a r y
AC Characteristics
CE#
CLK
AVD#
Addresses
OE#
VA
VA
tIACC
tIACC
Data
Status Data
Status Data
RDY
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Figure 30. Synchronous Data Polling Timings/Toggle Bit Timings
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Figure 31. DQ2 vs. DQ6
106
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
AC Characteristics
Temporary Sector Unprotect
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V
V
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VID
VID
RESET#
VIL or VIH
VIL or VIH
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
RDY
tRRB
tRSP
ꢃ
Figure 32. Temporary Sector Unprotect Timing Diagram
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
107
P r e l i m i n a r y
AC Characteristics
VID
VIH
RESET#
SA, A6,
A1, A0
Valid*
Sector Protect/Unprotect
60h 60h
Valid*
Valid*
Status
Verify
40h
Data
Sector Protect: 150 µs
Sector Unprotect: 1.5 ms
1 µs
CE#
WE#
OE#
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Figure 33. Sector/Sector Block Protect and Unprotect Timing Diagram
108
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
AC Characteristics
Address boundary occurs every 64 words, beginning at address
00003Fh: 00007Fh, 0000BFh, etc. Address 000000h is also a boundary crossing.
C60
C61
3D
C62
3E
C63
3F
C63
3F
C63
3F
C64
40
C65
41
C66
42
C67
43
CLK
3C
Address (hex)
(stays high)
AVD#
RDY
RDY
tRACC
tRACC
(Note 1)
(Note 2)
latency
tRACC
tRACC
latency
Data
D60
D61
D62
D63
D64
D65
D66
D67
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Figure 34. Latency with Boundary Crossing
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
109
P r e l i m i n a r y
AC Characteristics
Address boundary occurs every 64 words, beginning at address
00003Fh: 00007Fh, 0000BFh, etc. Address 000000h is also a boundary crossing.
C60
C61
3D
C62
3E
C63
3F
C63
3F
C63
3F
C64
40
CLK
3C
Address (hex)
(stays high)
AVD#
RDY
RDY
tRACC
tRACC
(Note 1)
(Note 2)
latency
tRACC
tRACC
latency
Data
Invalid
D60
D61
D62
D63
Read Status
OE#,
CE#
(stays low)
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Figure 35. Latency with Boundary Crossing into Program/Erase Bank
110
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
AC Characteristics
Data
D0
D1
Rising edge of next clock cycle
following last wait state triggers
next burst data
AVD#
OE#
total number of clock cycles
following addresses being latched
1
2
0
3
1
4
5
6
4
7
5
CLK
2
3
number of clock cycles
programmed
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A14, A13, A12 = “111” ⇒ Reserved
A14, A13, A12 = “110” ⇒ Reserved
A14, A13, A12 = “101” ⇒ 5 programmed, 7 total
A14, A13, A12 = “100” ⇒ 4 programmed, 6 total
A14, A13, A12 = “011” ⇒ 3 programmed, 5 total
A14, A13, A12 = “010” ⇒ 2 programmed, 4 total
A14, A13, A12 = “001” ⇒ 1 programmed, 3 total
A14, A13, A12 = “000” ⇒ 0 programmed, 2 total
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Figure 36. Example of Wait States Insertion
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
111
P r e l i m i n a r y
AC Characteristics
Last Cycle in
Program or
Sector Erase
Read status (at least two cycles) in same bank
and/or array data from other bank
Begin another
write or program
command sequence
Command Sequence
tWC
tRC
tRC
tWC
CE#
OE#
tOE
tOEH
tGHWL
WE#
Data
tWPH
tOEZ
tWP
tDS
tACC
tOEH
tDH
PD/30h
RD
RD
AAh
tSR/W
RA
Addresses
AVD#
PA/SA
tAS
RA
555h
tAH
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Figure 37. Back-to-Back Read/Write Cycle Timings
112
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Erase and Programming Performance
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S71WS-J Based MCPs
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P r e l i m i n a r y
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S71WS-J Based MCPs
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Functional Description
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S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
State Diagrams
Initial/Standby State
Asynchronous Operation
(Page Mode)
Power Up
Synchronous Operation
(Burst Mode)
Common State
CR Set
Pause Time
Power
Down
Power
Down
@M=1
@M=0
CE2=L
CE2=L
CE2=H
CE2=H
@RP=1
Standby
Standby
(64M Only)
CE2=H
@RP=0
Figure 38. Initial Standby State Diagram
Asynchronous Operation State
CE2=CE1# = H
Standby
CE1# = L
CE1# = H
CE1# = L &
WE# = L
CE1# = L &
OE# =
L
CE1#= H
Output
CE1# = H
Disable
WE# = H
OE# =
H
L
OE# =
WE# = L
Address Change
or Byte Control
Write
Read
Byte Control
Byte Control @OE# = L
Figure 39. Asynchronous Operation State Diagram
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
117
P r e l i m i n a r y
Synchronous Operation State
CE2 = CE1# = H
Standby
CE1# = H
CE1# = H
CE1# = H
CE1# = H
Write
Read
Suspend
Suspend
OE# = H
WE# = H
CE1# = L
CE1# = L
OE# = L
ADV# Low Pulse
& WE# = L
ADV# Low Pulse
& OE# = L
WE# = L
Write
Read
ADV# Low Pulse
ADV# Low Pulse
ADV# Low Pulse
(@BL = 8 or 16, and after burst
operation is completed)
Figure 40. Synchronous Operation Diagram
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S71WS-J_04_A2 August 19, 2005
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
121
P r e l i m i n a r y
CLK
ADDRESS
Valid
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WE#
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Figure 41. Burst Read Operation
CLK
ADDRESS
Valid
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OE#
WE#
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D1
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BL
WAIT#
Figure 42. Burst Write Operation
CLK Input Function
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122
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
ADV# Input Function
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$'9ꢓꢀ/RZꢀSXOVHꢀLVꢀPDQGDWRU\ꢀIRUꢀV\QFKURQRXVꢀEXUVWꢀUHDGꢒZULWHꢀRSHUDWLRQꢀPRGHꢀ
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WAIT# Output Function
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WLRQꢀIURPꢀ2(ꢓ /ꢀRUꢀ&(ꢈꢓ /ꢀZKLFKHYHUꢀRFFXUVꢀODVWꢃꢀ:$,7ꢓꢀRXWSXWꢀ/RZꢀLQGLFDWHVꢀ
GDWDꢀRXWꢀDWꢀQH[WꢀFORFNꢀF\FOHꢀLVꢀLQYDOLGꢄꢀDQGꢀ:$,7ꢓꢀRXWSXWꢀEHFRPHVꢀ+LJKꢀRQHꢀFORFNꢀ
F\FOHꢀSULRUꢀWRꢀYDOLGꢀGDWDꢀRXWꢃꢀ'XULQJꢀ2(ꢓꢀUHDGꢀVXVSHQGꢄꢀ:$,7ꢓꢀRXWSXWꢀGRHVQ¶Wꢀ
LQGLFDWHꢀGDWDꢀEXVꢀVWDWXVꢀEXWꢀFDUULHVꢀWKHꢀVDPHꢀOHYHOꢀIURPꢀSUHYLRXVꢀFORFNꢀF\FOHꢀꢁNHSWꢀ
+LJKꢂꢀH[FHSWꢀIRUꢀUHDGꢀVXVSHQGꢀRQꢀWKHꢀILQDOꢀGDWDꢀRXWSXWꢃꢀ,IꢀILQDOꢀUHDGꢀGDWDꢀRXWꢀLVꢀ
VXVSHQGHGꢄꢀ:$,7ꢓꢀRXWSXWꢀEHFRPHꢀKLJKꢀLPSHGDQFHꢀDIWHUꢀVSHFLILHGꢀWLPHꢀGXUDWLRQꢀ
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,QꢀFDVHꢀRIꢀFRQWLQXRXVꢀEXUVWꢀUHDGꢀRSHUDWLRQꢀRIꢀꢑꢎ0ꢄꢀDQꢀDGGLWLRQDOꢀRXWSXWꢀGHOD\ꢀPD\ꢀ
RFFXUꢀZKHQꢀDꢀEXUVWꢀVHTXHQFHꢀFURVVHVꢀLW¶VꢀGHYLFHꢅURZꢀERXQGDU\ꢃꢀ7KHꢀ:$,7ꢓꢀRXWꢅ
SXWꢀLQGLFDWHVꢀWKLVꢀGHOD\ꢃꢀ5HIHUꢀWRꢀWKHꢀꢗ%XUVWꢀ/HQJWKꢗꢀVHFWLRQꢀIRUꢀWKHꢀDGGLWLRQDOꢀ
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IRUꢀHQWLUHꢀZULWHꢀF\FOHVꢀLQFOXGLQJꢀ:(ꢓꢀZULWHꢀVXVSHQGꢃꢀ7KHꢀDFWXDOꢀZULWHꢀGDWDꢀODWFKꢅ
LQJꢀVWDUWVꢀRQꢀWKHꢀDSSURSULDWHꢀFORFNꢀHGJHꢀZLWKꢀUHVSHFWꢀWRꢀ9DOLGꢀ&ORFNꢀ(GJHꢄꢀ5HDGꢀ
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SHQGHGꢄꢀ:$,7ꢓꢀRXWSXWꢀEHFRPHꢀKLJKꢀLPSHGDQFHꢀDIWHUꢀVSHFLILHGꢀWLPHꢀGXUDWLRQꢀ
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7KHꢀEXUVWꢀZULWHꢀRSHUDWLRQꢀRIꢀꢑꢎ0ꢀDQGꢀWKHꢀERWKꢀEXUVWꢀUHDGꢒZULWHꢀRSHUDWLRQꢀRIꢀꢉꢊ0ꢀ
DUHꢀDOZD\VꢀVWDUWHGꢀDIWHUꢀIL[HGꢀODWHQF\ꢀZLWKꢀUHVSHFWꢀWRꢀ5HDGꢀ/DWHQF\ꢀVHWꢀLQꢀ&5ꢃꢀ
:KHQꢀWKHꢀGHYLFHꢀLVꢀRSHUDWLQJꢀLQꢀDV\QFKURQRXVꢀPRGHꢄꢀ:$,7ꢓꢀRXWSXWꢀLVꢀDOZD\VꢀLQꢀ
+LJKꢀ,PSHGDQFHꢃ
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
123
P r e l i m i n a r y
Latency
5HDGꢀ/DWHQF\ꢀꢁ5/ꢂꢀLVꢀWKHꢀQXPEHUꢀRIꢀFORFNꢀF\FOHVꢀEHWZHHQꢀWKHꢀDGGUHVVꢀEHLQJꢀ
ODWFKHGꢀDQGꢀILUVWꢀUHDGꢀGDWDꢀEHFRPLQJꢀDYDLODEOHꢀGXULQJꢀV\QFKURQRXVꢀEXUVWꢀUHDGꢀRSꢅ
HUDWLRQꢃꢀ,WꢀLVꢀVHWꢀWKURXJKꢀ&5ꢀ6HWꢀVHTXHQFHꢀDIWHUꢀSRZHUꢅXSꢃꢀ2QFHꢀVSHFLILFꢀ5/ꢀLVꢀVHWꢀ
WKURXJKꢀ&5ꢀ6HWꢀVHTXHQFHꢄꢀZULWHꢀODWHQF\ꢄꢀWKDWꢀLVꢀWKHꢀQXPEHUꢀRIꢀFORFNꢀF\FOHVꢀEHꢅ
WZHHQꢀDGGUHVVꢀEHLQJꢀODWFKHGꢀDQGꢀILUVWꢀZULWHꢀGDWDꢀEHLQJꢀODWFKHGꢄꢀLVꢀDXWRPDWLFDOO\ꢀ
VHWꢀWRꢀ5/ꢅꢈꢃ7KHꢀEXUVWꢀRSHUDWLRQꢀLVꢀDOZD\VꢀVWDUWHGꢀDIWHUꢀIL[HGꢀODWHQF\ꢀZLWKꢀUHVSHFWꢀ
WRꢀ5HDGꢀ/DWHQF\ꢀVHWꢀLQꢀ&5ꢃꢀ5/ ꢉꢀLVꢀDYDLODEOHꢀRQO\ꢀIRUꢀꢉꢊ0ꢃ
CLK
0
3
4
5
6
1
2
ADDRESS
ADV#
Valid
CE1#
OE# or WE#
RL=3
DQ [Out]
WAIT#
Q1
Q2
Q3
Q4
Q5
D5
High-Z
DQ [In]
WAIT#
D1
D2
D3
D4
D5
High-Z
RL=4
DQ [Out]
WAIT#
Q1
D2
Q2
D3
Q3
D4
Q4
D5
High-Z
DQ [In]
WAIT#
D1
High-Z
RL=5
DQ [Out]
WAIT#
Q1
D2
Q2
D3
Q3
D4
High-Z
DQ [In]
WAIT#
D1
High-Z
RL=6
DQ [Out]
WAIT#
Q1
D2
Q2
D3
High-Z
DQ [In]
WAIT#
D1
High-Z
Figure 43. Read Latency Diagram
124
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Address Latch by ADV#
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QRXVꢀEXUVWꢀUHDGꢒZULWHꢀRSHUDWLRQꢀPRGHꢄꢀDOOꢀWKHꢀDGGUHVVꢀDUHꢀGHWHUPLQHGꢀRQꢀWKHꢀ
SRVLWLYHꢀHGJHꢀRIꢀ$'9ꢓꢀZKHQꢀ&(ꢈꢓ /ꢃꢀ7KHꢀVSHFLILHGꢀPLQLPXPꢀYDOXHꢀRIꢀ$'9ꢓ /ꢀ
VHWXSꢀWLPHꢀDQGꢀKROGꢀWLPHꢀDJDLQVWꢀYDOLGꢀHGJHꢀRIꢀFORFNꢀZKHUHꢀ5/ꢀFRXQWꢀEHJLQꢀPXVWꢀ
EHꢀVDWLVILHGꢀIRUꢀDSSURSULDWHꢀ5/ꢀFRXQWVꢃꢀ9DOLGꢀDGGUHVVꢀPXVWꢀEHꢀGHWHUPLQHGꢀZLWKꢀ
VSHFLILHGꢀVHWXSꢀWLPHꢀDJDLQVWꢀHLWKHUꢀWKHꢀQHJDWLYHꢀHGJHꢀRIꢀ$'9ꢓꢀRUꢀQHJDWLYHꢀHGJHꢀ
RIꢀ&(ꢈꢓꢀZKLFKHYHUꢀFRPHVꢀODWHꢃꢀ$QGꢀWKHꢀGHWHUPLQHGꢀYDOLGꢀDGGUHVVꢀPXVWꢀQRWꢀEHꢀ
FKDQJHGꢀGXULQJꢀ$'9ꢓ /ꢀSHULRGꢃ
Burst Length
%XUVWꢀ/HQJWKꢀLVꢀWKHꢀQXPEHUꢀRIꢀZRUGꢀWRꢀEHꢀUHDGꢀRUꢀZULWHꢀGXULQJꢀV\QFKURQRXVꢀEXUVWꢀ
UHDGꢒZULWHꢀRSHUDWLRQꢀDVꢀWKHꢀUHVXOWꢀRIꢀDꢀVLQJOHꢀDGGUHVVꢀODWFKꢀF\FOHꢃꢀ,WꢀFDQꢀEHꢀVHWꢀRQꢀ
ꢇꢄꢀꢈꢉꢀZRUGVꢀERXQGDU\ꢀRUꢀFRQWLQXRXVꢀIRUꢀHQWLUHꢀDGGUHVVꢀWKURXJKꢀ&5ꢀ6HWꢀVHTXHQFHꢃꢀ
7KHꢀEXUVWꢀW\SHꢀLVꢀVHTXHQWLDOꢀWKDWꢀLVꢀLQFUHPHQWDOꢀGHFRGLQJꢀVFKHPHꢀZLWKLQꢀDꢀERXQGꢅ
DU\ꢀDGGUHVVꢃꢀ6WDUWLQJꢀIURPꢀLQLWLDOꢀDGGUHVVꢀEHLQJꢀODWFKHGꢄꢀGHYLFHꢀLQWHUQDOꢀDGGUHVVꢀ
FRXQWHUꢀDVVLJQꢀꢐꢈꢀWRꢀWKHꢀSUHYLRXVꢀDGGUHVVꢀXQWLOꢀUHDFKLQJꢀWKHꢀHQGꢀRIꢀERXQGDU\ꢀDGꢅ
GUHVVꢀDQGꢀWKHQꢀZUDSꢀURXQGꢀWRꢀOHDVWꢀVLJQLILFDQWꢀDGGUHVVꢀꢁ ꢍꢂꢃꢀ$IWHUꢀFRPSOHWLQJꢀ
UHDGꢀGDWDꢀRXWꢀRUꢀZULWHꢀGDWDꢀODWFKꢀIRUꢀWKHꢀVHWꢀEXUVWꢀOHQJWKꢄꢀRSHUDWLRQꢀDXWRPDWLFDOO\ꢀ
HQGHGꢀH[FHSWꢀIRUꢀFRQWLQXRXVꢀEXUVWꢀOHQJWKꢃꢀ:KHQꢀFRQWLQXRXVꢀEXUVWꢀOHQJWKꢀLVꢀVHWꢄꢀ
UHDGꢒZULWHꢀLVꢀHQGOHVVꢀXQOHVVꢀLWꢀLVꢀWHUPLQDWHGꢀE\ꢀWKHꢀSRVLWLYHꢀHGJHꢀRIꢀ&(ꢈꢓꢃ
'XULQJꢀFRQWLQXRXVꢀEXUVWꢀUHDGꢀRIꢀꢑꢎ0ꢄꢀDQꢀDGGLWLRQDOꢀRXWSXWꢀGHOD\ꢀPD\ꢀRFFXUꢀZKHQꢀ
DꢀEXUVWꢀVHTXHQFHꢀFURVVꢀLW¶VꢀGHYLFHꢅURZꢀERXQGDU\ꢃꢀ7KLVꢀLVꢀWKHꢀFDVHꢀZKHQꢀ$ꢍꢀWRꢀ$ꢉꢀ
RIꢀVWDUWLQJꢀDGGUHVVꢀLVꢀHLWKHUꢀꢋ'Kꢄꢀꢋ(KꢄꢀRUꢀꢋ)KꢀDVꢀVKRZQꢀLQꢀWKHꢀIROORZLQJꢀWDEOHꢃꢀ7KHꢀ
:$,7ꢓꢀVLJQDOꢀLQGLFDWHVꢀWKLVꢀGHOD\ꢃꢀ7KHꢀꢉꢊ0ꢀGHYLFHꢀKDVꢀQRꢀDGGLWLRQDOꢀRXWSXWꢀGHOD\ꢃ
Read Address Sequence
Start Address
(A6-A0)
ꢍꢍK
ꢍꢈK
ꢍꢎK
ꢍꢑK
ꢃꢃꢃ
BL = 8
BL = 16
Continuous
ꢍꢍꢅꢍꢈꢅꢍꢎꢅꢍꢑꢅꢍꢊꢅꢃꢃꢃ
ꢍꢈꢅꢍꢎꢅꢍꢑꢅꢍꢊꢅꢍꢏꢅꢃꢃꢃ
ꢍꢎꢅꢍꢑꢅꢍꢊꢅꢍꢏꢅꢍꢉꢅꢃꢃꢃ
ꢍꢑꢅꢍꢊꢅꢍꢏꢅꢍꢉꢅꢍꢋꢅꢃꢃꢃ
ꢃꢃꢃ
ꢍꢍꢅꢍꢈꢅꢍꢎꢅꢃꢃꢃꢅꢍꢉꢅꢍꢋ
ꢍꢈꢅꢍꢎꢅꢍꢑꢅꢃꢃꢃꢅꢍꢋꢅꢍꢍ
ꢍꢎꢅꢍꢑꢅꢃꢃꢃꢅꢍꢋꢅꢍꢍꢅꢍꢈ
ꢍꢑꢅꢃꢃꢃꢅꢍꢋꢅꢍꢍꢅꢍꢈꢅꢍꢎ
ꢃꢃꢃ
ꢍꢍꢅꢍꢈꢅꢍꢎꢅꢃꢃꢃꢅꢍ(ꢅꢍ)
ꢍꢈꢅꢍꢎꢅꢍꢑꢅꢃꢃꢃꢅꢍ)ꢅꢍꢍ
ꢍꢎꢅꢍꢑꢅꢃꢃꢃꢅꢍ)ꢅꢍꢍꢅꢍꢈ
ꢍꢑꢅꢃꢃꢃꢅꢍ)ꢅꢍꢍꢅꢍꢈꢅꢍꢎ
ꢃꢃꢃ
ꢋ&K
ꢋ'K
ꢋ(K
ꢋ)K
ꢋ&ꢅꢃꢃꢃꢅꢋ)ꢅꢋꢇꢅꢃꢃꢃꢅꢋ%
ꢋ'ꢅꢋ(ꢅꢋ)ꢅꢋꢇꢅꢃꢃꢃꢅꢋ&
ꢋ(ꢅꢋ)ꢅꢋꢇꢅꢋꢌꢅꢃꢃꢃꢅꢋ'
ꢋ)ꢅꢋꢇꢅꢋꢌꢅꢋ$ꢅꢃꢃꢃꢅꢋ(
ꢋ&ꢅꢃꢃꢃꢅꢋ)ꢅꢋꢍꢅꢃꢃꢃꢅꢋ%
ꢋ'ꢅꢋ(ꢅꢋ)ꢅꢋꢍꢅꢃꢃꢃꢅꢋ&
ꢋ(ꢅꢋ)ꢅꢋꢍꢅꢋꢈꢅꢃꢃꢃꢅꢋ'
ꢋ)ꢅꢋꢍꢅꢋꢈꢅꢋꢎꢅꢃꢃꢃꢅꢋ(
ꢋ&ꢅꢋ'ꢅꢋ(ꢅꢋ)ꢅꢇꢍꢅꢇꢈꢅꢃꢃꢃ
ꢋ'ꢅꢋ(ꢅꢋ)ꢅ:$,7ꢅꢇꢍꢅꢇꢈꢅꢃꢃꢃ
ꢋ(ꢅꢋ)ꢅ:$,7ꢅ:$,7ꢅꢇꢍꢅꢇꢈꢅꢃꢃꢃ
ꢋ)ꢅ:$,7 :$,7
ꢅ
ꢅ:$,7ꢅꢇꢍꢅꢇꢈ
1RWHꢀꢃ5HDGꢃDGGUHVVꢃLQꢃ+H[DGHFLPDOꢁ
Single Write
6LQJOHꢀ:ULWHꢀLVꢀV\QFKURQRXVꢀZULWHꢀRSHUDWLRQꢀZLWKꢀ%XUVWꢀ/HQJWKꢀ ꢈꢃꢀ7KHꢀGHYLFHꢀFDQꢀ
EHꢀFRQILJXUHGꢀHLWKHUꢀWRꢀ³%XUVWꢀ5HDGꢀꢔꢀ6LQJOHꢀ:ULWH´ꢀRUꢀWRꢀ³%XUVWꢀ5HDGꢀꢔꢀ%XUVWꢀ
:ULWH´ꢀWKURXJKꢀ&5ꢀVHWꢀVHTXHQFHꢃꢀ2QFHꢀWKHꢀGHYLFHꢀLVꢀFRQILJXUHGꢀWRꢀ³%XUVWꢀ5HDGꢀꢔꢀ
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
125
P r e l i m i n a r y
Write Control
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³:(ꢓꢀ6LQJOHꢀ&ORFNꢀ3XOVHꢀ&RQWURO´ꢄꢀIRUꢀV\QFKURQRXVꢀZULWHꢀRSHUDWLRQꢃꢀ,WꢀLVꢀFRQILJꢅ
XUHGꢀWKURXJKꢀ&5ꢀVHWꢀVHTXHQFHꢃ
CLK
0
3
4
5
6
1
2
ADDRESS
Valid
ADV#
CE1#
RL=5
WE# Level Control
WE#
tWLD
DQ [In]
WAIT#
D1
D2
D3
D4
tWLTH
High-Z
WE# Single Clock Pulse Control
tWSCK
WE#
tCKWH
DQ [In]
D1
D2
D3
D4
tCLTH
tWLTH
WAIT#
High-Z
Figure 44. Write Controls
Burst Read Suspend
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HUDWLRQꢄꢀ2(ꢓꢀEURXJKWꢀWRꢀ+LJKꢀVXVSHQGVꢀEXUVWꢀUHDGꢀRSHUDWLRQꢃꢀ2QFHꢀ2(ꢓꢀLVꢀ
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VXVSHQGHGꢄꢀWKHꢀGHYLFHꢀLQWHUQDOꢀFRXQWHUꢀLVꢀVXVSHQGHGꢄꢀDQGꢀWKHꢀGDWDꢀRXWSXWꢀEHꢅ
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GDWDꢀRXWSXWꢀEHFRPHꢀYDOLGꢀDIWHUꢀVSHFLILHGꢀWLPHꢀGXUDWLRQꢄꢀDQGꢀLQWHUQDOꢀDGGUHVVꢀ
FRXQWHUꢀLVꢀUHDFWLYDWHGꢃꢀ7KHꢀODVWꢀGDWDꢀRXWꢀEHLQJꢀVXVSHQGHGꢀDVꢀWKHꢀUHVXOWꢀRIꢀ2(ꢓ +ꢀ
DQGꢀILUVWꢀGDWDꢀRXWꢀDVꢀWKHꢀUHVXOWꢀRIꢀ2(ꢓ /ꢀDUHꢀIURPꢀWKHꢀVDPHꢀDGGUHVVꢃꢀ
,QꢀRUGHUꢀWRꢀJXDUDQWHHꢀWRꢀRXWSXWꢀODVWꢀGDWDꢀEHIRUHꢀVXVSHQVLRQꢀDQGꢀILUVWꢀGDWDꢀDIWHUꢀ
UHVXPSWLRQꢄꢀWKHꢀVSHFLILHGꢀPLQLPXPꢀYDOXHꢀRIꢀ2(ꢓ /ꢀKROGꢀWLPHꢀDQGꢀVHWXSꢀWLPHꢀ
DJDLQVWꢀFORFNꢀHGJHꢀPXVWꢀEHꢀVDWLVILHGꢀUHVSHFWLYHO\ꢃ
126
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
CLK
OE#
tCKOH tOSCK
tCKOH tOSCK
tAC
tOHZ
Q2
tAC
tAC
Q2
tAC
Q3
Q1
DQ
Q4
tCKQX
tOLZ
tCKQX
tCKQX
tCKTV
WAIT#
Figure 45. Burst Read Suspend Diagram
Burst Write Suspend
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RSHUDWLRQꢄꢀ:(ꢓꢀEURXJKWꢀWRꢀ+LJKꢀVXVSHQGVꢀEXUVWꢀZULWHꢀRSHUDWLRQꢃꢀ2QFHꢀ:(ꢓꢀLVꢀ
EURXJKWꢀWRꢀ+LJKꢀZLWKꢀWKHꢀVSHFLILHGꢀVHWꢀXSꢀWLPHꢀDJDLQVWꢀFORFNꢀZKHUHꢀWKHꢀGDWDꢀEHLQJꢀ
VXVSHQGHGꢄꢀGHYLFHꢀLQWHUQDOꢀFRXQWHUꢀLVꢀVXVSHQGHGꢄꢀGDWDꢀLQSXWꢀLVꢀLJQRUHGꢃꢀ,WꢀLVꢀLQꢅ
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ZULWHꢀRQO\ꢃ
CLK
tCKWH tWSCK
tCKWH tWSCK
WE#
tDSCK
tDSCK
tDSCK
tDSCK
DQ
D1
D2
D2
D3
D4
tDHCK
tDHCK
tDHCK
High
Figure 46. Burst Write Suspend Diagram
WAIT#
Burst Read Termination
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
127
P r e l i m i n a r y
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,QꢀRUGHUꢀWRꢀJXDUDQWHHꢀODVWꢀGDWDꢀRXWSXWꢄꢀWKHꢀVSHFLILHGꢀPLQLPXPꢀYDOXHꢀRIꢀ&(ꢈꢓ /ꢀ
KROGꢀWLPHꢀIURPꢀFORFNꢀHGJHꢀPXVWꢀEHꢀVDWLVILHGꢃꢀ$IWHUꢀWHUPLQDWLRQꢄꢀWKHꢀVSHFLILHGꢀPLQꢅ
LPXPꢀUHFRYHU\ꢀWLPHꢀLVꢀUHTXLUHGꢀWRꢀVWDUWꢀQHZꢀDFFHVVꢃ
CLK
ADDRESS
Valid
ADV#
CE1#
tTRB
tCKCLH
tCKOH
tCHZ
tOHZ
OE#
WAIT#
DQ
High-Z
tCHTZ
tCKQX
tAC
Q1
Q2
Figure 47. Burst Read Termination Diagram
Burst Write Termination
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CLK
ADDRESS
Valid
ADV#
CE1#
tTRB
tCKCLH
tCKWH
tCHCK
WE#
WAIT#
DQ
tCHTZ
High-Z
tDSCK
tDSCK
D1
D2
tDHCK
tDHCK
Figure 48. Burst Write Termination Diagram
128
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Absolute Maximum Ratings
Item
9ROWDJHꢀRIꢀ9''ꢀ6XSSO\ꢀ5HODWLYHꢀWRꢀ966
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6WRUDJHꢀWHPSHUDWXUH
Symbol
9''
Value
Unit
9
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ꢅꢍꢃꢏꢀWRꢀꢐꢑꢃꢉ
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Recommended Operating Conditions (See Warning Below)
32M
64M
Parameter
Symbol
9''
966
9,+
Min
ꢈꢃꢉꢏ
ꢍ
Max
ꢈꢃꢌꢏ
Min
ꢈꢃꢋ
Max
ꢈꢃꢌꢏ
Unit
9
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9
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Symbol
Description
Te s t S e t up
9,1ꢀ ꢀꢍ9
9,1ꢀ ꢀꢍ9
9,2ꢀ ꢀꢍ9
Typ
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Max
ꢏ
Unit
S)
&
&
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$GGUHVVꢀ,QSXWꢀ&DSDFLWDQFH
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
129
P r e l i m i n a r y
DC Characteristics
(Under Recommended Conditions Unless Otherwise Noted)
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130
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
AC Characteristics
(Under Recommended Operating Conditions Unless Otherwise Noted)
Read Operation
32M
64M
Parameter
Symbol
W5&
Min.
ꢋꢍ
²
Max.
ꢈꢍꢍꢍ
ꢋꢍ
ꢊꢍ
ꢋꢍ
ꢋꢍ
ꢑꢍ
ꢎꢍ
ꢈꢍꢍꢍ
²
Min.
ꢋꢍ
²
Max.
ꢈꢍꢍꢍ
ꢋꢍ
ꢊꢍ
ꢋꢍ
ꢋꢍ
ꢑꢍ
ꢎꢍ
ꢈꢍꢍꢍ
²
Unit
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
Notes
5HDGꢀ&\FOHꢀ7LPH
&(ꢈꢓꢀ$FFHVVꢀ7LPH
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ꢈꢄꢀꢎ
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²
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W%$
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²
ꢎꢍ
ꢏ
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²
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ꢏ
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2(ꢓꢀ+LJKꢀWRꢀ2XWSXWꢀ+LJKꢅ=
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W&/=
W2/=
W%/=
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W$62
W93/
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W$69
W$+9
W$;
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
131
P r e l i m i n a r y
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132
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Write Operation
32M
64M
Parameter
Symbol
W:&
W$6
Min.
ꢋꢍ
ꢍ
Max.
ꢈꢍꢍꢍ
²
Min.
ꢋꢍ
ꢍ
Max.
ꢈꢍꢍꢍ
²
Unit
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
Notes
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ꢑ
:ULWHꢀ&\FOHꢀ7LPH
$GGUHVVꢀ6HWXSꢀ7LPH
$'9ꢓꢀ/RZꢀ3XOVHꢀ:LGWK
W93/
W93+
W$69
W$+9
W&:
W:3
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²
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ꢈꢏ
ꢏ
²
ꢊ
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&(ꢈꢓꢀ:ULWHꢀ5HFRYHU\ꢀ7LPH
:ULWHꢀ5HFRYHU\ꢀ7LPH
²
²
²
²
ꢈꢍ
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ꢍ
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ꢑ
ꢑ
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ꢏ
ꢉ
ꢋ
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W%:
W%6
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W%+
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W:5&
W:5
W&3
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W:+3
W%+3
W'6
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W2+&/
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ꢅꢏ
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W%:2
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ꢈꢁ
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
133
P r e l i m i n a r y
Synchronous Operation - Clock Input (Burst Mode)
32M
64M
Parameter
Symbol
Min.
Max.
Min.
ꢈꢑ
ꢈꢏ
ꢈꢇ
ꢑꢍ
ꢊ
Max.
²
Unit
QV
QV
QV
QV
QV
QV
QV
Notes
5/ꢀ ꢀꢉ
5/ꢀ ꢀꢏ
5/ꢀ ꢀꢊ
5/ꢀ ꢀꢑ
1ꢒ$
ꢈꢏ
ꢎꢍ
ꢑꢍ
ꢏ
²
²
²
²
²
ꢑ
²
&ORFNꢀ3HULRG
W&.
ꢈ
²
&ORFNꢀ+LJKꢀ7LPH
&ORFNꢀ/RZꢀ7LPH
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1RWHVꢀ
W&.+
W&./
W&.7
²
²
ꢑ
ꢏ
ꢊ
²
²
ꢎ
ꢀꢁ &ORFNꢃSHULRGꢃLVꢃGHILQHGꢃEHWZHHQꢃYDOLGꢃFORFNꢃHGJHVꢁ
ꢄꢁ &ORFNꢃULVHꢑIDOOꢃWLPHꢃLVꢃGHILQHGꢃEHWZHHQꢃ9,+ꢃ0LQꢁꢃDQGꢃ9,/ꢃ0D[ꢁ
Synchronous Operation - Address Latch (Burst Mode)
32M
64M
Parameter
Symbol
W$69/
W$6&/
W$+9
Min.
ꢅꢏ
Max.
²
Min.
ꢅꢏ
ꢅꢏ
ꢏ
Max.
Unit
Notes
$GGUHVVꢀ6HWXSꢀ7LPHꢀWRꢀ$'9ꢓꢀ/RZ
$GGUHVVꢀ6HWXSꢀ7LPHꢀWRꢀ&(ꢈꢓꢀ/RZ
$GGUHVVꢀ+ROGꢀ7LPHꢀIURPꢀ$'9ꢓꢀ+LJK
$'9ꢓꢀ/RZꢀ3XOVHꢀ:LGWK
²
²
²
²
²
²
²
²
²
²
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
ꢈ
ꢎ
ꢅꢏ
²
ꢈꢍ
ꢈꢍ
²
W93/
²
ꢈꢍ
ꢏ
ꢑ
ꢊ
ꢊ
ꢊ
ꢊ
ꢊ
5/ꢀ ꢀꢉꢄꢀꢏ
²
$'9ꢓꢀ/RZꢀ6HWXSꢀ7LPHꢀWRꢀ&/.
W96&.
ꢋ
ꢋ
5/ꢀ ꢀꢊꢄꢀꢑ
5/ꢀ ꢀꢉꢄꢀꢏ
5/ꢀ ꢀꢊꢄꢀꢑ
²
ꢋ
²
ꢏ
&(ꢈꢀ/RZꢀ6HWXSꢀ7LPHꢀWRꢀ&/.
W&/&.
²
ꢋ
$'9ꢓꢀ/RZꢀ+ROGꢀ7LPHꢀIURPꢀ&/.
W&.9+
W9+9/
ꢈ
²
ꢈ
%XUVWꢀ(QGꢀ$'9ꢓꢀ+LJKꢀ+ROGꢀ7LPHꢀIURPꢀ&/.
ꢈꢏ
²
ꢈꢑ
1RWHVꢀ
ꢀꢁ W$6&/ꢃLVꢃDSSOLFDEOHꢃLIꢃ&(ꢀ!ꢃLVꢃEURXJKWꢃWRꢃ/RZꢃDIWHUꢃ$'9!ꢃLVꢃEURXJKWꢃWRꢃ/RZꢁ
ꢄꢁ
W$69/ꢃLVꢃDSSOLFDEOHꢃLIꢃ$'9!ꢃLVꢃEURXJKWꢃWRꢃ/RZꢃDIWHUꢃ&(ꢀ!ꢃLVꢃEURXJKWꢃWRꢃ/RZꢁ
ꢅꢁ
W93/ꢃLVꢃVSHFLILHGꢃIURPꢃWKHꢃQHJDWLYHꢃHGJHꢃRIꢃHLWKHUꢃ&(ꢀ!ꢃRUꢃ$'9!ꢃZKLFKHYHUꢃFRPHVꢃODWHꢁ
ꢈꢁ $SSOLFDEOHꢃWRꢃWKHꢃꢀVWꢃYDOLGꢃFORFNꢃHGJHꢁ
134
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Synchronous Read Operation (Burst Mode)
32M
64M
Parameter
%XUVWꢀ5HDGꢀ&\FOHꢀ7LPH
Symbol
Min.
Max.
Min.
²
²
²
ꢑ
Max.
ꢊꢍꢍꢍ
ꢈꢍ
ꢈꢎ
²
Unit
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
Notes
W5&%
²
ꢇꢍꢍꢍ
5/ꢀ ꢀꢉꢄꢀꢏ
5/ꢀ ꢀꢊꢄꢀꢑ
ꢈ
ꢈ
&/.ꢀ$FFHVVꢀ7LPH
W$&
²
ꢈꢎ
2XWSXWꢀ+ROGꢀ7LPHꢀIURPꢀ&/.
&(ꢈꢓꢀ/RZꢀWRꢀ:$,7ꢓꢀ/RZ
W&.4;
W&/7/
W2/7/
W9/7/
W&.79
W&.7;
W&/=
ꢑ
ꢏ
ꢍ
²
ꢎꢍ
ꢎꢍ
ꢈ
ꢏ
ꢎꢍ
ꢎꢍ
ꢎꢍ
ꢈꢍ
²
ꢈ
2(ꢓꢀ/RZꢀWRꢀ:$,7ꢓꢀ/RZ
ꢍ
ꢈꢄꢀꢎ
ꢈ
$'9ꢓꢀ/RZꢀWRꢀ:$,7ꢓꢀ/RZ
1ꢒ$
ꢍ
&/.ꢀWRꢀ:$,7ꢓꢀ9DOLGꢀ7LPH
²
ꢑ
ꢈꢎ
²
²
²
²
ꢈꢊ
ꢈꢊ
ꢈꢊ
ꢎꢍ
ꢎꢍ
²
²
²
²
²
²
²
²
²
ꢑ
ꢈꢄꢀꢑ
ꢈ
:$,7ꢓꢀ9DOLGꢀ+ROGꢀ7LPHꢀIURPꢀ&/.
&(ꢈꢓꢀ/RZꢀWRꢀ2XWSXWꢀ/RZꢅ=
2(ꢓꢀ/RZꢀWRꢀ2XWSXWꢀ/RZꢅ=
/%ꢓꢄꢀ8%ꢓꢀ/RZꢀWRꢀ2XWSXWꢀ/RZꢅ=
&(ꢈꢓꢀ+LJKꢀWRꢀ2XWSXWꢀ+LJKꢅ=
2(ꢓꢀ+LJKꢀWRꢀ2XWSXWꢀ+LJKꢅ=
/%ꢓꢄꢀ8%ꢓꢀ+LJKꢀWRꢀ2XWSXWꢀ+LJKꢅ=
&(ꢈꢓꢀ+LJKꢀWRꢀ:$,7ꢀ+LJKꢅ=
2(ꢓꢀ+LJKꢀWRꢀ:$,7ꢀ+LJKꢅ=
2(ꢓꢀ/RZꢀ6HWXSꢀ7LPHꢀWRꢀꢈVWꢀ'DWDꢅRXW
ꢏ
ꢏ
²
ꢊ
W2/=
ꢈꢍ
ꢍ
ꢈꢍ
ꢍ
²
ꢊ
W%/=
²
ꢊ
W&+=
²
²
²
²
²
ꢑꢍ
ꢑꢍ
ꢏ
²
²
²
²
²
ꢑꢍ
ꢎꢉ
ꢏ
ꢎꢍ
ꢎꢍ
ꢎꢍ
ꢎꢍ
ꢎꢍ
²
ꢈ
W2+=
ꢈ
W%+=
ꢈ
W&+7=
W2+7=
W2/4
ꢈ
ꢈ
8%ꢓꢄꢀ/%ꢓꢀ6HWXSꢀ7LPHꢀWRꢀꢈVWꢀ'DWDꢅRXW
2(ꢓꢀ6HWXSꢀ7LPHꢀWRꢀ&/.
W%/4
²
ꢏ
W26&.
W&.2+
W&.&/+
W&.%+
²
2(ꢓꢀ+ROGꢀ7LPHꢀIURPꢀ&/.
ꢏ
ꢏ
²
%XUVWꢀ(QGꢀ&(ꢈꢓꢀ/RZꢀ+ROGꢀ7LPHꢀIURPꢀ&/.
%XUVWꢀ(QGꢀ8%ꢓꢄꢀ/%ꢓꢀ+ROGꢀ7LPHꢀIURPꢀ&/.
ꢏ
ꢏ
²
ꢏ
ꢏ
²
%/ ꢇꢄꢀꢈꢉ
%/ &RQWLQXRXV
ꢑꢍ
ꢋꢍ
ꢎꢉ
ꢋꢍ
²
ꢉ
ꢉ
%XUVWꢀ7HUPLQDWHꢀ5HFRYHU\ꢀ7LPH
W75%
²
1RWHVꢀ
ꢀꢁ 7KHꢃRXWSXWꢃORDGꢃꢊꢌS)ꢃZLWKꢃꢊꢌRKPꢃWHUPLQDWLRQꢃWRꢃ9''ꢔꢌꢁꢊꢃ9ꢁ
ꢄꢁ :$,7!ꢃGULYHVꢃ+LJKꢃDWꢃWKHꢃEHJLQQLQJꢃGHSHQGLQJꢃRQꢃ2(!ꢃIDOOLQJꢃHGJHꢃWLPLQJꢁ
ꢅꢁ &.79ꢃLVꢃJXDUDQWHHGꢃDIWHUꢃW2/7/ꢃꢎPD[ꢏꢃIURPꢃ2(!ꢃIDOOLQJꢃHGJHꢃDQGꢃW26&.ꢃPXVWꢃEHꢃVDWLVILHGꢁ
W
ꢈꢁ 7KHꢃRXWSXWꢃORDGꢃLVꢃꢊS)ꢃZLWKRXWꢃDQ\ꢃRWKHUꢃORDGꢁ
ꢊꢁ 2QFHꢃWKH\ꢃDUHꢃGHWHUPLQHGꢆꢃWKH\ꢃPXVWꢃQRWꢃEHꢃFKDQJHGꢃXQWLOꢃWKHꢃHQGꢃRIꢃEXUVWꢁ
ꢋꢁ 'HILQHGꢃIURPꢃWKHꢃ/RZꢃWRꢃ+LJKꢃWUDQVLWLRQꢃRIꢃ&(ꢀ!ꢃWRꢃWKHꢃ+LJKꢃWRꢃ/RZꢃWUDQVLWLRQꢃRIꢃHLWKHUꢃ$'9!ꢃRUꢃ&(ꢀ!ꢃZKLFKHYHUꢃRFFXUVꢃODWHꢁ
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
135
P r e l i m i n a r y
Synchronous Write Operation (Burst Mode)
32M
64M
Parameter
%XUVWꢀ:ULWHꢀ&\FOHꢀ7LPH
Symbol
W:&%
Min.
²
ꢋ
Max.
ꢇꢍꢍꢍ
²
Min.
²
ꢏ
Max.
ꢊꢍꢍꢍ
²
Unit
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
QV
Notes
'DWDꢀ6HWXSꢀ7LPHꢀWRꢀ&ORFN
W'6&.
W'+&.
W:/'
'DWDꢀ+ROGꢀ7LPHꢀIURPꢀ&/.
ꢑ
²
ꢑ
²
:(ꢓꢀ/RZꢀ6HWXSꢀ7LPHꢀWRꢀꢈVWꢀ'DWDꢀ,Q
8%ꢓꢄꢀ/%ꢓꢀ6HWXSꢀ7LPHꢀIRUꢀ:ULWH
:(ꢓꢀ6HWXSꢀ7LPHꢀWRꢀ&/.
ꢑꢍ
ꢅꢏ
ꢏ
²
ꢑꢍ
ꢅꢏ
ꢏ
²
W%6
²
²
ꢈ
W:6&.
W&.:+
W&/7+
W:/7+
W&+7=
W:+7=
W&.&/+
W&+&.
W&.%+
W:5%
²
²
:(ꢓꢀ+ROGꢀ7LPHꢀIURPꢀ&/.
ꢏ
²
ꢏ
²
&(ꢈꢓꢀ/RZꢀWRꢀ:$,7ꢓꢀ+LJK
ꢏ
ꢎꢍ
ꢎꢍ
ꢎꢍ
ꢎꢍ
²
ꢏ
ꢎꢍ
ꢎꢍ
ꢎꢍ
ꢎꢍ
²
ꢎ
ꢎ
ꢎ
ꢎ
:(ꢓꢀ/RZꢀWRꢀ:$,7ꢓꢀ+LJK
ꢍ
ꢍ
&(ꢈꢓꢀ+LJKꢀWRꢀ:$,7ꢓꢀ+LJKꢅ=
:(ꢓꢀ+LJKꢀWRꢀ:$,7ꢓꢀ+LJKꢅ=
²
²
ꢏ
²
²
ꢏ
%XUVWꢀ(QGꢀ&(ꢈꢓꢀ/RZꢀ+ROGꢀ7LPHꢀIURPꢀ&/.
%XUVWꢀ(QGꢀ&(ꢈꢓꢀ+LJKꢀ6HWXSꢀ7LPHꢀWRꢀQH[Wꢀ&/.
%XUVWꢀ(QGꢀ8%ꢓꢄꢀ/%ꢓꢀ+ROGꢀ7LPHꢀIURPꢀ&/.
%XUVWꢀ:ULWHꢀ5HFRYHU\ꢀ7LPH
ꢏ
²
ꢏ
²
ꢏ
²
ꢏ
²
ꢑꢍ
ꢑꢍ
ꢋꢍ
ꢎꢉ
ꢎꢉ
ꢋꢍ
%/ ꢇꢄꢀꢈꢉ
%XUVWꢀ7HUPLQDWHꢀ5HFRYHU\ꢀ7LPH
%/ &RQWLQXRXV
W75%
²
²
²
²
ꢑ
ꢊ
W75%
1RWHVꢀ
ꢀꢁ 'HILQHGꢃIURPꢃWKHꢃYDOLGꢃLQSXWꢃHGJHꢃWRꢃWKHꢃ+LJKꢃWRꢃ/RZꢃWUDQVLWLRQꢃRIꢃHLWKHUꢃ$'9!ꢆꢃ&(ꢀ!ꢆꢃRUꢃ:(!ꢆꢃZKLFKHYHUꢃRFFXUVꢃODVWꢁꢃ$QGꢃ
RQFHꢃWKH\ꢃDUHꢃGHWHUPLQHGꢆꢃWKH\ꢃPXVWꢃQRWꢃEHꢃFKDQJHGꢃXQWLOꢃWKHꢃHQGꢃRIꢃEXUVWꢁ
ꢄꢁ 7KHꢃRXWSXWꢃORDGꢃꢊꢌS)ꢃZLWKꢃꢊꢌRKPꢃWHUPLQDWLRQꢃWRꢃ9''ꢔꢌꢁꢊꢃ9ꢁ
ꢅꢁ 'HILQHGꢃIURPꢃWKHꢃYDOLGꢃFORFNꢃHGJHꢃZKHUHꢃODVWꢃGDWDꢂLQꢃEHLQJꢃODWFKHGꢃDWꢃWKHꢃHQGꢃRIꢃEXUVWꢃZULWHꢃWRꢃWKHꢃ+LJKꢃWRꢃ/RZꢃWUDQVLWLRQꢃRIꢃ
HLWKHUꢃ$'9!ꢃRUꢃ&(ꢀ!ꢃZKLFKHYHUꢃRFFXUVꢃODWHꢃIRUꢃWKHꢃQH[WꢃDFFHVVꢁ
ꢈꢁ 'HILQHGꢃIURPꢃWKHꢃ/RZꢃWRꢃ+LJKꢃWUDQVLWLRQꢃRIꢃ&(ꢀ!ꢃWRꢃWKHꢃ+LJKꢃWRꢃ/RZꢃWUDQVLWLRQꢃRIꢃHLWKHUꢃ$'9!ꢃRUꢃ&(ꢀ!ꢃZKLFKHYHUꢃRFFXUVꢃODWHꢃ
IRUꢃWKHꢃQH[WꢃDFFHVVꢁ
136
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Power Down Parameters
32M
64M
Parameter
Symbol
W&63
Min.
ꢎꢍ
Max.
²
Min.
ꢈꢍ
Max.
²
Unit
QV
Notes
&(ꢎꢀ/RZꢀ6HWXSꢀ7LPHꢀIRUꢀ3RZHUꢀ'RZQꢀ(QWU\
&(ꢎꢀ/RZꢀ+ROGꢀ7LPHꢀDIWHUꢀ3RZHUꢀ'RZQꢀ(QWU\
&(ꢎꢀ/RZꢀ+ROGꢀ7LPHꢀIRUꢀ5HVHWꢀWRꢀ$V\QFKURQRXVꢀ0RGH
W&ꢎ/3
ꢋꢍ
²
ꢋꢍ
²
QV
W&ꢎ/35
1ꢒ$
ꢏꢍ
²
V
ꢈ
ꢎ
&(ꢈꢓꢀ+LJKꢀ+ROGꢀ7LPHꢀIROORZLQJꢀ&(ꢎꢀ+LJKꢀDIWHUꢀ3RZHUꢀ
'RZQꢀ([LWꢀ>6/((3ꢀPRGHꢀRQO\@
W&++
W&++3
W&+6
ꢑꢍꢍ
ꢋꢍ
ꢍ
²
²
²
ꢑꢍꢍ
ꢋꢍ
ꢍ
²
²
²
V
V
QV
&(ꢈꢓꢀ+LJKꢀ+ROGꢀ7LPHꢀIROORZLQJꢀ&(ꢎꢀ+LJKꢀDIWHUꢀ3RZHUꢀ
'RZQꢀ([LWꢀ>QRWꢀLQꢀ6/((3ꢀPRGH@
ꢑ
ꢎ
&(ꢈꢓꢀ+LJKꢀ6HWXSꢀ7LPHꢀIROORZLQJꢀ&(ꢎꢀ+LJKꢀDIWHUꢀ3RZHUꢀ
'RZQꢀ([LW
1RWHVꢀ
ꢀꢁ $SSOLFDEOHꢃZKHQꢃ53 ꢌꢃꢎ5HVHWꢃWRꢃ3DJHꢃPRGHꢏꢁꢃ53ꢃꢎ5HVHWꢃWRꢃ3DJHꢏꢃPRGHꢃLVꢃDYDLODEOHꢃRQO\ꢃIRUꢃꢋꢈ0ꢁ
ꢄꢁ $SSOLFDEOHꢃDOVRꢃWRꢃSRZHUꢂXSꢁ
ꢅꢁ $SSOLFDEOHꢃZKHQꢃ3DUWLDOꢃPRGHꢃLVꢃVHWꢁ
Other Timing Parameters
32M
64M
Parameter
&(ꢈꢀ+LJKꢀWRꢀ2(ꢀ,QYDOLGꢀ7LPHꢀIRUꢀ6WDQGE\ꢀ(QWU\
&(ꢈꢀ+LJKꢀWRꢀ:(ꢀ,QYDOLGꢀ7LPHꢀIRUꢀ6WDQGE\ꢀ(QWU\
&(ꢎꢀ/RZꢀ+ROGꢀ7LPHꢀDIWHUꢀ3RZHUꢅXS
&(ꢈꢀ+LJKꢀ+ROGꢀ7LPHꢀIROORZLQJꢀ&(ꢎꢀ+LJKꢀDIWHUꢀ3RZHUꢅXS
,QSXWꢀ7UDQVLWLRQꢀ7LPH
Symbol
W&+2;
W&+:;
W&ꢎ/+
W&++
Min.
ꢈꢍ
ꢈꢍ
ꢏꢍ
ꢑꢍꢍ
ꢈ
Max.
²
Min.
ꢈꢍ
ꢈꢍ
ꢏꢍ
ꢑꢍꢍ
ꢈ
Max.
²
Unit
QV
Notes
²
²
QV
ꢈ
²
²
V
²
²
V
W7
ꢎꢏ
ꢎꢏ
QV
ꢎ
1RWHVꢀ
ꢀꢁ 6RPHꢃGDWDꢃPLJKWꢃEHꢃZULWWHQꢃLQWRꢃDQ\ꢃDGGUHVVꢃORFDWLRQꢃLIꢃW&+:;ꢎPLQꢏꢃLVꢃQRWꢃVDWLVILHGꢁ
ꢄꢁ ([FHSWꢃIRUꢃFORFNꢃLQSXWꢃWUDQVLWLRQꢃWLPHꢁ
ꢅꢁ 7KHꢃ,QSXWꢃ7UDQVLWLRQꢃ7LPHꢃꢎW7ꢏꢃDWꢃ$&ꢃWHVWLQJꢃLVꢃꢊQVꢃIRUꢃ$V\QFKURQRXVꢃRSHUDWLRQꢃDQGꢃꢅQVꢃIRUꢃ6\QFKURQRXVꢃRSHUDWLRQꢃ
UHVSHFWLYHO\ꢁꢃ,IꢃDFWXDOꢃW7ꢃLVꢃORQJHUꢃWKDQꢃꢊQVꢃRUꢃꢅQVꢃVSHFLILHGꢃDVꢃ$&ꢃWHVWꢃFRQGLWLRQꢆꢃLWꢃPD\ꢃYLRODWHꢃ$&ꢃVSHFLILFDWLRQꢃRIꢃVRPHꢃ
WLPLQJꢃSDUDPHWHUVꢁꢃ6HHꢃWKHꢃꢙ$&ꢃ7HVWꢃ&RQGLWLRQVꢙꢃVHFWLRQ
AC Test Conditions
Symbol
9,+
Description
Te s t S e t up
Value
9''ꢀꢘꢀꢍꢃꢇ
9''ꢀꢘꢀꢍꢃꢎ
9''ꢀꢘꢀꢍꢃꢏ
ꢏ
Unit
9
Note
,QSXWꢀ+LJKꢀ/HYHO
,QSXWꢀ/RZꢀ/HYHO
9,/
9
95()
,QSXWꢀ7LPLQJꢀ0HDVXUHPHQWꢀ/HYHO
9
$V\QFꢃ
6\QFꢃ
QV
QV
W7
,QSXWꢀ7UDQVLWLRQꢀ7LPHꢀ
%HWZHHQꢀ9,/ꢀDQGꢀ9,+
ꢑ
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
137
P r e l i m i n a r y
AC Measurement Output Load Circuit
VDD*0.5V
50ohm
VDD
DEVICE
UNDER
TEST
OUT
0.1μF
VSS
50pF
Figure 49. Output Load Circuit
138
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Timing Diagrams
tRC
ADDRESS VALID
ADDRESS
ADV#
CE1#
Low
tASC
tCE
tCHAH
tASC
tCP
tCHZ
tOE
OE#
tOHZ
tBHZ
tBA
LB# / UB#
tBLZ
tOLZ
DQ
(Output)
VALID DATA OUTPUT
Figure 50. Asynchronous Read Timing #1-1 (Basic Timing)
tOH
1RWHꢀꢃ7KLVꢃWLPLQJꢃGLDJUDPꢃDVVXPHVꢃ&(ꢄ +ꢃDQGꢃ:(! +ꢁ
tRC
ADDRESS VALID
ADDRESS
ADV#
tAHV
tAV
tVPL
tASC
tASC
tCE
CE1#
tCP
tOE
tCHZ
OE#
tOHZ
tBHZ
tBA
LB# / UB#
tBLZ
tOLZ
DQ
(Output)
VALID DATA OUTPUT
Figure 51. Asynchronous Read Timing #1-2 (Basic Timing)
tOH
1RWHꢀꢃ7KLVꢃWLPLQJꢃGLDJUDPꢃDVVXPHVꢃ&(ꢄ +ꢃDQGꢃ:(! +ꢁ
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
139
P r e l i m i n a r y
tAX
tRC
tRC
ADDRESS
CE1#
ADDRESS VALID
ADDRESS VALID
tAA
tAA
tOHAH
Low
tASO
tOE
OE#
LB# / UB#
tOLZ
tOH
tOHZ
tOH
DQ
(Output)
VALID DATA OUTPUT
Figure 52. Asynchronous Read Timing #2 (OE# & Address Access)
VALID DATA OUTPUT
1RWHꢀꢃ7KLVꢃWLPLQJꢃGLDJUDPꢃDVVXPHVꢃ&(ꢄ +ꢆꢃ$'9! /ꢃDQGꢃ:(! +ꢁ
tAX
tRC
tAX
ADDRESS
ADDRESS VALID
tAA
Low
CE1#, OE#
LB#
tBA
tBA
tBA
UB#
tBHZ
tOH
tBHZ
tOH
tBLZ
tBLZ
DQ1-8
(Output)
VALID DATA
OUTPUT
tBHZ
VALID DATA
OUTPUT
tOH
tBLZ
DQ9-16
(Output)
VALID DATA OUTPUT
Figure 53. Asynchronous Read Timing #3 (LB# / UB# Byte Access)
1RWHꢀꢃ7KLVꢃWLPLQJꢃGLDJUDPꢃDVVXPHVꢃ&(ꢄ +ꢆꢃ$'9! /ꢃDQGꢃ:(! +ꢁ
140
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
tRC
ADDRESS
(A21-A3)
ADDRESS VALID
tRC
tPRC
tPRC
tPRC
ADDRESS
(A2-A0)
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS VALID
tPAA
tPAA
tPAA
tASC
tCHAH
ADV#
CE1#
tCHZ
tCE
OE#
LB# / UB#
tOH
tCLZ
tOH
tOH
tOH
DQ
(Output)
VALID DATA OUTPUT
(Page Access)
VALID DATA OUTPUT
(Normal Access)
Figure 54. Asynchronous Read Timing #4 (Page Address Access after CE1# Control Access)
1RWHꢀꢃ7KLVꢃWLPLQJꢃGLDJUDPꢃDVVXPHVꢃ&(ꢄ +ꢃDQGꢃ:(! +ꢁ
tRC
tAX
tRC
tAX
ADDRESS
(A21-A3)
ADDRESS VALID
ADDRESS VALID
tRC
tPRC
tRC
tPRC
ADDRESS
(A2-A0)
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
tAA
tPAA
tAA
tPAA
CE1#
Low
tASO
tOE
OE#
tBA
LB# / UB#
tOLZ
tBLZ
tOH
tOH
tOH
tOH
DQ
(Output)
VALID DATA OUTPUT
(Page Access)
VALID DATA OUTPUT
(Normal Access)
Figure 55. Asynchronous Read Timing #5 (Random and Page Address
Access)
1RWHVꢀ
ꢀꢁ 7KLVꢃWLPLQJꢃGLDJUDPꢃDVVXPHVꢃ&(ꢄ +ꢆꢃ$'9! /ꢃDQGꢃ:(! +ꢁ
ꢄꢁ (LWKHUꢃRUꢃERWKꢃ/%!ꢃDQGꢃ8%!ꢃPXVWꢃEHꢃ/RZꢃZKHQꢃERWKꢃ&(ꢀ!ꢃDQGꢃ2(!ꢃDUHꢃ/RZꢁ
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
141
P r e l i m i n a r y
tWC
ADDRESS
ADV#
ADDRESS VALID
Low
tAS
tCW
tWP
tBW
tWRC
tWR
tBR
tAS
CE1#
tAS
tAS
WE#
tAS
tAS
LB#, UB#
tOHCL
OE#
tDS
tDH
DQ
(Input)
VALID DATA INPUT
Figure 56. Asynchronous Write Timing #1-1 (Basic Timing)
1RWHꢀꢃ7KLVꢃWLPLQJꢃGLDJUDPꢃDVVXPHVꢃ&(ꢄ +ꢃDQGꢃ$'9! /ꢁ
tWC
ADDRESS
ADV#
ADDRESS VALID
tVPL
tAHV
tCW
tAS
tWRC
tWR
tBR
tAS
CE1#
tAS
tWP
tAS
WE#
tAS
tBW
tAS
LB#, UB#
tOHCL
OE#
tDS
tDH
DQ
(Input)
VALID DATA INPUT
Figure 57. Asynchronous Write Timing #1-2 (Basic Timing)
1RWHꢀꢃ7KLVꢃWLPLQJꢃGLDJUDPꢃDVVXPHVꢃ&(ꢄ +ꢁ
142
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
tWC
tWC
ADDRESS VALID
ADDRESS VALID
ADDRESS
CE1#
tOHAH
Low
tAS
tWP
tWR
tAS
tWP
tWR
WE#
UB#, LB#
OE#
tOES
tOHZ
tDS
tDH
tDS
tDH
DQ
(Input)
VALID DATA INPUT
VALID DATA INPUT
Figure 58. Asynchronous Write Timing #2 (WE# Control)
1RWHꢀꢃ7KLVꢃWLPLQJꢃGLDJUDPꢃDVVXPHVꢃ&(ꢄ +ꢃDQGꢃ$'9! /ꢁ
tWC
tWC
ADDRESS VALID
ADDRESS VALID
ADDRESS
CE1#
Low
tAS
tWP
tAS
tWP
WE#
LB#
UB#
tBH
tBR
tBS
tBR
tBS
tBH
tDS
tDH
DQ1-8
(Input)
VALID DATA INPUT
tDS
tDH
DQ9-16
(Input)
VALID DATA INPUT
Figure 59. Asynchronous Write Timing #3-1 (WE# / LB# / UB# Byte Write Control)
1RWHꢀꢃ7KLVꢃWLPLQJꢃGLDJUDPꢃDVVXPHVꢃ&(ꢄ +ꢆꢃ$'9! /ꢃDQGꢃ2(! +ꢁ
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
143
P r e l i m i n a r y
tWC
tWC
ADDRESS VALID
ADDRESS VALID
ADDRESS
CE1#
Low
tWR
tWR
WE#
LB#
UB#
tAS
tBW
tBS
tBH
tAS
tBW
tBH
tBS
tDS
tDH
DQ1-8
(Input)
VALID DATA INPUT
tDS
tDH
DQ9-16
(Input)
VALID DATA INPUT
Figure 60. Asynchronous Write Timing #3-2 (WE# / LB# / UB# Byte Write Control)
1RWHꢀꢃ7KLVꢃWLPLQJꢃGLDJUDPꢃDVVXPHVꢃ&(ꢄ +ꢆꢃ$'9! /ꢃDQGꢃ2(! +ꢁ
tWC
tWC
ADDRESS VALID
ADDRESS VALID
ADDRESS
CE1#
Low
WE#
LB#
UB#
tAS
tBW
tBR
tBS
tBH
tAS
tBW
tBR
tBS
tBH
tDS
tDH
DQ1-8
(Input)
VALID DATA INPUT
tDS
tDH
DQ9-16
(Input)
VALID DATA INPUT
Figure 61. Asynchronous Write Timing #3-3 (WE# / LB# / UB# Byte Write Control)
1RWHꢀꢃ7KLVꢃWLPLQJꢃGLDJUDPꢃDVVXPHVꢃ&(ꢄ +ꢆꢃ$'9! /ꢃDQGꢃ2(! +ꢁ
144
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
tWC
tWC
ADDRESS VALID
ADDRESS VALID
ADDRESS
CE1#
Low
WE#
LB#
tAS
tBW
tBR
tAS
tBW
tBR
tBWO
tDH
tDS
tDH
tDS
DQ1-8
(Input)
VALID
DATA INPUT
VALID
DATA INPUT
tAS
tBW
tBR
tAS
tBR
tBWO
tBW
UB#
tDS
tDH
tDS
tDH
DQ9-16
(Input)
VALID
DATA INPUT
VALID
DATA INPUT
Figure 62. Asynchronous Write Timing #3-4 (WE# / LB# / UB# Byte Write Control)
1RWHꢀꢃ7KLVꢃWLPLQJꢃGLDJUDPꢃDVVXPHVꢃ&(ꢄ +ꢆꢃ$'9! /ꢃDQGꢃ2(! +ꢁ
tWC
tRC
ADDRESS
CE1#
WRITE ADDRESS
READ ADDRESS
tCHAH
tAS
tCW
tWRC
tASC
tCE
tCHAH
tCP
tCP
WE#
UB#, LB#
OE#
tOHCL
tCHZ
tOH
tDS
tDH
tCLZ
tOH
DQ
READ DATA OUTPUT
WRITE DATA INPUT
Figure 63. Asynchronous Read / Write Timing #1-1 (CE1# Control)
1RWHVꢀ
ꢀꢁ 7KLVꢃWLPLQJꢃGLDJUDPꢃDVVXPHVꢃ&(ꢄ +ꢃDQGꢃ$'9! /ꢁ
ꢄꢁ :ULWHꢃDGGUHVVꢃLVꢃYDOLGꢃIURPꢃHLWKHUꢃ&(ꢀ!ꢃRUꢃ:(!ꢃRIꢃODVWꢃIDOOLQJꢃHGJHꢁ
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
145
P r e l i m i n a r y
tWC
tRC
ADDRESS
CE1#
WRITE ADDRESS
READ ADDRESS
tCHAH
tAS
tWR
tASC
tCE
tCHAH
tCP
tCP
tWP
WE#
UB#, LB#
OE
tOHCL
tOE
tCHZ
tOH
tDS
tDH
tOLZ
tOH
DQ
READ DATA OUTPUT
WRITE DATA INPUT
READ DATA OUTPUT
Figure 64. Asynchronous Read / Write Timing #1-2 (CE1# / WE# / OE# Control)
1RWHVꢀ
ꢀꢁ 7KLVꢃWLPLQJꢃGLDJUDPꢃDVVXPHVꢃ&(ꢄ +ꢃDQGꢃ$'9! /ꢁ
ꢄꢁ 2(!ꢃFDQꢃEHꢃIL[HGꢃ/RZꢃGXULQJꢃZULWHꢃRSHUDWLRQꢃLIꢃLWꢃLVꢃ&(ꢀ!ꢃFRQWUROOHGꢃZULWHꢃDWꢃ5HDGꢂ:ULWHꢂ5HDGꢃ6HTXHQFHꢁ
tWC
tRC
ADDRESS
CE1#
WRITE ADDRESS
READ ADDRESS
tOHAH
tOHAH
tAA
Low
tAS
tWR
tWP
WE#
tOES
UB#, LB#
OE#
tASO
tOE
tOHZ
tOH
tOHZ
tOH
tDS
tDH
tOLZ
DQ
READ DATA OUTPUT
READ DATA OUTPUT
WRITE DATA INPUT
Figure 65. Asynchronous Read / Write Timing #2 (OE#, WE# Control)
1RWHVꢀ
ꢀꢁ 7KLVꢃWLPLQJꢃGLDJUDPꢃDVVXPHVꢃ&(ꢄ +ꢃDQGꢃ$'9! /ꢁ
ꢄꢁ &(ꢀ!ꢃFDQꢃEHꢃWLHGꢃWRꢃ/RZꢃIRUꢃ:(!ꢃDQGꢃ2(!ꢃFRQWUROOHGꢃRSHUDWLRQꢁ
146
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
tWC
tRC
ADDRESS
CE1#
WRITE ADDRESS
READ ADDRESS
tAA
tOHAH
tOHAH
Low
WE#
tOES
tAS
tBW
tBR
tBA
UB#, LB#
OE#
tBHZ
tASO
tBHZ
tOH
tDS
tDH
tBLZ
tOH
DQ
READ DATA OUTPUT
READ DATA OUTPUT
WRITE DATA INPUT
Figure 66. Asynchronous Read / Write Timing #3 (OE,# WE#, LB#, UB# Control)
1RWHVꢀ
ꢀꢁ 7KLVꢃWLPLQJꢃGLDJUDPꢃDVVXPHVꢃ&(ꢄ +ꢃDQGꢃ$'9! /ꢁ
ꢄꢁ &(ꢀ!ꢃFDQꢃEHꢃWLHGꢃWRꢃ/RZꢃIRUꢃ:(!ꢃDQGꢃ2(!ꢃFRQWUROOHGꢃRSHUDWLRQꢁ
tCK
CLK
tCK
tCKH
tCKL
tCKT
tCKT
Figure 67. Clock Input Timing
1RWHVꢀ
ꢀꢁ 6WDEOHꢃFORFNꢃLQSXWꢃPXVWꢃEHꢃUHTXLUHGꢃGXULQJꢃ&(ꢀ! /ꢁꢃ
ꢄꢁ W&.ꢃLVꢃGHILQHGꢃEHWZHHQꢃYDOLGꢃFORFNꢃHGJHVꢁ
ꢅꢁ
W&.7ꢃLVꢃGHILQHGꢃEHWZHHQꢃ9,+ꢃ0LQꢁꢃDQGꢃ9,/ꢃ0D[
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
147
P r e l i m i n a r y
Case #1
Case #2
CLK
ADDRESS
Valid
Valid
tASCL
tCKVH
tAHV
tVSCK
tCKVH
tAHV
tASVL
tVSCK
ADV#
CE1#
tVPL
tVPL
tVLCL
tCLCK
Low
Figure 68. Address Latch Timing (Synchronous Mode)
1RWHVꢀ
ꢀꢁ &DVHꢃ!ꢀꢃLVꢃWKHꢃWLPLQJꢃZKHQꢃ&(ꢀ!ꢃLVꢃEURXJKWꢃWRꢃ/RZꢃDIWHUꢃ$'9!ꢃLVꢃEURXJKWꢃWRꢃ/RZꢁꢃ&DVHꢃ!ꢄꢃLVꢃWKHꢃWLPLQJꢃZKHQꢃ$'9!ꢃLVꢃ
EURXJKWꢃWRꢃ/RZꢃDIWHUꢃ&(ꢀ!ꢃLVꢃEURXJKWꢃWRꢃ/RZꢁ
ꢄꢁ
ꢅꢁ
W
93/ꢃLVꢃVSHFLILHGꢃIURPꢃWKHꢃQHJDWLYHꢃHGJHꢃRIꢃHLWKHUꢃ&(ꢀ!ꢃRUꢃ$'9!ꢃZKLFKHYHUꢃFRPHVꢃODWHꢁꢃ$WꢃOHDVWꢃRQHꢃYDOLGꢃFORFNꢃHGJHꢃPXVWꢃEHꢃ
LQSXWꢃGXULQJꢃ$'9! /ꢁ
W96&.ꢃDQGꢃW&/&.ꢃDUHꢃDSSOLHGꢃWRꢃWKHꢃꢀVWꢃYDOLGꢃFORFNꢃHGJHꢃGXULQJꢃ$'9! /ꢁ
148
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
RL=5
CLK
tRCB
ADDRESS
Valid
Valid
tASVL
tAHV
tCKVH
tASVL
tVSCK
tVSCK
tCKVH
ADV#
CE1#
tVPL
tVHVL
tVPL
tASCL
tASCL
tCLCK
tCLCK
tCKOH
tCP
OE#
WE#
tOLQ
High
tCKBH
tBLQ
LB#, UB#
WAIT#
DQ
tOHTZ
tCKTV
tCKTV
High-Z
High-Z
tOHZ
tOLTL
tCKTX
tAC
tAC
tAC
tCKTX
QBL
Q1
tOLZ
tCKQX
tCKQX
Figure 69. 32M Synchronous Read Timing #1 (OE# Control)
1RWHꢀꢃ7KLVꢃWLPLQJꢃGLDJUDPꢃDVVXPHVꢃ&(ꢄ +ꢆꢃWKHꢃYDOLGꢃFORFNꢃHGJHꢃRQꢃULVLQJꢃHGJHꢃDQGꢃ%/ ꢐꢃRUꢃꢀꢋꢁ
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
149
P r e l i m i n a r y
RL=5
CLK
tRCB
ADDRESS
Valid
Valid
tASVL
tAHV
tCKVH
tASVL
tAHV
tCKVH
tVSCK
tVSCK
ADV#
tVPL
tVHVL
tVPL
tASCL
tASCL
CE1#
tCP
tCLCK
tCKCLH
tCLCK
OE#
WE#
High
tCKBH
LB#, UB#
WAIT#
DQ
tCKTV
tCKTV
tCHTZ
tCLTL
tCLZ
tCLTL
tCKTX
tAC
tAC
tAC
tCKTX
tCHZ
Q1
QBL
tCLZ
tCKQX
tCKQX
Figure 70. 32M Synchronous Read Timing #2 (CE1# Control)
1RWHꢀꢃ7KLVꢃWLPLQJꢃGLDJUDPꢃDVVXPHVꢃ&(ꢄ +ꢆꢃWKHꢃYDOLGꢃFORFNꢃHGJHꢃRQꢃULVLQJꢃHGJHꢃDQGꢃ%/ ꢐꢃRUꢃꢀꢋꢁ
150
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
RL=5
CLK
tRCB
ADDRESS
Valid
Valid
tASVL
tAHV
tASVL
tAHV
tCKVH
tVSCK
tVSCK
tCKVH
ADV#
tVPL
tVHVL
tVPL
CE1#
Low
OE#
WE#
Low
High
LB#, UB#
WAIT#
DQ
tCKTV
tCKTV
tCKTX
tAC
tAC
tAC
tCKTX
QBL
Q1
tCKQX
tCKQX
Figure 71. 32M Synchronous Read Timing #3 (ADV# Control)
1RWHꢀꢃ7KLVꢃWLPLQJꢃGLDJUDPꢃDVVXPHVꢃ&(ꢄ +ꢆꢃWKHꢃYDOLGꢃFORFNꢃHGJHꢃRQꢃULVLQJꢃHGJHꢃDQGꢃ%/ ꢐꢃRUꢃꢀꢋꢁ
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
151
P r e l i m i n a r y
RL=5
CLK
ADDRESS
XXX7Fh
tASVL
tAHV
tCKVH
tVSCK
ADV#
CE1#
OE#
tVPL
tASCL
tCLCK
tOLQ
High
WE#
tBLQ
LB#, UB#
WAIT#
DQ
tCKTV
tCKTV
tCKTV
High-Z
High-Z
tCKTX
tOLTL
tCKTX
tAC
tAC
tCKTX
tAC
tAC
tAC
Q1
Q2
Q3
tOLZ
tCKQX
tCKQX
tCKQX
Figure 72. Synchronous Read - WAIT# Output Timing (Continuous Read)
1RWHꢀꢃ7KLVꢃWLPLQJꢃGLDJUDPꢃDVVXPHVꢃ&(ꢄ +ꢆꢃWKHꢃYDOLGꢃFORFNꢃHGJHꢃRQꢃULVLQJꢃHGJHꢃDQGꢃ%/ ꢐꢃRUꢃꢀꢋꢁ
152
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
RL=5
CLK
tRCB
ADDRESS
Valid
Valid
tASVL
tAHV
tCKVH
tASVL
tVSCK
tVSCK
tCKVH
ADV#
CE1#
tVPL
tVHVL
tVPL
tASCL
tASCL
tCLCK
tCLCK
tCKOH
tCP
OE#
WE#
tOLQ
High
tCKBH
tBLQ
LB#, UB#
tCKTV
tOHTZ
tOHZ
WAIT#
DQ
High-Z
High-Z
tOLTL
tCKTX
tAC
tAC
tAC
Q1
QBL
tOLZ
tCKQX
tCKQX
Figure 73. 64M Synchronous Read Timing #1 (OE# Control)
1RWHꢀꢃ7KLVꢃWLPLQJꢃGLDJUDPꢃDVVXPHVꢃ&(ꢄ +ꢆꢃWKHꢃYDOLGꢃFORFNꢃHGJHꢃRQꢃULVLQJꢃHGJHꢃDQGꢃ%/ ꢐꢃRUꢃꢀꢋꢁ
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
153
P r e l i m i n a r y
RL=5
CLK
tRCB
ADDRESS
Valid
Valid
tASVL
tAHV
tCKVH
tASVL
tAHV
tCKVH
tVSCK
tVSCK
ADV#
CE1#
tVPL
tVHVL
tVPL
tASCL
tASCL
tCP
tCLCK
tCKCLH
tCLCK
OE#
WE#
High
tCKBH
LB#, UB#
tCKTV
tCHTZ
tCLTL
WAIT#
DQ
tCLZ
tCLTL
tCKTX
tAC
tAC
tAC
tCHZ
Q1
QBL
tCLZ
tCKQX
tCKQX
Figure 74. 64M Synchronous Read Timing #2 (CE1# Control)
1RWHꢀꢃ7KLVꢃWLPLQJꢃGLDJUDPꢃDVVXPHVꢃ&(ꢄ +ꢆꢃWKHꢃYDOLGꢃFORFNꢃHGJHꢃRQꢃULVLQJꢃHGJHꢃDQGꢃ%/ ꢐꢃRUꢃꢀꢋꢁ
154
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
RL=5
CLK
tRCB
ADDRESS
Valid
Valid
tASVL
tAHV
tCKVH
tASVL
tAHV
tCKVH
tVSCK
tVSCK
ADV#
tVPL
tVHVL
tVPL
CE1#
Low
OE#
WE#
Low
High
LB#, UB#
WAIT#
DQ
tCKTV
tVLTL
tVLTL
tCKTX
tAC
tAC
tAC
Q1
QBL
tCKQX
tCKQX
Figure 75. 64M Synchronous Read Timing #3 (ADV# Control)
1RWHꢀꢃ7KLVꢃWLPLQJꢃGLDJUDPꢃDVVXPHVꢃ&(ꢄ +ꢆꢃWKHꢃYDOLGꢃFORFNꢃHGJHꢃRQꢃULVLQJꢃHGJHꢃDQGꢃ%/ ꢐꢃRUꢃꢀꢋꢁ
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
155
P r e l i m i n a r y
RL=5
CLK
tWCB
ADDRESS
Valid
Valid
tASVL
tAHV
tCKVH
tASVL
tAHV
tCKVH
tVSCK
tVSCK
tVHVL
tWRB
ADV#
CE1#
tVPL
tVPL
tCLCK
tASCL
tASCL
tCLCK
tCP
High
OE#
WE#
tWLD
tCKWH
tBS
tCKBH
tBS
LB#, UB#
WAIT#
DQ
High-Z
tWLTH
tDSCK
tDSCK
tDSCK
tWHTZ
D1
D2
DBL
tDHCK
tDHCK
Figure 76. Synchronous Write Timing #1 (WE# Level Control)
1RWHꢀꢃ7KLVꢃWLPLQJꢃGLDJUDPꢃDVVXPHVꢃ&(ꢄ +ꢆꢃWKHꢃYDOLGꢃFORFNꢃHGJHꢃRQꢃULVLQJꢃHGJHꢃDQGꢃ%/ ꢐꢃRUꢃꢀꢋꢁ
156
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
RL=5
CLK
tWCB
ADDRESS
Valid
Valid
tASVL
tAHV
tCKVH
tASVL
tAHV
tCKVH
tVSCK
tVSCK
tVHVL
tWRB
ADV#
CE1#
tVPL
tVPL
tCLCK
tASCL
tASCL
tCLCK
tCP
tCKCLH
High
OE#
WE#
tWSCK
tCKWH
tWSCK
tCKWH
tBS
tCKBH
tBS
LB#, UB#
WAIT#
High-Z
tWLTH
tDSCK
tDSCK
tDSCK
tCHTZ
tWLTH
D1
D2
DBL
DQ
tDHCK
tDHCK
Figure 77. Synchronous Write Timing #2 (WE# Single Clock Pulse Control)
1RWHꢀꢃ7KLVꢃWLPLQJꢃGLDJUDPꢃDVVXPHVꢃ&(ꢄ +ꢆꢃWKHꢃYDOLGꢃFORFNꢃHGJHꢃRQꢃULVLQJꢃHGJHꢃDQGꢃ%/ ꢐꢃRUꢃꢀꢋꢁ
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
157
P r e l i m i n a r y
RL=5
CLK
tWCB
ADDRESS
Valid
Valid
tASVL
tAHV
tCKVH
tASVL
tAHV
tCKVH
tVSCK
tVSCK
ADV#
CE1#
tVHVL
tVPL
tVPL
tWRB
High
OE#
WE#
tBS
tCKBH
tBS
LB#, UB#
WAIT#
DQ
High
tDSCK
tDSCK
tDSCK
D1
D2
DBL
tDHCK
tDHCK
Figure 78. Synchronous Write Timing #3 (ADV# Control)
1RWHꢀꢃ7KLVꢃWLPLQJꢃGLDJUDPꢃDVVXPHVꢃ&(ꢄ +ꢆꢃWKHꢃYDOLGꢃFORFNꢃHGJHꢃRQꢃULVLQJꢃHGJHꢃDQGꢃ%/ ꢐꢃRUꢃꢀꢋꢁ
158
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
RL=5
CLK
tWCB
ADDRESS
Valid
Valid
tASVL
tAHV
tCKVH
tASVL
tAHV
tCKVH
tVSCK
tVSCK
tVHVL
tWRB
ADV#
CE1#
tVPL
tVPL
tCLCK
tASCL
tASCL
tCLCK
tCP
High
OE#
WE#
tWLD
tCKWH
tBS
tCKBH
tBS
LB#, UB#
WAIT#
DQ
High-Z
tWLTH
tDSCK
tWHTZ
tWLTH
D1
tDHCK
Figure 79. Synchronous Write Timing #4 (WE# Level Control, Single Write)
1RWHVꢀ
ꢀꢁ 7KLVꢃWLPLQJꢃGLDJUDPꢃDVVXPHVꢃ&(ꢄ +ꢆꢃWKHꢃYDOLGꢃFORFNꢃHGJHꢃRQꢃULVLQJꢃHGJHꢃDQGꢃVLQJOHꢃZULWHꢃRSHUDWLRQꢁ
ꢄꢁ :ULWHꢃGDWDꢃLVꢃODWFKHGꢃRQꢃWKHꢃYDOLGꢃFORFNꢃHGJHꢁ
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
159
P r e l i m i n a r y
RL=5
CLK
tWCB
ADDRESS
Valid
tASVL
tVHVL
tAHV
tCKVH
tVSCK
ADV#
CE1#
tVPL
tCLCK
tCKCLH
tCKCLH
tASCL
tCP
OE#
WE#
LB#, UB#
WAIT#
DQ
tCKBH
tBS
tCKBH
tCHTZ
tCKTV
tCHZ
tCLTH
tAC
tCKTX
QBL
tDSCK
tDSCK
tDSCK
tDSCK
QBL-1
D1
D2
D3
DBL
tDHCK
tDHCK
tDHCK
tDHCK
tCKQX
tCKQX
Figure 80. 32M Synchronous Read to Write Timing #1(CE1# Control)
1RWHꢀꢃ7KLVꢃWLPLQJꢃGLDJUDPꢃDVVXPHVꢃ&(ꢄ +ꢆꢃWKHꢃYDOLGꢃFORFNꢃHGJHꢃRQꢃULVLQJꢃHGJHꢃDQGꢃ%/ ꢐꢃRUꢃꢀꢋꢁ
160
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
RL=5
CLK
ADDRESS
Valid
tASVL
tAHV
tVSCK
tCKVH
ADV#
CE1#
tVPL
tVHVL
tCKOH
OE#
tWLD
tCKWH
WE#
tCKBH
tBS
tCKBH
LB#, UB#
tOHTZ
tCKTV
WAIT#
DQ
tOHZ
tAC
tCKTX
tWLTH
tDSCK
tDSCK
tDSCK
tDSCK
QBL-1
QBL
D1
D2
D3
DBL
tDHCK
tDHCK
tDHCK
tDHCK
tCKQX
tCKQX
Figure 81. 32M Synchronous Read to Write Timing #2(ADV# Control)
1RWHꢀꢃ7KLVꢃWLPLQJꢃGLDJUDPꢃDVVXPHVꢃ&(ꢄ +ꢆꢃWKHꢃYDOLGꢃFORFNꢃHGJHꢃRQꢃULVLQJꢃHGJHꢃDQGꢃ%/ ꢐꢃRUꢃꢀꢋꢁ
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
161
P r e l i m i n a r y
RL=5
CLK
tWCB
ADDRESS
Valid
tASVL
tAHV
tCKVH
tVSCK
ADV#
tVHVL
tASCL
tVPL
tCLCK
tCKCLH
tCKCLH
CE1#
tCP
OE#
WE#
tCKBH
tBS
tCKBH
LB#, UB#
WAIT#
DQ
tCHTZ
tCHZ
tAC
tCLTH
tDSCK
tDSCK
tDSCK
tDSCK
QBL-1
QBL
D1
D2
D3
DBL
tDHCK
tDHCK
tDHCK
tDHCK
tCKQX
tCKQX
Figure 82. 64M Synchronous Read to Write Timing #1(CE1# Control)
1RWHꢀꢃ7KLVꢃWLPLQJꢃGLDJUDPꢃDVVXPHVꢃ&(ꢄ +ꢆꢃWKHꢃYDOLGꢃFORFNꢃHGJHꢃRQꢃULVLQJꢃHGJHꢃDQGꢃ%/ ꢐꢃRUꢃꢀꢋꢁ
162
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
RL=5
CLK
ADDRESS
Valid
tASVL
tAHV
tVSCK
tCKVH
ADV#
tVPL
tVHVL
CE1#
tCKOH
OE#
WE#
tWLD
tCKWH
tCKBH
tBS
tCKBH
LB#, UB#
WAIT#
DQ
tOHTZ
tOHZ
tAC
tWLTH
tDSCK
tDSCK
tDSCK
tDSCK
QBL-1
QBL
D1
D2
D3
DBL
tDHCK
tDHCK
tDHCK
tDHCK
tCKQX
tCKQX
Figure 83. 64M Synchronous Read to Write Timing #2(ADV# Control)
1RWHꢀꢃ7KLVꢃWLPLQJꢃGLDJUDPꢃDVVXPHVꢃ&(ꢄ +ꢆꢃWKHꢃYDOLGꢃFORFNꢃHGJHꢃRQꢃULVLQJꢃHGJHꢃDQGꢃ%/ ꢐꢃRUꢃꢀꢋꢁ
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
163
P r e l i m i n a r y
RL=5
CLK
tCKT
ADDRESS
Valid
tASVL
tAHV
tVSCK
tCKVH
ADV#
CE1#
tVPL
tASCL
tCKCLH
tCP
tCLCK
tWRB
OE#
WE#
tCKBH
LB#, UB#
tCKTV
High-Z
WAIT#
tDSCK
tDSCK
tCHTZ
tCLTL
tCKTX
tAC
tAC
DBL-1
DBL
Q1
Q2
DQ
tDHCK
tDHCK
tCLZ
tCKQX
tCKQX
Figure 84. Synchronous Write to Read Timing #1 (CE1# Control)
1RWHꢀꢃ7KLVꢃWLPLQJꢃGLDJUDPꢃDVVXPHVꢃ&(ꢄ +ꢆꢃWKHꢃYDOLGꢃFORFNꢃHGJHꢃRQꢃULVLQJꢃHGJHꢃDQGꢃ%/ ꢐꢃRUꢃꢀꢋꢁ
164
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
RL=5
CLK
tCKT
ADDRESS
Valid
tASVL
tVSCK
tAHV
tCKVH
ADV#
CE1#
tVPL
tWRB
Low
OE#
WE#
tOLQ
tCKWH
tCKBH
tBLQ
LB#, UB#
WAIT#
tCKTV
High-Z
tDSCK
tDSCK
tWHTZ
tOLTL
tCKTX
tAC
tAC
DBL-1
DBL
Q1
Q2
DQ
tDHCK
tDHCK
tOLZ
tCKQX
tCKQX
Figure 85. Synchronous Write to Read Timing #2 (ADV# Control)
1RWHꢀꢃ7KLVꢃWLPLQJꢃGLDJUDPꢃDVVXPHVꢃ&(ꢄ +ꢆꢃWKHꢃYDOLGꢃFORFNꢃHGJHꢃRQꢃULVLQJꢃHGJHꢃDQGꢃ%/ ꢐꢃRUꢃꢀꢋꢁ
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
165
P r e l i m i n a r y
CE1#
CE2
tCHS
tC2LH
tCHH
V
DD
VDD min
0V
Figure 86. Power-up Timing #1
1RWHꢀꢃ7KHꢃW
ꢃVSHFLILHVꢃDIWHUꢃ9 ꢃUHDFKHVꢃVSHFLILHGꢃPLQLPXPꢃOHYHOꢁ
&ꢄ/+
''
CE1#
tCHH
CE2
VDD
VDD min
0V
Figure 87. Power-up Timing #2
1RWHꢀꢃ7KHꢃW
ꢃVSHFLILHVꢃDIWHUꢃ9 ꢃUHDFKHVꢃVSHFLILHGꢃPLQLPXPꢃOHYHOꢃDQGꢃDSSOLFDEOHꢃWRꢃERWKꢃ&(ꢀ!ꢃDQGꢃ&(ꢄꢁ
&++
''
CE1#
tCHS
CE2
DQ
tCSP
tC2LP
tCHH (tCHHP)
High-Z
Power Down Entry
Power Down Mode
Power Down Exit
Figure 88. Power Down Entry and Exit Timing
1RWHꢀꢃ7KLVꢃ3RZHUꢃ'RZQꢃPRGHꢃFDQꢃEHꢃDOVRꢃXVHGꢃDVꢃDꢃUHVHWꢃWLPLQJꢃLIꢃWKHꢃ32:(5ꢂ83ꢃWLPLQJꢃDERYHꢃFRXOGꢃQRWꢃEHꢃVDWLVILHGꢃ
DQGꢃ3RZHUꢂ'RZQꢃSURJUDPꢃZDVꢃQRWꢃSHUIRUPHGꢃSULRUꢃWRꢃWKLVꢃUHVHWꢁ
166
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
CE1#
OE#
tCHOX
tCHWX
WE#
Active (Read)
Standby
Active (Write)
Standby
Figure 89. Standby Entry Timing after Read or Write
1RWHꢀꢃ%RWKꢃW
ꢃDQGꢃW
ꢃGHILQHꢃWKHꢃHDUOLHVWꢃHQWU\ꢃWLPLQJꢃIRUꢃ6WDQGE\ꢃPRGHꢁꢃ,IꢃHLWKHUꢃRIꢃWLPLQJꢃLVꢃQRWꢃVDWLVILHGꢆꢃLWꢃWDNHVꢃ
&+2;
&+:;
W
ꢃꢎPLQꢏꢃSHULRGꢃIRUꢃ6WDQGE\ꢃPRGHꢃIURPꢃ&(ꢀ!ꢃ/RZꢃWRꢃ+LJKꢃWUDQVLWLRQꢁ
5&
tRC
tWC
tWC
tWC
tWC
tRC
MSB*1
MSB*1
MSB*1
MSB*1
MSB*1
Key*2
ADDRESS
tCP*3
(tRC)
tCP
tCP
tCP
tCP
tCP
CE1#
OE#
WE#
LB#, UB#
DQ*3
RDa
Cycle #1
RDa
Cycle #2
RDa
Cycle #3
X
X
RDb
Cycle #6
Cycle #4
Cycle #5
Figure 90. Configuration Register Set Timing #1 (Asynchronous Operation)
1RWHVꢀ
ꢀꢁ 7KHꢃDOOꢃDGGUHVVꢃLQSXWVꢃPXVWꢃEHꢃ+LJKꢃIURPꢃ&\FOHꢃ!ꢀꢃWRꢃ!ꢊꢁ
ꢄꢁ 7KHꢃDGGUHVVꢃNH\ꢃPXVWꢃFRQILUPꢃWKHꢃIRUPDWꢃVSHFLILHGꢃLQꢃWKHꢃꢙ)XQFWLRQDOꢃ'HVFULSWLRQꢙꢃVHFWLRQꢁꢃ,IꢃQRWꢆꢃWKHꢃRSHUDWLRQꢃDQGꢃGDWDꢃDUHꢃ
QRWꢃJXDUDQWHHGꢁ
ꢅꢁ $IWHUꢃW&3ꢃRUꢃW5&ꢃIROORZLQJꢃ&\FOHꢃ!ꢋꢆꢃWKHꢃ&RQILJXUDWLRQꢃ5HJLVWHUꢃ6HWꢃLVꢃFRPSOHWHGꢃDQGꢃUHWXUQHGꢃWRꢃWKHꢃQRUPDOꢃRSHUDWLRQꢁꢃW&3ꢃDQGꢃ
W5&ꢃDUHꢃDSSOLFDEOHꢃWRꢃUHWXUQLQJꢃWRꢃDV\QFKURQRXVꢃPRGHꢃDQGꢃWRꢃV\QFKURQRXVꢃPRGHꢃUHVSHFWLYHO\ꢁ
ꢈꢁ %\WHꢃUHDGꢃRUꢃZULWHꢃLVꢃDYDLODEOHꢃLQꢃDGGLWLRQꢃWRꢃ:RUGꢃUHDGꢃRUꢃZULWHꢁꢃ$WꢃOHDVWꢃRQHꢃE\WHꢃFRQWUROꢃVLJQDOꢃꢎ/%!ꢃRUꢃ8%!ꢏꢃQHHGꢃWRꢃEHꢃ
/RZꢁ
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
167
P r e l i m i n a r y
CLK
ADDRESS
MSB
MSB
MSB
MSB
MSB
Key
tRCB
tWCB
tWCB
tWCB
tWCB
tRCB
ADV#
CE1#
tTRB
tTRB
tTRB
tTRB
tTRB
tTRB
OE#
WE#
LB#, UB#
WAIT#
RL
RL-1
RDa
Cycle#2
RL-1
RDa
Cycle#3
RL-1
RL-1
RL
RDa
X
X
RDb
Cycle#6
DQ
Cycle#1
Cycle#4
Cycle#5
Figure 91. Configuration Register Set Timing #2 (Synchronous Operation)
1RWHVꢀ
ꢀꢁ 7KHꢃDOOꢃDGGUHVVꢃLQSXWVꢃPXVWꢃEHꢃ+LJKꢃIURPꢃ&\FOHꢃ!ꢀꢃWRꢃ!ꢊꢁ
ꢄꢁ 7KHꢃDGGUHVVꢃNH\ꢃPXVWꢃFRQILUPꢃWKHꢃIRUPDWꢃVSHFLILHGꢃLQꢃWKHꢃꢙ)XQFWLRQDOꢃ'HVFULSWLRQꢙꢃVHFWLRQꢁꢃ,IꢃQRWꢆꢃWKHꢃRSHUDWLRQꢃDQGꢃGDWDꢃDUHꢃ
QRWꢃJXDUDQWHHGꢁ
ꢅꢁ $IWHUꢃW75%ꢃIROORZLQJꢃ&\FOHꢃ!ꢋꢆꢃWKHꢃ&RQILJXUDWLRQꢃ5HJLVWHUꢃ6HWꢃLVꢃFRPSOHWHGꢃDQGꢃUHWXUQHGꢃWRꢃWKHꢃQRUPDOꢃRSHUDWLRQꢁ
ꢈꢁ %\WHꢃUHDGꢃRUꢃZULWHꢃLVꢃDYDLODEOHꢃLQꢃDGGLWLRQꢃWRꢃ:RUGꢃUHDGꢃRUꢃZULWHꢁꢃ$WꢃOHDVWꢃRQHꢃE\WHꢃFRQWUROꢃVLJQDOꢃꢎ/%!ꢃRUꢃ8%!ꢏꢃQHHGꢃWRꢃEHꢃ
/RZꢁ
168
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
COSMORAM Type 1 – 1.8 V, 16 Mb
CMOS 1,048,576-Word x 16 Bit pSRAM
PRELIMINARY
Features
$V\QFKURQRXVꢀ65$0ꢀ,QWHUIDFH
)DVWꢀ5DQGRPꢀ$FFHVVꢀ7LPH
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General Description
7KHꢀ&26025$0ꢀ7\SHꢀꢈꢀLVꢀDꢀ&026ꢀS65$0ꢀZLWKꢀDV\QFKURQRXVꢀ6WDWLFꢀ5DQGRPꢀ$FFHVVꢀ0HPRU\ꢀ
ꢁ65$0ꢂꢀLQWHUIDFHꢀFRQWDLQLQJꢀꢈꢉꢄꢋꢋꢋꢄꢎꢈꢉꢀVWRUDJHVꢀDFFHVVLEOHꢀLQꢀDꢀꢈꢉꢅELWꢀIRUPDWꢃꢀ7KLVꢀ&26025$0ꢀ
7\SHꢀꢈꢀLVꢀVXLWHGꢀIRUꢀPRELOHꢀDSSOLFDWLRQVꢀVXFKꢀDVꢀ&HOOXODUꢀ+DQGVHWꢀDQGꢀ3'$ꢃ
Publication Number S71WS-J_04 Revision A Amendment 2 Issue Date August 19, 2005
P r e l i m i n a r y
Pin Description
3LQꢀ1DPH
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:ULWHꢀ(QDEOHꢀꢁ/RZꢀ$FWLYHꢂꢀ
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8SSHUꢀ%\WHꢀ&RQWUROꢀꢁ/RZꢀ$FWLYHꢂꢀ
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170
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Function Truth Table
'DWDꢀ
5HWHQWLRQ
0RGH
&(ꢐ &(ꢒꢄ :(ꢒ 2(ꢒ /%ꢒ 8%ꢒ
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+
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2XWSXWꢀ'LVDEOHꢀꢁ1RWHꢀꢈꢂ
2XWSXWꢀ'LVDEOHꢀꢁ1Rꢀ5HDGꢂ
+
+
ꢁ1RWHꢀꢑꢂ +LJKꢅ=
9DOLG
9DOLG
9DOLG
9DOLG
+LJKꢅ=
2XWSXW
9DOLG
5HDGꢀꢁ8SSHUꢀ%\WHꢂ
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+
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S71WS-J Based MCPs
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P r e l i m i n a r y
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COSMORAM Type 1 Revision Summary
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Revision A0 (October 27, 2004)
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The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary
industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that
includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal
injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and
artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-
mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels
and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on ex-
port under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the
prior authorization by the respective government entity will be required for export of those products.
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The contents of this document are subject to change without notice. This document may contain information on a Spansion LLC product under development
by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided
as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement
of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the
use of the information in this document.
Copyright ©2004-2005 Spansion LLC. All rights reserved. Spansion, the Spansion logo, and MirrorBit are trademarks of Spansion LLC. Other company and
product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
184
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
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