S72NS128PE0AJGLG0 [SPANSION]
MirrorBit Flash Memory and DRAM; MirrorBit闪存和DRAM
| 型号： | S72NS128PE0AJGLG0 |
| 厂家： | 
SPANSION |
| 描述： | MirrorBit Flash Memory and DRAM |
| 文件： | 总14页 (文件大小：463K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S72NS-P Based MCPs/PoPs
MirrorBit™ Flash Memory and DRAM
128/256/512 Mb (8/16/32 M x 16 bit), 1.8 Volt-only,
Multiplexed Simultaneous Read/Write, Burst Mode Flash
Memory
S72NS-P Based MCPs/PoPs Cover Sheet
128/256 Mb (8/16 M x 16 bit) DDR DRAM on Split Bus
Data Sheet (Advance Information)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S72NS-P_00
Revision 01
Issue Date September 6, 2006
D a t a S h e e t
( A d v a n c e I n f o r m a t i o n )
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has been
completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or V range. Changes may also include those needed to clarify a
IO
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume such
that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local Spansion sales office.
ii
S72NS-P Based MCPs/PoPs
September 6, 2006 S72NS-P_00-01
S72NS-P Based MCPs/PoPs
MirrorBit™ Flash Memory and DRAM
128/256/512 Mb (8/16/32 M x 16 bit), 1.8 Volt-only,
Multiplexed Simultaneous Read/Write, Burst Mode Flash
Memory
128/256 Mb (8/16 M x 16 bit) DDR DRAM on Split Bus
Data Sheet (Advance Information)
Features
Power supply voltage of 1.7 V to 1.95 V
Packages
– 11.0 x 10.0 mm, 133-ball MCP
Burst Speeds
– 8.0 x 8.0 mm, 133-ball MCP
– 12.0 x 12.0 mm, 128-ball PoP
– Flash = 66 MHz, 80 MHz
– DRAM = 133 MHz
Operating Temperature of –25°C to +85°C
General Description
This document contains information on the S72NS-P MCP stacked products. Refer to the S29NS-P data sheet (S29NS-P_00)
for full electrical specifications of the Flash memory component.
The S72NS Series is a product line of stacked products (MCPs and PoPs), and consists of:
NS family multiplexed Flash memory die
DDR DRAM
The products covered by this document are listed in the tables below.
DRAM Density
Flash Density
128 Mb
128 Mb
256 Mb
S72NS128PD0
S72NS256PD0
S72NS512PD0
256 Mb
512 Mb
S72NS512PE0
For detailed specifications, please refer to the individual data sheets.
Density
Manufacturer
DRAM1
Publication Number
SDRAM_03
128
DRAM5
SDRAM_07
Density
Manufacturer
DRAM1
Publication Number
TBD
256
DRAM5
SDRAM_11
Publication Number S72NS-P_00
Revision 01
Issue Date September 6, 2006
This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in
this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.
D a t a S h e e t
( A d v a n c e I n f o r m a t i o n )
1. Product Selector Guide
Flash
DDR DRAM Flash Speed
DDR DRAM
Device OPN
Density
Density
(MHz)
66
80
66
80
66
80
66
80
66
80
66
80
66
80
66
80
66
80
66
80
66
80
66
80
66
80
66
80
66
80
66
80
Speed (MHz)
Supplier
Package
S72NS128PD0AJBGG
S72NS128PD0AJBGC
S72NS128PD0AJBLG
S72NS128PD0AJBLC
S72NS128PD0KJFGG
S72NS128PD0KJFGC
S72NS128PD0KJFLG
S72NS128PD0KJFLC
S72NS256PD0AJBGG
S72NS256PD0AJBGC
S72NS256PD0AJBLG
S72NS256PD0AJBLC
S72NS256PD0KJFGG
S72NS256PD0KJFGC
S72NS256PD0KJFLG
S72NS256PD0KJFLC
S72NS512PD0AJGGG
S72NS512PD0AJGGC
S72NS512PD0AJGLG
S72NS512PD0AJGLC
S72NS512PD0KJFGG
S72NS512PD0KJFGC
S72NS512PD0KJFLG
S72NS512PD0KJFLC
S72NS512PE0AJGGG
S72NS512PE0AJGGC
S72NS512PE0AJGLG
S72NS512PE0AJGLC
S72NS512PE0KJFGG
S72NS512PE0KJFGC
S72NS512PE0KJFLG
S72NS512PE0KJFLC
DRAM1
128 Mb
128 Mb
256 Mb
256 Mb
512 Mb
512 Mb
512 Mb
512 Mb
128 Mb
133
133
133
133
133
133
133
133
8.0 x 8.0mm133-ball MCP
DRAM5
DRAM1
DRAM5
DRAM1
DRAM5
DRAM1
DRAM5
DRAM1
DRAM5
DRAM1
DRAM5
DRAM1
DRAM5
DRAM1
DRAM5
128 Mb
128 Mb
128 Mb
128 Mb
128 Mb
256 Mb
256 Mb
12.0 x 12.0mm 128-ball PoP
8.0 x 8.0mm133-ball MCP
12.0 x 12.0mm 128-ball PoP
11.0 x 10.0mm 133-ball MCP
12.0 x 12.0mm 128-ball PoP
11.0 x 10.0mm 133-ball MCP
12.0 x 12.0mm 128-ball PoP
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S72NS-P Based MCPs/PoPs
S72NS-P_00_01 September 6, 2006
D a t a S h e e t
( A d v a n c e I n f o r m a t i o n )
2. Product Block Diagram
F-RST#
F-ACC
RST#
ACC
A15-A0
ADQ15-ADQ0
DQ15-DQ0
CLK
F-CLK
F-RDY
F-WP#
WP#
MUX
Flash
Memory
NS-P
RDY
F-CE#
F-OE#
CE#
OE#
Amax - A16
Amax - A16
F-WE#
WE#
VCC
F-VCC
AVD#
F-VSS
AVD#
VSS
VCCQ
F-VCCQ
F2-CE#
CLK
CLK#
D-CLK
D-RAS#
D-CAS#
RAS#
CAS#
D-CLK#
DQS0
D-LDQS
D-UDQS
D-LDQM
D-UDQM
D-TEST
D-DQ15 - D-DQ0
D-VSS
BA0
BA1
CKE
WE#
D-BA0
D-BA1
D-CKE
D-WE#
D-CE#
DQS1
DDR
DRAM
Memory
LDQM
UDQM
TEST
DQ15-DQ0
VSS
CE#
D-Amax - D-A0
VSSQ
D-VSSQ
VCC
D-VCC
VCCQ
D-VCCQ
Notes:
1. Amax indicates highest address bit for memory component:
a. Amax = A24 for NS512P, A23 for NS256P, A22 for NS128P
b. Amax = A11 for 128 Mb DDR DRAM
c. Amax = A12 for 256Mb DDR DRAM
2. For Flash, A15 - A0 is tied to DQ15 - DQ0.
S72NS-P_00_01 September 6, 2006
S72NS-P Based MCPs/PoPs
3
D a t a S h e e t
( A d v a n c e I n f o r m a t i o n )
3. Connection Diagrams
Figure 3.1 133-ball Fine-Pitch Ball Grid Array MCP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Legend
A
B
C
D
E
F
Index Location
DNU
DNU D-VSSQ D-VCCQ D-DQ9 D-DQ8 D-VSS D-VCC D-VCC D-DQ5 D-DQ3 D-VSSQ DNU
DNU
DNU D-VSS D-DQ13 D-UDQS D-DQ10 D-VSSQ D-VCCQD-VCCQD-LDQM D-DQ6 D-DQ4 D-DQ1 D-VCCQ DNU
D-VCC D-DQ15 D-DQ14 D-DQ12 D-DQ11 D-UDQM D-VSS D-VCC D-VSSQ D-DQ7 D-LDQS D-DQ2 D-DQ0 D-VSS
Do Not Use
No Connect
RFU
A24
A23
NC
A22
A19
NC
A17
A18
INDEX
F-OE# ADQ8 D-VCC
ADQ9 ADQ1 ADQ0
F-VSS ADQ3 ADQ2
F-VCCQ ADQ11 ADQ10
ADQ13 ADQ12 ADQ4
F-VSS F-VSS ADQ5
DRAM Only
Code Flash Only
Reserved for Future Use
G
F-CE# F-WP# F-WE#
F-ACC F-VCC F-CLK
H
J
A16
F-VSS
NC
NC
K
L
A21 F-AVD#
NC
ADQ7 ADQ6
A20 F-RST# D-CE#
F-VCCQ ADQ15 ADQ14
M
N
NC
NC
D-A3
D-A6
D-A9 D-CKE D-VSS D-WE# D-A10
D-A8 D-CAS# D-CLK# D-BA1 D-A11
D-A1
D-A2
NC
NC
NC
F-RDY F-VSS
F-VCC DNU
DNU D-VSS D-VCC D-A5
D-A12
P
DNU
DNU
NC
D-A4
D-A7 D-RAS# D-CLK D-VCC D-BA0 D-A0 D-VCC D-VSS DNU
DNU
Note:
Additional NC locations are in reference to the superset connection diagram shown here
Device OPN
S72NS128PD0
S72NS256PD0
S72NS512PD0
S72NS512PE0
Flash Address Amax
DDR DRAM Address Amax
Additional NC Locations
Ball F1, Ball E1, Ball N11
Ball E1, Ball N11
Ball N11
A22
A23
A24
A24
A11
A11
A11
A12
N/A
4
S72NS-P Based MCPs/PoPs
S72NS-P_00_01 September 6, 2006
D a t a S h e e t
( A d v a n c e I n f o r m a t i o n )
Figure 3.2 128-ball Fine-Pitch Ball Grid Array, PoP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Legend
A
B
C
D
E
F
NC
NC
NC
NC
ADQ8 ADQ9 ADQ10 ADQ11 ADQ12 ADQ13 ADQ14 ADQ15 D-VSS D-VSS D-VCCQD-VCCQ D-VCC D-VCC D-VSSQ NC
NO Connect
ADQ0 ADQ1 ADQ2 ADQ3 ADQ4 ADQ5 ADQ6 ADQ7 F-CLK D-VSS D-VCCQD-VCCQD-VCCQ D-VCC
NC D-VSSQ
D-VSSQ D-VSSQ
D-UDQS D-DQ15
D-DQ13 D-DQ14
D-DQ11 D-DQ12
D-DQ9 D-DQ10
D-DQ8 D-UDQM
D-CLK D-CLK#
LDQM D-DQ07
D-DQ6 D-DQ5
D-DQ4 D-DQ3
D-DQ2 D-DQ1
D-DQ0 D-LDQS
D-VCCQ D-VSSQ
D-VCC D-VSSQ
NOR Flash Only
DDR DRAM Only
F-AVD# F-OE#
F-RST# F-RDY
F-VCCQ F-WE#
F-VCCQ F-VSS
F-VSS F-VSS
F-VSS F-VSS
F-VSS F-VSS
A23 F1-CE#
G
H
J
K
L
A20
A21
A18
A16
A19
M
N
F-ACC
P
R
T
F-VCC F-VCC
A17
NC
A22
A24
NC
U
F-WP#
NC
NC
NC
NC
NC
D-CE# D-A3
D-A1
D-A10 D-CKE D-A12 D-A11 D-WE# D-A9
D-A7 D-CAS# D-A5
D-A8 D-RAS# D-A6
NC
D-VSS
NC
V
NC
D-VCC D-VCC D-A2
D-A0 D-BA1 D-BA0 D-VSS D-VSS
NC
D-A4
Note:
Additional NC locations are in reference to the superset connection diagram shown here.
Device OPN
S72NS128PD0
S72NS256PD0
S72NS512PD0
S72NS512PE0
Flash Address Amax
DDR DRAM Address Amax
Additional NC Locations
Ball K1, Ball T2, Ball U10
Ball K1, Ball U10
Ball U10
A22
A23
A24
A24
A11
A11
A11
A12
N/A
S72NS-P_00_01 September 6, 2006
S72NS-P Based MCPs/PoPs
5
D a t a S h e e t
( A d v a n c e I n f o r m a t i o n )
4. Input/Output Descriptions
Signal
Amax – A16
ADQ15 – ADQ0
F-CE#
Description
Flash
DRAM
=
=
=
=
=
=
=
=
=
Flash Address inputs
Flash multiplexed Address and Data
Flash Chip-enable input. Asynchronous relative to CLK for Burst Mode
Flash Output Enable input. Asynchronous relative to CLK for Burst mode.
Flash Write Enable input
X
X
X
X
X
X
F-OE#
F-WE#
F-VCC
Flash device power supply (1.7 V to 1.95 V)
Flash Input/Output Buffer power supply
Flash Ground
F-VCCQ
F-VSS
Flash ready output. Indicates the status of the Burst read. VOL = data invalid. VOH
= data valid.
F-RDY
X
=
Flash Clock. The first rising edge of CLK in conjunction with AVD# low latches the
address input and activates burst mode operation. After the initial word is output,
subsequent rising edges of CLK increment the internal address counter. CLK
should remain low during asynchronous access.
F-CLK
X
=
Flash Address Valid input. Indicates to device that the valid address is present on
the address inputs. VIL = for asynchronous mode, indicates valid address; for burst
mode, causes starting address to be latched on rising edge of CLK. VIH= device
ignores address inputs
F-AVD#
X
F-RST#
F-WP#
=
=
Flash hardware reset input. VIL= device resets and returns to reading array data
X
X
Flash hardware write protect input. VIL = disables program and erase functions in
the four outermost sectors
=
Flash accelerated input. At VHH, accelerates programming; automatically places
device in unlock bypass mode. At VIL, disables all program and erase functions.
Should be at VIH for all other conditions.
F-ACC
X
D-A12 – D-A0
D-DQ15 – D-DQ0
D-CLK
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
DRAM Address inputs.
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
DRAM Data input/output
DRAM System Clock
D-CE#
DRAM Chip Select
D-CKE
DRAM Clock Enable
D-BA1 – BA0
D-RAS#
D-CAS#
D-UDQM – D-LDQM
D-WE#
DRAM Bank Select
DRAM Row Address Strobe
DRAM Column Address Strobe
DRAM Data Input Mask
DRAM Write Enable input
D-VSS
DRAM Ground
D-VSSQ
D-VCCQ
D-VCC
DRAM Input/Output Buffer ground
DRAM Input/Output Buffer power supply
DRAM device power supply
D-UDQS
D-LDQS
D-CLK#
DRAM Upper Data Strobe, output with read data and input with write data
DRAM Lower Data Strobe, output with read data and input with write data
DDR Clock for negative edge of CLK
Reserved for Future Use
RFU
NC
No Connect. Can be connected to ground or left floating.
Do Not Use. This signal must be left floating
DNU
6
S72NS-P Based MCPs/PoPs
S72NS-P_00_01 September 6, 2006
D a t a S h e e t
( A d v a n c e I n f o r m a t i o n )
5. Ordering Information
The order number (Valid Combination) is formed by the following:
S72NS
256
P
D0
AJ
B
L
G
3
PACKING TYPE
0 = Tray
2 = 7-inch Tape and Reel
3 = 13-inch Tape and Reel
FLASH and DDR SPEED
G = 66 MHz Flash, 133 MHz DDR DRAM
C = 80 MHz Flash, 133 MHz DDR DRAM
DDR SUPPLIER
G = DRAM Type 1 x16 DDR DRAM
L = DRAM Type 5 x16 DDR DRAM
PACKAGE MODIFIER
G = 133-ball, 11x10mm, FBGA MCP
B = 133-ball, 8x8mm, FBGA MCP
F = 128-ball, 12x12mm, FBGA PoP
PACKAGE AND MATERIAL TYPE
AJ = Thin profile Fine-pitch BGA Pb-free LF35 MCP (0.5 mm pitch)
KJ = Thin profile Fine-pitch BGA Pb-free PoP (0.65 mm pitch)
DDR DRAM AND DATA FLASH DENSITY
D0 = 128 Mb DRAM, No Data Flash
E0 = 256 Mb DRAM, No Data Flash
PROCESS TECHNOLOGY
P = 90 nm, MirrorBitTM Technology
CODE FLASH DENSITY
512 = 512 Mb
256 = 256 Mb
128 = 128 Mb
PRODUCT FAMILY
S72NS Multi-Chip Product (MCP)
1.8 V Multiplexed, SRW, Burst Mode Flash and DDR DRAM on Split Bus
Valid Combinations
DRAM
Code Flash
Density
(Mb)
Product
Family
Process
Technology
Density
(Mb)
Package Type/
Material
Flash & DDR
Speed
Packing
Type
DDR Vendor
128
256
512
G, C
D0
AJB, KJF
AJG, KJF
0, 2, 3
(Note 1)
S72NS
P
G, L
G, C
D0, E0
Notes:
1. Packing Type 0 is standard. Specify other options as required.
2. BGA package marking omits leading “S” and packing type designator from ordering part number.
3. Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid
combinations and to check on newly released combinations.
S72NS-P_00_01 September 6, 2006
S72NS-P Based MCPs/PoPs
7
D a t a S h e e t
( A d v a n c e I n f o r m a t i o n )
6. Physical Dimensions
6.1
NLC133—133-ball Fine-Pitch Ball Grid Array (FBGA) 11.0 x 10.0 mm
NOTES:
PACKAGE
JEDEC
NLC 133
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
11.0 mm x 10.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
NOM
1.00
MAX
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
0.90
0.20
0.70
10.9
9.9
1.10
0.30
0.82
11.1
10.1
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.25
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
0.76
BODY THICKNESS
BODY SIZE
D
11.0
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
10.0
BODY SIZE
D1
E1
6.50 BSC.
6.50 BSC.
14
MATRIX FOOTPRINT
MATRIX FOOTPRINT
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
14
133
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
Øb
eE
0.25
0.30
0.35
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
0.50 BSC.
0.50 BSC
0.25 BSC.
BALL PITCH
eD
SD / SE
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
D5-D11, E4-E11, F4-F11
G4-G11, H4-H11, J4-J11
K4-K11, L4-L11
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3436 \ 16-039.22 \ 12.09.04
8
S72NS-P Based MCPs/PoPs
S72NS-P_00_01 September 6, 2006
D a t a S h e e t
( A d v a n c e I n f o r m a t i o n )
6.2
NSC133—133-ball Fine-Pitch Ball Grid Array (FBGA) 8.0 x 8.0 mm
NOTES:
PACKAGE
JEDEC
NSC 133
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
8.00 mm x 8.00 mm
PACKAGE
NOTE
3. BALL POSITION DESIGNATION PER JESD 95-1
SPP-010.
SYMBOL
MIN
NOM
1.00
MAX
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
0.90
0.20
0.70
1.10
0.30
0.82
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.25
BALL HEIGHT
A2
0.76
BODY THICKNESS
BODY SIZE
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
D
8.00 BSC
8.00 BSC
6.50 BSC.
6.50 BSC.
14
E
BODY SIZE
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
D1
E1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
MD
ME
n
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
14
133
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
Øb
eE
0.25
0.30
0.35
BALL DIAMETER
BALL PITCH
0.50 BSC.
0.50 BSC
0.25 BSC.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
eD
SD / SE
BALL PITCH
SOLDER BALL PLACEMENT
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
D5-D11,E4-E11,F4-F11,G4-G11 DEPOPULATED SOLDER BALLS
H4-H11,J4-J11,K4-K11,L4-L11
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3583 \ 16-039.22 \ 8.15.06
S72NS-P_00_01 September 6, 2006
S72NS-P Based MCPs/PoPs
9
D a t a S h e e t
( A d v a n c e I n f o r m a t i o n )
6.3
ALJ128—128-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 12.0 mm
A
D
PIN A1
CORNER
D1
PIN A1
CORNER
9
eD
SD
7
INDEX MARK
A
B
C
D
E
F
SE
7
G
H
J
E
B
E1
K
L
M
N
P
R
T
eE
U
V
0.10
(2X)
C
18 17 16 15 14 13 12 11 10
9
7
6
8
5
4
3
2
1
BOTTOM VIEW
0.10
(2X)
C
TOP VIEW
0.10
0.10
C
C
A2
A
A1
C
SIDE VIEW
6
128X
b
0.15
0.08
M
C
C
A
B
M
NOTES:
PACKAGE
JEDEC
ALJ 128
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
D x E
12.00 mm x 12.00 mm
PACKAGE
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JEP95, SECTION
3.0, SPP-010.
SYMBOL
MIN
NOM
---
MAX
NOTE
A
A1
A2
D
---
1.15
---
PROFILE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
0.35
0.60
---
BALL HEIGHT
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
---
0.72
BODY THICKNESS
BODY SIZE
12.00 BSC.
12.00 BSC.
11.05 BSC.
11.05 BSC.
18
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
E
BODY SIZE
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
D1
E1
MD
ME
n
MATRIX FOOTPRINT
MATRIX FOOTPRINT
N IS THE MAXIMUM NUMBER OF BALLS ON THE FBGA PACKAGE.
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
18
128
DATUM C IS THE SEATING PLANE AND IS DEFINED BY THE
CROWNS OF THE SOLDER BALLS.
N
128
MAXIMUM NUMBER OF BALLS
NUMBER OF LAND PERIMETERS
BALL DIAMETER
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
R
2
Øb
eE
eD
SE / SD
0.40
0.45
0.50
0.65 BSC.
0.65 BSC
0.325 BSC.
BALL PITCH
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
BALL PITCH
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
C3~C16, D3~D16, E3~E16, F3~F16
G3~G16, H3~H16, J3~J16, K3~K16
L3~L16, M3~M16, N3~N16, P3~P16
R3~R16, T3~T16
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
10 OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.
3561 16 038 24 \ 5 15 6
10
S72NS-P Based MCPs/PoPs
S72NS-P_00_01 September 6, 2006
D a t a S h e e t
( A d v a n c e I n f o r m a t i o n )
6.4
ASF128—128-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 12.0 mm
NOTES:
PACKAGE
JEDEC
ASF128
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
D x E
12.00 mm x 12.00 mm
PACKAGE
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JEP95, SECTION
3.0, SPP-010.
SYMBOL
MIN
NOM
1.05
MAX
NOTE
A
A1
A2
D
0.95
0.35
0.59
1.15
0.45
0.72
PROFILE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
0.40
BALL HEIGHT
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
---
BODY THICKNESS
12.00 BSC.
12.00 BSC.
11.05 BSC.
11.05 BSC.
18
BODY SIZE
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
E
BODY SIZE
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
D1
E1
MD
ME
n
MATRIX FOOTPRINT
MATRIX FOOTPRINT
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
N IS THE MAXIMUM NUMBER OF BALLS ON THE FBGA PACKAGE.
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
18
128
DATUM C IS THE SEATING PLANE AND IS DEFINED BY THE
CROWNS OF THE SOLDER BALLS.
N
128
MAXIMUM NUMBER OF BALLS
NUMBER OF LAND PERIMETERS
BALL DIAMETER
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
R
2
Øb
eE
eD
SE / SD
0.40
0.45
0.50
0.65 BSC.
0.65 BSC
0.325 BSC.
BALL PITCH
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
BALL PITCH
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
C3-C16,D3-D16,E3-E16,
F3-F16,G3-G16,H3-H16,
J3-J16,K3-K16,L3-L16,
M3-M16,N3-N16,P3-P16,
R3-R16,T3-T16
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
10 OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.
3581\16-039.24\8.3.6
S72NS-P_00_01 September 6, 2006
S72NS-P Based MCPs/PoPs
11
D a t a S h e e t
( A d v a n c e I n f o r m a t i o n )
7. Revision History
7.1
Revision 01 (September 6, 2006)
Initial release.
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,
the prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any
damages of any kind arising out of the use of the information in this document.
Copyright © 2006 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, and combinations thereof are
trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.
12
S72NS-P Based MCPs/PoPs
S72NS-P_00_01 September 6, 2006
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