S75PL127JCFBAWB0_技术文档

S75PL127J MCPs

Stacked Multi-Chip Product (MCP)

CODE Flash, pSRAM and DATA Flash 128M (8M x 16-Bit CMOS 3.0 Volt-

Only, Simultaneous Operation, Page Mode CODE Flash Memory, with

64M/32M (4M/2M x 16-Bit) pSRAM and 512M/256/128M (32M/16M/8M x 16-

Bit) Data Flash Memory

ADVANCE

INFORMATION

Data Sheet

Package

— 9 x 12 mm 84 ball FBGA

MCP Features

Power supply voltage of 2.7 to 3.1 volt

High Performance

Operating Temperature

— 65ns for PL-J, 70ns for pSRAM, and 110ns for GL-N

— Page access - 25ns

— –25°C to +85°C (Wireless)

Other temperature grade options

— Please contact the factory through the local sales

support team

General Description

The 75PL Series is a product line of stacked Multi-Chip Product (MCP) packages

and consists of:

One S29PL127J based CODE Flash device(s)

pSRAM

One or more S29GLxxxN based DATA Flash device(s)

32M pSRAM

Density

128M

Data Flash

256M

128M

512M

Code Flash

S75PL127JBD

S75PL127JBE

S75PL127JBF

64M pSRAM

Data Flash

256M

Density

128M

512M

Code Flash

S75PL127JCD S75PL127JCE

S75PL127JCF

Publication Number S75PL127J_00 Revision A Amendment 1 Issue Date January 6, 2005

A d v a n c e I n f o r m a t i o n

Low VCC Write Inhibit ................................................................................39

S75PL127J MCPs .................................................1

General Description ...................................................1

Product Selector Guide ............................................ 5

MCP Block Diagram ................................................ 6

Connection Diagram ................................................ 7

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Ordering Information ...............................................9

Valid Combinations .................................................10

Write Pulse “Glitch” Protection ...............................................................39

Logical Inhibit ...................................................................................................39

Power-Up Write Inhibit ...............................................................................39

Common Flash Memory Interface (CFI) ............ 40

Table 9. CFI Query Identification String ................................ 40

Table 10. System Interface String ........................................ 41

Table 11. Device Geometry Definition ................................... 41

Table 12. Primary Vendor-Specific Extended Query ................ 42

Command Definitions .............................................44

Reading Array Data ...........................................................................................44

Reset Command .................................................................................................44

Autoselect Command Sequence ....................................................................45

Enter SecSi™ Sector/Exit SecSi Sector Command Sequence ................45

Word Program Command Sequence ...........................................................45

Unlock Bypass Command Sequence ........................................................46

Figure 4. Program Operation............................................... 47

Chip Erase Command Sequence ...................................................................47

Sector Erase Command Sequence ................................................................48

Figure 5. Erase Operation................................................... 49

Erase Suspend/Erase Resume Commands ..................................................49

Command Definitions Tables .........................................................................50

Table 13. Memory Array Command Definitions ...................... 50

Table 14. Sector Protection Command Definitions .................. 51

Write Operation Status ........................................ 52

Data: S29GL128N ................................................................................................10

Data: S29GL256N ................................................................................................ 11

Data: S29GL512N ............................................................................................... 12

S29PL127J/S29PL064J/S29PL032J for MCP .....13

General Description .................................................15

Simultaneous Read/Write Operation with Zero Latency .......................15

Page Mode Features ............................................................................................15

Standard Flash Memory Features ....................................................................15

Pin Description .........................................................17

Device Bus Operations ............................................18

Table 1. PL127J Device Bus Operations ................................ 18

Requirements for Reading Array Data ......................................................... 18

Random Read (Non-Page Read) ................................................................ 18

Page Mode Read .............................................................................................. 19

Table 2. Page Select .......................................................... 19

DQ7: Data# Polling ............................................................................................52

Figure 6. Data# Polling Algorithm........................................ 54

RY/BY#: Ready/Busy# ........................................................................................55

Simultaneous Read/Write Operation ........................................................... 19

Table 3. Bank Select .......................................................... 19

DQ6: Toggle Bit I ............................................................................................... 55

Figure 7. Toggle Bit Algorithm............................................. 56

Writing Commands/Command Sequences ................................................20

Accelerated Program Operation ..............................................................20

Autoselect Functions ....................................................................................20

Standby Mode .......................................................................................................20

Automatic Sleep Mode ...................................................................................... 21

RESET#: Hardware Reset Pin ......................................................................... 21

Output Disable Mode ........................................................................................ 21

Table 4. PL127J Sector Architecture ..................................... 22

DQ2: Toggle Bit II ..............................................................................................56

Reading Toggle Bits DQ6/DQ2 .....................................................................56

DQ5: Exceeded Timing Limits ........................................................................ 57

DQ3: Sector Erase Timer ................................................................................ 57

Table 15. Write Operation Status ......................................... 58

Absolute Maximum Ratings ...................................59

Figure 8. Maximum Overshoot Waveforms............................ 59

Operating Ranges ................................................... 60

Industrial (I) Devices ..........................................................................................60

Wireless Devices ................................................................................................60

Supply Voltages ...................................................................................................60

DC Characteristics .................................................. 61

Table 16. CMOS Compatible ................................................ 61

AC Characteristic ....................................................62

Test Conditions ..................................................................................................62

Figure 9. Test Setups........................................................ 62

Table 17. Test Specifications ............................................... 62

Table 5. SecSiTM Sector Addresses ...................................... 27

Autoselect Mode .................................................................................................27

Table 6. Autoselect Codes (High Voltage Method) .................. 28

Table 7. PL127J Boot Sector/Sector Block Addresses for

Protection/Unprotection ..................................................... 29

Selecting a Sector Protection Mode ............................................................. 30

Table 8. Sector Protection Schemes ..................................... 30

Sector Protection ................................................... 30

Sector Protection Schemes .................................. 30

Password Sector Protection ........................................................................... 30

WP# Hardware Protection ............................................................................ 30

Selecting a Sector Protection Mode ............................................................. 30

Persistent Sector Protection ................................. 31

Persistent Protection Bit (PPB) ........................................................................31

Persistent Protection Bit Lock (PPB Lock) ..................................................31

Persistent Sector Protection Mode Locking Bit ........................................33

Password Protection Mode ................................... 33

Password and Password Mode Locking Bit ................................................34

64-bit Password ...................................................................................................34

Write Protect (WP#) ........................................................................................34

Persistent Protection Bit Lock ....................................................................35

High Voltage Sector Protection ......................................................................35

Figure 1. In-System Sector Protection/Sector

SWITCHING WAVEFORMS .........................................................................63

Table 18. KEY TO SWITCHING WAVEFORMS .......................... 63

Figure 10. Input Waveforms and Measurement Levels............ 63

VCC RampRate ...................................................................................................63

Read Operations .................................................................................................64

Table 19. Read-Only Operations .......................................... 64

Figure 11. Read Operation Timings ...................................... 64

Figure 12. Page Read Operation Timings............................... 65

Reset .......................................................................................................................65

Table 20. Hardware Reset (RESET#) .................................... 65

Figure 13. Reset Timings .................................................... 66

Erase/Program Operations ..............................................................................67

Table 21. Erase and Program Operations .............................. 67

Timing Diagrams .................................................................................................68

Figure 14. Program Operation Timings ................................. 68

Figure 15. Accelerated Program Timing Diagram.................... 68

Figure 16. Chip/Sector Erase Operation Timings .................... 69

Figure 17. Back-to-back Read/Write Cycle Timings................. 69

Figure 18. Data# Polling Timings (During Embedded

Algorithms)....................................................................... 70

Figure 19. Toggle Bit Timings (During Embedded

Algorithms)....................................................................... 70

Figure 20. DQ2 vs. DQ6 ..................................................... 71

Unprotection Algorithms...................................................... 36

Temporary Sector Unprotect .........................................................................37

Figure 2. Temporary Sector Unprotect Operation.................... 37

SecSi™ (Secured Silicon) Sector Flash Memory Region ...........................37

Factory-Locked Area (64 words) ..............................................................37

Customer-Lockable Area (64 words) ......................................................38

SecSi Sector Protection Bits ........................................................................38

Figure 3. SecSi Sector Protect Verify..................................... 39

Hardware Data Protection ..............................................................................39

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27631A5 September 28, 2004

A d v a n c e I n f o r m a t i o n

Table 11. Primary Vendor-Specific Extended Query............... 126

Command Definitions .......................................... 126

Protect/Unprotect .................................................. 71

Table 22. Temporary Sector Unprotect ................................. 71

Figure 21. Temporary Sector Unprotect Timing Diagram.......... 71

Figure 22. Sector/Sector Block Protect and Unprotect

Reading Array Data ..........................................................................................127

Reset Command ................................................................................................127

Autoselect Command Sequence ...................................................................127

Enter Secured Silicon Sector/Exit Secured Silicon

Sector Command Sequence ...........................................................................128

Word Program Command Sequence ..........................................................128

Unlock Bypass Command Sequence .......................................................129

Write Buffer Programming .........................................................................129

Accelerated Program ...................................................................................130

Figure 1. Write Buffer Programming Operation .................... 131

Timing Diagram ................................................................. 72

Controlled Erase Operations ..........................................................................73

Table 23. Alternate CE# Controlled Erase and Program

Operations ....................................................................... 73

Table 24. Alternate CE# Controlled Write (Erase/Program) Opera-

tion Timings ..................................................................... 74

Table 25. Erase And Programming Performance .................... 75

BGA Pin Capacitance ............................................ 75

S29GLxxxN MirrorBit^TMFlash Family ........... 77

General Description ................................................78

Product Selector Guide ..........................................80

Block Diagram ........................................................ 81

Pin Description ....................................................... 82

Logic Symbol .......................................................... 83

Figure 2. Program Operation............................................. 132

Program Suspend/Program Resume Command Sequence ...................132

Figure 3. Program Suspend/Program Resume...................... 133

Chip Erase Command Sequence ..................................................................133

Sector Erase Command Sequence ...............................................................134

Figure 4. Erase Operation................................................. 135

Erase Suspend/Erase Resume Commands .................................................135

Lock Register Command Set Definitions ...................................................136

Password Protection Command Set Definitions .....................................136

Non-Volatile Sector Protection Command Set Definitions .................138

Global Volatile Sector Protection Freeze Command Set .....................138

Volatile Sector Protection Command Set .................................................139

Secured Silicon Sector Entry Command ....................................................140

Secured Silicon Sector Exit Command .......................................................140

Command Definitions .......................................................................................141

S29GL512N ........................................................................................................83

S29GL256N .......................................................................................................83

S29GL128N .......................................................................................................83

Device Bus Operations ...........................................84

Table 1. Device Bus Operations ........................................... 84

VersatileIO^TM(V ) Control ............................................................................84

IO

Table 12. S29GL512N, S29GL256N, S29GL128N

Command Definitions, x16 ................................................ 141

Requirements for Reading Array Data ........................................................84

Page Mode Read ............................................................................................. 85

Writing Commands/Command Sequences ................................................ 85

Write Buffer .................................................................................................... 85

Accelerated Program Operation .............................................................. 85

Autoselect Functions ....................................................................................86

Standby Mode ......................................................................................................86

Automatic Sleep Mode ..................................................................................... 86

RESET#: Hardware Reset Pin ........................................................................86

Output Disable Mode ....................................................................................... 87

Table 2. Sector Address Table–S29GL512N ........................... 87

Write Operation Status ..................................................................................144

DQ7: Data# Polling ...........................................................................................144

Figure 5. Data# Polling Algorithm...................................... 145

RY/BY#: Ready/Busy# ......................................................................................145

DQ6: Toggle Bit I ..............................................................................................146

Figure 6. Toggle Bit Algorithm........................................... 147

DQ2: Toggle Bit II .............................................................................................147

Reading Toggle Bits DQ6/DQ2 ....................................................................148

DQ5: Exceeded Timing Limits .......................................................................148

DQ3: Sector Erase Timer ...............................................................................148

DQ1: Write-to-Buffer Abort ..........................................................................149

Table 13. Write Operation Status ....................................... 149

Table 3. Sector Address Table–S29GL256N ..........................102

Table 4. Sector Address Table–S29GL128N ..........................109

Autoselect Mode ................................................................................................ 113

Table 5. Autoselect Codes, (High Voltage Method) ...............114

Absolute Maximum Ratings ................................ 150

Sector Protection ...............................................................................................114

Persistent Sector Protection ......................................................................114

Password Sector Protection .......................................................................114

WP# Hardware Protection ........................................................................114

Selecting a Sector Protection Mode ........................................................114

Advanced Sector Protection .......................................................................... 115

Lock Register ....................................................................................................... 115

Table 6. Lock Register .......................................................116

Figure 7. Maximum Negative Overshoot Waveform .............. 150

Figure 8. Maximum Positive Overshoot Waveform................ 150

Operating Ranges ................................................. 150

DC Characteristics ................................................. 151

Test Conditions ......................................................152

Figure 9. Test Setup ........................................................ 152

Table 14. Test Specifications ............................................. 152

Persistent Sector Protection ..........................................................................116

Dynamic Protection Bit (DYB) ..................................................................116

Persistent Protection Bit (PPB) ................................................................. 117

Persistent Protection Bit Lock (PPB Lock Bit) ..................................... 117

Table 7. Sector Protection Schemes ....................................118

Key to Switching Waveforms .............................. 152

Figure 10. Input Waveforms and Measurement Levels.......... 152

AC Characteristics .................................................153

Read-Only Operations–S29GL128N, S29GL256N, S29GL512N ..........153

Figure 11. Read Operation Timings .................................... 154

Figure 12. Page Read Timings ........................................... 154

Hardware Reset (RESET#) .............................................................................155

Figure 13. Reset Timings .................................................. 155

Erase and Program Operations–S29GL128N, S29GL256N,

Persistent Protection Mode Lock Bit ..........................................................118

Password Sector Protection ...........................................................................119

Password and Password Protection Mode Lock Bit ...............................119

64-bit Password .................................................................................................120

Persistent Protection Bit Lock (PPB Lock Bit) .........................................120

Secured Silicon Sector Flash Memory Region ..........................................120

Write Protect (WP#) ......................................................................................122

Hardware Data Protection ............................................................................122

Low VCC Write Inhibit ..............................................................................122

Write Pulse “Glitch” Protection ..............................................................122

Logical Inhibit .................................................................................................122

Power-Up Write Inhibit ..............................................................................122

Common Flash Memory Interface (CFI) ............ 122

S29GL512N ..........................................................................................................156

Figure 14. Program Operation Timings ............................... 157

Figure 15. Accelerated Program Timing Diagram.................. 157

Figure 16. Chip/Sector Erase Operation Timings .................. 158

Figure 17. Data# Polling Timings (During Embedded

Algorithms)..................................................................... 159

Figure 18. Toggle Bit Timings (During Embedded Algorithms) 160

Figure 19. DQ2 vs. DQ6 ................................................... 160

Alternate CE# Controlled Erase and Program Operations-

Table 8. CFI Query Identification String............................... 123

Table 9. System Interface String........................................ 124

Table 10. Device Geometry Definition ................................. 125

S29GL128N, S29GL256N, S29GL512N .........................................................161

September 28, 2004 27631A5

3

A d v a n c e I n f o r m a t i o n

Figure 20. Alternate CE# Controlled Write (Erase/

Figure 29. Timing Waveform of Write Cycle(3)

Program) Operation Timings.............................................. 162

(CS2 Controlled) ............................................................. 173

Figure 30. Timing Waveform of Write Cycle(4) (UB#, LB#

Controlled) ..................................................................... 173

Erase And Programming Performance .............. 163

TSOP Pin and BGA Package Capacitance ......... 163

pSRAM Type 2 ................................................164

Features ................................................................ 164

Product Information ............................................ 164

Pin Description ..................................................... 164

Power Up Sequence ............................................. 165

Timing Diagrams ...................................................166

Power Up ............................................................................................................166

Figure 21. Power Up 1 (CS1# Controlled)............................ 166

Figure 22. Power Up 2 (CS2 Controlled) .............................. 166

Functional Description ........................................ 166

Absolute Maximum Ratings ................................. 167

DC Recommended Operating Conditions ......... 167

Capacitance (Ta = 25°C, f = 1 MHz) .................... 167

DC and Operating Characteristics ..................... 167

pSRAM Type 6 ................................................174

Features ................................................................. 174

Pin Description ..................................................... 174

Functional Description ......................................... 175

Absolute Maximum Ratings ................................ 175

DC Recommended Operating Conditions

(Ta = -40°C to 85°C) ............................................. 175

DC Characteristics (Ta = -40°C to 85°C,

VDD = 2.6 to 3.3 V) (See Note 3 to 4) ................ 176

Capacitance (Ta = 25°C, f = 1 MHz) .................... 176

AC Characteristics and Operating

Conditions ............................................................. 176

(Ta = -40°C to 85°C, VDD = 2.6 to 3.3 V) (See Note 5 to 11) ............176

AC Test Conditions .............................................. 177

Common .............................................................................................................. 167

16M pSRAM .........................................................................................................168

32M pSRAM ........................................................................................................168

64M pSRAM ........................................................................................................169

AC Operating Conditions ................................... 169

Timing Diagrams ................................................... 178

Read Timings .......................................................................................................178

Figure 1. Read Cycle........................................................ 178

Figure 2. Page Read Cycle (8 Words Access) ....................... 179

Write Timings .................................................................................................... 180

Figure 3. Write Cycle #1 (WE# Controlled) (See Note 8) ...... 180

Figure 4. Write Cycle #2 (CE# Controlled) (See Note 8) ....... 181

Test Conditions (Test Load and Test Input/Output Reference) .......169

Figure 23. Output Load ..................................................... 169

ACC Characteristics (Ta = -40°C to 85°C, V = 2.7 to 3.1 V) ........170

Deep Power-down Timing ..............................................................................181

CC

Figure 5. Deep Power Down Timing.................................... 181

Timing Diagrams ....................................................171

Power-on Timing ................................................................................................181

Read Timings ....................................................................................................... 171

Figure 24. Timing Waveform of Read Cycle(1)...................... 171

Figure 25. Timing Waveform of Read Cycle(2)...................... 171

Figure 26. Timing Waveform of Read Cycle(2)...................... 171

Write Timings .................................................................................................... 172

Figure 27. Write Cycle #1 (WE# Controlled) ........................ 172

Figure 28. Write Cycle #2 (CS1# Controlled)....................... 172

Figure 6. Power-on Timing................................................ 181

Provisions of Address Skew ...........................................................................182

Read ...................................................................................................................182

Figure 7. Read ................................................................ 182

Write .................................................................................................................182

Figure 8. Write................................................................ 182

Revision Summary .........................................183

4

27631A5 September 28, 2004

P r e l i m i a r y

Product Selector Guide

PL127J

Access

pSRAM

Access

Data

Storage

pSRAM

Device-Model#

S75PL127JBD-KU

S75PL127JBD-KB

S75PL127JCD-KU

S75PL127JCD-KB

S75PL127JBE-KU

S75PL127JBE-KB

S75PL127JCE-KU

S75PL127JCE-KB

S75PL127JBF-KU

S75PL127JBF-KB

S75PL127JCF-KU

S75PL127JCF-KB

Times (ns) density Time (ns) Supplier Density

Package

Type 6

32 Mb

Type 2

Type 6

Type 2

Type 6

Type 2

Type 6

Type 2

Type 6

Type 2

Type 6

Type 2

128 Mb

(110ns)

65

70

9x12 mm 84-ball FBGA

64 Mb

32 Mb

64 Mb

32 Mb

64 Mb

256 Mb

(110ns)

9x12 mm 84-ball FBGA

512 Mb

(110ns)

January 6, 2005 S75PL127J_00_A1_E

S75PL127J MCPs

5

A d v a n c e I n f o r m a t i o n

MCP Block Diagram

V

f

CC

A

*-A22

23

max

V

f

Flash-Only Address

Shared Address

CC

16

DQ15 to DQ0

S29PL127J

DQ15 to DQ0

WP#ACC

WP#

CE#

OE#

F1-CE# (See Note)

OE#

WE#

RESET#

S29GL-N

RY/BY#

RDY

VSS

F-RST#

V

F2-CW# (See Note)

SS

R-V

CC

V

CC

CCO

16

23

DQ15 to DQ0

pSRAM

R-CE#

CE#

WE#

OE#

UB#

LB#

R-UB#

R-LB#

V

SSQ

V

SS

(Note 1) R-CE2

Note:

F1-CE# and F2-CE# are the chip-enable pins for the PL and GL Flash devices, respectively.

Amax -A24 for GL512, A23 for GL256N, A22 for GL128 and PL127J. Flash-only addressess

may be shared between PL and GL, but is not shared with pSRAM. For more details, refer

to the table following the connection diagram.

6

S75PL127J MCPs

S75PL127J_00_A1_E January 6, 2005

P r e l i m i a r y

Connection Diagram

Legend:

All Shared

Top View

A2

A1

DNU

B3

B4

B5

B6

B7

B8

B9

B2

VSS

RFU

F-VCC

RFU

GL (Data) only

pSRAM only

C2

C3

A7

C4

C5

C6

C7

A8

C8

C9

RFU

R-LB# F1-WP/ACC WE#

A11

F2-CE#

D5

D6

D7

D8

D9

D2

A3

D3

A6

D4

R-UB# F-RST#

R-CE2

A19

A12

A15

Reserved for Future Use

PL (Code) Only

E5

E2

A2

E3

A5

E4

E6

E7

A9

E8

E9

A18

RY/BY#

A20

A13

A21

F2

A1

F3

A4

F4

F5

F6

F7

F8

F9

A17

RFU

A23

A10

A14

A22

PL and GL Shared

G2

A0

G5

G6

G8

G3

G4

G7

G9

VSS

DQ1

RFU

DQ6

A24

A16

Shared (See Table Below)

H2

H3

H4

H5

H6

H7

H8

H9

F1-CE#

OE#

DQ9

DQ3

DQ4

DQ13

DQ15

RFU

J2

J3

J4

J5

J6

J7

J8

J9

R-CE1#

DQ0

DQ10

F-VCC

R-VCC

DQ12

DQ7

VSS

K2

K4

K5

K6

K7

K8

K9

RFU

DQ8

DQ2

DQ11

RFU

DQ5

DQ14 F2-WP#/ACC

L2

L3

L4

L5

L6

L7

L8

L9

RFU

VSS

F-VCC

RFU

DNU

Note:

Connect 2-WP#/ ACC (K9) to Flash Vcc.

PL, GL, and pSRAM

Shared Addresses

MCP

GL-Only Addresses PL-GL Shared Addresses

S75PL127JBD

S75PL127JCD

S75PL127JBE

S75PL127JCE

S75PL127JBF

S75PL127JCF

-

A22–A21

A22

A20–A0

A21–A0

A20–A0

A21–A0

A20–A0

A21–A0

A23

A22–A21

A22

A23

A24-A23

A22–A21

A22

January 6, 2005 S75PL127J_00_A1_E

S75PL127J MCPs

7

A d v a n c e I n f o r m a t i o n

Pin Description

Amax–A0

DQ15–DQ0

F1-CE#

=

Address Inputs

16 Data Inputs/Outputs (Common)

Chip Enable for PL

F2-CE

Chip Enable for GL

R-CE#1

R-CE#2

OE#

Chip Enable 1 (pSRAM)

Chip Enable 2 (pSRAM)

Output Enable (Common)

WE#

Write Enable (Common)

RY/BY#

R-UB#

R-LB#

F-RST#

Ready/Busy Output (Flash)

Upper Byte Control (pSRAM)

Lower Byte Control (pSRAM)

Hardware Reset Pin (Flash)

Hardware Write Protect /Acceleration Pin (PL)

Hardware Write Protect/Acceleration Pin (GL) Should be tied to Vcc

Flash 3.0 volt-only single power supply

pSRAM Power Supply

F1-WP#/ACC

F-VCC

R-VCCs

VSS

=

Device Ground (Common)

DNU

Do Not Use

8

S75PL127J MCPs

S75PL127J_00_A1_E January 6, 2005

P r e l i m i a r y

Ordering Information

S75PL

127

J

C

D

BA

W

K

Z

0

PACKING TYPE

0

2

3

=

Tray

7” Tape and Reel

13” Tape and Reel

SUPPPLIER; SPEED COMBINATION

B

U

=

pSRAM2, 70 ns

pSRAM6, 70 ns

PACKAGE HEIGHT; DATA TYPE; PSRAM SPEED

1.4 mm, GL as data; 70 ns

K

=

TEMPERATURE RANGE

Wireless (-25 C to +85°C)

W

=

°

PACKAGE TYPE

BA

BF

=

Very Thin Fine-Pitch BGA Lead (Pb)-free compliant package

Very Thin Fine-Pitch BGA Lead (Pb)-free package

GL DATA Flash Density

D

E

F

=

128 Mb

256 Mb

512 Mb

pSRAM Density

B

C

=

32 Mb

64 Mb

PROCESS TECHNOLOGY

110 nm, Floating Gate

J

=

PL CODE FLASH DENSITY

127 128 Mb

=

PRODUCT FAMILY

S75PL= Multi-Chip Product (MCP)

3.0 V Simultaneous Read/Write Page Mode

CODE Flash + pSRAM + 3.0V DATA Flash

January 6, 2005 S75PL127J_00_A1_E

S75PL127J MCPs

9

A d v a n c e I n f o r m a t i o n

Valid Combinations

Data: S29GL128N

PL127J

Package

&

Package

Modifier/

Speed

Base Ordering

Packing Options pSRAM Supplier/ Package

Part Number Temperature Model Number

Type

(ns)

Access Time (ns) Marking

S75PL127JBD

S75PL127JCD

S75PL127JBD

S75PL127JCD

KU

KB

KU

KB

KU

KB

KU

KB

Type 6 / 70

Type 2 / 70

BAW

BFW

Type 6/ 70

Type 2 / 70

(Note 2)

Type 6 / 70

0, 2, 3,

(Note 1)

65

Type 2 / 70

Type 6 / 70

Type 2 / 70

Notes:

1. Type 0 is standard. Specify other options as required.

2. BGA package marking omits leading S and packing type designator from ordering part number.

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device.

Consult your local sales office to confirm availability of specific valid combinations and to

check on newly released combinations.

Data: S29GL256N

PL127J

Package

&

Package

Modifier/

Speed

Base Ordering

Packing Options pSRAM Supplier/ Package

Part Number Temperature Model Number

Type

(ns)

Access Time (ns) Marking

S75PL127JBE

S75PL127JCE

S75PL127JBE

S75PL127JCE

KU

KB

KU

KB

KU

KB

KU

KB

Type 6 / 70

Type 2 / 70

BAW

BFW

Type 6 / 70

Type 2 / 70

(Note 2)

Type 6 / 70

0, 2, 3,

(Note 1)

65

Type 2 / 70

Type 6 / 70

Type 2 / 70

Notes:

1. Type 0 is standard. Specify other options as required.

2. BGA package marking omits leading S and packing type designator from ordering part number.

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device.

Consult your local sales office to confirm availability of specific valid combinations and to

check on newly released combinations.

10

S75PL127J MCPs

S75PL127J_00_A1_E January 6, 2005

P r e l i m i a r y

Data: S29GL512N

PL127J

Package

&

Package

Modifier/

Speed

Base Ordering

Packing Options pSRAM Supplier/ Package

Part Number Temperature Model Number

Type

(ns)

Access Time (ns) Marking

S75PL127JBF

S75PL127JCF

S75PL127JBF

S75PL127JCF

KU

KB

KU

KB

KU

KB

KU

KB

Type 6 / 70

Type 2 / 70

BAW

BFW

Type 6 / 70

Type 2 / 70

(Note 2)

Type 6 / 70

0, 2, 3,

(Note 1)

65

Type 2 / 70

Type 6 / 70

Type 2 / 70

Notes:

1. Type 0 is standard. Specify other options as required.

2. BGA package marking omits leading S and packing type designator from ordering part number.

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device.

Consult your local sales office to confirm availability of specific valid combinations and to

check on newly released combinations.

January 6, 2005 S75PL127J_00_A1_E

S75PL127J MCPs

11

S29PL127J/S29PL064J/S29PL032J for MCP

128/64/32 Megabit (8/4/2 M x 16-Bit)

CMOS 3.0 Volt-only, Simultaneous Read/Write

Flash Memory with Enhanced VersatileIO^TMControl

PRELIMINARY

Distinctive Characteristics

SecSi^TM(Secured Silicon) Sector region

— Up to 128 words accessible through a command

sequence

ARCHITECTURAL ADVANTAGES

128/64/32 Mbit Page Mode devices

— Page size of 8 words: Fast page read access from

random locations within the page

— Up to 64 factory-locked words

— Up to 64 customer-lockable words

Single power supply operation

— Full Voltage range: 2.7 to 3.1 volt read, erase, and

program operations for battery-powered applications

Both top and bottom boot blocks in one device

Manufactured on 110 nm process technology

Data Retention: 20 years typical

Simultaneous Read/Write Operation

— Data can be continuously read from one bank while

executing erase/program functions in another bank

— Zero latency switching from write to read operations

Cycling Endurance: 1 million cycles per sector

typical

FlexBank Architecture (PL127J/PL064J/PL032J)

— 4 separate banks, with up to two simultaneous

operations per device

PERFORMANCE CHARACTERISTICS

High Performance

— Page access times as fast as 20 ns

— Random access times as fast as 55 ns

— Bank A:

PL127J -16 Mbit (4 Kw x 8 and 32 Kw x 31)

PL064J - 8 Mbit (4 Kw x 8 and 32 Kw x 15)

PL032J - 4 Mbit (4 Kw x 8 and 32 Kw x 7)

Power consumption (typical values at 10 MHz)

— 45 mA active read current

— Bank B:

— 17 mA program/erase current

PL127J - 48 Mbit (32 Kw x 96)

PL064J - 24 Mbit (32 Kw x 48)

PL032J - 12 Mbit (32 Kw x 24)

— 0.2 µA typical standby mode current

SOFTWARE FEATURES

— Bank C:

Software command-set compatible with JEDEC

42.4 standard

— Backward compatible with Am29F, Am29LV,

Am29DL, and AM29PDL families and MBM29QM/RM,

MBM29LV, MBM29DL, MBM29PDL families

PL127J - 48 Mbit (32 Kw x 96)

PL064J - 24 Mbit (32 Kw x 48)

PL032J - 12 Mbit (32 Kw x 24)

— Bank D:

PL127J -16 Mbit (4 Kw x 8 and 32 Kw x 31)

PL064J - 8 Mbit (4 Kw x 8 and 32 Kw x 15)

PL032J - 4 Mbit (4 Kw x 8 and 32 Kw x 7)

CFI (Common Flash Interface) compliant

— Provides device-specific information to the system,

allowing host software to easily reconfigure for

different Flash devices

Enhanced VersatileI/O^TM(V_IO) Control

— Output voltage generated and input voltages

tolerated on all control inputs and I/Os is determined

by the voltage on the V_IOpin

Erase Suspend / Erase Resume

— Suspends an erase operation to allow read or

program operations in other sectors of same bank

— V_IOoptions at 1.8 V and 3 V I/O for PL127J devices

— 3V V_IOfor PL064J and PL032J devices

Unlock Bypass Program command

— Reduces overall programming time when issuing

multiple program command sequences

Publication Number S29PL127J_064J_032J_MCP Revision A Amendment 3 Issue Date August 12, 2004

P r e l i m i n a r y

to prevent program or erase operations within that

sector

HARDWARE FEATURES

Ready/Busy# pin (RY/BY#)

— Provides a hardware method of detecting program or

erase cycle completion

— Sectors can be locked and unlocked in-system at V_CC

level

Password Sector Protection

Hardware reset pin (RESET#)

— Hardware method to reset the device to reading

array data

— A sophisticated sector protection method to lock

combinations of individual sectors and sector groups

to prevent program or erase operations within that

sector using a user-defined 64-bit password

WP#/ ACC (Write Protect/Acceleration) input

— At V_IL, hardware level protection for the first and

last two 4K word sectors.

Package options

— Standard discrete pinouts

— At V_IH, allows removal of sector protection

— At V_HH, provides accelerated programming in a

factory setting

11 x 8 mm, 80-ball Fine-pitch BGA (PL127J)

(VBG080)

8 x 6 mm, 48-ball Fine pitch BGA (PL064J/PL032J)

(VBK048)

Persistent Sector Protection

— A command sector protection method to lock

combinations of individual sectors and sector groups

— MCP-compatible pinout

8 x 11.6 mm, 64-ball Fine-pitch BGA (PL127J) 7 x 9

mm, 56-ball Fine-pitch BGA (PL064J and PL032J)

Compatible with MCP pinout, allowing easy

integration of RAM into existing designs

14

S29PL127J/S29PL064J/S29PL032J for MCP

S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

P r e l i m i n a r y

General Description

The PL127J/PL064J/PL032J is a 128/128/64/32 Mbit, 3.0 volt-only Page Mode

and Simultaneous Read/Write Flash memory device organized as 8/8/4/2

Mwords. The devices are offered in the following packages:

11mm x 8mm, 64-ball Fine-pitch BGA standalone (all)

9mm x 8mm, 80-ball Fine-pitch BGA standalone (PL127J)

8mm x 11.6mm, 64-ball Fine pitch BGA multi-chip compatible (PL127J)

The word-wide data (x16) appears on DQ15-DQ0. This device can be pro-

grammed in-system or in standard EPROM programmers. A 12.0 V V_PPis not

required for write or erase operations.

The device offers fast page access times of 20 to 30 ns, with corresponding ran-

dom access times of 55 to 70 ns, respectively, allowing high speed

microprocessors to operate without wait states. To eliminate bus contention the

device has separate chip enable (CE#), write enable (WE#) and output enable

(OE#) controls.

Simultaneous Read/Write Operation with Zero Latency

The Simultaneous Read/Write architecture provides simultaneous operation

by dividing the memory space into 4 banks, which can be considered to be four

separate memory arrays as far as certain operations are concerned. The device

can improve overall system performance by allowing a host system to program

or erase in one bank, then immediately and simultaneously read from another

bank with zero latency (with two simultaneous operations operating at any one

time). This releases the system from waiting for the completion of a program or

erase operation, greatly improving system performance.

The device can be organized in both top and bottom sector configurations. The

banks are organized as follows:

Bank

A

PL127J Sectors

16 Mbit (4 Kw x 8 and 32 Kw x 31)

48 Mbit (32 Kw x 96)

B

C

48 Mbit (32 Kw x 96)

D

16 Mbit (4 Kw x 8 and 32 Kw x 31)

Page Mode Features

The page size is 8 words. After initial page access is accomplished, the page mode

operation provides fast read access speed of random locations within that page.

Standard Flash Memory Features

The device requires a single 3.0 volt power supply (2.7 V to 3.6 V) for both

read and write functions. Internally generated and regulated voltages are pro-

vided for the program and erase operations.

The device is entirely command set compatible with the JEDEC 42.4 single-

power-supply Flash standard. Commands are written to the command regis-

ter using standard microprocessor write timing. Register contents serve as inputs

to an internal state-machine that controls the erase and programming circuitry.

August 12, 2004 S29PL127J_064J_032J_MCP_00_A3

S29PL127J/S29PL064J/S29PL032J for MCP

15

P r e l i m i n a r y

Write cycles also internally latch addresses and data needed for the programming

and erase operations. Reading data out of the device is similar to reading from

other Flash or EPROM devices.

Device programming occurs by executing the program command sequence. The

Unlock Bypass mode facilitates faster programming times by requiring only two

write cycles to program data instead of four. Device erasure occurs by executing

the erase command sequence.

The host system can detect whether a program or erase operation is complete by

reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program

or erase cycle has been completed, the device is ready to read array data or ac-

cept another command.

The sector erase architecture allows memory sectors to be erased and repro-

grammed without affecting the data contents of other sectors. The device is fully

erased when shipped from the factory.

Hardware data protection measures include a low V_CCdetector that automat-

ically inhibits write operations during power transitions. The hardware sector

protection feature disables both program and erase operations in any combina-

tion of sectors of memory. This can be achieved in-system or via programming

equipment.

The Erase Suspend/Erase Resume feature enables the user to put erase on

hold for any period of time to read data from, or program data to, any sector that

is not selected for erasure. True background erase can thus be achieved. If a read

is needed from the SecSi Sector area (One Time Program area) after an erase

suspend, then the user must use the proper command sequence to enter and exit

this region.

The device offers two power-saving features. When addresses have been stable

for a specified amount of time, the device enters the automatic sleep mode.

The system can also place the device into the standby mode. Power consumption

is greatly reduced in both these modes.

The device electrically erases all bits within a sector simultaneously via Fowler-

Nordheim tunneling. The data is programmed using hot electron injection.

16

S29PL127J/S29PL064J/S29PL032J for MCP

S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

P r e l i m i n a r y

Pin Description

Amax–A0

DQ15–DQ0

CE#

OE#

WE#

V_SS

NC

RY/BY#

=

Address bus

16-bit data inputs/outputs/float

Chip Enable Inputs

Output Enable Input

Write Enable

Device Ground

Pin Not Connected Internally

Ready/Busy output and open drain.

When RY/BY#= V_IH, the device is ready to accept

read operations and commands. When RY/BY#=

V_OL, the device is either executing an embedded

algorithm or the device is executing a hardware

reset operation.

WP#/ACC

=

Write Protect/Acceleration Input.

When WP#/ACC= V_IL, the highest and lowest two

4K-word sectors are write protected regardless of

other sector protection configurations. When WP#/

ACC= V_IH, these sector are unprotected unless the

DYB or PPB is programmed. When WP#/ACC= 12V,

program and erase operations are accelerated.

V_IO

=

Input/Output Buffer Power Supply

(1.65 V to 1.95 V (for PL127J) or 2.7 V to 3.6 V (for

all PLxxxJ devices)

V_CC

Chip Power Supply

(2.7 V to 3.6 V or 2.7 to 3.3 V)

RESET#

CE#1

=

Hardware Reset Pin

Chip Enable Inputs

Notes:

1. Amax = A22 (PL127J), A21 (PL064J), A20 (PL032J)

August 12, 2004 S29PL127J_064J_032J_MCP_00_A3

S29PL127J/S29PL064J/S29PL032J for MCP

17

P r e l i m i n a r y

Device Bus Operations

This section describes the requirements and use of the device bus operations,

which are initiated through the internal command register. The command register

itself does not occupy any addressable memory location. The register is a latch

used to store the commands, along with the address and data information

needed to execute the command. The contents of the register serve as inputs to

the internal state machine. The state machine outputs dictate the function of the

device. Table 1 lists the device bus operations, the inputs and control levels they

require, and the resulting output. The following subsections describe each of

these operations in further detail.

Table 1. PL127J Device Bus Operations

Addresses

(Amax–A0)

DQ15–

DQ0

Operation

CE#

L

OE#

L

WE#

RESET#

WP#/ACC

X

Read

Write

H

L

H

A_IN

D_OUT

D_IN

L

H

X (Note 2)

A_IN

V_IO

0.3 V

±

V_IO±

0.3 V

Standby

X

X (Note 2)

X

High-Z

Output Disable

Reset

L

X

H

X

H

X

H

X

High-Z

D_IN

L

Temporary Sector Unprotect (High Voltage)

V_ID

A_IN

Legend: L= Logic Low = V_IL, H = Logic High = V_IH

V_ID= 11.5-12.5 V, V_HH= 8.5-9.5 V, X = Don’t Care,

,

SA = Sector Address, A_IN= Address In, D_IN= Data

In, D_OUT= Data Out

Notes:

1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the

High Voltage Sector Protection section.

2. WP#/ACC must be high when writing to upper two and lower two sectors.

Requirements for

Reading Array Data

To read array data from the outputs, the system must drive the OE# and appro-

priate CE# pins. OE# is the output control and gates array data to the output

pins. WE# should remain at V_IH.

The internal state machine is set for reading array data upon device power-up,

or after a hardware reset. This ensures that no spurious alteration of the memory

content occurs during the power transition. No command is necessary in this

mode to obtain array data. Standard microprocessor read cycles that assert valid

addresses on the device address inputs produce valid data on the device data

outputs. Each bank remains enabled for read access until the command register

contents are altered.

Refer to Table 19 for timing specifications and to Figure 11 for the timing diagram.

I_CC1in the DC Characteristics table represents the active current specification for

reading array data.

Random Read (Non-Page Read)

Address access time (t_ACC) is equal to the delay from stable addresses to valid

output data. The chip enable access time (t_CE) is the delay from the stable ad-

dresses and stable CE# to valid data at the output inputs. The output enable ac-

cess time is the delay from the falling edge of the OE# to valid data at the output

inputs (assuming the addresses have been stable for at least t_ACC–t_OEtime).

18

S29PL127J/S29PL064J/S29PL032J for MCP

S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

P r e l i m i n a r y

Page Mode Read

The device is capable of fast page mode read and is compatible with the page

mode Mask ROM read operation. This mode provides faster read access speed for

random locations within a page. Address bits Amax–A3 select an 8 word page,

and address bits A2–A0 select a specific word within that page. This is an asyn-

chronous operation with the microprocessor supplying the specific word location.

The random or initial page access is t_ACCor t_CEand subsequent page read ac-

cesses (as long as the locations specified by the microprocessor falls within that

page) is equivalent to t_PACC. Fast page mode accesses are obtained by keeping

Amax–A3 constant and changing A2–A0 to select the specific word within that

page.

Table 2. Page Select

Word

A2

0

A1

0

1

0

1

A0

0

Word 0

Word 1

Word 2

Word 3

Word 4

Word 5

Word 6

Word 7

0

1

0

1

0

1

0

1

Simultaneous Read/Write Operation

In addition to the conventional features (read, program, erase-suspend read, and

erase-suspend program), the device is capable of reading data from one bank of

memory while a program or erase operation is in progress in another bank of

memory (simultaneous operation). The bank can be selected by bank addresses

(PL127J: A22–A20, L064J: A21–A19, PL032J: A20–A18) with zero latency.

The simultaneous operation can execute multi-function mode in the same bank.

Table 3. Bank Select

PL127J: A22–A20

PL064J: A21–A19

PL032J: A20–A18

Bank

Bank A

Bank B

Bank C

Bank D

000

001, 010, 011

100, 101, 110

111

August 12, 2004 S29PL127J_064J_032J_MCP_00_A3

S29PL127J/S29PL064J/S29PL032J for MCP

19

P r e l i m i n a r y

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data

to the device and erasing sectors of memory), the system must drive WE# and

CE# to V_IL, and OE# to V_IH.

The device features an Unlock Bypass mode to facilitate faster programming.

Once a bank enters the Unlock Bypass mode, only two write cycles are required

to program a word, instead of four. The “Word Program Command Sequence”

section has details on programming data to the device using both standard and

Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sectors, or the entire device.

Table 4 indicates the set of address space that each sector occupies. A “bank ad-

dress” is the set of address bits required to uniquely select a bank. Similarly, a

“sector address” refers to the address bits required to uniquely select a sector.

The “Command Definitions” section has details on erasing a sector or the entire

chip, or suspending/resuming the erase operation.

I_CC2in the DC Characteristics table represents the active current specification for

the write mode. See the timing specification tables and timing diagrams in the

Reset for write operations.

Accelerated Program Operation

The device offers accelerated program operations through the ACC function. This

function is primarily intended to allow faster manufacturing throughput at the

factory.

If the system asserts V_HHon this pin, the device automatically enters the afore-

mentioned Unlock Bypass mode, temporarily unprotects any protected sectors,

and uses the higher voltage on the pin to reduce the time required for program

operations. The system would use a two-cycle program command sequence as

required by the Unlock Bypass mode. Removing V_HHfrom the WP#/ACC pin re-

turns the device to normal operation. Note that V_HHmust not be asserted on

WP#/ACC for operations other than accelerated programming, or device damage

may result. In addition, the WP#/ACC pin should be raised to V_CCwhen not in

use. That is, the WP#/ACC pin should not be left floating or unconnected; incon-

sistent behavior of the device may result.

Autoselect Functions

If the system writes the autoselect command sequence, the device enters the au-

toselect mode. The system can then read autoselect codes from the internal

register (which is separate from the memory array) on DQ15–DQ0. Standard

read cycle timings apply in this mode. Refer to the SecSiTM Sector Addresses and

Autoselect Command Sequence for more information.

Standby Mode

When the system is not reading or writing to the device, it can place the device

in the standby mode. In this mode, current consumption is greatly reduced, and

the outputs are placed in the high impedance state, independent of the OE#

input.

The device enters the CMOS standby mode when the CE# and RESET# pins are

both held at V_IO± 0.3 V. (Note that this is a more restricted voltage range than

V_IH.) If CE# and RESET# are held at V_IH, but not within V_IO± 0.3 V, the device

will be in the standby mode, but the standby current will be greater. The device

20

S29PL127J/S29PL064J/S29PL032J for MCP

S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

P r e l i m i n a r y

requires standard access time (t_CE) for read access when the device is in either

of these standby modes, before it is ready to read data.

If the device is deselected during erasure or programming, the device draws ac-

tive current until the operation is completed.

I_CC3in “DC Characteristics” represents the CMOS standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The de-

vice automatically enables this mode when addresses remain stable for t_ACC

+

30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# con-

trol signals. Standard address access timings provide new data when addresses

are changed. While in sleep mode, output data is latched and always available to

the system. Note that during automatic sleep mode, OE# must be at V_IHbefore

the device reduces current to the stated sleep mode specification. I_CC5in “DC

Characteristics” represents the automatic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading

array data. When the RESET# pin is driven low for at least a period of t_RP, the

device immediately terminates any operation in progress, tristates all output

pins, and ignores all read/write commands for the duration of the RESET# pulse.

The device also resets the internal state machine to reading array data. The op-

eration that was interrupted should be reinitiated once the device is ready to

accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held

at V_SS±0.3 V, the device draws CMOS standby current (I_CC4). If RESET# is held

at V_ILbut not within V_SS±0.3 V, the standby current will be greater.

The RESET# pin may be tied to the system reset circuitry. A system reset would

thus also reset the Flash memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

If RESET# is asserted during a program or erase operation, the RY/BY# pin re-

mains a “0” (busy) until the internal reset operation is complete, which requires

a time of t_READY(during Embedded Algorithms). The system can thus monitor RY/

BY# to determine whether the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing (RY/BY# pin is “1”), the reset

operation is completed within a time of t_READY(not during Embedded Algorithms).

The system can read data t_RHafter the RESET# pin returns to V_IH.

Refer to the AC Characteristic tables for RESET# parameters and to 13 for the

timing diagram.

Output Disable Mode

When the OE# input is at V_IH, output from the device is disabled. The output pins

(except for RY/BY#) are placed in the highest Impedance state

August 12, 2004 S29PL127J_064J_032J_MCP_00_A3

S29PL127J/S29PL064J/S29PL032J for MCP

21

P r e l i m i n a r y

Table 4. PL127J Sector Architecture

Bank

Sector

SA0

Sector Address (A22-A12)

00000000000

00000000001

00000000010

00000000011

00000000100

00000000101

00000000110

00000000111

00000001XXX

00000010XXX

00000011XXX

00000100XXX

00000101XXX

00000110XXX

00000111XXX

00001000XXX

00001001XXX

00001010XXX

00001011XXX

00001100XXX

00001101XXX

00001110XXX

00001111XXX

00010000XXX

00010001XXX

00010010XXX

00010011XXX

00010100XXX

00010101XXX

00010110XXX

00010111XXX

00011000XXX

00011001XXX

00011010XXX

00011011XXX

00011100XXX

00011101XXX

00011110XXX

00011111XXX

Sector Size (Kwords)

Address Range (x16)

000000h–000FFFh

001000h–001FFFh

002000h–002FFFh

003000h–003FFFh

004000h–004FFFh

005000h–005FFFh

006000h–006FFFh

007000h–007FFFh

008000h–00FFFFh

010000h–017FFFh

018000h–01FFFFh

020000h–027FFFh

028000h–02FFFFh

030000h–037FFFh

038000h–03FFFFh

040000h–047FFFh

048000h–04FFFFh

050000h–057FFFh

058000h–05FFFFh

060000h–067FFFh

068000h–06FFFFh

070000h–077FFFh

078000h–07FFFFh

080000h–087FFFh

088000h–08FFFFh

090000h–097FFFh

098000h–09FFFFh

0A0000h–0A7FFFh

0A8000h–0AFFFFh

0B0000h–0B7FFFh

0B8000h–0BFFFFh

0C0000h–0C7FFFh

0C8000h–0CFFFFh

0D0000h–0D7FFFh

0D8000h–0DFFFFh

0E0000h–0E7FFFh

0E8000h–0EFFFFh

0F0000h–0F7FFFh

0F8000h–0FFFFFh

4

SA1

4

SA2

4

SA3

4

SA4

4

SA5

4

SA6

4

SA7

4

SA8

32

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

22

S29PL127J/S29PL064J/S29PL032J for MCP

S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

P r e l i m i n a r y

Table 4. PL127J Sector Architecture (Continued)

Bank

Sector

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

SA71

SA72

SA73

SA74

SA75

SA76

SA77

SA78

Sector Address (A22-A12)

00100000XXX

00100001XXX

00100010XXX

00100011XXX

00100100XXX

00100101XXX

00100110XXX

00100111XXX

00101000XXX

00101001XXX

00101010XXX

00101011XXX

00101100XXX

00101101XXX

00101110XXX

00101111XXX

00110000XXX

00110001XXX

00110010XXX

00110011XXX

00110100XXX

00110101XXX

00110110XXX

00110111XXX

00111000XXX

00111001XXX

00111010XXX

00111011XXX

00111100XXX

00111101XXX

00111110XXX

00111111XXX

01000000XXX

01000001XXX

01000010XXX

01000011XXX

01000100XXX

01000101XXX

01000110XXX

01000111XXX

Sector Size (Kwords)

Address Range (x16)

100000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1FFFFFh

200000h–207FFFh

208000h–20FFFFh

210000h–217FFFh

218000h–21FFFFh

220000h–227FFFh

228000h–22FFFFh

230000h–237FFFh

238000h–23FFFFh

32

August 12, 2004 S29PL127J_064J_032J_MCP_00_A3

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P r e l i m i n a r y

Table 4. PL127J Sector Architecture (Continued)

Bank

Sector

SA79

Sector Address (A22-A12)

01001000XXX

01001001XXX

01001010XXX

01001011XXX

01001100XXX

01001101XXX

01001110XXX

01001111XXX

01010000XXX

01010001XXX

01010010XXX

01010011XXX

01010100XXX

01010101XXX

01010110XXX

01010111XXX

01011000XXX

01011001XXX

01011010XXX

01011011XXX

01011100XXX

01011101XXX

01011110XXX

01011111XXX

01100000XXX

01100001XXX

01100010XXX

01100011XXX

01100100XXX

01100101XXX

01100110XXX

01100111XXX

01101000XXX

01101001XXX

01101010XXX

01101011XXX

01101100XXX

01101101XXX

01101110XXX

01101111XXX

Sector Size (Kwords)

Address Range (x16)

240000h–247FFFh

248000h–24FFFFh

250000h–257FFFh

258000h–25FFFFh

260000h–267FFFh

268000h–26FFFFh

270000h–277FFFh

278000h–27FFFFh

280000h–287FFFh

288000h–28FFFFh

290000h–297FFFh

298000h–29FFFFh

2A0000h–2A7FFFh

2A8000h–2AFFFFh

2B0000h–2B7FFFh

2B8000h–2BFFFFh

2C0000h–2C7FFFh

2C8000h–2CFFFFh

2D0000h–2D7FFFh

2D8000h–2DFFFFh

2E0000h–2E7FFFh

2E8000h–2EFFFFh

2F0000h–2F7FFFh

2F8000h–2FFFFFh

300000h–307FFFh

308000h–30FFFFh

310000h–317FFFh

318000h–31FFFFh

320000h–327FFFh

328000h–32FFFFh

330000h–337FFFh

338000h–33FFFFh

340000h–347FFFh

348000h–34FFFFh

350000h–357FFFh

358000h–35FFFFh

360000h–367FFFh

368000h–36FFFFh

370000h–377FFFh

378000h–37FFFFh

32

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

SA95

SA96

SA97

SA98

SA99

SA100

SA101

SA102

SA103

SA104

SA105

SA106

SA107

SA108

SA109

SA110

SA111

SA112

SA113

SA114

SA115

SA116

SA117

SA118

24

S29PL127J/S29PL064J/S29PL032J for MCP

S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

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Table 4. PL127J Sector Architecture (Continued)

Bank

Sector

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

SA128

SA129

SA130

SA131

SA132

SA133

SA134

SA135

SA136

SA137

SA138

SA139

SA140

SA141

SA142

SA143

SA144

SA145

SA146

SA147

SA148

SA149

SA150

SA151

SA152

SA153

SA154

SA155

SA156

SA157

SA158

Sector Address (A22-A12)

01110000XXX

01110001XXX

01110010XXX

01110011XXX

01110100XXX

01110101XXX

01110110XXX

01110111XXX

01111000XXX

01111001XXX

01111010XXX

01111011XXX

01111100XXX

01111101XXX

01111110XXX

01111111XXX

10000000XXX

10000001XXX

10000010XXX

10000011XXX

10000100XXX

10000101XXX

10000110XXX

10000111XXX

10001000XXX

10001001XXX

10001010XXX

10001011XXX

10001100XXX

10001101XXX

10001110XXX

10001111XXX

10010000XXX

10010001XXX

10010010XXX

10010011XXX

10010100XXX

10010101XXX

10010110XXX

10010111XXX

Sector Size (Kwords)

Address Range (x16)

380000h–387FFFh

388000h–38FFFFh

390000h–397FFFh

398000h–39FFFFh

3A0000h–3A7FFFh

3A8000h–3AFFFFh

3B0000h–3B7FFFh

3B8000h–3BFFFFh

3C0000h–3C7FFFh

3C8000h–3CFFFFh

3D0000h–3D7FFFh

3D8000h–3DFFFFh

3E0000h–3E7FFFh

3E8000h–3EFFFFh

3F0000h–3F7FFFh

3F8000h–3FFFFFh

400000h–407FFFh

408000h–40FFFFh

410000h–417FFFh

418000h–41FFFFh

420000h–427FFFh

428000h–42FFFFh

430000h–437FFFh

438000h–43FFFFh

440000h–447FFFh

448000h–44FFFFh

450000h–457FFFh

458000h–45FFFFh

460000h–467FFFh

468000h–46FFFFh

470000h–477FFFh

478000h–47FFFFh

480000h–487FFFh

488000h–48FFFFh

490000h–497FFFh

498000h–49FFFFh

4A0000h–4A7FFFh

4A8000h–4AFFFFh

4B0000h–4B7FFFh

4B8000h–4BFFFFh

32

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P r e l i m i n a r y

Table 4. PL127J Sector Architecture (Continued)

Bank

Sector

SA159

SA160

SA161

SA162

SA163

SA164

SA165

SA166

SA167

SA168

SA169

SA170

SA171

SA172

SA173

SA174

SA175

SA176

SA177

SA178

SA179

SA180

SA181

SA182

SA183

SA184

SA185

SA186

SA187

SA188

SA189

SA190

SA191

SA192

SA193

SA194

SA195

SA196

SA197

SA198

Sector Address (A22-A12)

10011000XXX

10011001XXX

10011010XXX

10011011XXX

10011100XXX

10011101XXX

10011110XXX

10011111XXX

10100000XXX

10100001XXX

10100010XXX

10100011XXX

10100100XXX

10100101XXX

10100110XXX

10100111XXX

10101000XXX

10101001XXX

10101010XXX

10101011XXX

10101100XXX

10101101XXX

10101110XXX

10101111XXX

10110000XXX

10110001XXX

10110010XXX

10110011XXX

10110100XXX

10110101XXX

10110110XXX

10110111XXX

10111000XXX

10111001XXX

10111010XXX

10111011XXX

10111100XXX

10111101XXX

10111110XXX

10111111XXX

Sector Size (Kwords)

Address Range (x16)

4C0000h–4C7FFFh

4C8000h–4CFFFFh

4D0000h–4D7FFFh

4D8000h–4DFFFFh

4E0000h–4E7FFFh

4E8000h–4EFFFFh

4F0000h–4F7FFFh

4F8000h–4FFFFFh

500000h–507FFFh

508000h–50FFFFh

510000h–517FFFh

518000h–51FFFFh

520000h–527FFFh

528000h–52FFFFh

530000h–537FFFh

538000h–53FFFFh

540000h–547FFFh

548000h–54FFFFh

550000h–557FFFh

558000h–15FFFFh

560000h–567FFFh

568000h–56FFFFh

570000h–577FFFh

578000h–57FFFFh

580000h–587FFFh

588000h–58FFFFh

590000h–597FFFh

598000h–59FFFFh

5A0000h–5A7FFFh

5A8000h–5AFFFFh

5B0000h–5B7FFFh

5B8000h–5BFFFFh

5C0000h–5C7FFFh

5C8000h–5CFFFFh

5D0000h–5D7FFFh

5D8000h–5DFFFFh

5E0000h–5E7FFFh

5E8000h–5EFFFFh

5F0000h–5F7FFFh

5F8000h–5FFFFFh

32

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Table 4. PL127J Sector Architecture (Continued)

Bank

Sector

SA199

SA200

SA201

SA202

SA203

SA204

SA205

SA206

SA207

SA208

SA209

SA210

SA211

SA212

SA213

SA214

SA215

SA216

SA217

SA218

SA219

SA220

SA221

SA222

SA223

SA224

SA225

SA226

SA227

SA228

SA229

SA230

Sector Address (A22-A12)

11000000XXX

11000001XXX

11000010XXX

11000011XXX

11000100XXX

11000101XXX

11000110XXX

11000111XXX

11001000XXX

11001001XXX

11001010XXX

11001011XXX

11001100XXX

11001101XXX

11001110XXX

11001111XXX

11010000XXX

11010001XXX

11010010XXX

11010011XXX

11010100XXX

11010101XXX

11010110XXX

11010111XXX

11011000XXX

11011001XXX

11011010XXX

11011011XXX

11011100XXX

11011101XXX

11011110XXX

11011111XXX

Sector Size (Kwords)

Address Range (x16)

600000h–607FFFh

608000h–60FFFFh

610000h–617FFFh

618000h–61FFFFh

620000h–627FFFh

628000h–62FFFFh

630000h–637FFFh

638000h–63FFFFh

640000h–647FFFh

648000h–64FFFFh

650000h–657FFFh

658000h–65FFFFh

660000h–667FFFh

668000h–66FFFFh

670000h–677FFFh

678000h–67FFFFh

680000h–687FFFh

688000h–68FFFFh

690000h–697FFFh

698000h–69FFFFh

6A0000h–6A7FFFh

6A8000h–6AFFFFh

6B0000h–6B7FFFh

6B8000h–6BFFFFh

6C0000h–6C7FFFh

6C8000h–6CFFFFh

6D0000h–6D7FFFh

6D8000h–6DFFFFh

6E0000h–6E7FFFh

6E8000h–6EFFFFh

6F0000h–6F7FFFh

6F8000h–6FFFFFh

32

Table 5. SecSiTM Sector Addresses

Sector Size

64 words

Address Range

Factory-Locked Area

000000h-00003Fh

000040h-00007Fh

Customer-Lockable Area

Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sector

protection verification, through identifier codes output on DQ7–DQ0. This mode

is primarily intended for programming equipment to automatically match a device

August 12, 2004 S29PL127J_064J_032J_MCP_00_A3

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P r e l i m i n a r y

to be programmed with its corresponding programming algorithm. However, the

autoselect codes can also be accessed in-system through the command register.

When using programming equipment, the autoselect mode requires V_IDon ad-

dress pin A9. Address pins must be set as shown in Table 6. In addition, when

verifying sector protection, the sector address must appear on the appropriate

highest order address bits (see Table 3). Table 6 shows the remaining address

bits that are don’t care. When all necessary bits have been set as required, the

programming equipment may then read the corresponding identifier code on

DQ7–DQ0. However, the autoselect codes can also be accessed in-system

through the command register, for instances when the device is erased or pro-

grammed in a system without access to high voltage on the A9 pin. The command

sequence is illustrated in Table 13. Note that if a Bank Address (BA) (on address

bits PL127J: A22–A20, PL064J: A21–A19, PL032J: A20–A18) is asserted during

the third write cycle of the autoselect command, the host system can read au-

toselect data that bank and then immediately read array data from the other

bank, without exiting the autoselect mode.

To access the autoselect codes in-system, the host system can issue the autose-

lect command via the command register, as shown in Table 13. This method does

not require V_ID. Refer to the Autoselect Command Sequence for more

information.

Table 6. Autoselect Codes (High Voltage Method)

Amax

to

A12

A5

to

A4

A1

0

DQ15

to DQ0

Description

CE#

OE#

WE#

A9 A8

A7

A6

A3 A2

A1

A0

Manufacturer ID:

Spansion

L

H

BA

X

V_ID

X

L

X

L

H

L

0001h

227Eh

products

Read

Cycle 1

2220h (PL127J)

2202h (PL064J)

220Ah (PL032J)

Read

Cycle 2

H

L

H

V_ID

L

2200h (PL127J)

2201h (PL064J)

2201h (PL032J)

Read

L

H

L

H

L

H

L

Cycle 3

Sector Protection

Verification

0001h (protected),

0000h (unprotected)

L

H

SA

BA

X

V_ID

X

L

00C4h (factory and

customer locked), 0084h

(factory locked), 0004h

(not locked)

SecSi Indicator

Bit (DQ7, DQ6)

L

V_ID

X

L

H

Legend: L = Logic Low = V_IL, H = Logic High = V_IH, BA = Bank Address, SA = Sector Address, X = Don’t care.

Note: The autoselect codes may also be accessed in-system via command sequences

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Table 7. PL127J Boot Sector/Sector Block Addresses for Protection/Unprotection

Sector/

Sector

SA0

A22-A12

Sector Block Size

Sector

A22-A12

Sector Block Size

00000000000

00000000001

00000000010

00000000011

00000000100

00000000101

00000000110

00000000111

00000001XXX

00000010XXX

00000011XXX

000001XXXXX

000010XXXXX

000011XXXXX

000100XXXXX

000101XXXXX

000110XXXXX

000111XXXXX

001000XXXXX

001001XXXXX

001010XXXXX

001011XXXXX

001100XXXXX

001101XXXXX

001110XXXXX

001111XXXXX

010000XXXXX

010001XXXXX

010010XXXXX

010011XXXXX

010100XXXXX

010101XXXXX

010110XXXXX

010111XXXXX

011000XXXXX

011001XXXXX

011010XXXXX

011011XXXXX

011100XXXXX

011101XXXXX

011110XXXXX

4 Kwords

SA131-SA134

SA135-SA138

SA139-SA142

SA143-SA146

SA147-SA150

SA151-SA154

SA155-SA158

SA159-SA162

SA163-SA166

SA167-SA170

SA171-SA174

SA175-SA178

SA179-SA182

SA183-SA186

SA187-SA190

SA191-SA194

SA195-SA198

SA199-SA202

SA203-SA206

SA207-SA210

SA211-SA214

SA215-SA218

SA219-SA222

SA223-SA226

SA227-SA230

SA231-SA234

SA235-SA238

SA239-SA242

SA243-SA246

SA247-SA250

SA251-SA254

SA255-SA258

SA259

011111XXXXX

100000XXXXX

100001XXXXX

100010XXXXX

100011XXXXX

100100XXXXX

100101XXXXX

100110XXXXX

100111XXXXX

101000XXXXX

101001XXXXX

101010XXXXX

101011XXXXX

101100XXXXX

101101XXXXX

101110XXXXX

101111XXXXX

110000XXXXX

110001XXXXX

110010XXXXX

110011XXXXX

110100XXXXX

110101XXXXX

110110XXXXX

110111XXXXX

111000XXXXX

111001XXXXX

111010XXXXX

111011XXXXX

111100XXXXX

111101XXXXX

111110XXXXX

11111100XXX

11111101XXX

11111110XXX

11111111000

11111111001

11111111010

11111111011

128 (4x32) Kwords

32 Kwords

SA1

4 Kwords

SA2

4 Kwords

SA3

4 Kwords

SA4

4 Kwords

SA5

4 Kwords

SA6

4 Kwords

SA7

4 Kwords

SA8

32 Kwords

SA9

32 Kwords

SA10

32 Kwords

SA11-SA14

SA15-SA18

SA19-SA22

SA23-SA26

SA27-SA30

SA31-SA34

SA35-SA38

SA39-SA42

SA43-SA46

SA47-SA50

SA51-SA54

SA55-SA58

SA59-SA62

SA63-SA66

SA67-SA70

SA71-SA74

SA75-SA78

SA79-SA82

SA83-SA86

SA87-SA90

SA91-SA94

SA95-SA98

SA99-SA102

SA103-SA106

SA107-SA110

SA111-SA114

SA115-SA118

SA119-SA122

SA123-SA126

SA127-SA130

128 (4x32) Kwords

SA260

32 Kwords

SA261

32 Kwords

SA262

4 Kwords

SA263

4 Kwords

SA264

4 Kwords

SA265

4 Kwords

August 12, 2004 S29PL127J_064J_032J_MCP_00_A3

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Selecting a Sector Protection Mode

The device is shipped with all sectors unprotected. Optional Spansion program-

ming services enable programming and protecting sectors at the factory prior to

shipping the device. Contact your local sales office for details.

It is possible to determine whether a sector is protected or unprotected. See the

SecSiTM Sector Addresses for details.

Table 8. Sector Protection Schemes

DYB

0

PPB

0

PPB Lock

Sector State

0

1

0

1

Unprotected—PPB and DYB are changeable

Unprotected—PPB not changeable, DYB is changeable

0

1

0

Protected—PPB and DYB are changeable

1

0

1

0

Protected—PPB not changeable, DYB is changeable

1

Sector Protection

The PL127J, PL064J, and PL032J features several levels of sector protection,

which can disable both the program and erase operations in certain sectors or

sector groups.

Sector Protection Schemes

Password Sector Protection

A highly sophisticated protection method that requires a password before

changes to certain sectors or sector groups are permitted

WP# Hardware Protection

A write protect pin that can prevent program or erase operations in sectors SA1-

133, SA1-134, SA2-0 and SA2-1.

The WP# Hardware Protection feature is always available, independent of the

software managed protection method chosen.

Selecting a Sector Protection Mode

All parts default to operate in the Persistent Sector Protection mode. The cus-

tomer must then choose if the Persistent or Password Protection method is most

desirable. There are two one-time programmable non-volatile bits that define

which sector protection method will be used. If the Persistent Sector Protection

method is desired, programming the Persistent Sector Protection Mode Locking

Bit permanently sets the device to the Persistent Sector Protection mode. If the

Password Sector Protection method is desired, programming the Password Mode

Locking Bit permanently sets the device to the Password Sector Protection mode.

It is not possible to switch between the two protection modes once a locking bit

has been set. One of the two modes must be selected when the device is first

programmed. This prevents a program or virus from later setting the Password

30

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S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

P r e l i m i n a r y

Mode Locking Bit, which would cause an unexpected shift from the default Per-

sistent Sector Protection Mode into the Password Protection Mode.

The device is shipped with all sectors unprotected. Optional Spansion program-

ming services enable programming and protecting sectors at the factory prior to

shipping the device. Contact your local sales office for details.

It is possible to determine whether a sector is protected or unprotected. See Au-

toselect Mode for details.

Persistent Sector Protection

The Persistent Sector Protection method replaces the 12 V controlled protection

method in previous flash devices. This new method provides three different sec-

tor protection states:

Persistently Locked—The sector is protected and cannot be changed.

Dynamically Locked—The sector is protected and can be changed by a simple

command.

Unlocked—The sector is unprotected and can be changed by a simple com-

mand.

To achieve these states, three types of “bits” are used:

Persistent Protection Bit

Persistent Protection Bit Lock

Persistent Sector Protection Mode Locking Bit

Persistent Protection Bit (PPB)

A single Persistent (non-volatile) Protection Bit is assigned to a maximum four

sectors (see the sector address tables for specific sector protection groupings).

All 4 Kword boot-block sectors have individual sector Persistent Protection Bits

(PPBs) for greater flexibility. Each PPB is individually modifiable through the PPB

Write Command.

The device erases all PPBs in parallel. If any PPB requires erasure, the device

must be instructed to preprogram all of the sector PPBs prior to PPB erasure. Oth-

erwise, a previously erased sector PPBs can potentially be over-erased. The flash

device does not have a built-in means of preventing sector PPBs over-erasure.

Persistent Protection Bit Lock (PPB Lock)

The Persistent Protection Bit Lock (PPB Lock) is a global volatile bit. When set to

“1”, the PPBs cannot be changed. When cleared (“0”), the PPBs are changeable.

There is only one PPB Lock bit per device. The PPB Lock is cleared after power-

up or hardware reset. There is no command sequence to unlock the PPB Lock.

Dynamic Protection Bit (DYB)

A volatile protection bit is assigned for each sector. After power-up or hardware

reset, the contents of all DYBs is “0”. Each DYB is individually modifiable through

the DYB Write Command.

When the parts are first shipped, the PPBs are cleared, the DYBs are cleared, and

PPB Lock is defaulted to power up in the cleared state – meaning the PPBs are

changeable.

When the device is first powered on the DYBs power up cleared (sectors not pro-

tected). The Protection State for each sector is determined by the logical OR of

the PPB and the DYB related to that sector. For the sectors that have the PPBs

cleared, the DYBs control whether or not the sector is protected or unprotected.

August 12, 2004 S29PL127J_064J_032J_MCP_00_A3

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P r e l i m i n a r y

By issuing the DYB Write command sequences, the DYBs will be set or cleared,

thus placing each sector in the protected or unprotected state. These are the so-

called Dynamic Locked or Unlocked states. They are called dynamic states be-

cause it is very easy to switch back and forth between the protected and

unprotected conditions. This allows software to easily protect sectors against in-

advertent changes yet does not prevent the easy removal of protection when

changes are needed. The DYBs maybe set or cleared as often as needed.

The PPBs allow for a more static, and difficult to change, level of protection. The

PPBs retain their state across power cycles because they are non-volatile. Indi-

vidual PPBs are set with a command but must all be cleared as a group through

a complex sequence of program and erasing commands. The PPBs are also lim-

ited to 100 erase cycles.

The PPB Lock bit adds an additional level of protection. Once all PPBs are pro-

grammed to the desired settings, the PPB Lock may be set to “1”. Setting the PPB

Lock disables all program and erase commands to the non-volatile PPBs. In ef-

fect, the PPB Lock Bit locks the PPBs into their current state. The only way to clear

the PPB Lock is to go through a power cycle. System boot code can determine if

any changes to the PPB are needed; for example, to allow new system code to

be downloaded. If no changes are needed then the boot code can set the PPB

Lock to disable any further changes to the PPBs during system operation.

The WP#/ACC write protect pin adds a final level of hardware protection to sec-

tors SA1-133, SA1-134, SA2-0 and SA2-1. When this pin is low it is not possible

to change the contents of these sectors. These sectors generally hold system

boot code. The WP#/ACC pin can prevent any changes to the boot code that could

override the choices made while setting up sector protection during system

initialization.

For customers who are concerned about malicious viruses there is another level

of security - the persistently locked state. To persistently protect a given sector

or sector group, the PPBs associated with that sector need to be set to “1”. Once

all PPBs are programmed to the desired settings, the PPB Lock should be set to

“1”. Setting the PPB Lock automatically disables all program and erase commands

to the Non-Volatile PPBs. In effect, the PPB Lock “freezes” the PPBs into their cur-

rent state. The only way to clear the PPB Lock is to go through a power cycle.

It is possible to have sectors that have been persistently locked, and sectors that

are left in the dynamic state. The sectors in the dynamic state are all unprotected.

If there is a need to protect some of them, a simple DYB Write command se-

quence is all that is necessary. The DYB write command for the dynamic sectors

switch the DYBs to signify protected and unprotected, respectively. If there is a

need to change the status of the persistently locked sectors, a few more steps

are required. First, the PPB Lock bit must be disabled by either putting the device

through a power-cycle, or hardware reset. The PPBs can then be changed to re-

flect the desired settings. Setting the PPB lock bit once again will lock the PPBs,

and the device operates normally again.

The best protection is achieved by executing the PPB lock bit set command early

in the boot code, and protect the boot code by holding WP#/ACC = VIL.

Table 8 contains all possible combinations of the DYB, PPB, and PPB lock relating

to the status of the sector.

In summary, if the PPB is set, and the PPB lock is set, the sector is protected and

the protection can not be removed until the next power cycle clears the PPB lock.

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If the PPB is cleared, the sector can be dynamically locked or unlocked. The DYB

then controls whether or not the sector is protected or unprotected.

If the user attempts to program or erase a protected sector, the device ignores

the command and returns to read mode. A program command to a protected sec-

tor enables status polling for approximately 1 µs before the device returns to read

mode without having modified the contents of the protected sector. An erase

command to a protected sector enables status polling for approximately 50 µs

after which the device returns to read mode without having erased the protected

sector.

The programming of the DYB, PPB, and PPB lock for a given sector can be verified

by writing a DYB/PPB/PPB lock verify command to the device. There is an alter-

native means of reading the protection status. Take RESET# to VIL and hold WE#

at VIH.(The high voltage A9 Autoselect Mode also works for reading the status of

the PPBs). Scanning the addresses (A18–A11) while (A6, A1, A0) = (0, 1, 0) will

produce a logical ‘1” code at device output DQ0 for a protected sector or a “0” for

an unprotected sector. In this mode, the other addresses are don’t cares. Address

location with A1 = VIL are reserved for autoselect manufacturer and device

codes.

Persistent Sector Protection Mode Locking Bit

Like the password mode locking bit, a Persistent Sector Protection mode locking

bit exists to guarantee that the device remain in software sector protection. Once

set, the Persistent Sector Protection locking bit prevents programming of the

password protection mode locking bit. This guarantees that a hacker could not

place the device in password protection mode.

Password Protection Mode

The Password Sector Protection Mode method allows an even higher level of se-

curity than the Persistent Sector Protection Mode. There are two main differences

between the Persistent Sector Protection and the Password Sector Protection

Mode:

When the device is first powered on, or comes out of a reset cycle, the PPB Lock

bit set to the locked state, rather than cleared to the unlocked state.

The only means to clear the PPB Lock bit is by writing a unique 64-bit Password

to the device.

The Password Sector Protection method is otherwise identical to the Persistent

Sector Protection method.

A 64-bit password is the only additional tool utilized in this method.

Once the Password Mode Locking Bit is set, the password is permanently set with

no means to read, program, or erase it. The password is used to clear the PPB

Lock bit. The Password Unlock command must be written to the flash, along with

a password. The flash device internally compares the given password with the

pre-programmed password. If they match, the PPB Lock bit is cleared, and the

PPBs can be altered. If they do not match, the flash device does nothing. There

is a built-in 2 µs delay for each “password check.” This delay is intended to thwart

any efforts to run a program that tries all possible combinations in order to crack

the password.

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Password and Password Mode Locking Bit

In order to select the Password sector protection scheme, the customer must first

program the password. The password may be correlated to the unique Electronic

Serial Number (ESN) of the particular flash device. Each ESN is different for every

flash device; therefore each password should be different for every flash device.

While programming in the password region, the customer may perform Password

Verify operations.

Once the desired password is programmed in, the customer must then set the

Password Mode Locking Bit. This operation achieves two objectives:

Permanently sets the device to operate using the Password Protection Mode. It is

not possible to reverse this function.

Disables all further commands to the password region. All program, and read op-

erations are ignored.

Both of these objectives are important, and if not carefully considered, may lead

to unrecoverable errors. The user must be sure that the Password Protection

method is desired when setting the Password Mode Locking Bit. More importantly,

the user must be sure that the password is correct when the Password Mode

Locking Bit is set. Due to the fact that read operations are disabled, there is no

means to verify what the password is afterwards. If the password is lost after set-

ting the Password Mode Locking Bit, there will be no way to clear the PPB Lock bit.

The Password Mode Locking Bit, once set, prevents reading the 64-bit password

on the DQ bus and further password programming. The Password Mode Locking

Bit is not erasable. Once Password Mode Locking Bit is programmed, the Persis-

tent Sector Protection Locking Bit is disabled from programming, guaranteeing

that no changes to the protection scheme are allowed.

64-bit Password

The 64-bit Password is located in its own memory space and is accessible through

the use of the Password Program and Verify commands (see “Password Verify

Command”). The password function works in conjunction with the Password

Mode Locking Bit, which when set, prevents the Password Verify command from

reading the contents of the password on the pins of the device.

Write Protect (WP#)

The Write Protect feature provides a hardware method of protecting the upper

two and lower two sectors without using V_ID. This function is provided by the WP#

pin and overrides the previously discussed High Voltage Sector Protection

method.

If the system asserts V_ILon the WP#/ACC pin, the device disables program and

erase functions in the two outermost 4 Kword sectors on both ends of the flash

array independent of whether it was previously protected or unprotected.

If the system asserts V_IHon the WP#/ACC pin, the device reverts the upper two

and lower two sectors to whether they were last set to be protected or unpro-

tected. That is, sector protection or unprotection for these sectors depends on

whether they were last protected or unprotected using the method described in

the High Voltage Sector Protection.

Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent

behavior of the device may result.

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Persistent Protection Bit Lock

The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of

the Password Mode Locking Bit after power-up reset. If the Password Mode Lock

Bit is also set after a hardware reset (RESET# asserted) or a power-up reset, the

ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to issue

the Password Unlock command. Successful execution of the Password Unlock

command clears the PPB Lock Bit, allowing for sector PPBs modifications. Assert-

ing RESET#, taking the device through a power-on reset, or issuing the PPB Lock

Bit Set command sets the PPB Lock Bit to a “1” when the Password Mode Lock Bit

is not set.

If the Password Mode Locking Bit is not set, including Persistent Protection Mode,

the PPB Lock Bit is cleared after power-up or hardware reset. The PPB Lock Bit is

set by issuing the PPB Lock Bit Set command. Once set the only means for clear-

ing the PPB Lock Bit is by issuing a hardware or power-up reset. The Password

Unlock command is ignored in Persistent Protection Mode.

High Voltage Sector Protection

Sector protection and unprotection may also be implemented using programming

equipment. The procedure requires high voltage (V_ID) to be placed on the RE-

SET# pin. Refer to Figure 1 for details on this procedure. Note that for sector

unprotect, all unprotected sectors must first be protected prior to the first sector

write cycle.

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START

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

PLSCNT = 1

RESET# = V_ID

unprotected sectors

prior to issuing the

first sector

Wait 4 µs

unprotect address

No

First Write

Cycle = 60h?

Temporary Sector

Unprotect Mode

Temporary Sector

Unprotect Mode

Cycle = 60h?

Yes

Set up sector

address

No

All sectors

protected?

Sector Protect:

Write 60h to sector

address with

A7-A0 =

Yes

Set up first sector

address

00000010

Sector Unprotect:

Wait 100 µs

Write 60h to sector

address with

A7-A0 =

Verify Sector

Protect: Write 40h

to sector address

with A7-A0 =

01000010

Reset

PLSCNT = 1

Increment

PLSCNT

Wait 1.2 ms

00000010

Verify Sector

Unprotect: Write

40h to sector

address with

A7-A0 =

Read from

sector address

with A7-A0 =

00000010

Increment

PLSCNT

No

00000010

No

PLSCNT

= 25?

Read from

sector address

with A7-A0 =

00000010

Data = 01h?

Yes

No

Yes

Set up

next sector

address

Yes

Remove V_ID

from RESET#

No

PLSCNT

= 1000?

Protect another

sector?

Data = 00h?

Yes

No

Write reset

command

Yes

Remove V_ID

from RESET#

Remove V_ID

from RESET#

No

Last sector

verified?

Sector Protect

complete

Write reset

command

Yes

Write reset

command

Remove V_ID

from RESET#

Device failed

Sector Protect

complete

Sector Unprotect

complete

Write reset

command

Sector Protect

Algorithm

Device failed

Sector Unprotect

complete

Sector Unprotect

Algorithm

Figure 1. In-System Sector Protection/Sector Unprotection Algorithms

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Temporary Sector Unprotect

This feature allows temporary unprotection of previously protected sectors to

change data in-system. The Sector Unprotect mode is activated by setting the

RESET# pin to V_ID. During this mode, formerly protected sectors can be pro-

grammed or erased by selecting the sector addresses. Once V_IDis removed from

the RESET# pin, all the previously protected sectors are protected again. 2 shows

the algorithm, and 21 shows the timing diagrams, for this feature. While PPB lock

is set, the device cannot enter the Temporary Sector Unprotection Mode.

START

RESET# = V_ID

(Note 1)

Perform Erase or

Program Operations

RESET# = V_IH

Temporary Sector

Unprotect Completed

(Note 2)

Notes:

1. All protected sectors unprotected (If WP#/ACC = V , upper two and lower two

IL

sectors will remain protected).

2. All previously protected sectors are protected once again

Figure 2. Temporary Sector Unprotect Operation

SecSi™ (Secured Silicon) Sector Flash Memory Region

The SecSi (Secured Silicon) Sector feature provides a Flash memory region that

enables permanent part identification through an Electronic Serial Number (ESN)

The 128-word SecSi sector is divided into 64 factory-lockable words that can be

programmed and locked by the customer. The SecSi sector is located at ad-

dresses 000000h-00007Fh in both Persistent Protection mode and Password

Protection mode. It uses indicator bits (DQ6, DQ7) to indicate the factory-locked

and customer-locked status of the part.

The system accesses the SecSi Sector through a command sequence (see the

Enter SecSi™ Sector/Exit SecSi Sector Command Sequence). After the system

has written the Enter SecSi Sector command sequence, it may read the SecSi

Sector by using the addresses normally occupied by the boot sectors. This mode

of operation continues until the system issues the Exit SecSi Sector command se-

quence, or until power is removed from the device. On power-up, or following a

hardware reset, the device reverts to sending commands to the normal address

space. Note that the ACC function and unlock bypass modes are not available

when the SecSi Sector is enabled.

Factory-Locked Area (64 words)

The factory-locked area of the SecSi Sector (000000h-00003Fh) is locked when

the part is shipped, whether or not the area was programmed at the factory. The

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SecSi Sector Factory-locked Indicator Bit (DQ7) is permanently set to a “1”. Op-

tional Spansion programming services can program the factory-locked area with

a random ESN, a customer-defined code, or any combination of the two. Because

only Spansion can program and protect the factory-locked area, this method en-

sures the security of the ESN once the product is shipped to the field. Contact

your local sales office for details on using Spansion’s programming services. Note

that the ACC function and unlock bypass modes are not available when the SecSi

sector is enabled.

Customer-Lockable Area (64 words)

The customer-lockable area of the SecSi Sector (000040h-00007Fh) is shipped

unprotected, which allows the customer to program and optionally lock the area

as appropriate for the application. The SecSi Sector Customer-locked Indicator

Bit (DQ6) is shipped as “0” and can be permanently locked to “1” by issuing the

SecSi Protection Bit Program Command. The SecSi Sector can be read any num-

ber of times, but can be programmed and locked only once. Note that the

accelerated programming (ACC) and unlock bypass functions are not available

when programming the SecSi Sector.

The Customer-lockable SecSi Sector area can be protected using one of the

following procedures:

Write the three-cycle Enter SecSi Sector Region command sequence, and

then follow the in-system sector protect algorithm as shown in Figure 1, ex-

cept that RESET# may be at either V_IHor V_ID. This allows in-system protec-

tion of the SecSi Sector Region without raising any device pin to a high

voltage. Note that this method is only applicable to the SecSi Sector.

To verify the protect/unprotect status of the SecSi Sector, follow the algo-

rithm shown in Figure 3.

Once the SecSi Sector is locked and verified, the system must write the Exit SecSi

Sector Region command sequence to return to reading and writing the remainder

of the array.

The SecSi Sector lock must be used with caution since, once locked, there is no

procedure available for unlocking the SecSi Sector area and none of the bits in

the SecSi Sector memory space can be modified in any way.

SecSi Sector Protection Bits

The SecSi Sector Protection Bits prevent programming of the SecSi Sector mem-

ory area. Once set, the SecSi Sector memory area contents are non-modifiable.

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START

If data = 00h,

SecSi Sector is

unprotected.

If data = 01h,

SecSi Sector is

protected.

RESET# =

V_IHor V_ID

Wait 1 µs

Write 60h to

any address

Remove V_IHor V_ID

from RESET#

Write 40h to SecSi

Sector address

with A6 = 0,

Write reset

command

A1 = 1, A0 = 0

SecSi Sector

Protect Verify

complete

Read from SecSi

Sector address

with A6 = 0,

A1 = 1, A0 = 0

Figure 3. SecSi Sector Protect Verify

Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing

provides data protection against inadvertent writes. In addition, the following

hardware data protection measures prevent accidental erasure or programming,

which might otherwise be caused by spurious system level signals during V_CC

power-up and power-down transitions, or from system noise.

Low V

Write Inhibit

CC

When V_CCis less than V_LKO, the device does not accept any write cycles. This pro-

tects data during V_CCpower-up and power-down. The command register and all

internal program/erase circuits are disabled, and the device resets to the read

mode. Subsequent writes are ignored until V_CCis greater than V_LKO. The system

must provide the proper signals to the control pins to prevent unintentional writes

when V_CCis greater than V_LKO

.

Write Pulse “Glitch” Protection

Noise pulses of less than 3 ns (typical) on OE#, CE#, or WE# do not initiate a

write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# = V_IL, CE# = V_IHor WE# =

V_IH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a

logical one.

Power-Up Write Inhibit

If WE# = CE# = V_ILand OE# = V_IHduring power up, the device does not accept

commands on the rising edge of WE#. The internal state machine is automatically

reset to the read mode on power-up.

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Common Flash Memory Interface (CFI)

The Common Flash Interface (CFI) specification outlines device and host system

software interrogation handshake, which allows specific vendor-specified soft-

ware algorithms to be used for entire families of devices. Software support can

then be device-independent, JEDEC ID-independent, and forward- and back-

ward-compatible for the specified flash device families. Flash vendors can

standardize their existing interfaces for long-term compatibility.

This device enters the CFI Query mode when the system writes the CFI Query

command, 98h, to address 55h, any time the device is ready to read array data.

The system can read CFI information at the addresses given in Tables 9–12. To

terminate reading CFI data, the system must write the reset command. The CFI

Query mode is not accessible when the device is executing an Embedded Program

or embedded Erase algorithm.

The system can also write the CFI query command when the device is in the au-

toselect mode. The device enters the CFI query mode, and the system can read

CFI data at the addresses given in Tables 9–12. The system must write the reset

command to return the device to reading array data.

For further information, please refer to the CFI Specification and CFI Publication

100. Contact your local sales office for copies of these documents.

Table 9. CFI Query Identification String

Addresses

Data

Description

10h

11h

12h

0051h

0052h

0059h

Query Unique ASCII string “QRY”

13h

14h

0002h

0000h

Primary OEM Command Set

15h

16h

0040h

0000h

Address for Primary Extended Table

17h

18h

0000h

Alternate OEM Command Set (00h = none exists)

19h

1Ah

0000h

Address for Alternate OEM Extended Table (00h = none exists)

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Table 10. System Interface String

Addresses

Data

Description

V_CCMin. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Bh

0027h

V_CCMax. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Ch

0036h

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

0000h

0003h

0000h

0009h

0000h

0004h

0000h

0004h

0000h

V_PPMin. voltage (00h = no V_PPpin present)

V_PPMax. voltage (00h = no V_PPpin present)

Typical timeout per single byte/word write 2^Nµs

Typical timeout for Min. size buffer write 2^N

Typical timeout per individual block erase 2^Nms

µs (00h = not supported)

Typical timeout for full chip erase 2^Nms (00h = not supported)

Max. timeout for byte/word write 2^Ntimes typical

Max. timeout for buffer write 2^Ntimes typical

Max. timeout per individual block erase 2^Ntimes typical

Max. timeout for full chip erase 2^Ntimes typical (00h = not supported)

Table 11. Device Geometry Definition

Addresses

Data

Description

0018h (PL127J)

0017h (PL064J)

0016h (PL032J)

27h

Device Size = 2^Nbyte

28h

29h

0001h

0000h

Flash Device Interface description (refer to CFI publication 100)

2Ah

2Bh

0000h

Max. number of byte in multi-byte write = 2^N

(00h = not supported)

2Ch

0003h

Number of Erase Block Regions within device

2Dh

2Eh

2Fh

30h

0007h

0000h

0020h

0000h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

00FDh (PL127J)

007Dh (PL064J)

003Dh (PL032J)

31h

Erase Block Region 2 Information

(refer to the CFI specification or CFI publication 100)

32h

33h

34h

0000h

0001h

35h

36h

37h

38h

0007h

0000h

0020h

0000h

Erase Block Region 3 Information

(refer to the CFI specification or CFI publication 100)

39h

3Ah

3Bh

3Ch

0000h

Erase Block Region 4 Information

(refer to the CFI specification or CFI publication 100)

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Table 12. Primary Vendor-Specific Extended Query

Addresses

Data

Description

40h

41h

42h

0050h

0052h

0049h

Query-unique ASCII string “PRI”

43h

44h

0031h

0033h

Major version number, ASCII (reflects modifications to the silicon)

Minor version number, ASCII (reflects modifications to the CFI table)

Address Sensitive Unlock (Bits 1-0)

0 = Required, 1 = Not Required

45h

TBD

Silicon Revision Number (Bits 7-2)

Erase Suspend

46h

47h

48h

49h

0002h

0001h

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

Sector Protect

0 = Not Supported, X = Number of sectors in per group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

07 = Advanced Sector Protection

0007h (PLxxxJ)

00E7h (PL127J)

0077h (PL064J)

003Fh (PL032J)

Simultaneous Operation

00 = Not Supported, X = Number of Sectors excluding Bank 1

4Ah

Burst Mode Type

00 = Not Supported, 01 = Supported

4Bh

4Ch

4Dh

4Eh

0000h

0002h (PLxxxJ)

0085h

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

ACC (Acceleration) Supply Minimum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

ACC (Acceleration) Supply Maximum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

0095h

Top/Bottom Boot Sector Flag

00h = Uniform device, 01h = Both top and bottom boot with write protect,

02h = Bottom Boot Device, 03h = Top Boot Device,

04h = Both Top and Bottom

4Fh

0001h

Program Suspend

0 = Not supported, 1 = Supported

50h

57h

0001h

0004h

Bank Organization

00 = Data at 4Ah is zero, X = Number of Banks

0027h (PL127J)

0017h (PL064J)

000Fh (PL032J)

Bank 1 Region Information

X = Number of Sectors in Bank 1

58h

59h

5Ah

0060h (PL127J)

0030h (PL064J)

0018h (PL032J)

Bank 2 Region Information

X = Number of Sectors in Bank 2

0060h (PL127J)

0030h (PL064J)

0018h (PL032J)

Bank 3 Region Information

X = Number of Sectors in Bank 3

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Table 12. Primary Vendor-Specific Extended Query (Continued)

Addresses

Data

Description

0027h (PL127J)

0017h (PL064J)

000Fh (PL032J)

Bank 4 Region Information

X = Number of Sectors in Bank 4

5Bh

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Command Definitions

Writing specific address and data commands or sequences into the command

register initiates device operations. Table 13 defines the valid register command

sequences. Writing incorrect address and data values or writing them in the

improper sequence may place the device in an unknown state. A reset com-

mand is then required to return the device to reading array data.

All addresses are latched on the falling edge of WE# or CE#, whichever happens

later. All data is latched on the rising edge of WE# or CE#, whichever happens

first. Refer to the AC Characteristic section for timing diagrams.

Reading Array Data

The device is automatically set to reading array data after device power-up. No

commands are required to retrieve data. Each bank is ready to read array data

after completing an Embedded Program or Embedded Erase algorithm.

After the device accepts an Erase Suspend command, the corresponding bank

enters the erase-suspend-read mode, after which the system can read data from

any non-erase-suspended sector within the same bank. The system can read

array data using the standard read timing, except that if it reads at an address

within erase-suspended sectors, the device outputs status data. After completing

a programming operation in the Erase Suspend mode, the system may once

again read array data with the same exception. See the Erase Suspend/Erase Re-

sume Commands section for more information.

The system must issue the reset command to return a bank to the read (or erase-

suspend-read) mode if DQ5 goes high during an active program or erase opera-

tion, or if the bank is in the autoselect mode. See the next section, Reset

Command, for more information.

See also Requirements for Reading Array Data in the Device Bus Operations sec-

tion for more information. The AC Characteristic table provides the read

parameters, and Figure 12 shows the timing diagram.

Reset Command

Writing the reset command resets the banks to the read or erase-suspend-read

mode. Address bits are don’t cares for this command.

The reset command may be written between the sequence cycles in an erase

command sequence before erasing begins. This resets the bank to which the sys-

tem was writing to the read mode. Once erasure begins, however, the device

ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in a program

command sequence before programming begins. This resets the bank to which

the system was writing to the read mode. If the program command sequence is

written to a bank that is in the Erase Suspend mode, writing the reset command

returns that bank to the erase-suspend-read mode. Once programming begins,

however, the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in an autoselect

command sequence. Once in the autoselect mode, the reset command must be

written to return to the read mode. If a bank entered the autoselect mode while

in the Erase Suspend mode, writing the reset command returns that bank to the

erase-suspend-read mode.

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If DQ5 goes high during a program or erase operation, writing the reset command

returns the banks to the read mode (or erase-suspend-read mode if that bank

was in Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manu-

facturer and device codes, and determine whether or not a sector is protected.

The autoselect command sequence may be written to an address within a bank

that is either in the read or erase-suspend-read mode. The autoselect command

may not be written while the device is actively programming or erasing in the

other bank.

The autoselect command sequence is initiated by first writing two unlock cycles.

This is followed by a third write cycle that contains the bank address and the au-

toselect command. The bank then enters the autoselect mode. The system may

read any number of autoselect codes without reinitiating the command sequence.

Table 13 shows the address and data requirements. To determine sector protec-

tion information, the system must write to the appropriate bank address (BA) and

sector address (SA). Table 3 shows the address range and bank number associ-

ated with each sector.

The system must write the reset command to return to the read mode (or erase-

suspend-read mode if the bank was previously in Erase Suspend).

Enter SecSi™ Sector/Exit SecSi Sector Command Sequence

The SecSi Sector region provides a secured data area containing a random, eight

word electronic serial number (ESN). The system can access the SecSi Sector re-

gion by issuing the three-cycle Enter SecSi Sector command sequence. The

device continues to access the SecSi Sector region until the system issues the

four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command

sequence returns the device to normal operation. The SecSi Sector is not acces-

sible when the device is executing an Embedded Program or embedded Erase

algorithm. Table 13 shows the address and data requirements for both command

sequences. See also “SecSi™ (Secured Silicon) Sector Flash Memory Region” for

further information. Note that the ACC function and unlock bypass modes are not

available when the SecSi Sector is enabled.

Word Program Command Sequence

Programming is a four-bus-cycle operation. The program command sequence is

initiated by writing two unlock write cycles, followed by the program set-up com-

mand. The program address and data are written next, which in turn initiate the

Embedded Program algorithm. The system is not required to provide further con-

trols or timings. The device automatically provides internally generated program

pulses and verifies the programmed cell margin. Table 13 shows the address and

data requirements for the program command sequence. Note that the SecSi Sec-

tor, autoselect, and CFI functions are unavailable when a [program/erase]

operation is in progress.

When the Embedded Program algorithm is complete, that bank then returns to

the read mode and addresses are no longer latched. The system can determine

the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the

Write Operation Status section for information on these status bits.

Any commands written to the device during the Embedded Program Algorithm

are ignored. Note that a hardware reset immediately terminates the program

August 12, 2004 S29PL127J_064J_032J_MCP_00_A3

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P r e l i m i n a r y

operation. The program command sequence should be reinitiated once that bank

has returned to the read mode, to ensure data integrity. Note that the SecSi Sec-

tor, autoselect and CFI functions are unavailable when the SecSi Sector is

enabled.

Programming is allowed in any sequence and across sector boundaries. A bit

cannot be programmed from “0” back to a “1.” Attempting to do so may

cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate

the operation was successful. However, a succeeding read will show that the data

is still “0.” Only erase operations can convert a “0” to a “1.”

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to program data to a bank faster

than using the standard program command sequence. The unlock bypass com-

mand sequence is initiated by first writing two unlock cycles. This is followed by

a third write cycle containing the unlock bypass command, 20h. That bank then

enters the unlock bypass mode. A two-cycle unlock bypass program command

sequence is all that is required to program in this mode. The first cycle in this se-

quence contains the unlock bypass program command, A0h; the second cycle

contains the program address and data. Additional data is programmed in the

same manner. This mode dispenses with the initial two unlock cycles required in

the standard program command sequence, resulting in faster total programming

time. Table 13 shows the requirements for the command sequence.

During the unlock bypass mode, only the Unlock Bypass Program and Unlock By-

pass Reset commands are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset command sequence. (See Table 14)

The device offers accelerated program operations through the WP#/ACC pin.

When the system asserts V_HHon the WP#/ACC pin, the device automatically en-

ters the Unlock Bypass mode. The system may then write the two-cycle Unlock

Bypass program command sequence. The device uses the higher voltage on the

WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not

be at V_HHany operation other than accelerated programming, or device damage

may result. In addition, the WP#/ACC pin must not be left floating or uncon-

nected; inconsistent behavior of the device may result.

4 illustrates the algorithm for the program operation. Refer to the Erase/Program

Operations table in the AC Characteristics section for parameters, and Figure 14

for timing diagrams.

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START

Write Program

Command Sequence

Data Poll

from System

Embedded

Program

algorithm

in progress

Verify Data?

Yes

No

Increment Address

Last Address?

Yes

Programming

Completed

Note: See Table 13 for program command sequence.

Figure 4. Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase command sequence is ini-

tiated by writing two unlock cycles, followed by a set-up command. Two

additional unlock write cycles are then followed by the chip erase command,

which in turn invokes the Embedded Erase algorithm. The device does not require

the system to preprogram prior to erase. The Embedded Erase algorithm auto-

matically preprograms and verifies the entire memory for an all zero data pattern

prior to electrical erase. The system is not required to provide any controls or tim-

ings during these operations. Table 13 shows the address and data requirements

for the chip erase command sequence.

When the Embedded Erase algorithm is complete, that bank returns to the read

mode and addresses are no longer latched. The system can determine the status

of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to the Write

Operation Status section for information on these status bits.

Any commands written during the chip erase operation are ignored. Note that

SecSi Sector, autoselect, and CFI functions are unavailable when a [program/

erase] operation is in progress. However, note that a hardware reset immedi-

ately terminates the erase operation. If that occurs, the chip erase command

sequence should be reinitiated once that bank has returned to reading array data,

to ensure data integrity.

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5 illustrates the algorithm for the erase operation. Refer to the Erase/Program

Operations tables in the AC Characteristics section for parameters, and Figure 16

section for timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase command sequence is

initiated by writing two unlock cycles, followed by a set-up command. Two addi-

tional unlock cycles are written, and are then followed by the address of the

sector to be erased, and the sector erase command. Table 13 shows the address

and data requirements for the sector erase command sequence.

The device does not require the system to preprogram prior to erase. The Em-

bedded Erase algorithm automatically programs and verifies the entire memory

for an all zero data pattern prior to electrical erase. The system is not required to

provide any controls or timings during these operations.

After the command sequence is written, a sector erase time-out of 50 µs occurs.

During the time-out period, additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer may be done in any

sequence, and the number of sectors may be from one sector to all sectors. The

time between these additional cycles must be less than 50 µs, otherwise erasure

may begin. Any sector erase address and command following the exceeded time-

out may or may not be accepted. It is recommended that processor interrupts be

disabled during this time to ensure all commands are accepted. The interrupts

can be re-enabled after the last Sector Erase command is written. Any com-

mand other than Sector Erase or Erase Suspend during the time-out

period resets that bank to the read mode. The system must rewrite the com-

mand sequence and any additional addresses and commands. Note that SecSi

Sector, autoselect, and CFI functions are unavailable when a [program/erase]

operation is in progress.

The system can monitor DQ3 to determine if the sector erase timer has timed out

(See the section on DQ3: Sector Erase Timer). The time-out begins from the ris-

ing edge of the final WE# pulse in the command sequence.

When the Embedded Erase algorithm is complete, the bank returns to reading

array data and addresses are no longer latched. Note that while the Embedded

Erase operation is in progress, the system can read data from the non-erasing

bank. The system can determine the status of the erase operation by reading

DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer to the Write Operation Sta-

tus section for information on these status bits.

Once the sector erase operation has begun, only the Erase Suspend command is

valid. All other commands are ignored. However, note that a hardware reset im-

mediately terminates the erase operation. If that occurs, the sector erase

command sequence should be reinitiated once that bank has returned to reading

array data, to ensure data integrity.

5 illustrates the algorithm for the erase operation. Refer to the Erase/Program

Operations tables in the AC Characteristics section for parameters, and Figure 16

section for timing diagrams.

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START

Write Erase

Command Sequence

(Notes 1, 2)

Data Poll to Erasing

Bank from System

Embedded

Erase

algorithm

in progress

No

Data = FFh?

Yes

Erasure Completed

Notes:

1. See Table 13 for erase command sequence.

2. See the section on DQ3 for information on the sector erase timer.

Figure 5. Erase Operation

Erase Suspend/Erase Resume Commands

The Erase Suspend command, B0h, allows the system to interrupt a sector erase

operation and then read data from, or program data to, any sector not selected

for erasure. The bank address is required when writing this command. This com-

mand is valid only during the sector erase operation, including the 80 µs time-out

period during the sector erase command sequence. The Erase Suspend command

is ignored if written during the chip erase operation or Embedded Program

algorithm.

When the Erase Suspend command is written during the sector erase operation,

the device requires a maximum of 35 µs to suspend the erase operation. How-

ever, when the Erase Suspend command is written during the sector erase

time-out, the device immediately terminates the time-out period and suspends

the erase operation. Addresses are “don’t-cares” when writing the Erase suspend

command.

After the erase operation has been suspended, the bank enters the erase-sus-

pend-read mode. The system can read data from or program data to any sector

not selected for erasure. (The device “erase suspends” all sectors selected for

erasure.) Reading at any address within erase-suspended sectors produces sta-

tus information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2

together, to determine if a sector is actively erasing or is erase-suspended. Refer

to the Write Operation Status section for information on these status bits.

After an erase-suspended program operation is complete, the bank returns to the

erase-suspend-read mode. The system can determine the status of the program

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operation using the DQ7 or DQ6 status bits, just as in the standard Word Program

operation. Refer to the Write Operation Status section for more information.

In the erase-suspend-read mode, the system can also issue the autoselect com-

mand sequence. The device allows reading autoselect codes even at addresses

within erasing sectors, since the codes are not stored in the memory array. When

the device exits the autoselect mode, the device reverts to the Erase Suspend

mode, and is ready for another valid operation. Refer to the SecSiTM Sector Ad-

dresses and the Autoselect Command Sequence sections for details.

To resume the sector erase operation, the system must write the Erase Resume

command (address bits are don’t care). The bank address of the erase-sus-

pended bank is required when writing this command. Further writes of the

Resume command are ignored. Another Erase Suspend command can be written

after the chip has resumed erasing.

If the Persistent Sector Protection Mode Locking Bit is verified as programmed

without margin, the Persistent Sector Protection Mode Locking Bit Program Com-

mand should be reissued to improve program margin. If the SecSi Sector

Protection Bit is verified as programmed without margin, the SecSi Sector Pro-

tection Bit Program Command should be reissued to improve program margin.

µµAfter programming a PPB, two additional cycles are needed to determine

whether the PPB has been programmed with margin. If the PPB has been pro-

grammed without margin, the program command should be reissued to improve

the program margin. Also note that the total number of PPB program/erase cycles

is limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed.

After erasing the PPBs, two additional cycles are needed to determine whether

the PPB has been erased with margin. If the PPBs has been erased without mar-

gin, the erase command should be reissued to improve the program margin. The

programming of either the PPB or DYB for a given sector or sector group can be

verified by writing a Sector Protection Status command to the device.

Note that there is no single command to independently verify the programming

of a DYB for a given sector group.

Command Definitions Tables

Table 13. Memory Array Command Definitions

Bus Cycles (Notes 1–4)

Command (Notes)

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read (Note 5)

Reset (Note 6)

1

RA

RD

F0

XXX

(BA)

555

(BA)

X00

Manufacturer ID

4

6

4

555

AA

2AA

55

90

01

(BA)

555

(BA)

X01

(BA)

X0E

(Note

10)

(BA)

X0F

(Note

10)

Device ID (Note 10)

227E

Autoselect

(Note 7)

SecSi Sector Factory

Protect (Note 8)

(BA)

555

(Note

8)

AA

X03

Sector Group Protect

Verify (Note 9)

(BA)

555

(SA) XX00/

X02

AAA

XX01

Program

4

6

1

555

BA

AA

B0

30

2AA

55

555

A0

80

PA

PD

Chip Erase

Sector Erase

555

AA

2AA

55

555

SA

10

30

AA

Program/Erase Suspend (Note 11)

Program/Erase Resume (Note 12)

BA

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Table 13. Memory Array Command Definitions

Bus Cycles (Notes 1–4)

Command (Notes)

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

CFI Query (Note 13)

1

2

3

2

1

2

55

XX

98

A0

AA

A0

80

98

90

Accelerated Program (Note 15)

Unlock Bypass Entry (Note 15)

Unlock Bypass Program (Note 15)

Unlock Bypass Erase (Note 15)

Unlock Bypass CFI (Notes 13, 15)

Unlock Bypass Reset (Note 15)

PA

2AA

PA

PD

55

PD

10

555

XX

555

20

XX

XXX

00

Legend:

BA = Address of bank switching to autoselect mode, bypass

mode, or erase operation. Determined by PL127J: Amax:A20,

PL064J: Amax:A19, PL032J: Amax:A18.

PA = Program Address (Amax:A0). Addresses latch on falling

edge of WE# or CE# pulse, whichever happens later.

PD = Program Data (DQ15:DQ0) written to location PA. Data

latches on rising edge of WE# or CE# pulse, whichever happens

first.

RA = Read Address (Amax:A0).

RD = Read Data (DQ15:DQ0) from location RA.

SA = Sector Address (Amax:A12) for verifying (in autoselect

mode) or erasing.

WD = Write Data. See “Configuration Register” definition for

specific write data. Data latched on rising edge of WE#.

X = Don’t care

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

9. The data is 00h for an unprotected sector group and 01h for

a protected sector group.

10. Device ID must be read across cycles 4, 5, and 6. PL127J

(X0Eh = 2220h, X0Fh = 2200h),PL064J (X0Eh = 2202h,

X0Fh = 2201h), PL032J (X0Eh = 220Ah, X0Fh = 2201h).

3. Shaded cells in table denote read cycles. All other cycles are

write operations.

4. During unlock and command cycles, when lower address bits

are 555 or 2AAh as shown in table, address bits higher than

A11 (except where BA is required) and data bits higher than

DQ7 are don’t cares.

11. System may read and program in non-erasing sectors, or

enter autoselect mode, when in Program/Erase Suspend

mode. Program/Erase Suspend command is valid only

during a sector erase operation, and requires bank address.

5. No unlock or command cycles required when bank is reading

array data.

12. Program/Erase Resume command is valid only during Erase

Suspend mode, and requires bank address.

6. The Reset command is required to return to reading array

(or to erase-suspend-read mode if previously in Erase

Suspend) when bank is in autoselect mode, or if DQ5 goes

high (while bank is providing status information).

13. Command is valid when device is ready to read array data or

when device is in autoselect mode.

14. WP#/ACC must be at V during the entire operation of

ID

command.

7. Fourth cycle of autoselect command sequence is a read

cycle. System must provide bank address to obtain

manufacturer ID or device ID information. See Autoselect

Command Sequence section for more information.

15. Unlock Bypass Entry command is required prior to any

Unlock Bypass operation. Unlock Bypass Reset command is

required to return to the reading array.

8. The data is C4h for factory and customer locked, 84h for

factory locked and 04h for not locked.

Table 14. Sector Protection Command Definitions

Bus Cycles (Notes 1-4)

Command (Notes)

Addr Data Addr Data Addr Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Reset

1

3

4

XXX

555

F0

AA

SecSi Sector Entry

SecSi Sector Exit

2AA

55

555

88

90

XX

00

68

SecSi Protection Bit

Program (Notes 5, 6)

6

5

4

7

6

555

AA

2AA

55

555

60

38

C8

28

60

OW

48

OW

RD(0)

SecSi Protection Bit

Status

OW

48

RD(0)

Password Program

(Notes 5, 7, 8)

XX[0-3]

PD[0-3]

Password Verify (Notes

6, 8, 9)

PWA[0-3] PWD[0-3]

Password Unlock (Notes

7, 10, 11)

PWA[0]

(SA)WP

PWD[0] PWA[1] PWD[1] PWA[2] PWD[2] PWA[3] PWD[3]

68 (SA)WP 48 (SA)WP RD(0)

PPB Program (Notes 5,

6, 12)

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Table 14. Sector Protection Command Definitions

PPB Status

4

6

3

4

555

AA

2AA

55

555

90

60

78

58

(SA)WP

RD(0)

All PPB Erase (Notes 5,

6, 13, 14)

WP

60

(SA)

40

(SA)WP RD(0)

PPB Lock Bit Set

PPB Lock Bit Status

(Note 15)

SA

RD(1)

DYB Write (Note 7)

DYB Erase (Note 7)

DYB Status (Note 6)

4

555

AA

2AA

55

555

48

58

SA

X1

X0

RD(0)

PPMLB Program (Notes

5, 6, 12)

6

5

6

5

555

AA

2AA

55

555

60

PL

SL

68

48

68

48

PL

SL

48

PL

SL

RD(0)

PPMLB Status (Note 5)

RD(0)

48

SPMLB Program (Notes

5, 6, 12)

SPMLB Status (Note 5)

RD(0)

Legend:

RD(0) = Read Data DQ0 for protection indicator bit.

RD(1) = Read Data DQ1 for PPB Lock status.

SA = Sector Address where security command applies. Address

bits Amax:A12 uniquely select any sector.

SL = Persistent Protection Mode Lock Address (A7:A0) is

(00010010)

WP = PPB Address (A7:A0) is (00000010)

X = Don’t care

PPMLB = Password Protection Mode Locking Bit

SPMLB = Persistent Protection Mode Locking Bit

DYB = Dynamic Protection Bit

OW = Address (A7:A0) is (00011010)

PD[3:0] = Password Data (1 of 4 portions)

PPB = Persistent Protection Bit

PWA = Password Address. A1:A0 selects portion of password.

PWD = Password Data being verified.

PL = Password Protection Mode Lock Address (A7:A0) is

(00001010)

Notes:

1. See Table 1 for description of bus operations.

9. Command sequence returns FFh if PPMLB is set.

2. All values are in hexadecimal.

10. The password is written over four consecutive cycles, at

addresses 0-3.

3. Shaded cells in table denote read cycles. All other cycles are

write operations.

11. A 2 µs timeout is required between any two portions of

password.

4. During unlock and command cycles, when lower address bits

are 555 or 2AAh as shown in table, address bits higher than

A11 (except where BA is required) and data bits higher than

DQ7 are don’t cares.

12. A 100 µs timeout is required between cycles 4 and 5.

13. A 1.2 ms timeout is required between cycles 4 and 5.

14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have

been fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6,

erase command must be issued and verified again. Before

issuing erase command, all PPBs should be programmed to

prevent PPB overerasure.

5. The reset command returns device to reading array.

6. Cycle 4 programs the addressed locking bit. Cycles 5 and 6

validate bit has been fully programmed when DQ0 = 1. If

DQ0 = 0 in cycle 6, program command must be issued and

verified again.

15. DQ1 = 1 if PPB locked, 0 if unlocked.

7. Data is latched on the rising edge of WE#.

8. Entire command sequence must be entered for each portion

of password.

Write Operation Status

The device provides several bits to determine the status of a program or erase opera-

tion: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 15 and the following subsections describe

the function of these bits. DQ7 and DQ6 each offer a method for determining whether

a program or erase operation is complete or in progress. The device also provides a

hardware-based output signal, RY/BY#, to determine whether an Embedded Program

or Erase operation is in progress or has been completed.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Pro-

gram or Erase algorithm is in progress or completed, or whether a bank is in Erase

Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the com-

mand sequence.

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During the Embedded Program algorithm, the device outputs on DQ7 the complement

of the datum programmed to DQ7. This DQ7 status also applies to programming during

Erase Suspend. When the Embedded Program algorithm is complete, the device out-

puts the datum programmed to DQ7. The system must provide the program address

to read valid status information on DQ7. If a program address falls within a protected

sector, Data# Polling on DQ7 is active for approximately 1 µs, then that bank returns

to the read mode.

During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7.

When the Embedded Erase algorithm is complete, or if the bank enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide

an address within any of the sectors selected for erasure to read valid status in-

formation on DQ7.

After an erase command sequence is written, if all sectors selected for erasing

are protected, Data# Polling on DQ7 is active for approximately 400 µs, then the

bank returns to the read mode. If not all selected sectors are protected, the Em-

bedded Erase algorithm erases the unprotected sectors, and ignores the selected

sectors that are protected. However, if the system reads DQ7 at an address within

a protected sector, the status may not be valid.

When the system detects DQ7 has changed from the complement to true data,

it can read valid data at DQ15–DQ0 on the following read cycles. Just prior to the

completion of an Embedded Program or Erase operation, DQ7 may change asyn-

chronously with DQ15–DQ0 while Output Enable (OE#) is asserted low. That is,

the device may change from providing status information to valid data on DQ7.

Depending on when the system samples the DQ7 output, it may read the status

or valid data. Even if the device has completed the program or erase operation

and DQ7 has valid data, the data outputs on DQ15–DQ0 may be still invalid. Valid

data on DQ15–DQ0 will appear on successive read cycles.

Table 15 shows the outputs for Data# Polling on DQ7. 6 shows the Data# Polling

algorithm. 18 in the AC Characteristic section shows the Data# Polling timing

diagram.

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START

Read DQ7–DQ0

Addr = VA

Yes

DQ7 = Data?

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Addr = VA

Yes

DQ7 = Data?

No

PASS

FAIL

Notes:

1. VA = Valid address for programming. During a sector erase operation, a valid address is

any sector address within the sector being erased. During chip erase, a valid address is

any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously

with DQ5.

Figure 6. Data# Polling Algorithm

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RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin which indicates whether an

Embedded Algorithm is in progress or complete. The RY/BY# status is valid after

the rising edge of the final WE# pulse in the command sequence. Since RY/BY#

is an open-drain output, several RY/BY# pins can be tied together in parallel with

a pull-up resistor to V_CC

.

If the output is low (Busy), the device is actively erasing or programming. (This

includes programming in the Erase Suspend mode.) If the output is high (Ready),

the device is in the read mode, the standby mode, or one of the banks is in the

erase-suspend-read mode.

Table 15 shows the outputs for RY/BY#.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm

is in progress or complete, or whether the device has entered the Erase Suspend

mode. Toggle Bit I may be read at any address, and is valid after the rising edge

of the final WE# pulse in the command sequence (prior to the program or erase

operation), and during the sector erase time-out.

During an Embedded Program or Erase algorithm operation, successive read cy-

cles to any address cause DQ6 to toggle. The system may use either OE# or CE#

to control the read cycles. When the operation is complete, DQ6 stops toggling.

After an erase command sequence is written, if all sectors selected for erasing

are protected, DQ6 toggles for approximately 400 µs, then returns to reading

array data. If not all selected sectors are protected, the Embedded Erase algo-

rithm erases the unprotected sectors, and ignores the selected sectors that are

protected.

The system can use DQ6 and DQ2 together to determine whether a sector is ac-

tively erasing or is erase-suspended. When the device is actively erasing (that is,

the Embedded Erase algorithm is in progress), DQ6 toggles. When the device en-

ters the Erase Suspend mode, DQ6 stops toggling. However, the system must

also use DQ2 to determine which sectors are erasing or erase-suspended. Alter-

natively, the system can use DQ7 (see the DQ7: Data# Polling).

If a program address falls within a protected sector, DQ6 toggles for approxi-

mately 1 µs after the program command sequence is written, then returns to

reading array data.

DQ6 also toggles during the erase-suspend-program mode, and stops toggling

once the Embedded Program algorithm is complete.

Table 15 shows the outputs for Toggle Bit I on DQ6. Figure 7 shows the toggle bit

algorithm. Figure 19 in “Read Operation Timings” shows the toggle bit timing di-

agrams. Figure 20 shows the differences between DQ2 and DQ6 in graphical

form. See also the DQ2: Toggle Bit II.

August 12, 2004 S29PL127J_064J_032J_MCP_00_A3

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START

Read Byte

(DQ7–DQ0)

Address =VA

Read Byte

(DQ7–DQ0)

Address =VA

No

Toggle Bit

= Toggle?

Yes

No

DQ5 = 1?

Yes

Read Byte Twice

(DQ7–DQ0)

Address = VA

Toggle Bit

= Toggle?

No

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle

bit may stop toggling as DQ5 changes to “1.” See the DQ6: Toggle Bit I and DQ2:

Toggle Bit II for more information.

Figure 7. Toggle Bit Algorithm

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular

sector is actively erasing (that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit II is valid after the rising

edge of the final WE# pulse in the command sequence.

DQ2 toggles when the system reads at addresses within those sectors that have

been selected for erasure. (The system may use either OE# or CE# to control the

read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or

is erase-suspended. DQ6, by comparison, indicates whether the device is actively

erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected

for erasure. Thus, both status bits are required for sector and mode information.

Refer to Table 15 to compare outputs for DQ2 and DQ6.

Figure 7 shows the toggle bit algorithm in flowchart form, and the DQ2: Toggle

Bit II explains the algorithm. See also the DQ6: Toggle Bit I. Figure 19 shows the

toggle bit timing diagram. Figure 20 shows the differences between DQ2 and DQ6

in graphical form.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 7 for the following discussion. Whenever the system initially be-

gins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to

determine whether a toggle bit is toggling. Typically, the system would note and

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store the value of the toggle bit after the first read. After the second read, the

system would compare the new value of the toggle bit with the first. If the toggle

bit is not toggling, the device has completed the program or erase operation. The

system can read array data on DQ7–DQ0 on the following read cycle.

However, if after the initial two read cycles, the system determines that the toggle

bit is still toggling, the system also should note whether the value of DQ5 is high

(see the section on DQ5). If it is, the system should then determine again

whether the toggle bit is toggling, since the toggle bit may have stopped toggling

just as DQ5 went high. If the toggle bit is no longer toggling, the device has suc-

cessfully completed the program or erase operation. If it is still toggling, the

device did not completed the operation successfully, and the system must write

the reset command to return to reading array data.

The remaining scenario is that the system initially determines that the toggle bit

is toggling and DQ5 has not gone high. The system may continue to monitor the

toggle bit and DQ5 through successive read cycles, determining the status as de-

scribed in the previous paragraph. Alternatively, it may choose to perform other

system tasks. In this case, the system must start at the beginning of the algo-

rithm when it returns to determine the status of the operation (top of Figure 7).

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has exceeded a specified inter-

nal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the

program or erase cycle was not successfully completed.

The device may output a “1” on DQ5 if the system tries to program a “1” to a

location that was previously programmed to “0.” Only an erase operation can

change a “0” back to a “1.” Under this condition, the device halts the opera-

tion, and when the timing limit has been exceeded, DQ5 produces a “1.”

Under both these conditions, the system must write the reset command to return

to the read mode (or to the erase-suspend-read mode if a bank was previously

in the erase-suspend-program mode).

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the system may read DQ3 to de-

termine whether or not erasure has begun. (The sector erase timer does not

apply to the chip erase command.) If additional sectors are selected for erasure,

the entire time-out also applies after each additional sector erase command.

When the time-out period is complete, DQ3 switches from a “0” to a “1.” See also

the Sector Erase Command Sequence.

After the sector erase command is written, the system should read the status of

DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted

the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase

algorithm has begun; all further commands (except Erase Suspend) are ignored

until the erase operation is complete. If DQ3 is “0,” the device will accept addi-

tional sector erase commands. To ensure the command has been accepted, the

system software should check the status of DQ3 prior to and following each sub-

sequent sector erase command. If DQ3 is high on the second status check, the

last command might not have been accepted.

Table 15 shows the status of DQ3 relative to the other status bits.

August 12, 2004 S29PL127J_064J_032J_MCP_00_A3

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Table 15. Write Operation Status

DQ7

DQ5

DQ2

Status

(Note 2)

DQ6

(Note 1)

DQ3

N/A

1

(Note 2)

RY/BY#

Embedded Program Algorithm

Embedded Erase Algorithm

Erase

DQ7#

0

Toggle

0

No toggle

Toggle

0

Standard

Mode

1

No toggle

0

N/A

Toggle

1

Suspended Sector

Erase-Suspend-

Read

Erase

Suspend

Mode

Non-Erase

Suspended Sector

Data

0

Data

N/A

Data

N/A

1

0

Erase-Suspend-Program

DQ7#

Toggle

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing

limits. Refer to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for

further details.

3. When reading write operation status bits, the system must always provide the bank address where the Embedded

Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank.

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Absolute Maximum Ratings

Storage Temperature Plastic Packages. . . . . . . . . . . . . . . . .–65°C to +150°C

Ambient Temperature with Power Applied. . . . . . . . . . . . . . .–65°C to +125°C

Voltage with Respect to Ground

V_CC(Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.0 V

RESET# (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +13.0 V

WP#/ACC (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +10.5 V

All other pins (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V_CC+0.5 V

Output Short Circuit Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions,

input or I/O pins may overshoot V to –2.0 V for periods of up to 20 ns. Maximum

SS

DC voltage on input or I/O pins is V +0.5 V. During voltage transitions, input or

CC

I/O pins may overshoot to V +2.0 V for periods up to 20 ns. See Figure 8.

CC

2. Minimum DC input voltage on pins A9, OE#, RESET#, and WP#/ACC is –0.5 V.

During voltage transitions, A9, OE#, WP#/ACC, and RESET# may overshoot V

SS

to –2.0 V for periods of up to 20 ns. See Figure 8. Maximum DC input voltage on

pin A9, OE#, and RESET# is +12.5 V which may overshoot to +14.0 V for periods

up to 20 ns. Maximum DC input voltage on WP#/ACC is +9.5 V which may

overshoot to +12.0 V for periods up to 20 ns.

3. No more than one output may be shorted to ground at a time. Duration of the

short circuit should not be greater than one second.

4. Stresses above those listed under “Absolute Maximum Ratings” may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the operational

sections of this data sheet is not implied. Exposure of the device to absolute max-

imum rating conditions for extended periods may affect device reliability.

20 ns

V_CC

+2.0 V

+0.8 V

V_CC

–0.5 V

–2.0 V

+0.5 V

2.0 V

20 ns

Maximum Negative Overshoot Waveform

Maximum Positive Overshoot Waveform

Figure 8. Maximum Overshoot Waveforms

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Operating Ranges

Operating ranges define those limits between which the functionality of the de-

vice is guaranteed.

Industrial (I) Devices

Ambient Temperature (T_A) . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Wireless Devices

Ambient Temperature (T_A) . . . . . . . . . . . . . . . . . . . . . . . . . –25°C to +85°C

Supply Voltages

V_CC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7–3.1 V

V_IO(see Note). .1.65–1.95 V (for PL127J) or 2.7–3.1 V (for all PLxxxJ devices)

Notes:

For all AC and DC specifications, V = V ; contact your local sales office for other

IO

CC

V

options.

IO

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S29PL127J/S29PL064J/S29PL032J for MCP

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DC Characteristics

Table 16. CMOS Compatible

Parameter

Symbol

Parameter Description

Test Conditions

Min

Typ

Max

Unit

V_IN= V_SSto V_CC

,

I_LI

Input Load Current

±1.0

µA

V_CC= V_{CC max}

I_LIT

I_LR

A9, OE#, RESET# Input Load Current

Reset Leakage Current

V_CC= V_{CC max}; V_ID= 12.5 V

35

µA

V_OUT= V_SSto V_CC, OE# = V_IH

V_CC= V_{CC max}

I_LO

Output Leakage Current

±1.0

µA

5 MHz

15

45

15

25

55

25

OE# = V_IH, V_CC= V_{CC max}

(Note 1)

I_CC1

V_CCActive Read Current (Notes 1, 2)

mA

10 MHz

I_CC2

I_CC3

I_CC4

I_CC5

V_CCActive Write Current (Notes 2, 3)

V_CCStandby Current (Note 2)

V_CCReset Current (Note 2)

OE# = V_IH, WE# = V_IL

mA

µA

CE#, RESET#, WP#/ACC

= V_IO± 0.3 V

0.2

5

RESET# = V_SS± 0.3 V

V_IH= V_IO± 0.3 V;

V_IL= V_SS± 0.3 V

Automatic Sleep Mode (Notes 2, 4)

5 MHz

10 MHz

5 MHz

21

46

21

46

45

70

45

70

V_CCActive Read-While-Program Current

(Notes 1, 2)

I_CC6

OE# = V_IH

,

mA

V_CCActive Read-While-Erase Current

(Notes 1, 2)

I_CC7

OE# = V_IH

mA

10 MHz

V_CCActive Program-While-Erase-

Suspended Current (Notes 2, 5)

I_CC8

I_CC9

17

10

25

V_CCActive Page Read Current (Note 2)

OE# = V_IH, 8 word Page Read

V_IO= 1.65–1.95 V (PL127J)

V_IO= 2.7–3.6 V

15

0.4

mA

V

–0.4

–0.5

V_IL

Input Low Voltage

0.8

V

V_IO= 1.65–1.95 V (PL127J)

V_IO= 2.7–3.6 V

V_IO–0.4

2.0

V_IO+0.4

V_CC+0.3

9.5

V

V_IH

Input High Voltage

V

V_HH

V_ID

Voltage for ACC Program Acceleration

V_CC= 3.0 V ± 10%

8.5

V

Voltage for Autoselect and Temporary

Sector Unprotect

V_CC= 3.0 V ± 10%

11.5

12.5

0.1

V

I_OL= 100 µA, V_CC= V_{CC min}, V_IO= 1.65–

1.95 V (PL127J)

V_OL

Output Low Voltage

I_OL= 2.0 mA, V_CC= V_{CC min}, V_IO= 2.7–3.6

V

0.4

I_OH= –100 µA, V_CC= V_{CC min}, V_IO= 1.65–

1.95 V (PL127J)

V_IO–0.1

V_OH

Output High Voltage

I_OH= –2.0 mA, V_CC= V_{CC min}, V_IO= 2.7–3.6

V

2.4

2.3

V

V_LKO

Low V_CCLock-Out Voltage (Note 5)

2.5

Notes:

1. The I current listed is typically less than 5 mA/MHz, with OE# at V

.

IH

CC

2. Maximum I specifications are tested with V = V .

CCmax

CC

3. I active while Embedded Erase or Embedded Program is in progress.

CC

4. Automatic sleep mode enables the low power mode when addresses remain stable for t

+ 30 ns. Typical sleep

ACC

mode current is 1 mA.

5. Not 100% tested.

6. Valid CE1#/CE2# conditions: (CE1# = V CE2# = V ) or (CE1# = V CE2# = V ) or (CE1# = V CE2# = V )

IH

IL,

IH,

IL

IH,

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AC Characteristic

Test Conditions

3.6 V

2.7 kΩ

Device

Under

Test

Device

Under

Test

C

L

C

6.2 kΩ

L

V_IO= 3.0 V

V_IO= 1.8 V (PL127J)

Note: Diodes are IN3064 or equivalent

Figure 9. Test Setups

Table 17. Test Specifications

Test Condition

All Speeds

1 TTL gate

30

Unit

Output Load

Output Load Capacitance, C_L(including jig capacitance)

pF

ns

V_IO= 1.8 V

(PL127J)

Input Rise and Fall Times

5

V_IO= 3.0 V

V_IO= 1.8 V

(PL127J)

0.0 - 1.8

Input Pulse Levels

V

V_IO= 3.0 V

0.0–3.0

V_IO/2

Input timing measurement reference levels

Output timing measurement reference levels

V

V_IO/2

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SWITCHING WAVEFORMS

Table 18. KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

VIO

VIO/2

In

Measurement Level

Output

0.0 V

Figure 10. Input Waveforms and Measurement Levels

VCC RampRate

All DC characteristics are specified for a V_CCramp rate > 1V/100 µs and V_CC

>=V_CCQ- 100 mV. If the V_CCramp rate is < 1V/100 µs, a hardware reset

required.+

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Read Operations

Table 19. Read-Only Operations

Parameter

Speed Options

JEDEC

t_AVAV

t_AVQV

t_ELQV

Std. Description

Test Setup

55

20

60

25

65

70

Unit

ns

t_RC

Read Cycle Time (Note 1)

Min

t_ACCAddress to Output Delay

CE#, OE# = V_IL

OE# = V_IL

Max

ns

t_CE

t_PACCPage Access Time

t_OEOutput Enable to Output Delay

t_DF

Chip Enable to Output Delay

ns

30

ns

t_GLQV

t_EHQZ

ns

Chip Enable to Output High Z (Note 3)

16

ns

Output Enable to Output High Z (Notes 1,

3)

t_GHQZ

t_DF

Max

ns

Output Hold Time From Addresses, CE# or

OE#, Whichever Occurs First (Note 3)

t_AXQX

t_OH

Min

5

0

ns

Read

Output Enable Hold

Time (Note 1)

t_OEH

Toggle and

10

Data# Polling

Notes:

1. Not 100% tested.

2. See Figure 9 and Table 17 for test specifications

3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of V /2. The time from OE#

CC

high to the data bus driven to V /2 is taken as t

.

CC

DF

4. For 70pF Output Load Capacitance, 2 ns will be added to the above t

,t ,t

,t values for all speed grades

ACC CE PACC OE

t_RC

Addresses Stable

t_ACC

Addresses

CE#

t_RH

t_DF

t_OE

OE#

t_OEH

WE#

Data

t_CE

t_OH

HIGH Z

Valid Data

RESET#

RY/BY#

0 V

Figure 11. Read Operation Timings

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S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

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Same Page

Amax

-

A3

A0

A2

Ad

Aa

Ab

Ac

t_PACC

t_ACC

Data

Qa

Qb

Qc

Qd

CE#

OE#

Figure 12. Page Read Operation Timings

Reset

Table 20. Hardware Reset (RESET#)

Parameter

JEDEC Std

Description

All Speed Options

Unit

RESET# Pin Low (During Embedded Algorithms)

to Read Mode (See Note)

t_Ready

Max

35

µs

RESET# Pin Low (NOT During Embedded

Algorithms) to Read Mode (See Note)

t_Ready

500

ns

t_RP

t_RH

t_RPD

t_RB

RESET# Pulse Width

Min

500

50

20

0

ns

µs

ns

Reset High Time Before Read (See Note)

RESET# Low to Standby Mode

RY/BY# Recovery Time

Note: Not 100% tested.

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RY/BY#

CE#, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t_Ready

RY/BY#

t_RB

CE#, OE#

RESET#

t_RP

Figure 13. Reset Timings

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Erase/Program Operations

Table 21. Erase and Program Operations

Parameter

Speed Options

JEDEC

t_AVAV

t_AVWL

Std

t_WC

t_AS

Description

55

60

65

70

Unit

ns

Write Cycle Time (Note 1)

Address Setup Time

Min

55

60

65

70

0

ns

Address Setup Time to OE# low during toggle bit

polling

t_ASO

t_AH

Min

15

ns

t_WLAX

Address Hold Time

30

25

35

30

Address Hold Time From CE# or OE# high during

toggle bit polling

t_AHT

0

t_DVWH

t_WHDX

t_DS

t_DH

Data Setup Time

Min

ns

Data Hold Time

0

t_OEPH

Output Enable High during toggle bit polling

10

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHWL

Min

0

ns

t_ELWL

t_WHEH

t_WLWH

t_WHDL

t_CS

t_CH

CE# Setup Time

Min

Typ

Min

Max

0

ns

µs

sec

µs

ns

CE# Hold Time

t_WP

Write Pulse Width

35

20

40

25

t_WPH

t_SR/W

Write Pulse Width High

Latency Between Read and Write Operations

0

6

t_WHWH1

t_WHWH2

t_WHWH1Programming Operation (Note 2)

t_WHWH1Accelerated Programming Operation (Note 2)

t_WHWH2Sector Erase Operation (Note 2)

4

0.5

50

0

t_VCS

t_RB

V_CCSetup Time (Note 1)

Write Recovery Time from RY/BY#

Program/Erase Valid to RY/BY# Delay

t_BUSY

90

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

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Timing Diagrams

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

t_WC

Addresses

555h

PA

t_AH

CE#

OE#

t_CH

t_WHWH1

t_WP

WE#

Data

t_WPH

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. PA = program address, PD = program data, D

is the true data at the program address

OUT

Figure 14. Program Operation Timings

V_HH

V_ILor V_IH

WP#/ACC

t_VHH

Figure 15. Accelerated Program Timing Diagram

t_VHH

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Erase Command Sequence (last two cycles)

Read Status Data

VA

t_AS

SA

t_WC

VA

Addresses

CE#

2AAh

555h for chip erase

t_AH

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

Data

Status

D

OUT

55h

30h

10 for Chip Erase

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”

Figure 16. Chip/Sector Erase Operation Timings

t_WC

t_RC

t_WC

Valid PA

t_AH

Valid RA

Valid PA

Addresses

t_AS

t_CPH

t_AS

t_AH

t_ACC

t_CE

CE#

OE#

t_CP

t_OE

t_OEH

t_GHWL

t_WP

WE#

Data

t_DF

t_WPH

t_DS

t_OH

t_DH

Valid

Out

Valid

In

Valid

In

Valid

In

t_SR/W

WE# Controlled Write Cycle

Read Cycle

CE# Controlled Write Cycles

Figure 17. Back-to-back Read/Write Cycle Timings

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t_RC

VA

Addresses

CE#

VA

t_ACC

t_CE

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ7

Valid Data

Complement

Status Data

True

DQ6–DQ0

Status Data

True

Valid Data

t_BUSY

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and

array data read cycle

Figure 18. Data# Polling Timings (During Embedded Algorithms)

t_AHT

t_AS

Addresses

CE#

t_AHT

t_ASO

t_CEPH

t_OEH

WE#

OE#

t_OEPH

t_DH

Valid Data

t_OE

Valid

Status

Valid

Status

Valid

Status

DQ6/DQ2

Valid Data

(first read)

(second read)

(stops toggling)

RY/BY#

Notes:

1. VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last

status read cycle, and array data read cycle

Figure 19. Toggle Bit Timings (During Embedded Algorithms)

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P r e l i m i n a r y

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note:Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE#

or CE# to toggle DQ2 and DQ6.

Figure 20. DQ2 vs. DQ6

Protect/Unprotect

Table 22. Temporary Sector Unprotect

Parameter

JEDEC

Std

t_VIDR

t_VHH

Description

All Speed Options

Unit

ns

V_IDRise and Fall Time (See Note)

V_HHRise and Fall Time (See Note)

Min

500

250

ns

RESET# Setup Time for Temporary Sector

Unprotect

t_RSP

Min

4

µs

RESET# Hold Time from RY/BY# High for

Temporary Sector Unprotect

t_RRB

Note: Not 100% tested.

V_ID

RESET#

V_ILor V_IH

t_VIDR

Program or Erase Command Sequence

CE#

WE#

t_RRB

t_RSP

RY/BY#

Figure 21. Temporary Sector Unprotect Timing Diagram

August 12, 2004 S29PL127J_064J_032J_MCP_00_A3

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P r e l i m i n a r y

V

ID

IH

RESET#

SA, A6,

A1, A0

Valid*

Status

Sector Group Protect/Unprotect

Verify

40h

Data

60h

1 µs

Sector Group Protect: 150 µs

Sector Group Unprotect: 15 ms

CE#

WE#

OE#

Notes:

1. For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 22. Sector/Sector Block Protect and Unprotect Timing Diagram

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Controlled Erase Operations

Table 23. Alternate CE# Controlled Erase and Program Operations

Parameter

JEDEC

Speed Options

Std

t_WC

t_AS

t_AH

t_DS

t_DH

Description

55

60

65

70

Unit

ns

t_AVAV

t_AVWL

t_ELAX

t_DVEH

t_EHDX

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Data Hold Time

Min

55

60

65

70

0

ns

30

25

35

30

ns

0

ns

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHEL

Min

ns

t_WLEL

t_EHWH

t_ELEH

t_WS

t_WH

WE# Setup Time

Min

Typ

0

ns

µs

sec

WE# Hold Time

t_CP

CE# Pulse Width

35

20

40

25

t_EHEL

t_CPH

CE# Pulse Width High

t_WHWH1

t_WHWH2

t_WHWH1

t_WHWH2

Programming Operation (Note 2)

Accelerated Programming Operation (Note 2)

Sector Erase Operation (Note 2)

6

4

0.5

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

August 12, 2004 S29PL127J_064J_032J_MCP_00_A3

S29PL127J/S29PL064J/S29PL032J for MCP

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P r e l i m i n a r y

555 for program

2AA for erase

PA for program

SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_WH

t_AS

t_AH

WE#

OE#

t_GHEL

t_{WHWH1 or 2}

t_CP

CE#

Data

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#

D_OUT

t_RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Notes:

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = program address, SA = sector address, PD = program data.

3. DQ7# is the complement of the data written to the device. D

is the data written to the device

OUT

Table 24. Alternate CE# Controlled Write (Erase/Program) Operation Timings

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Table 25. Erase And Programming Performance

Parameter

Typ (Note 1)

Max (Note 2)

Unit

sec

Comments

0.5

135

71

2

Sector Erase Time

PL127J

PL064J

PL032J

216

Excludes 00h programming

prior to erasure (Note 4)

113.6

62.4

Chip Erase Time

39

Excludes system level

overhead (Note 5)

6

100

µs

Word Program Time

4

60

µs

Accelerated Word Program Time

PL127J

50.4

25.2

12.6

200

50.4

25.2

sec

Chip Program Time

PL064J

PL032J

(Note 3)

Notes:

1. Typical program and erase times assume the following conditions: 25×C, 3.0 V V , 100,000 cycles. Additionally,

CC

programming typicals assume checkerboard pattern. All values are subject to change.

2. Under worst case conditions of 90×C, V = 2.7 V, 100,000 cycles. All values are subject to change.

CC

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most

bytes program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program

command. See Table 13 for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 100,000 cycles.

BGA Pin Capacitance

Parameter Symbol

Parameter Description

Input Capacitance

Test Setup

V_IN= 0

Typ

6.3

7.0

5.5

11

Max

7

Unit

pF

C_IN

C_OUT

C_IN2

C_IN3

Output Capacitance

V_OUT= 0

V_IN= 0

8

pF

Control Pin Capacitance

WP#/ACC Pin Capacitance

8

pF

V_IN= 0

12

pF

Notes:

1. Sampled, not 100% tested.

2. Test conditions T = 25°C, f = 1.0 MHz.

A

August 12, 2004 S29PL127J_064J_032J_MCP_00_A3

S29PL127J/S29PL064J/S29PL032J for MCP

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76

S29PL127J/S29PL064J/S29PL032J for MCP

S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

S29GLxxxN MirrorBit^TMFlash Family

S29GL512N, S29GL256N, S29GL128N

512 Megabit, 256 Megabit, and 128 Megabit, 3.0 Volt-only

Page Mode Flash Memory featuring 110 nm MirrorBit

process technology

ADVANCE

INFORMATION

Data Sheet

Distinctive Characteristics

Architectural Advantages

Software & Hardware Features

Single power supply operation

— 3 volt read, erase, and program operations

Software features

— Program Suspend & Resume: read other sectors

before programming operation is completed

— Erase Suspend & Resume: read/program other

sectors before an erase operation is completed

— Data# polling & toggle bits provide status

— Unlock Bypass Program command reduces overall

multiple-word programming time

— CFI (Common Flash Interface) compliant: allows host

system to identify and accommodate multiple flash

devices

Enhanced VersatileI/O™ control

— All input levels (address, control, and DQ input levels)

and outputs are determined by voltage on V_IOinput.

V

_IOrange is 1.65 to V_CC

Manufactured on 110 nm MirrorBit process

technology

Secured Silicon Sector region

— 128-word/256-byte sector for permanent, secure

identification through an 8-word/16-byte random

Electronic Serial Number, accessible through a

command sequence

— May be programmed and locked at the factory or by

the customer

Hardware features

— Advanced Sector Protection

— WP#/ACC input accelerates programming time

(when high voltage is applied) for greater throughput

during system production. Protects first or last sector

regardless of sector protection settings

— Hardware reset input (RESET#) resets device

— Ready/Busy# output (RY/BY#) detects program or

erase cycle completion

Flexible sector architecture

— S29GL512N: Five hundred twelve 64 Kword (128

Kbyte) sectors

— S29GL256N: Two hundred fifty-six 64 Kword (128

Kbyte) sectors

— S29GL128N: One hundred twenty-eight 64 Kword

(128 Kbyte) sectors

Compatibility with JEDEC standards

— Provides pinout and software compatibility for single-

power supply flash, and superior inadvertent write

protection

100,000 erase cycles per sector typical

20-year data retention typical

Performance Characteristics

High performance

— 90 ns access time (S29GL128N, S29GL256N,

S29GL512N)

— 8-word/16-byte page read buffer

— 25 ns page read times

— 16-word/32-byte write buffer reduces overall

programming time for multiple-word updates

Low power consumption (typical values at 3.0 V, 5

MHz)

— 25 mA typical active read current;

— 50 mA typical erase/program current

— 1 µA typical standby mode current

Publication Number S29GLxxxN_MCP Revision A Amendment 1 Issue Date December 15, 2004

This document contains information on a product under development at Spansion LLC. The information is intended to help you evaluate this product. Spansion LLC

reserves the right to change or discontinue work on this proposed product without notice.

A d v a n c e I n f o r m a t i o n

General Description

The S29GL512/256/128N family of devices are 3.0V single power flash memory

manufactured using 110 nm MirrorBit technology. The S29GL512N is a 512 Mbit,

organized as 33,554,432 words or 67,108,864 bytes. The S29GL256N is a 256

Mbit, organized as 16,777,216 words or 33,554,432 bytes. The S29GL128N is a

128 Mbit, organized as 8,388,608 words or 16,777,216 bytes. The device can be

programmed either in the host system or in standard EPROM programmers.

Access times as fast as 90 ns (S29GL128N, S29GL256N, S29GL512N) are avail-

able. Note that each access time has a specific operating voltage range (V_CC) and

an I/O voltage range (V_IO), as specified in the “Product Selector Guide” section.

The devices are offered in a 56-pin TSOP or 64-ball Fortified BGA package. Each

device has separate chip enable (CE#), write enable (WE#) and output enable

(OE#) controls.

Each device requires only a single 3.0 volt power supply for both read and

write functions. In addition to a V_CCinput, a high-voltage accelerated program

(WP#/ACC) input provides shorter programming times through increased cur-

rent. This feature is intended to facilitate factory throughput during system

production, but may also be used in the field if desired.

The devices are entirely command set compatible with the JEDEC single-

power-supply Flash standard. Commands are written to the device using

standard microprocessor write timing. Write cycles also internally latch addresses

and data needed for the programming and erase operations.

The sector erase architecture allows memory sectors to be erased and repro-

grammed without affecting the data contents of other sectors. The device is fully

erased when shipped from the factory.

Device programming and erasure are initiated through command sequences.

Once a program or erase operation has begun, the host system need only poll the

DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy#

(RY/BY#) output to determine whether the operation is complete. To facilitate

programming, an Unlock Bypass mode reduces command sequence overhead

by requiring only two write cycles to program data instead of four.

The Enhanced VersatileI/O™ (V_IO) control allows the host system to set the

voltage levels that the device generates and tolerates on all input levels (address,

chip control, and DQ input levels) to the same voltage level that is asserted on

the V_IOpin. This allows the device to operate in a 1.8 V or 3 V system environ-

ment as required.

Hardware data protection measures include a low V_CCdetector that automat-

ically inhibits write operations during power transitions. Persistent Sector

Protection provides in-system, command-enabled protection of any combina-

tion of sectors using a single power supply at V_CC. Password Sector Protection

prevents unauthorized write and erase operations in any combination of sectors

through a user-defined 64-bit password.

The Erase Suspend/Erase Resume feature allows the host system to pause an

erase operation in a given sector to read or program any other sector and then

complete the erase operation. The Program Suspend/Program Resume fea-

ture enables the host system to pause a program operation in a given sector to

read any other sector and then complete the program operation.

The hardware RESET# pin terminates any operation in progress and resets the

device, after which it is then ready for a new operation. The RESET# pin may be

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S29GLxxxN MirrorBit^TMFlash Family

S29GLxxxN_MCP_A1 December 15, 2004

A d v a n c e I n f o r m a t i o n

tied to the system reset circuitry. A system reset would thus also reset the device,

enabling the host system to read boot-up firmware from the Flash memory

device.

The device reduces power consumption in the standby mode when it detects

specific voltage levels on CE# and RESET#, or when addresses have been stable

for a specified period of time.

The Secured Silicon Sector provides a 128-word/256-byte area for code or

data that can be permanently protected. Once this sector is protected, no further

changes within the sector can occur.

The Write Protect (WP#/ACC) feature protects the first or last sector by as-

serting a logic low on the WP# pin.

MirrorBit flash technology combines years of Flash memory manufacturing expe-

rience to produce the highest levels of quality, reliability and cost effectiveness.

The device electrically erases all bits within a sector simultaneously via hot-hole

assisted erase. The data is programmed using hot electron injection.

December 15, 2004 S29GLxxxN_MCP_A1

S29GLxxxN MirrorBit^TMFlash Family

79

A d v a n c e I n f o r m a t i o n

Product Selector Guide

S29GL512N

Part Number

S29GL512N

V

= 2.7–3.6 V

10

11

IO

V_CC= 2.7–3.6 V

Speed Option

= 1.65–1.95 V

11

IO

V_CC= 3.0-3.6V

Max. Access Time (ns)

V_IO= 3.0-3.6V

90

25

100

25

110

25

110

30

Max. CE# Access Time (ns)

Max. Page access time (ns)

Max. OE# Access Time (ns)

25

30

S29GL256N

Part Number

S29GL256N

V

= 2.7–3.6 V

10

11

IO

V_CC= 2.7–3.6 V

Speed Option

= 1.65–1.95 V

11

IO

V_CC= Regulated (3.0-3.6V)

V_IO= Regulated (3.0-3.6V)

90

25

Max. Access Time (ns)

100

25

110

25

110

30

Max. CE# Access Time (ns)

Max. Page access time (ns)

Max. OE# Access Time (ns)

25

30

S29GL128N

Part Number

S29GL128N

V

= 2.7–3.6 V

10

11

IO

V_CC= 2.7–3.6 V

V_CC= Regulated (3.0-3.6V)

Speed Option

= 1.65–1.95 V

11

IO

V_IO= Regulated (3.0-3.6V)

90

25

Max. Access Time (ns)

100

25

110

25

110

30

Max. CE# Access Time (ns)

Max. Page access time (ns)

Max. OE# Access Time (ns)

25

30

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S29GLxxxN MirrorBit^TMFlash Family

S29GLxxxN_MCP_A1 December 15, 2004

A d v a n c e I n f o r m a t i o n

Block Diagram

DQ15–DQ0 (A-1)

RY/BY#

V_CC

Sector Switches

V_SS

V_IO

Erase Voltage

Generator

Input/Output

Buffers

RESET#

WE#

State

WP#/ACC

Control

Command

Register

PGM Voltage

Generator

Data

Latch

Chip Enable

Output Enable

Logic

STB

CE#

OE#

Y-Decoder

Y-Gating

STB

V_CCDetector

Timer

Cell Matrix

X-Decoder

A_Max**–A0

Notes:

1.

A_MaxGL512N = A24, A_MaxGL256N = A23, A_MaxGL128N = A22

December 15, 2004 S29GLxxxN_MCP_A1

S29GLxxxN MirrorBit^TMFlash Family

81

A d v a n c e I n f o r m a t i o n

Pin Description

A24–A0

=

25 Address inputs (512 Mb)

24 Address inputs (256 Mb)

23 Address inputs (128 Mb)

15 Data inputs/outputs

DQ15 (Data input/output, word mode), A-1 (LSB

Address input

A23–A0

A22–A0

DQ14–DQ0

DQ15/A-1

CE#

OE#

WE#

WP#/ACC

=

Chip Enable input

Output Enable input

Write Enable input

Hardware Write Protect input;

Acceleration input

RESET#

RY/BY#

V_CC

=

Hardware Reset Pin input

Ready/Busy output

3.0 volt-only single power supply

(see Product Selector Guide for speed options and

voltage supply tolerances)

Output Buffer power

V_IO

V_SS

NC

=

Device Ground

Pin Not Connected Internally

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S29GLxxxN MirrorBit^TMFlash Family

S29GLxxxN_MCP_A1 December 15, 2004

A d v a n c e I n f o r m a t i o n

Logic Symbol

S29GL512N

25

A24–A0

16 or 8

DQ15–DQ0

(A-1)

CE#

OE#

WE#

WP#/ACC

RESET#

V_IO

RY/BY#

S29GL256N

24

A23–A0

16 or 8

DQ15–DQ0

(A-1)

CE#

OE#

WE#

WP#/ACC

RESET#

V_IO

RY/BY#

S29GL128N

23

A22–A0

16 or 8

DQ15–DQ0

(A-1)

CE#

OE#

WE#

WP#/ACC

RESET#

V_IO

RY/BY#

December 15, 2004 S29GLxxxN_MCP_A1

S29GLxxxN MirrorBit^TMFlash Family

83