S75WS256NDFBAWMB [SPANSION]
Stacked Multi-Chip Product (MCP); 堆叠式多芯片产品（ MCP ）
| 型号： | S75WS256NDFBAWMB |
| 厂家： | 
SPANSION |
| 描述： | Stacked Multi-Chip Product (MCP) |
| 文件： | 总216页 (文件大小：3550K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S75WS256Nxx Based MCPs
Stacked Multi-Chip Product (MCP)
256 Megabit (16M x 16-bit) CMOS 1.8 Volt-only
Simultaneous Read/Write, Burst-mode Flash Memory with
128 Mb (8M x 16-Bit) CellularRAM and
512 Mb (32M x 16-bit) Data Storage
PRELIMINARY
Data Sheet
Notice to Readers: This document states the current technical specifications
regarding the Spansion product(s) described herein. Each product described
herein may be designated as Advance Information, Preliminary, or Full
Production. See Notice On Data Sheet Designations for definitions.
Publication Number S75WS-N-00 Revision A Amendment 0 Issue Date February 17, 2005
A d v a n c e I n f o r m a t i o n
This page intentionally left blank.
S75WS256Nxx Based MCPs
S75WS-N-00_A0 February 17, 2005
S75WS256Nxx Based MCPs
Stacked Multi-Chip Product (MCP)
256 Megabit (16M x 16-bit) CMOS 1.8 Volt-only
Simultaneous Read/Write, Burst-mode Flash Memory with
128 Mb (8M x 16-Bit) CellularRAM and
512 Mb (32M x 16-bit) Data Storage
Data Sheet
PRELIMINARY
General Description
The S75WS-N Series is a product line of stacked Multi-Chip Product (MCP) packages and consists
of the following items:
One or more S29WSxxxN code Flash
CellularRAM
One or more S29RS-N data storage Flash
The products covered by this document are listed in the table below:
Code Flash
Density
RAM
Density
Data Storage
Flash Density
Device
256 Mb
128 Mb
512 Mb
S75WS256NDF
Distinctive Characteristics
MCP Features
Power supply voltage of 1.7 V to 1.95 V
High Performance
— 54 MHz, 66 MHz
Packages
— 9 x 12 mm 84 ball FBGA
Operating Temperature
— Wireless, –25°C to +85°C
Publication Number S75WS-N-00 Revision A Amendment 0 Issue Date February 17, 2005
A d v a n c e I n f o r m a t i o n
Notice On Data Sheet Designations
Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise
readers of product information or intended specifications throughout the product life cycle, includ-
ing development, qualification, initial production, and full production. In all cases, however,
readers are encouraged to verify that they have the latest information before finalizing their de-
sign. The following descriptions of Spansion data sheet designations are presented here to
highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion LLC is developing one or more spe-
cific products, but has not committed any design to production. Information presented in a
document with this designation is likely to change, and in some cases, development on the prod-
uct may discontinue. Spansion LLC therefore places the following conditions upon Advance
Information content:
“This document contains information on one or more products under development at Spansion LLC. The
information is intended to help you evaluate this product. Do not design in this product without con-
tacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a
commitment to production has taken place. This designation covers several aspects of the product
life cycle, including product qualification, initial production, and the subsequent phases in the
manufacturing process that occur before full production is achieved. Changes to the technical
specifications presented in a Preliminary document should be expected while keeping these as-
pects of production under consideration. Spansion places the following conditions upon
Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s) described
herein. The Preliminary status of this document indicates that product qualification has been completed,
and that initial production has begun. Due to the phases of the manufacturing process that require
maintaining efficiency and quality, this document may be revised by subsequent versions or modifica-
tions due to changes in technical specifications.”
Combination
Some data sheets will contain a combination of products with different designations (Advance In-
formation, Preliminary, or Full Production). This type of document will distinguish these products
and their designations wherever necessary, typically on the first page, the ordering information
page, and pages with the DC Characteristics table and the AC Erase and Program table (in the
table notes). The disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal
changes are expected, the Preliminary designation is removed from the data sheet. Nominal
changes may include those affecting the number of ordering part numbers available, such as the
addition or deletion of a speed option, temperature range, package type, or VIO range. Changes
may also include those needed to clarify a description or to correct a typographical error or incor-
rect specification. Spansion LLC applies the following conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s) described
herein. Spansion LLC deems the products to have been in sufficient production volume such that sub-
sequent versions of this document are not expected to change. However, typographical or specification
corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local AMD or Fujitsu
sales office.
2
S75WS256Nxx Based MCPs
S75WS-N-00_A0 February 17, 2005
A d v a n c e I n f o r m a t i o n
Contents
S75WS256Nxx Based MCPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Input/Output Descriptions and Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
MCP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Connection Diagrams/Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1 Special Handling Instructions for FBGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
5.2 Connection Diagram – Cellular Ram-Based Pinout, 9 x 12 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
5.3 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
2
3
4
5
5.3.1
Physical Dimensions – xxx084 – Fine Pitch Ball Grid Array 9 x 12 mm . . . . . . . . . . . . . . . . . . . . . . . . .16
5.4 Look-Ahead Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
S29PL256N MirrorBit™ Flash Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6
7
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Product Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
7.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.1 Device Operation Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.2 Asynchronous Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.3 Synchronous (Burst) Read Mode and Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8
8.3.1
Continuous Burst Read Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.3.2 8-, 16-, 32-Word Linear Burst Read with Wrap Around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.3.3 8-, 16-, 32-Word Linear Burst without Wrap Around. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.3.4 Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.4 Autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.5 Program/Erase Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.5.1
Single Word Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.5.2 Write Buffer Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.5.3 Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.5.4 Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.5.5 Erase Suspend/Erase Resume Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.5.6 Program Suspend/Program Resume Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
8.5.7 Accelerated Program/Chip Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.5.8 Unlock Bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.5.9 Write Operation Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.6 Simultaneous Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.7 Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.8 Handshaking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.9 Hardware Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.10 Software Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Advanced Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9.1 Lock Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.2 Persistent Protection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.3 Dynamic Protection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
9.4 Persistent Protection Bit Lock Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.5 Password Protection Method. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.6 Advanced Sector Protection Software Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.7 Hardware Data Protection Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9
9.7.1
WP# Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.7.2 ACC Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.7.3 Low VCC Write Inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.7.4 Write Pulse Glitch Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.7.5 Power-Up Write Inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
February 17, 2005 S75WS-N-00_A0
S75WS256Nxx Based MCPs
3
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10 Power Conservation Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
10.1 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
10.2 Automatic Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
10.3 Hardware RESET# Input Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
10.4 Output Disable (OE#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
11 Secured Silicon Sector Flash Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
11.1 Factory Secured SiliconSector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
11.2 Customer Secured Silicon Sector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
11.3 Secured Silicon Sector Entry and Secured Silicon Sector Exit Command Sequences. . . . . . . . . . . . . . . . . . . . . 63
12 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
12.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
12.2 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
12.3 Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
12.4 Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
12.5 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
12.6 VCC Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
12.7 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
12.8 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
12.8.1 CLK Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
12.8.2 Synchronous/Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
12.8.3 Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
12.8.4 AC Characteristics—Asynchronous Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
12.8.5 Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
12.8.6 Erase/Program Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
12.8.7 Erase and Programming Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
12.8.8 BGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
13 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
13.1 Common Flash Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
14 Commonly Used Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
S29PL256N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
15 Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
16 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
17 Logic Symbol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
18 Device Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
18.1 Requirements for Asynchronous Read Operation (Non-Burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
18.2 Requirements for Synchronous (Burst) Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
18.2.1 Continuous Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
18.2.2 8-, 16-, and 32-Word Linear Burst with Wrap Around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
18.2.3 8-, 16-, and 32-Word Linear Burst without Wrap Around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
18.3 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
18.4 RDY: Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
18.5 Handshaking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
18.6 Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
18.7 Accelerated Program/Chip Erase Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
18.8 Write Buffer Programming Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
18.9 Autoselect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
18.10 Dynamic Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
18.10.1 Dynamic Protection Bit (DYB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
18.11 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
18.12 Automatic Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
18.13 RESET#: Hardware Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
18.14 Output Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
18.15 Hardware Data Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
18.15.1 Low VCC Write Inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
18.15.2 Write Pulse Glitch Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
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18.15.3 Logical Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
18.15.4 Power-Up Write Inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
19 Sector Address / Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
19.1 Reading Array Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
19.2 Set Configuration Register Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
19.3 Read Configuration Register Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
19.3.1 Read Mode Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
19.3.2 Programmable Wait State Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
19.3.3 Programmable Wait State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
19.3.4 Boundary Crossing Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
19.3.5 Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
19.3.6 Burst Length Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
19.3.7 Burst Wrap Around. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
19.3.8 RDY Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
19.3.9 RDY Polarity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
19.4 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
19.5 Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
19.6 Autoselect Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
19.7 Program Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
19.8 Write Buffer Programming Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
19.8.1 Unlock Bypass Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
19.9 Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
19.10 Sector Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
19.10.1 Accelerated Sector Erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
20 Erase Suspend/Erase Resume Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
20.1 Program Suspend/Program Resume Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
20.2 Volatile Sector Protection Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
21 Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
22 Write Operation Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
22.1 DQ7: Data# Polling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
22.2 DQ6: Toggle Bit I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
22.3 Reading Toggle Bits DQ6/DQ2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
22.4 DQ5: Exceeded Timing Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
22.5 DQ3: Sector Erase Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
22.6 DQ1: Write to Buffer Abort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
23 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
24 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
25 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
25.1 CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
26 Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
27 Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
28 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
29 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
29.1 VCC Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
29.2 CLK Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
29.3 Synchronous/Burst Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
29.4 Asynchronous Mode Read @ VIO = 1.8 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
29.5 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
29.6 Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
29.7 Erase/Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
30 Erase and Programming Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
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CellularRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
31 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
32 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
32.1 Power-Up Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
33 Bus Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
33.1 Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
33.2 Page Mode Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
33.3 Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
33.4 Mixed-Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
33.5 Wait Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
33.6 LB#/UB# Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
34 Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
34.1 Standby Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
34.2 Temperature Compensated Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
34.3 Partial Array Refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
34.4 Deep Power-Down Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
35 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
35.1 Access Using CRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
35.2 Bus Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
35.2.1 Burst Length (BCR[2:0]): Default = Continuous Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
35.2.2 Burst Wrap (BCR[3]): Default = No Wrap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
35.2.3 Output Impedance (BCR[5:4]): Default = Outputs Use Full Drive Strength . . . . . . . . . . . . . . . . . . . . .166
35.2.4 Wait Configuration (BCR[8]): Default = Wait Transitions One Clock Before Data Valid/Invalid. . . .167
35.2.5 Wait Polarity (BCR[10]): Default = Wait Active High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
35.2.6 Latency Counter (BCR[13:11]): Default = Three-Clock Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
35.2.7 Operating Mode (BCR[15]): Default = Asynchronous Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
35.3 Refresh Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
35.3.1 Partial Array Refresh (RCR[2:0]): Default = Full Array Refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
35.3.2 Deep Power-Down (RCR[4]): Default = DPD Disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
35.3.3 Temperature Compensated Refresh (RCR[6:5]): Default = +85ºC Operation . . . . . . . . . . . . . . . . . . .170
35.3.4 Page Mode Operation (RCR[7]): Default = Disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
36 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
37 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
38 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
38.1 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
39 How Extended Timings Impact CellularRAM™ Operation. . . . . . . . . . . . . . . . . . . . . . . . . . 217
39.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
39.2 Asynchronous Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
39.2.1 Extended Write Timing— Asynchronous Write Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
39.3 Page Mode Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
39.4 Burst-Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
39.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
40 Revisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
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Tables
Table 2.1
Table 3.1
Table 7.1
Table 7.2
Table 7.3
Table 8.1
Table 8.2
Table 8.3
Table 8.4
Table 8.5
Table 8.6
Table 8.7
Table 8.8
Table 8.9
MCP Configurations and Valid Combinations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
S29WS256N Sector & Memory Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
S29WS128N Sector & Memory Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
S29WS064N Sector & Memory Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Device Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Address Latency (S29WS256N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Address Latency (S29WS128N/S29WS064N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Address/Boundary Crossing Latency (S29WS256N @ 80/66 MHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Address/Boundary Crossing Latency (S29WS256N @ 54MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Address/Boundary Crossing Latency (S29WS128N/S29WS064N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Burst Address Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Autoselect Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 8.10 Autoselect Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 8.11 Autoselect Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 8.12 Single Word Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 8.13 Write Buffer Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 8.14 Sector Erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 8.15 Chip Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 8.16 Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 8.17 Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 8.18 Program Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 8.19 Program Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 8.20 Unlock Bypass Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 8.21 Unlock Bypass Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 8.22 Unlock Bypass Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 8.23 Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 8.24 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 9.1
Table 9.2
Table 11.1
Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 11.2 Secured Silicon Sector Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 11.3 Secured Silicon Sector Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 11.4 Secured Silicon Sector Exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 12.1 Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 13.1 Memory Array Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 13.2 Sector Protection Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 13.3 CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 13.4 System Interface String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 13.5 Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 13.6 Primary Vendor-Specific Extended Query. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 18.1 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 18.2 Address Latency Scheme for < 56Mhz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 18.3 Address Latency Scheme for < 70Mhz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 18.4 Address Latency Scheme for < 84Mhz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 18.5 Burst Address Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 19.6 Sector Address / Memory Address Map for the RS512N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 19.7 Programmable Wait State Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 19.8 Burst Length Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 19.9 Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 19.10 Autoselect Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 19.11 Write Buffer Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
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Table 22.1 Maximum Negative Overshoot Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 24.1 Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 27.1 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 27.2 Bus Operations—Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 27.3 Bus Operations—Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 31.1 Bus Configuration Register Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 31.2 Sequence and Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 31.3 Output Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 31.4 Variable Latency Configuration Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 31.5 Refresh Configuration Register Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 31.6 128Mb Address Patterns for PAR (RCR[4] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 31.7 64Mb Address Patterns for PAR (RCR[4] = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 31.8 32Mb Address Patterns for PAR (RCR[4] = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 33.1 Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 33.2 Temperature Compensated Refresh Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 33.3 Partial Array Refresh Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 33.4 Deep Power-Down Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 34.1 Output Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 34.2 Asynchronous Read Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 34.3 Burst Read Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Table 34.4 Asynchronous Write Cycle Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Table 34.5 Burst Write Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 34.1 Initialization Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 34.2 Asynchronous Read Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Table 34.3 Asynchronous Read Timing Parameters Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 34.4 Asynchronous Read Timing Parameters—Page Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 34.5 Burst Read Timing Parameters—Single Access, Variable Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 34.6 Burst Read Timing Parameters—4-word Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 34.7 Burst Read Timing Parameters—4-word Burst with LB#/UB# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 34.8 Burst Read Timing Parameters—Burst Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 34.10 Burst Read Timing Parameters—BCR[8] = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 34.11 Asynchronous Write Timing Parameters—CE#-Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 34.12 Asynchronous Write Timing Parameters—LB#/UB#-Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 34.13 Asynchronous Write Timing Parameters—WE#-Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Table 34.14 Asynchronous Write Timing Parameters Using ADV#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 34.15 Burst Write Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 34.16 Burst Write Timing Parameters—BCR[8] = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 34.17 Write Timing Parameters—Burst Write Followed by Burst Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 34.18 Read Timing Parameters—Burst Write Followed by Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Table 34.19 Write Timing Parameters—Asynchronous Write Followed by Burst Read. . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Table 34.20 Read Timing Parameters—Asynchronous Write Followed by Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Table 34.21 Asynchronous Write Timing Parameters—ADV# Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Table 34.22 Burst Read Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Table 34.24 Burst Read Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 34.25 Asynchronous Write Timing Parameters—WE# Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 34.27 Burst Read Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 34.28 Asynchronous Write Timing Parameters Using ADV#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 34.30 Write Timing Parameters—ADV# Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 34.31 Read Timing Parameters—ADV# Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 34.33 Write Timing Parameters—Asynchronous Write Followed by Asynchronous Read . . . . . . . . . . . . . . . . . . . . 211
Table 34.34 Read Timing Parameters—Asynchronous Write Followed by Asynchronous Read. . . . . . . . . . . . . . . . . . . . . 211
Table 35.1 Extended Cycle Impact on Read and Write Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
8
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A d v a n c e I n f o r m a t i o n
Figures
Figure 5.1
Figure 5.2
Figure 8.1
Figure 8.2
Figure 8.3
Figure 8.4
Figure 8.5
Figure 8.6
Figure 9.1
Figure 9.2
Figure 9.3
Figure 12.1
Figure 12.2
Figure 12.3
Figure 12.4
Figure 12.5
Figure 12.6
Figure 12.7
Figure 12.8
Figure 12.9
Connection Diagram – Cellular Ram-Based 84-ball Fine-Pitch Ball Grid Array.............................................15
Look Ahead Pinout – 1.8 V only x 16NOR + x16pSRAM + x16MirrorBit Data..............................................16
Synchronous/Asynchronous State Diagram...........................................................................................24
Synchronous Read ............................................................................................................................27
Single Word Program.........................................................................................................................33
Write Buffer Programming Operation ...................................................................................................37
Sector Erase Operation ......................................................................................................................39
Write Operation Status Flowchart ........................................................................................................46
Advanced Sector Protection/Unprotection .............................................................................................52
PPB Program/Erase Algorithm.............................................................................................................55
Lock Register Program Algorithm.........................................................................................................58
Maximum Negative Overshoot Waveform .............................................................................................65
Maximum Positive Overshoot Waveform...............................................................................................65
Test Setup .......................................................................................................................................66
Input Waveforms and Measurement Levels...........................................................................................66
VCC Power-up Diagram ......................................................................................................................67
CLK Characterization .........................................................................................................................69
CLK Synchronous Burst Mode Read......................................................................................................70
8-word Linear Burst with Wrap Around.................................................................................................71
8-word Linear Burst without Wrap Around ............................................................................................71
Figure 12.10 Linear Burst with RDY Set One Cycle Before Data..................................................................................72
Figure 12.11 Asynchronous Mode Read...................................................................................................................73
Figure 12.12 Reset Timings...................................................................................................................................73
Figure 12.13 Chip/Sector Erase Operation Timings...................................................................................................75
Figure 12.14 Asynchronous Program Operation Timings............................................................................................76
Figure 12.15 Synchronous Program Operation Timings .............................................................................................77
Figure 12.16 Accelerated Unlock Bypass Programming Timing ...................................................................................77
Figure 12.17 Data# Polling Timings (During Embedded Algorithm).............................................................................78
Figure 12.18 Toggle Bit Timings (During Embedded Algorithm)..................................................................................78
Figure 12.19 Synchronous Data Polling Timings/Toggle Bit Timings ............................................................................79
Figure 12.20 DQ2 vs. DQ6....................................................................................................................................79
Figure 12.21 Latency with Boundary Crossing when Frequency > 66 MHz....................................................................80
Figure 12.22 Latency with Boundary Crossing into Program/Erase Bank......................................................................81
Figure 12.23 Example of Wait State Insertion..........................................................................................................82
Figure 12.24 Back-to-Back Read/Write Cycle Timings ...............................................................................................83
Figure 19.1
Figure 19.2
Figure 19.3
Figure 20.4
Figure 22.5
Figure 22.6
Figure 22.7
Figure 24.1
Figure 24.2
Figure 25.1
Figure 25.2
Figure 25.3
Figure 25.4
Figure 25.5
Figure 25.6
Figure 25.7
Figure 25.8
Figure 25.9
Synchronous/Asynchronous State Diagram.........................................................................................110
Program Word Operation..................................................................................................................115
Write Buffer Programming Operation .................................................................................................116
Erase Operation..............................................................................................................................119
Data# Polling Algorithm...................................................................................................................122
Toggle Bit Algorithm........................................................................................................................123
Maximum Positive Overshoot Waveform.............................................................................................125
Test Setup .....................................................................................................................................127
Input Waveforms and Measurement Levels.........................................................................................127
VCC Power-up Diagram ....................................................................................................................128
CLK Characterization .......................................................................................................................128
CLK Synchronous Burst Mode Read....................................................................................................130
8-word Linear Burst with Wrap Around...............................................................................................131
8-word Linear Burst without Wrap Around ..........................................................................................131
Burst with RDY Set One Cycle Before Data..........................................................................................132
Asynchronous Mode Read with Latched Addresses ...............................................................................133
Asynchronous Mode Read.................................................................................................................133
Reset Timings.................................................................................................................................134
Figure 25.10 Asynchronous Program Operation Timings: WE# Latched Addresses ......................................................136
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9
A d v a n c e I n f o r m a t i o n
Figure 25.11 Synchronous Program Operation Timings: CLK Latched Addresses.........................................................137
Figure 25.12 Accelerated Unlock Bypass Programming Timing .................................................................................137
Figure 25.13 Data# Polling Timings (During Embedded Algorithm)...........................................................................138
Figure 25.14 Toggle Bit Timings (During Embedded Algorithm)................................................................................138
Figure 25.15 Synchronous Data Polling Timings/Toggle Bit Timings ..........................................................................139
Figure 25.16 DQ2 vs. DQ6..................................................................................................................................139
Figure 25.17 Latency with Boundary Crossing........................................................................................................140
Figure 25.18 Example of Wait States Insertion ......................................................................................................140
Figure 25.19 Back-to-Back Read/Write Cycle Timings .............................................................................................141
Figure 27.1
Figure 28.2
Figure 29.1
Figure 29.2
Figure 29.3
Figure 29.4
Figure 29.5
Figure 29.6
Figure 29.7
Figure 29.8
Figure 31.1
Figure 31.2
Figure 31.3
Figure 31.4
Figure 31.5
Figure 31.6
Figure 34.1
Figure 34.2
Figure 34.3
Figure 34.4
Figure 34.5
Figure 34.6
Figure 34.7
Figure 34.8
Figure 34.9
Functional Block Diagram.................................................................................................................144
Power-Up Initialization Timing...........................................................................................................148
Read Operation (ADV# Low).............................................................................................................149
Write Operation (ADV# Low) ............................................................................................................150
Page Mode Read Operation (ADV# Low).............................................................................................151
Burst Mode Read (4-word burst) .......................................................................................................152
Burst Mode Write (4-word burst).......................................................................................................152
Wired or Wait Configuration..............................................................................................................153
Refresh Collision During Read Operation.............................................................................................154
Refresh Collision During Write Operation ............................................................................................155
Configuration Register Write, Asynchronous Mode Followed by Read ......................................................158
Configuration Register Write, Synchronous Mode Followed by Read0......................................................159
Wait Configuration (BCR[8] = 0).......................................................................................................162
Wait Configuration (BCR[8] = 1).......................................................................................................162
Wait Configuration During Burst Operation .........................................................................................163
Latency Counter (Variable Initial Latency, No Refresh Collision).............................................................163
AC Input/Output Reference Waveform ...............................................................................................170
Output Load Circuit .........................................................................................................................170
Initialization Period..........................................................................................................................174
Asynchronous Read.........................................................................................................................175
Asynchronous Read Using ADV# .......................................................................................................177
Page Mode Read .............................................................................................................................179
Single-Access Burst Read Operation—Variable Latency.........................................................................181
Four-word Burst Read Operation—Variable Latency..............................................................................183
Four-word Burst Read Operation (with LB#/UB#)................................................................................185
Figure 34.10 Refresh Collision During Write Operation ............................................................................................187
Figure 34.9. Continuous Burst Read Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition.....................188
Figure 34.11 CE#-Controlled Asynchronous Write ..................................................................................................189
Figure 34.12 LB#/UB#-Controlled Asynchronous Write ...........................................................................................191
Figure 34.13 WE#-Controlled Asynchronous Write..................................................................................................193
Figure 34.14 Asynchronous Write Using ADV#.......................................................................................................195
Figure 34.15 Burst Write Operation......................................................................................................................197
Figure 34.16 Continuous Burst Write Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition ....................198
Figure 34.17 Burst Write Followed by Burst Read...................................................................................................199
Figure 34.18 Asynchronous Write Followed by Burst Read .......................................................................................200
Figure 34.19 Asynchronous Write (ADV# Low) Followed By Burst Read.....................................................................202
Figure 34.23. Burst Read Followed by Asynchronous Write (WE#-Controlled)..............................................................204
Figure 34.26. Burst Read Followed by Asynchronous Write Using ADV# .....................................................................206
Figure 34.29. Asynchronous Write Followed by Asynchronous Read—ADV# Low..........................................................208
Figure 34.32. Asynchronous Write Followed by Asynchronous Read ...........................................................................210
Figure 35.1
Figure 35.2
Figure 35.3
Extended Timing for tCEM............................................................................................................................................... 212
Extended Timing for tTM................................................................................................................................................. 212
Extended Write Operation ................................................................................................................213
10
S75WS256Nxx Based MCPs
S75WS-N-00_A0 February 17, 2005
A d v a n c e I n f o r m a t i o n
1 Product Selector Guide
b
MCP Configuration
Code
Flash
Density
DYB
Power-Up
State
Package
84 ball
FBGA
(mm)
RAM Data Storage Flash pSRAM
Density Flash Density Speed Speed
pSRAM
(Cellular RAM)
Supplier
Model
Numbers
Device
Code Code pSRAM Data Storage
(Mb)
(Mb/Gb)
(MHz) (MHz)
Flash
(Mb)
Flash
(Mb)
(See Note)
MA
PA
0
1
0
1
54
66
54
66
S75WS256NDF
WS256N
128
RS512N
256
128
512 Mb
2
9x12
MB
PB
Note: 0 (Protected), 1 (Unprotected [Default State])
February 17, 2005 S75WS-N-00_A0
S75WS256Nxx Based MCPs
11
A d v a n c e I n f o r m a t i o n
2 Ordering Information
The ordering part number is formed by a valid combination of the following:
S75WS 256
N
D
F
BA
W
M
A
RAM Supplier; Speed Combination
A
B
=
=
Cellular RAM2, 54 MHz
Cellular RAM2, 66 MHz
Package Dimensions and Ball Count; DYB Power Up;
Flash Device Family (Data Storage)
M
P
=
=
1.4 mm, 9 x 12, 84 ball; 0; RS
1.4 mm, 9 x 12, 84 ball; 1; RS
Temperature Range
Wireless (–25°C to +85°C)
W
=
Package Type And Material
BA
=
Very Thin Fine-Pitch Ball Grid Array (BGA),
Lead (Pb)-free Compliant Package
Very Thin Fine-Pitch Ball Grid Array (BGA),
Lead (Pb)-free Package
BF
=
Data Storage Density
512 Mb
Code Flash Density
128 Mb
F
=
D
=
Process Technology
110 nm, Mirror Bit Technology
N
=
Flash Density
256 256 Mb
=
Device Family
S75WS = Multi-chip Product (MCP)
1.8-volt Burst Mode Flash Memory, RAM, and NAND Data Storage
Table 2.1 MCP Configurations and Valid Combinations
Valid Combinations
S75WS256N
D
F
BA, BF
W
M, P
A, B
Package Marking Note:
The BGA package marking omits the leading S75 and packing type designator from the ordering part number.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult
your local sales office to confirm availability of specific valid combinations and to check on newly
released combinations.
12
S75WS256Nxx Based MCPs
S75WS-N-00_A0 February 17, 2005
A d v a n c e I n f o r m a t i o n
3 Input/Output Descriptions and Logic Symbol
Table 3.1 identifies the input and output package connections provided on the device.
Table 3.1 Input/Output Descriptions
Symbol
– A0
Description
A
Address Inputs
max
DQ15 - DQ0
OE#
Data Inputs/Outputs
Output Enable input
Write Enable input
Ground
(Common)
WE#
V
SS
NC
No Connect; not connected internally.
RDY
Ready output. Indicates the status of the Burst read.
(Flash)
Clock input. In burst mode, after the initial word is output, subsequent
CLK
active edges of CLK increment the internal address counter. Should be at (Common)
V
or V while in asynchronous mode.
IL
IH
Address Valid input.
Indicates to device that the valid address is present on the address inputs.
AVD#
F-RST#
Hardware reset input.
Hardware write protect input.
F-WP#
F-ACC
At V , disables program and erase functions in the four outermost sectors.
(Flash)
IL
Should be at V for all other conditions.
IH
Accelerated input.
At V , accelerates programming; automatically places device in unlock
HH
bypass mode. At V , disables all program and erase functions. Should be
IL
at V for all other conditions.
IH
R-CE#
F-CE#
Chip-enable input for pSRAM
Chip-enable input for Flash.
Chip-enable input for Flash 1.
Chip-enable input for Flash 2.
Chip-enable input for Flash 3.
Control Register Enable .
Flash 1.8 Volt-only single power supply.
pSRAM Power Supply.
F1-CE#
F2-CE#
F3-CE#
R-CRE
Asynchronous relative to
CLK for Burst Mode.
(pSRAM – CellularRAM only)
F-V
CC
R-V
CC
R-UB#
R-LB#
Upper Byte Control.
(pSRAM)
Lower Byte Control .
A
– A0
max
16
DQ15 – DQ0
CLK
CE#
F-WP
F-ACC
F-CE#
R-CE#
OE#
WE#
RDY
F-RST#
AVD#
R-UB#
R-LB#
R-CRE
(See Note
)
Note: R-CRE is only present in CellularRAM-compatible pSRAM.
February 17, 2005 S75WS-N-00_A0
S75WS256Nxx Based MCPs
13
A d v a n c e I n f o r m a t i o n
4 MCP Block Diagram
V
CCf
VCC
VID
Flash-only Address
Shared Address
CLK
Amax – A0
16
DQ15 – DQ0
DQ15 – DQ0
CLK
WP#
ACC
CE#f1
OE#
WE#
WP#
ACC
CE#
OE#
WE#
RESET#
AVD#
Flash 1
(Note 2)—
Flash 2
Flash 3
(Note 3)
RESET#
AVD#
RDY
VSS
RDY
(Note 2)—
(Note 2)—
CE#f2
CE#f3
VCC
s
VCC
VCCQ
Amax – A0
16
I/O15 – I/O0
CLK
CE#s
CE#
WE#
OE#
UB#
LB#
pSRAM
UB#s
LB#s
VSSQ
AVD#
CRE
CREs
Notes:
1. CREs is only present in CellularRAM-compatible pSRAM.
2. CE#f1, CE#f2, and CE#f3 are the chip enable pins for the first, second, and third Flash devices, respectively. CE#f3
may not be needed depending on the package.
3. If necessary.
14
S75WS256Nxx Based MCPs
S75WS-N-00_A0 February 17, 2005
A d v a n c e I n f o r m a t i o n
5 Connection Diagrams/Physical Dimensions
This section contains the I/O designations and package specifications for the S75WS.
5.1
Special Handling Instructions for FBGA Package
Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning meth-
ods. The package and/or data integrity may be compromised if the package body is exposed to
temperatures above 150°C for prolonged periods of time.
5.2 Connection Diagram – Cellular Ram-Based Pinout, 9 x 12 mm
Legend:
A10
A1
X
DNU
DNU
RFU
B2
B4
B3
B5
B6
B7
B8
B9
X
ADV#
RFU
CLK
RFU
F-VCC
RFU
RFU
RFU
DNU
C3
A7
C5
C2
C4
C6
C7
C8
C9
X
F1-WP#
R-LB#
F-ACC
WE#
A8
A11
F2-CE#
All Shared
D2
D3
D5
D7
D8
D9
D4
D6
X
A3
A6
R-UB# F-RST#
RFU
A19
A12
A15
MirrorBit™
Data Flash Only
E2
E3
E4
E5
E6
E7
E8
E9
X
A2
A5
A18
RDY
A20
A9
A13
A21
Code
Flash Only
F2
F3
F4
F5
F7
F8
F9
F5
A1
A4
A17
RFU
A23
A10
A14
A22
X
RAM Only
G2
G3
G4
G7
G9
G5
G6
G8
X
A0
VSS
DQ1
RFU
RFU
DQ6
A24
A16
Flash
Shared Only
H3
H4
H5
H6
H7
H8
H2
H9
F-CE#
OE#
DQ9
DQ3
DQ4
DQ13
R-CRE
DQ15
J3
J4
J7
J8
J9
J2
J5
J6
R-CE1#
DQ0
DQ10
F-VCC
R-VCC
DQ12
DQ7
VSS
K3
K4
K5
K7
K8
K2
K6
K9
RFU
DQ8
DQ2
DQ11
A25
DQ5
DQ14
RFU
L2
L3
L4
L5
L6
L7
L8
L9
RFU
RFU
RFU
F-VCC
RFU
RFU
RFU
RFU
M1
M10
DNU
DNU
Figure 5.1 Connection Diagram – Cellular Ram-Based 84-ball Fine-Pitch Ball Grid Array
5.3
Physical Dimensions
5.3.1
Physical Dimensions – xxx084 – Fine Pitch Ball Grid Array 9 x 12 mm
TBD
February 17, 2005 S75WS-N-00_A0
S75WS256Nxx Based MCPs
15
A d v a n c e I n f o r m a t i o n
5.4 Look-Ahead Connection Diagram
Look Ahead Pinout – 1.8 V only x 16NOR + x16pSRAM + x16MirrorBit Data
A2
RFU
B2
A10
RFU
B10
RFU
A9
RFU
B9
A1
RFU
B1
Legend:
X
RFU
(Reserved for
Future Use)
RFU
RFU
C2
RFU
C9
C8
C3
VSS
D3
A7
C4
CLK
D4
C5
F2-CE#
D5
C6
F-VCC
D6
C7
X
AVD#
D2
F-CLK# R-OE# F2-OE#
Code Flash Only
D7
A8
D8
A11
E8
D9
F3-CE#
E9
WP#
E2
R-LB#
D4
ACC
WE#
E6
X
E3
E7
C7
MirrorBit Data
Only
A3
A6
R-UB# F-RST# R1-CE2
F4 F5 F6
A18 RDY/WAIT# A20
A19
A12
A15
F2
F3
F7
F8
F9
X
A2
A5
A9
A13
A21
Flash/Data
Shared
G2
A1
G3
A4
G4
A17
H4
G5
G6
A23
H6
G7
A10
H7
G8
A14
H8
G9
A22
H9
R2-CE1
X
H2
H3
H5
Flash/xRAM
Shared
A0
VSS
DQ1
R2-VCC R2-CE2
DQ6
A24
A16
J9
J3
J4
J5
J6
J7
J8
J2
X
F1-CE#
OE#
DQ9
DQ3
DQ4
DQ13
DQ15 R-CRE or
R-MRS
pSRAM Only
K2
R1-CE1#
L2
K3
DQ0
L3
K4
DQ10
L4
E6
R1-VCC
L6
K7
K8
DQ7
L8
K9
K5
F-VCC
L5
DQ12
VSS
XX
L7
DQ5
M7
L9
WP#
M9
xRAM Shared
R-VCC
M2
DQ8
M3
DQ2
M4
DQ11
M5
A25
DQ14
M8
M6
A27
A26
VSS
F-VCC
F4-CE# R-VCCQ F-VCCQ R-CLK#
N2
N1
N10
F-DQS1
P10
N9
RFU
P9
RFU
P2
F-DQS0
P1
RFU
RFU
RFU
RFU
Notes:
1. F1 and F2 denote XIP/Code Flash, while F3 and F4 denote Data/Companion Flash
2. In addition to being defined as F2-CE#, Ball C5 can also be assigned as F1-CE2# for code that has two chip enable
signals.
Figure 5.2 Look Ahead Pinout – 1.8 V only x 16NOR + x16pSRAM + x16MirrorBit Data
To provide customers with a migration path to higher densities, as well as the option to stack more
die in a package, Spansion has prepared a standard pinout that supports:
NOR Flash and SRAM densities up to 4 Gigabits
NOR Flash and PSRAM densities up to 4 Gigabits
NOR Flash and PSRAM and DATA STORAGE densities up to 4 Gigabits
The signal locations of the resultant MCP device are shown above. Note that for different densi-
ties, the actual package outline may vary. However, any pinout in any MCP will be a subset of the
pinout above.
16
S75WS256Nxx Based MCPs
S75WS-N-00_A0 February 17, 2005
A d v a n c e I n f o r m a t i o n
In some cases, there may be outrigger balls in locations outside the grid shown above. In such
cases, the user is recommended to treat these as RFUs, and not connect them to any other signal.
In case of any further inquiries about the above look-ahead pinout, please refer to the application
note on this subject, or contact your Spansion or Fujitsu sales office.
February 17, 2005 S75WS-N-00_A0
S75WS256Nxx Based MCPs
17
S75WS-N MirrorBit™ Flash Family
S29WS256N, S29WS128N, S29WS064N
256/128/64 Megabit (16/8/4 M x 16-Bit) CMOS 1.8 Volt-only
Simultaneous Read/Write, Burst Mode Flash Memory
Data Sheet
PRELIMINARY
General Description
The Spansion S29WS256/128/064N are Mirrorbit™Flash products fabricated on 110 nm process technology. These burst
mode Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate
banks using separate data and address pins. These products can operate up to 80 MHz and use a single VCC of
1.7 V to 1.95 V that makes them ideal for today’s demanding wireless applications requiring higher density, better per-
formance and lowered power consumption.
Distinctive Characteristics
Single 1.8 V read/program/erase (1.70–1.95 V)
110 nm MirrorBit™ Technology
Simultaneous Read/Write operation with zero
latency
Hardware (WP#) protection of top and bottom
sectors
Dual boot sector configuration (top and bottom)
Offered Packages
32-word Write Buffer
—
—
WS064N: 80-ball FBGA (7 mm x 9 mm)
WS256N/128N: 84-ball FBGA (8 mm x 11.6 mm)
Sixteen-bank architecture consisting of 16/8/4
Mwords for WS256N/128N/064N, respectively
Four 16 Kword sectors at both top and bottom of
memory array
254/126/62 64 Kword sectors (WS256N/128N/
064N)
Low VCC write inhibit
Persistent and Password methods of Advanced
Sector Protection
Write operation status bits indicate program and
erase operation completion
Programmable burst read modes
—
Linear for 32, 16 or 8 words linear read with or
without wrap-around
Suspend and Resume commands for Program and
Erase operations
Unlock Bypass program command to reduce
programming time
Synchronous or Asynchronous program operation,
independent of burst control register settings
ACC input pin to reduce factory programming time
Support for Common Flash Interface (CFI)
Industrial Temperature range (contact factory)
—
Continuous sequential read mode
Secured Silicon Sector region consisting of 128
words each for factory and customer
20-year data retention (typical)
Cycling Endurance: 100,000 cycles per sector
(typical)
RDY output indicates data available to system
Command set compatible with JEDEC (42.4)
standard
Performance Characteristics
Read Access Times
Current Consumption (typical values)
Speed Option (MHz)
Max. Synch. Latency, ns (t
80
80
66
80
54
80
Continuous Burst Read @ 66 MHz
35 mA
50 mA
19 mA
19 mA
20 µA
)
Simultaneous Operation (asynchronous)
Program (asynchronous)
IACC
Max. Synch. Burst Access, ns (t
)
9
11.2
80
13.5
80
BACC
Max. Asynch. Access Time, ns (t
)
80
Erase (asynchronous)
ACC
Max CE# Access Time, ns (t
)
80
80
80
Standby Mode (asynchronous)
CE
Max OE# Access Time, ns (t
)
13.5
13.5
13.5
OE
Typical Program & Erase Times
Single Word Programming
Effective Write Buffer Programming (V ) Per Word
40 µs
9.4 µs
6 µs
CC
Effective Write Buffer Programming (V
Sector Erase (16 Kword Sector)
Sector Erase (64 Kword Sector)
) Per Word
ACC
150 ms
600 ms
Publication Number S75WS-N-00 Revision A Amendment 0 Issue Date February 17, 2005
A d v a n c e I n f o r m a t i o n
6 Additional Resources
Visit www.amd.com and www.fujitsu.com to obtain the following related documents:
Application Notes
Using the Operation Status Bits in AMD Devices
Understanding Burst Mode Flash Memory Devices
Simultaneous Read/Write vs. Erase Suspend/Resume
MirrorBit™ Flash Memory Write Buffer Programming and Page Buffer Read
Design-In Scalable Wireless Solutions with Spansion Products
Common Flash Interface Version 1.4 Vendor Specific Extensions
Specification Bulletins
Contact your local sales office for details.
Drivers and Software Support
Spansion low-level drivers
Enhanced Flash drivers
Flash file system
CAD Modeling Support
VHDL and Verilog
IBIS
ORCAD
Technical Support
Contact your local sales office or contact Spansion LLC directly for additional technical support:
Email
US and Canada: HW.support@amd.com
Asia Pacific: asia.support@amd.com
Europe, Middle East, and Africa
Japan: http://edevice.fujitsu.com/jp/support/tech/#b7
Frequently Asked Questions (FAQ)
http://ask.amd.com/
http://edevice.fujitsu.com/jp/support/tech/#b7
Phone
US: (408) 749-5703
Japan (03) 5322-3324
Spansion LLC Locations
915 DeGuigne Drive, P.O. Box 3453
Sunnyvale, CA 94088-3453, USA
Telephone: 408-962-2500 or
1-866-SPANSION
Spansion Japan Limited
4-33-4 Nishi Shinjuku, Shinjuku-ku
Tokyo, 160-0023
Telephone: +81-3-5302-2200
Facsimile: +81-3-5302-2674
http://www.spansion.com
February 17, 2005 S75WS-N-00_A0
S75WS256Nxx Based MCPs
19
A d v a n c e I n f o r m a t i o n
7 Product Overview
The S29WS-N family consists of 256, 128 and 64Mbit, 1.8 volts-only, simultaneous read/write
burst mode Flash device optimized for today’s wireless designs that demand a large storage array,
rich functionality, and low power consumption.
These devices are organized in 16, 8 or 4 Mwords of 16 bits each and are capable of continuous,
synchronous (burst) read or linear read (8-, 16-, or 32-word aligned group) with or without wrap
around. These products also offer single word programming or a 32-word buffer for programming
with program/erase and suspend functionality. Additional features include:
Advanced Sector Protection methods for protecting sectors as required
256 words of Secured Silicon area for storing customer and factory secured information. The
Secured Silicon Sector is One Time Programmable.
7.1
Memory Map
The S29WS256/128/064N Mbit devices consist of 16 banks organized as shown in Tables
Table 7.1, Table 7.2, and Table 7.3.
Table 7.1 S29WS256N Sector & Memory Address Map
Bank Sector Sector Size
Sector/
Sector Range
Bank
Address Range
Notes
Size Count
(KB)
SA000
000000h–003FFFh
SA001
004000h–007FFFh
Contains four smaller sectors at
bottom of addressable memory.
4
32
2 MB
0
SA002
008000h–00BFFFh
SA003
00C000h–00FFFFh
15
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
SA004 to SA018
SA019 to SA034
SA035 to SA050
SA051 to SA066
SA067 to SA082
SA083 to SA098
SA099 to SA114
SA115 to SA130
SA131 to SA146
SA147 to SA162
SA163 to SA178
SA179 to SA194
SA195 to SA210
SA211 to SA226
SA227 to SA242
SA243 to SA257
SA258
010000h–01FFFFh to 0F0000h–0FFFFFh
100000h–10FFFFh to 1F0000h–1FFFFFh
200000h–20FFFFh to 2F0000h–2FFFFFh
300000h–30FFFFh to 3F0000h–3FFFFFh
400000h–40FFFFh to 4F0000h–4FFFFFh
500000h–50FFFFh to 5F0000h–5FFFFFh
600000h–60FFFFh to 6F0000h–6FFFFFh
700000h–70FFFFh to 7F0000h–7FFFFFh
800000h–80FFFFh to 8F0000h–8FFFFFh
900000h–90FFFFh to 9F0000h–9FFFFFh
A00000h–A0FFFFh to AF0000h–AFFFFFh
B00000h–B0FFFFh to BF0000h–BFFFFFh
C00000h–C0FFFFh to CF0000h–CFFFFFh
D00000h–D0FFFFh to DF0000h–DFFFFFh
E00000h–E0FFFFh to EF0000h–EFFFFFh
F00000h–F0FFFFh to FE0000h–FEFFFFh
FF0000h–FF3FFFh
2 MB
2 MB
2 MB
2 MB
2 MB
2 MB
2 MB
2 MB
2 MB
2 MB
2 MB
2 MB
2 MB
2 MB
16
16
16
16
16
16
16
16
16
16
16
16
16
16
15
1
2
3
4
5
6
All 128 KB sectors.
Pattern for sector address
range is xx0000h–xxFFFFh.
(see note)
7
8
9
10
11
12
13
14
2 MB
15
SA259
FF4000h–FF7FFFh
Contains four smaller sectors
at top of addressable memory.
4
32
SA260
FF8000h–FFBFFFh
SA261
FFC000h–FFFFFFh
Note: This table has been condensed to show sector-related information for an entire device on a single page.
Sectors and their address ranges that are not explicitly listed (such as SA005–SA017) have sector
starting and ending addresses that form the same pattern as all other sectors of that size. For example,
all 128 KB sectors have the pattern xx00000h–xxFFFFh.
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Table 7.2 S29WS128N Sector & Memory Address Map
Bank Sector Sector Size
Sector/
Sector Range
Bank
Address Range
Notes
Size Count
(KB)
32
SA000
000000h–003FFFh
32
SA001
004000h–007FFFh
Contains four smaller sectors at
bottom of addressable memory.
4
1 MB
32
0
SA002
008000h–00BFFFh
32
SA003
00C000h–00FFFFh
7
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
32
SA004 to SA010
SA011 to SA018
SA019 to SA026
SA027 to SA034
SA035 to SA042
SA043 to SA050
SA051 to SA058
SA059 to SA066
SA067 to SA074
SA075 to SA082
SA083 to SA090
SA091 to SA098
SA099 to SA106
SA107 to SA114
SA115 to SA122
SA123 to SA129
SA130
010000h–01FFFFh to 070000h–07FFFFh
080000h–08FFFFh to 0F0000h–0FFFFFh
100000h–10FFFFh to 170000h–17FFFFh
180000h–18FFFFh to 1F0000h–1FFFFFh
200000h–20FFFFh to 270000h–27FFFFh
280000h–28FFFFh to 2F0000h–2FFFFFh
300000h–30FFFFh to 370000h–37FFFFh
380000h–38FFFFh to 3F0000h–3FFFFFh
400000h–40FFFFh to 470000h–47FFFFh
480000h–48FFFFh to 4F0000h–4FFFFFh
500000h–50FFFFh to 570000h–57FFFFh
580000h–58FFFFh to 5F0000h–5FFFFFh
600000h–60FFFFh to 670000h–67FFFFh
680000h–68FFFFh to 6F0000h–6FFFFFh
700000h–70FFFFh to 770000h–77FFFFh
780000h–78FFFFh to 7E0000h–7EFFFFh
7F0000h–7F3FFFh
1 MB
1 MB
1 MB
1 MB
1 MB
1 MB
1 MB
1 MB
1 MB
1 MB
1 MB
1 MB
1 MB
1 MB
8
8
8
8
8
8
8
8
8
8
8
8
8
8
7
1
2
3
4
5
6
All 128 KB sectors.
Pattern for sector
address range is
xx0000h–xxFFFFh.
(See Note)
7
8
9
10
11
12
13
14
1 MB
32
15
SA131
7F4000h–7F7FFFh
Contains four smaller sectors
at top of addressable memory.
4
32
SA132
7F8000h–7FBFFFh
32
SA133
7FC000h–7FFFFFh
Note: This table has been condensed to show sector-related information for an entire device on a single page.
Sectors and their address ranges that are not explicitly listed (such as SA005–SA009) have sector
starting and ending addresses that form the same pattern as all other sectors of that size. For example,
all 128 KB sectors have the pattern xx00000h–xxFFFFh.
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Table 7.3 S29WS064N Sector & Memory Address Map
Bank Sector Sector Size
Sector/
Sector Range
Bank
Address Range
Notes
Size
Count
(KB)
SA000
SA001
000000h–003FFFh
004000h–007FFFh
Contains four smaller sectors
at bottom of addressable memory.
4
32
SA002
008000h–00BFFFh
0.5 MB
0
SA003
00C000h–00FFFFh
SA004
010000h–01FFFFh
3
128
SA005
020000h–02FFFFh
SA006
030000h–03FFFFh
0.5 MB
0.5 MB
0.5 MB
0.5 MB
0.5 MB
0.5 MB
0.5 MB
0.5 MB
0.5 MB
0.5 MB
0.5 MB
0.5 MB
0.5 MB
0.5 MB
4
4
4
4
4
4
4
4
4
4
4
4
4
4
128
128
128
128
128
128
128
128
128
128
128
128
128
128
1
2
SA007–SA010
SA011–SA014
SA015–SA018
SA019–SA022
SA023–SA026
SA027–SA030
SA031–SA034
SA035–SA038
SA039–SA042
SA043–SA046
SA047–SA050
SA051–SA054
SA055–SA058
SA059–SA062
SA063
040000h–04FFFFh to 070000h–07FFFFh
080000h–08FFFFh to 0B0000h–0BFFFFh
0C0000h–0CFFFFh to 0F0000h–0FFFFFh
100000h–10FFFFh to 130000h–13FFFFh
140000h–14FFFFh to 170000h–17FFFFh
180000h–18FFFFh to 1B0000h–1BFFFFh
1C0000h–1CFFFFh to 1F0000h–1FFFFFh
200000h–20FFFFh to 230000h–23FFFFh
240000h–24FFFFh to 270000h–27FFFFh
280000h–28FFFFh to 2B0000h–2BFFFFh
2C0000h–2CFFFFh to 2F0000h–2FFFFFh
300000h–30FFFFh to 330000h–33FFFFh
340000h–34FFFFh to 370000h–37FFFFh
380000h–38FFFFh to 3B0000h–3BFFFFh
3C0000h–3CFFFFh
3
4
5
6
All 128 KB sectors.
Pattern for sector
address range is
xx0000h–xxFFFFh.
(see note)
7
8
9
10
11
12
13
14
3
128
SA064
3D0000h–3DFFFFh
SA065
3E0000h–3EFFFFh
0.5 MB
15
SA066
3F0000h–3F3FFFh
SA067
3F4000h–3F7FFFh
Contains four smaller sectors a
t top of addressable memory.
4
32
SA068
3F8000h–3FBFFFh
SA069
3FC000h–3FFFFFh
Note: This table has been condensed to show sector-related information for an entire device on a single page.
Sectors and their address ranges that are not explicitly listed (such as SA008–SA009) have sector
starting and ending addresses that form the same pattern as all other sectors of that size. For example,
all 128 KB sectors have the pattern xx00000h–xxFFFFh.
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8 Device Operations
This section describes the read, program, erase, simultaneous read/write operations, handshak-
ing, and reset features of the Flash devices.
Operations are initiated by writing specific commands or a sequence with specific address and
data patterns into the command registers (see Table 13.1 and Table 13.2). The command register
itself does not occupy any addressable memory location; rather, it is composed of latches that
store the commands, along with the address and data information needed to execute the com-
mand. The contents of the register serve as input to the internal state machine and the state
machine outputs dictate the function of the device. Writing incorrect address and data values or
writing them in an improper sequence may place the device in an unknown state, in which case
the system must write the reset command to return the device to the reading array data mode.
8.1
Device Operation Table
The device must be setup appropriately for each operation. Table 8.1 describes the required state
of each control pin for any particular operation.
Table 8.1 Device Operations
Operation
CE# OE#
WE#
Addresses
Addr In
Addr In
Addr In
Addr In
X
DQ15–0
Data Out
Data Out
I/O
RESET#
CLK
X
AVD#
Asynchronous Read - Addresses Latched
Asynchronous Read - Addresses Steady State
Asynchronous Write
L
L
L
L
H
H
L
H
H
H
H
H
L
X
L
L
L
H
H
X
X
X
Synchronous Write
L
L
I/O
Standby (CE#)
H
X
X
X
HIGH Z
HIGH Z
X
X
X
X
Hardware Reset
X
Burst Read Operations (Synchronous)
Load Starting Burst Address
L
L
X
L
H
H
Addr In
X
X
H
H
Advance Burst to next address with appropriate Data
presented on the Data Bus
Burst
Data Out
H
Terminate current Burst read cycle
H
X
X
X
H
H
X
X
HIGH Z
HIGH Z
H
L
X
X
Terminate current Burst read cycle via RESET#
X
Terminate current Burst read cycle and start new Burst
read cycle
L
X
H
Addr In
I/O
H
Legend: L = Logic 0, H = Logic 1, X = Don’t Care, I/O = Input/Output.
8.2 Asynchronous Read
All memories require access time to output array data. In an asynchronous read operation, data
is read from one memory location at a time. Addresses are presented to the device in random
order, and the propagation delay through the device causes the data on its outputs to arrive asyn-
chronously with the address on its inputs.
The device defaults to reading array data asynchronously after device power-up or hardware re-
set. Asynchronous read requires that the CLK signal remain at VIL during the entire memory read
operation. To read data from the memory array, the system must first assert a valid address on
Amax–A0, while driving AVD# and CE# to VIL. WE# must remain at VIH. The rising edge of AVD#
latches the address. The OE# signal must be driven to VIL, once AVD# has been driven to VIH.
Data is output on A/DQ15-A/DQ0 pins after the access time (tOE) has elapsed from the falling
edge of OE#.
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8.3 Synchronous (Burst) Read Mode and Configuration Register
When a series of adjacent addresses needs to be read from the device (in order from lowest to
highest address), the synchronous (or burst read) mode can be used to significantly reduce the
overall time needed for the device to output array data. After an initial access time required for
the data from the first address location, subsequent data is output synchronized to a clock input
provided by the system.
The device offers both continuous and linear methods of burst read operation, which are dis-
cussed in sections 8.3.1, 8.3.2, and 8.3.3.
Since the device defaults to asynchronous read mode after power-up or a hardware reset, the
configuration register must be set to enable the burst read mode. Other Configuration Register
settings include the number of wait states to insert before the initial word (tIACC) of each burst
access, the burst mode in which to operate, and when RDY indicates data is ready to be read.
Prior to entering the burst mode, the system should first determine the configuration register set-
tings (and read the current register settings if desired via the Read Configuration Register
command sequence), and then write the configuration register command sequence. See 8.3.4
and Table 13.1 for further details.
Power-up/
Hardware Reset
Asynchronous Read
Mode Only
Set Burst Mode
Configuration Register
Command for
Set Burst Mode
Configuration Register
Command for
Synchronous Mode
(CR15 = 0)
Asynchronous Mode
(CR15 = 1)
Synchronous Read
Mode Only
Figure 8.1 Synchronous/Asynchronous State Diagram
The device outputs the initial word subject to the following operational conditions:
tIACC specification: the time from the rising edge of the first clock cycle after addresses are
latched to valid data on the device outputs.
Configuration register setting CR13–CR11: the total number of clock cycles (wait states)
that occur before valid data appears on the device outputs. The effect is that tIACC is
lengthened.
The device outputs subsequent words tBACC after the active edge of each successive clock cycle,
which also increments the internal address counter. The device outputs burst data at this rate sub-
ject to the following operational conditions:
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Starting address: whether the address is divisible by four (where A[1:0] is 00). A divisible-
by-four address incurs the least number of additional wait states that occur after the initial
word. The number of additional wait states required increases for burst operations in which
the starting address is one, two, or three locations above the divisible-by-four address (i.e.,
where A[1:0] is 01, 10, or 11).
Boundary crossing: There is a boundary at every 128 words due to the internal architecture
of the device. One additional wait state must be inserted when crossing this boundary if the
memory bus is operating at a high clock frequency. Please refer to the tables below.
Clock frequency: the speed at which the device is expected to burst data. Higher speeds
require additional wait states after the initial word for proper operation.
In all cases, with or without latency, the RDY output indicates when the next data is available to
be read.
Tables 8.2 – 8.6 reflect wait states required for S29WS256/128/064N devices. Refer to the Con-
figuration Register table (CR11 – CR14) and timing diagrams for more details.
Table 8.2 Address Latency (S29WS256N)
Word
Wait States
x ws
Cycle
D4
0
1
2
3
D0
D1
D2
D3
D1
D2
D2
D3
D3
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
D8
D8
D8
D8
x ws
1 ws
1 ws
1 ws
D4
x ws
D3
1 ws
1 ws
D4
x ws
1 ws
D4
Table 8.3 Address Latency (S29WS128N/S29WS064N)
Word
Wait States
Cycle
D4
0
1
2
3
5, 6, 7 ws
5, 6, 7 ws
5, 6, 7 ws
5, 6, 7 ws
D0
D1
D2
D3
D1
D2
D2
D3
D3
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
D8
D8
D8
D8
1 ws
1 ws
1 ws
D4
D3
1 ws
1 ws
D4
1 ws
D4
Table 8.4 Address/Boundary Crossing Latency (S29WS256N @ 80/66 MHz)
Word
Wait States
7, 6 ws
Cycle
1 ws
1 ws
1 ws
1 ws
0
1
2
3
D0
D1
D2
D3
D1
D2
D2
D3
D3
D4
D4
D4
D4
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
7, 6 ws
1 ws
1 ws
1 ws
7, 6 ws
D3
1 ws
1 ws
7, 6 ws
1 ws
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Table 8.5 Address/Boundary Crossing Latency (S29WS256N @ 54MHz)
Word
Wait States
5 ws
Cycle
D4
0
1
2
3
D0
D1
D2
D3
D1
D2
D2
D3
D3
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
D8
D8
D8
D8
5 ws
1 ws
1 ws
1 ws
D4
5 ws
D3
1 ws
1 ws
D4
5 ws
1 ws
D4
Table 8.6 Address/Boundary Crossing Latency (S29WS128N/S29WS064N)
Word
Wait States
5, 6, 7 ws
5, 6, 7 ws
5, 6, 7 ws
5, 6, 7 ws
Cycle
1 ws
1 ws
1 ws
1 ws
0
1
2
3
D0
D1
D2
D3
D1
D2
D2
D3
D3
D4
D4
D4
D4
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
1 ws
1 ws
1 ws
D3
1 ws
1 ws
1 ws
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Note: Setup Configuration Register parameters
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write Set Configuration Register
Command and Settings:
Address 555h, Data D0h
Address X00h, Data CR
Command Cycle
CR = Configuration Register Bits CR15-CR0
Load Initial Address
Address = RA
RA = Read Address
CR13-CR11 sets initial access time
(from address latched to
valid data) from 2 to 7 clock cycles
Wait tIACC
Programmable Wait State Setting
+
Read Initial Data
RD = DQ[15:0]
RD = Read Data
Wait X Clocks:
Additional Latency Due to Starting
Address, Clock Frequency, and
Boundary Crossing
Read Next Data
RD = DQ[15:0]
Delay X Clocks
Crossing
Boundary?
No
End of Data?
Yes
Yes
Completed
Figure 8.2 Synchronous Read
8.3.1
Continuous Burst Read Mode
In the continuous burst read mode, the device outputs sequential burst data from the starting
address given and then wrap around to address 000000h when it reaches the highest addressable
memory location. The burst read mode continues until the system drives CE# high, or RESET=
VIL. Continuous burst mode can also be aborted by asserting AVD# low and providing a new ad-
dress to the device.
If the address being read crosses a 128-word line boundary (as mentioned above) and the sub-
sequent word line is not being programmed or erased, additional latency cycles are required as
reflected by the configuration register table (Table 8.8).
If the address crosses a bank boundary while the subsequent bank is programming or erasing,
the device provides read status information and the clock is ignored. Upon completion of status
read or program or erase operation, the host can restart a burst read operation using a new ad-
dress and AVD# pulse.
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8.3.2
8-, 16-, 32-Word Linear Burst Read with Wrap Around
In a linear burst read operation, a fixed number of words (8, 16, or 32 words) are read from con-
secutive addresses that are determined by the group within which the starting address falls. The
groups are sized according to the number of words read in a single burst sequence for a given
mode (see Table 8.7).
For example, if the starting address in the 8-word mode is 3Ch, the address range to be read
would be 38-3Fh, and the burst sequence would be 3C-3D-3E-3F-38-39-3A-3Bh. Thus, the device
outputs all words in that burst address group until all word are read, regardless of where the start-
ing address occurs in the address group, and then terminates the burst read.
In a similar fashion, the 16-word and 32-word Linear Wrap modes begin their burst sequence on
the starting address provided to the device, then wrap back to the first address in the selected
address group.
Note that in this mode the address pointer does not cross the boundary that occurs every 128
words; thus, no additional wait states are inserted due to boundary crossing.
Table 8.7 Burst Address Groups
Mode
Group Size
8 words
Group Address Ranges
0-7h, 8-Fh, 10-17h,...
0-Fh, 10-1Fh, 20-2Fh,...
00-1Fh, 20-3Fh, 40-5Fh,...
8-word
16-word
32-word
16 words
32 words
8.3.3
8-, 16-, 32-Word Linear Burst without Wrap Around
If wrap around is not enabled for linear burst read operations, the 8-word, 16-word, or 32-word
burst executes up to the maximum memory address of the selected number of words. The burst
stops after 8, 16, or 32 addresses and does not wrap around to the first address of the selected
group.
For example, if the starting address in the 8- word mode is 3Ch, the address range to be read
would be 39-40h, and the burst sequence would be 3C-3D-3E-3F-40-41-42-43h if wrap around
is not enabled. The next address to be read requires a new address and AVD# pulse. Note that
in this burst read mode, the address pointer may cross the boundary that occurs every 128 words,
which will incur the additional boundary crossing wait state.
8.3.4
Configuration Register
The configuration register sets various operational parameters associated with burst mode. Upon
power-up or hardware reset, the device defaults to the asynchronous read mode, and the config-
uration register settings are in their default state. The host system should determine the proper
settings for the entire configuration register, and then execute the Set Configuration Register
command sequence, before attempting burst operations. The configuration register is not reset
after deasserting CE#. The Configuration Register can also be read using a command sequence
(see Table 13.1). The following list describes the register settings.
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Table 8.8 Configuration Register
CR Bit
Function
Settings (Binary)
Set Device Read
Mode
0 = Synchronous Read (Burst Mode) Enabled
1 = Asynchronous Read Mode (default) Enabled
CR15
54 MHz 66 Mhz 80 MHz
S29WS064N
S29WS128N
N/A
0
N/A
1
N/A
1
Default value is 0
CR14 Boundary Crossing
0 = No extra boundary crossing latency
1 = With extra boundary crossing latency (default)
Must be set to 1 greater than 54 MHz.
S29WS256N
S29WS064N
S29WS128N
011 = Data valid on 5th active CLK
edge after addresses latched
100 = Data valid on 6th active CLK
edge after addresses latched
CR13
0
1
1
1
0
0
1
0
1
S29WS256N
101 = Data valid on 7th active CLK
edge after addresses latched (default)
110 = Reserved
S29WS064N
S29WS128N
Programmable
CR12
Wait State
S29WS256N
111 = Reserved
Inserts wait states before initial data
is available. Setting greater number of wait
states before initial data reduces latency
after initial data. (Notes 1, 2)
S29WS064N
S29WS128N
CR11
S29WS256N
0 = RDY signal active low
CR10
CR9
RDY Polarity
Reserved
1 = RDY signal active high (default)
1 = default
0 = RDY active one clock cycle before data
1 = RDY active with data (default)
When CR13-CR11 are set to 000,
CR8
RDY
RDY is active with data regardless of CR8 setting.
CR7
CR6
CR5
CR4
Reserved
Reserved
Reserved
Reserved
1 = default
1 = default
0 = default
0 = default
0 = No Wrap Around Burst
1 = Wrap Around Burst (default)
CR3
Burst Wrap Around
000 = Continuous (default)
010 = 8-Word Linear Burst
011 = 16-Word Linear Burst
100 = 32-Word Linear Burst
(All other bit settings are reserved)
CR2
CR1
CR0
Burst Length
Notes:
1. Refer to Tables 8.2 - 8.6 for wait states requirements.
2. Refer to Synchronous Burst Read timing diagrams
3. Configuration Register is in the default state upon power-up or hardware reset.
Reading the Configuration Table. The configuration register can be read with a four-cycle com-
mand sequence. See Table 13.1 for sequence details. Once the data has been read from the
configuration register, a software reset command is required to set the device into the correct
state.
8.4 Autoselect
The Autoselect is used for manufacturer ID, Device identification, and sector protection informa-
tion. This mode is primarily intended for programming equipment to automatically match a device
with its corresponding programming algorithm. The Autoselect codes can also be accessed in-sys-
tem. When verifying sector protection, the sector address must appear on the appropriate highest
order address bits (see Table 8.9). The remaining address bits are don't care. The most significant
four bits of the address during the third write cycle selects the bank from which the Autoselect
codes are read by the host. All other banks can be accessed normally for data read without exiting
the Autoselect mode.
To access the Autoselect codes, the host system must issue the Autoselect command.
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The Autoselect command sequence may be written to an address within a bank that is either
in the read or erase-suspend-read mode.
The Autoselect command may not be written while the device is actively programming or
erasing. Autoselect does not support simultaneous operations or burst mode.
The system must write the reset command to return to the read mode (or erase-suspend-
read mode if the bank was previously in Erase Suspend).
See Table 13.1 for command sequence details.
Table 8.9 Autoselect Addresses
Description
Manufacturer ID
Device ID, Word 1
Address
Read Data
(BA) + 00h 0001h
(BA) + 01h 227Eh
2230 (WS256N)
Device ID, Word 2
Device ID, Word 3
(BA) + 0Eh 2231 (WS128N)
2232 (WS064N)
(BA) + 0Fh 2200
DQ15 - DQ8 = Reserved
DQ7 (Factory Lock Bit): 1 = Locked, 0 = Not Locked
DQ6 (Customer Lock Bit): 1 = Locked, 0 = Not Locked
DQ5 (Handshake Bit): 1 = Reserved, 0 = Standard Handshake
DQ4, DQ3 (WP# Protection Boot Code): 00 = WP# Protects both Top Boot and
Bottom Boot Sectors. 01, 10, 11 = Reserved
Indicator Bits
(See Note)
(BA) + 03h
DQ2 = Reserved
DQ1 (DYB Power up State [Lock Register DQ4]): 1 = Unlocked (user option),
0 = Locked (default)
DQ0 (PPB Eraseability [Lock Register DQ3]): 1 = Erase allowed,
0 = Erase disabled
Sector Block Lock/
Unlock
(SA) + 02h 0001h = Locked, 0000h = Unlocked
Note: For WS128N and WS064, DQ1 and DQ0 are reserved.
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Software Functions and Sample Code
Table 8.10 Autoselect Entry
(LLD Function = lld_AutoselectEntryCmd)
Cycle
Operation
Write
Byte Address
BAxAAAh
BAx555h
Word Address
BAx555h
Data
Unlock Cycle 1
Unlock Cycle 2
Autoselect Command
0x00AAh
0x0055h
0x0090h
Write
BAx2AAh
Write
BAxAAAh
BAx555h
Table 8.11 Autoselect Exit
(LLD Function = lld_AutoselectExitCmd)
Cycle
Operation
Write
Byte Address
Word Address
base + XXXh
Data
Unlock Cycle 1
base + XXXh
0x00F0h
Notes:
1. Any offset within the device works.
2. BA = Bank Address. The bank address is required.
3. base = base address.
The following is a C source code example of using the autoselect function to read the manu-
facturer ID. Refer to the Spansion Low Level Driver User Guide (available on www.amd.com
and www.fujitsu.com) for general information on Spansion Flash memory software develop-
ment guidelines.
/* Here is an example of Autoselect mode (getting manufacturer ID) */
/* Define UINT16 example: typedef unsigned short UINT16; */
UINT16 manuf_id;
/* Auto Select Entry */
*( (UINT16 *)bank_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */
*( (UINT16 *)bank_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */
*( (UINT16 *)bank_addr + 0x555 ) = 0x0090; /* write autoselect command */
/* multiple reads can be performed after entry */
manuf_id = *( (UINT16 *)bank_addr + 0x000 ); /* read manuf. id */
/* Autoselect exit */
*( (UINT16 *)base_addr + 0x000 ) = 0x00F0; /* exit autoselect (write reset command) */
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8.5 Program/Erase Operations
These devices are capable of several modes of programming and or erase operations which are
described in detail in the following sections. However, prior to any programming and or erase op-
eration, devices must be setup appropriately as outlined in the configuration register (Table 8.8).
For any program and or erase operations, including writing command sequences, the system
must drive AVD# and CE# to VIL, and OE# to VIH when providing an address to the device, and
drive WE# and CE# to VIL, and OE# to VIH when writing commands or programming data.
Addresses are latched on the last falling edge of WE# or CE#, while data is latched on the 1st
rising edge of WE# or CE#.
Note the following:
When the Embedded Program algorithm is complete, the device returns to the read mode.
The system can determine the status of the program operation by using DQ7 or DQ6. Refer
to the Write Operation Status section for information on these status bits.
A 0 cannot be programmed back to a 1. Attempting to do so causes the device to set DQ5 = 1
(halting any further operation and requiring a reset command). A succeeding read shows that
the data is still 0. Only erase operations can convert a 0 to a 1.
Any commands written to the device during the Embedded Program Algorithm are ignored
except the Program Suspend command.
Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a program oper-
ation is in progress.
A hardware reset immediately terminates the program operation and the program command
sequence should be reinitiated once the device has returned to the read mode, to ensure data
integrity.
Programming is allowed in any sequence and across sector boundaries for single word pro-
gramming operation.
8.5.1
Single Word Programming
Single word programming mode is the simplest method of programming. In this mode, four Flash
command write cycles are used to program an individual Flash address. The data for this pro-
gramming operation could be 8-, 16- or 32-bits wide. While this method is supported by all
Spansion devices, in general it is not recommended for devices that support Write Buffer Pro-
gramming. See Table 13.1 for the required bus cycles and Figure 8.3 for the flowchart.
When the Embedded Program algorithm is complete, the device then returns to the read mode
and addresses are no longer latched. The system can determine the status of the program oper-
ation by using DQ7 or DQ6. Refer to the Write Operation Status section for information on these
status bits.
During programming, any command (except the Suspend Program command) is ignored.
The Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a program op-
eration is in progress.
A hardware reset immediately terminates the program operation. The program command se-
quence should be reinitiated once the device has returned to the read mode, to ensure data
integrity.
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Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write Program Command:
Address 555h, Data A0h
Setup Command
Program Address (PA),
Program Data (PD)
Program Data to Address:
PA, PD
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Yes
Polling Status
= Busy?
No
Yes
Polling Status
= Done?
Error condition
No
(Exceeded Timing Limits)
PASS. Device is in
read mode.
FAIL. Issue reset command
to return to read array mode.
Figure 8.3 Single Word Program
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Software Functions and Sample Code
Table 8.12 Single Word Program
(LLD Function = lld_ProgramCmd)
Cycle
Operation
Write
Byte Address
Base + AAAh
Base + 554h
Base + AAAh
Word Address
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Word Address
Data
00AAh
Unlock Cycle 1
Unlock Cycle 2
Program Setup
Program
Write
0055h
Write
00A0h
Write
Data Word
Note: Base = Base Address.
The following is a C source code example of using the single word program function. Refer to
the Spansion Low Level Driver User’s Guide (available on www.amd.com and
www.fujitsu.com) for general information on Spansion Flash memory software development
guidelines.
/* Example: Program Command
*/
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x00A0;
/* write unlock cycle 1
/* write unlock cycle 2
/* write program setup command
/* write data to be programmed
*/
*/
*/
*/
*( (UINT16 *)pa )
= data;
/* Poll for program completion */
8.5.2
Write Buffer Programming
Write Buffer Programming allows the system to write a maximum of 32 words in one program-
ming operation. This results in a faster effective word programming time than the standard word
programming algorithms. The Write Buffer Programming command sequence is initiated by first
writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load
command written at the Sector Address in which programming occurs. At this point, the system
writes the number of word locations minus 1 that are loaded into the page buffer at the Sector
Address in which programming occurs. This tells the device how many write buffer addresses are
loaded with data and therefore when to expect the Program Buffer to Flash confirm command.
The number of locations to program cannot exceed the size of the write buffer or the operation
aborts. (Number loaded = the number of locations to program minus 1. For example, if the sys-
tem programs 6 address locations, then 05h should be written to the device.)
The system then writes the starting address/data combination. This starting address is the first
address/data pair to be programmed, and selects the write-buffer-page address. All subsequent
address/data pairs must fall within the elected-write-buffer-page.
The write-buffer-page is selected by using the addresses AMAX - A5.
The write-buffer-page addresses must be the same for all address/data pairs loaded into the write
buffer. (This means Write Buffer Programming cannot be performed across multiple write-buffer-
pages. This also means that Write Buffer Programming cannot be performed across multiple sec-
tors. If the system attempts to load programming data outside of the selected write-buffer-page,
the operation ABORTs.)
After writing the Starting Address/Data pair, the system then writes the remaining address/data
pairs into the write buffer.
Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter
is decremented for every data load operation. Also, the last data loaded at a location before the
Program Buffer to Flash confirm command is programmed into the device. It is the software's re-
sponsibility to comprehend ramifications of loading a write-buffer location more than once. The
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counter decrements for each data load operation, NOT for each unique write-buffer-address loca-
tion. Once the specified number of write buffer locations have been loaded, the system must then
write the Program Buffer to Flash command at the Sector Address. Any other address/data write
combinations abort the Write Buffer Programming operation. The device goes busy. The Data Bar
polling techniques should be used while monitoring the last address location loaded into the write
buffer. This eliminates the need to store an address in memory because the system can load the
last address location, issue the program confirm command at the last loaded address location,
and then data bar poll at that same address. DQ7, DQ6, DQ5, DQ2, and DQ1 should be monitored
to determine the device status during Write Buffer Programming.
The write-buffer embedded programming operation can be suspended using the standard sus-
pend/resume commands. Upon successful completion of the Write Buffer Programming operation,
the device returns to READ mode.
The Write Buffer Programming Sequence is ABORTED under any of the following conditions:
Load a value that is greater than the page buffer size during the Number of Locations to Pro-
gram step.
Write to an address in a sector different than the one specified during the Write-Buffer-Load
command.
Write an Address/Data pair to a different write-buffer-page than the one selected by the
Starting Address during the write buffer data loading stage of the operation.
Write data other than the Confirm Command after the specified number of data load cycles.
The ABORT condition is indicated by DQ1 = 1, DQ7 = Data# (for the last address location loaded),
DQ6 = TOGGLE, DQ5 = 0. This indicates that the Write Buffer Programming Operation was
ABORTED. A Write-to-Buffer-Abort reset command sequence is required when using the write
buffer Programming features in Unlock Bypass mode. Note that the Secured Silicon sector, au-
toselect, and CFI functions are unavailable when a program operation is in progress.
Write buffer programming is allowed in any sequence of memory (or address) locations. These
flash devices are capable of handling multiple write buffer programming operations on the same
write buffer address range without intervening erases.
Use of the write buffer is strongly recommended for programming when multiple words are to be
programmed. Write buffer programming is approximately eight times faster than programming
one word at a time.
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Software Functions and Sample Code
Table 8.13 Write Buffer Program
(LLD Functions Used = lld_WriteToBufferCmd, lld_ProgramBufferToFlashCmd)
Cycle
Description
Unlock
Operation
Write
Byte Address
Base + AAAh
Base + 554h
Word Address
Base + 555h
Base + 2AAh
Data
00AAh
1
2
3
4
Unlock
Write
0055h
Write Buffer Load Command
Write Word Count
Write
Program Address
Program Address
0025h
Write
Word Count (N–1)h
Number of words (N) loaded into the write buffer can be from 1 to 32 words.
5 to 36
Last
Load Buffer Word N
Write Buffer to Flash
Write
Write
Program Address, Word N
Sector Address
Word N
0029h
Notes:
1. Base = Base Address.
2. Last = Last cycle of write buffer program operation; depending on number of words written, the total
number of cycles may be from 6 to 37.
3. For maximum efficiency, it is recommended that the write buffer be loaded with
the highest number of words (N words) possible.
The following is a C source code example of using the write buffer program function. Refer to
the Spansion Low Level Driver User Guide (available on www.amd.com and
www.fujitsu.comm) for general information on Spansion Flash memory software develop-
ment guidelines.
/* Example: Write Buffer Programming Command
*/
/* NOTES: Write buffer programming limited to 16 words. */
/*
/*
/*
/*
All addresses to be written to the flash in
one operation must be within the same flash
page. A flash page begins at addresses
evenly divisible by 0x20.
*/
*/
*/
*/
UINT16 *src = source_of_data;
UINT16 *dst = destination_of_data;
/* address of source data
/* flash destination address
/* word count (minus 1)
/* write unlock cycle 1
/* write unlock cycle 2
*/
*/
*/
*/
*/
UINT16 wc
= words_to_program -1;
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)sector_address )
*( (UINT16 *)sector_address )
= 0x0025;
= wc;
/* write write buffer load command */
/* write word count (minus 1) */
loop:
*dst = *src; /* ALL dst MUST BE SAME PAGE */ /* write source data to destination */
dst++;
src++;
/* increment destination pointer
/* increment source pointer
*/
*/
if (wc == 0) goto confirm
wc--;
goto loop;
/* done when word count equals zero */
/* decrement word count
/* do it again
*/
*/
confirm:
*( (UINT16 *)sector_address )
/* poll for completion */
= 0x0029;
/* write confirm command
*/
/* Example: Write Buffer Abort Reset */
*( (UINT16 *)addr + 0x555 ) = 0x00AA;
*( (UINT16 *)addr + 0x2AA ) = 0x0055;
*( (UINT16 *)addr + 0x555 ) = 0x00F0;
/* write unlock cycle 1
/* write unlock cycle 2
/* write buffer abort reset
*/
*/
*/
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Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Issue
Write Buffer Load Command:
Address 555h, Data 25h
Load Word Count to Program
Program Data to Address:
SA = wc
wc = number of words – 1
Yes
Confirm command:
wc = 0?
No
SA 29h
Wait 4 µs
Write Next Word,
Decrement wc:
PA data , wc = wc – 1
No
Write Buffer
Abort Desired?
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Yes
Write to a Different
Sector Address to Cause
Write Buffer Abort
Yes
Polling Status
= Done?
No
Error?
Yes
No
Yes
Write Buffer
Abort?
No
RESET. Issue Write Buffer
Abort Reset Command
PASS. Device is in
read mode.
FAIL. Issue reset command
to return to read array mode.
Figure 8.4 Write Buffer Programming Operation
8.5.3
Sector Erase
The sector erase function erases one or more sectors in the memory array. (See Table 13.1 and
Figure 8.5) The device does not require the system to preprogram prior to erase. The Embedded
Erase algorithm automatically programs and verifies the entire memory for an all zero data pat-
tern prior to electrical erase. After a successful sector erase, all locations within the erased sector
contain FFFFh. The system is not required to provide any controls or timings during these
operations.
After the command sequence is written, a sector erase time-out of no less than tSEA occurs. Dur-
ing the time-out period, additional sector addresses and sector erase commands may be written.
Loading the sector erase buffer may be done in any sequence, and the number of sectors may be
from one sector to all sectors. The time between these additional cycles must be less than tSEA
.
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Any sector erase address and command following the exceeded time-out (tSEA) may or may not
be accepted. Any command other than Sector Erase or Erase Suspend during the time-out period
resets that bank to the read mode. The system can monitor DQ3 to determine if the sector erase
timer has timed out (see DQ3: Sector Erase Timeout State Indicator). The time-out begins from
the rising edge of the final WE# pulse in the command sequence.
When the Embedded Erase algorithm is complete, the bank returns to reading array data and ad-
dresses are no longer latched. Note that while the Embedded Erase operation is in progress, the
system can read data from the non-erasing banks. The system can determine the status of the
erase operation by reading DQ7 or DQ6/DQ2 in the erasing bank. See Write Operation Status for
information on these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other
commands are ignored. However, note that a hardware reset immediately terminates the erase
operation. If that occurs, the sector erase command sequence should be reinitiated once that
bank has returned to reading array data, to ensure data integrity.
Figure 8.5 illustrates the algorithm for the erase operation. See Erase/Program Timing for param-
eters and timing diagrams.
Software Functions and Sample Code
Table 8.14 Sector Erase
(LLD Function = lld_SectorEraseCmd)
Cycle
Description
Unlock
Operation
Write
Byte Address
Base + AAAh
Base + 554h
Base + AAAh
Base + AAAh
Base + 554h
Sector Address
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Base + 555h
Base + 2AAh
Sector Address
Data
1
2
3
4
5
6
00AAh
0055h
0080h
00AAh
0055h
0030h
Unlock
Write
Setup Command
Unlock
Write
Write
Unlock
Write
Sector Erase Command
Write
Unlimited additional sectors may be selected for erase; command(s) must be written within tSEA
.
The following is a C source code example of using the sector erase function. Refer to the
Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.
/* Example: Sector Erase Command */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0080;
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
/* write unlock cycle 1
/* write unlock cycle 2
/* write setup command
/* write additional unlock cycle 1 */
/* write additional unlock cycle 2 */
*/
*/
*/
*( (UINT16 *)sector_address )
= 0x0030;
/* write sector erase command
*/
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Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write Sector Erase Cycles:
Address 555h, Data 80h
Address 555h, Data AAh
Address 2AAh, Data 55h
Sector Address, Data 30h
Command Cycle 1
Command Cycle 2
Command Cycle 3
Specify first sector for erasure
Select
Additional
No
Sectors?
Yes
Write Additional
Sector Addresses
• Each additional cycle must be written within tSEA timeout
• Timeout resets after each additional cycle is written
• The host system may monitor DQ3 or wait tSEA to ensure
acceptance of erase commands
Yes
Last Sector
Selected?
No
• No limit on number of sectors
Poll DQ3.
DQ3 = 1?
• Commands other than Erase Suspend or selecting
additional sectors for erasure during timeout reset device
to reading array data
No
Yes
Wait 4 µs
Perform Write Operation
Status Algorithm
Status may be obtained by reading DQ7, DQ6 and/or DQ2.
Yes
Done?
No
No
DQ5 = 1?
Yes
Error condition (Exceeded Timing Limits)
PASS. Device returns
to reading array.
FAIL. Write reset command
to return to reading array.
Notes:
1. See Table 13.1 for erase command sequence.
2. See the section on DQ3 for information on the sector erase timeout.
Figure 8.5 Sector Erase Operation
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8.5.4
Chip Erase Command Sequence
Chip erase is a six-bus cycle operation as indicated by Table 13.1. These commands invoke the
Embedded Erase algorithm, which does not require the system to preprogram prior to erase. The
Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all
zero data pattern prior to electrical erase. After a successful chip erase, all locations of the chip
contain FFFFh. The system is not required to provide any controls or timings during these oper-
ations. Table 13.1 and Table 13.2 in the appendix show the address and data requirements for
the chip erase command sequence.
When the Embedded Erase algorithm is complete, that bank returns to the read mode and ad-
dresses are no longer latched. The system can determine the status of the erase operation by
using DQ7 or DQ6/DQ2. See Write Operation Status for information on these status bits.
Any commands written during the chip erase operation are ignored. However, note that a hard-
ware reset immediately terminates the erase operation. If that occurs, the chip erase command
sequence should be reinitiated once that bank has returned to reading array data, to ensure data
integrity.
Software Functions and Sample Code
Table 8.15 Chip Erase
(LLD Function = lld_ChipEraseCmd)
Cycle
Description
Unlock
Operation
Write
Byte Address
Base + AAAh
Base + 554h
Base + AAAh
Base + AAAh
Base + 554h
Base + AAAh
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Base + 555h
Base + 2AAh
Base + 555h
Data
1
2
3
4
5
6
00AAh
0055h
0080h
00AAh
0055h
0010h
Unlock
Write
Setup Command
Unlock
Write
Write
Unlock
Write
Chip Erase Command
Write
The following is a C source code example of using the chip erase function. Refer to the Span-
sion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for
general information on Spansion Flash memory software development guidelines.
/* Example: Chip Erase Command */
/* Note: Cannot be suspended
*/
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0080;
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x000 ) = 0x0010;
/* write unlock cycle 1
/* write unlock cycle 2
/* write setup command
/* write additional unlock cycle 1 */
/* write additional unlock cycle 2 */
*/
*/
*/
/* write chip erase command
*/
8.5.5
Erase Suspend/Erase Resume Commands
When the Erase Suspend command is written during the sector erase time-out, the device imme-
diately terminates the time-out period and suspends the erase operation. The Erase Suspend
command allows the system to interrupt a sector erase operation and then read data from, or
program data to, any sector not selected for erasure. The bank address is required when writing
this command. This command is valid only during the sector erase operation, including the min-
imum tSEA time-out period during the sector erase command sequence. The Erase Suspend
command is ignored if written during the chip erase operation.
When the Erase Suspend command is written after the tSEA time-out period has expired and dur-
ing the sector erase operation, the device requires a maximum of tESL (erase suspend latency) to
suspend the erase operation.
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After the erase operation has been suspended, the bank enters the erase-suspend-read mode.
The system can read data from or program data to any sector not selected for erasure. (The de-
vice erase suspends all sectors selected for erasure.) Reading at any address within erase-
suspended sectors produces status information on DQ7-DQ0. The system can use DQ7, or DQ6,
and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to
Table 8.23 for information on these status bits.
After an erase-suspended program operation is complete, the bank returns to the erase-suspend-
read mode. The system can determine the status of the program operation using the DQ7 or DQ6
status bits, just as in the standard program operation.
In the erase-suspend-read mode, the system can also issue the Autoselect command sequence.
See Write Buffer Programming and Autoselect for details.
To resume the sector erase operation, the system must write the Erase Resume command. The
bank address of the erase-suspended bank is required when writing this command. Further writes
of the Resume command are ignored. Another Erase Suspend command can be written after the
chip has resumed erasing.
Software Functions and Sample Code
Table 8.16 Erase Suspend
(LLD Function = lld_EraseSuspendCmd)
Cycle
Operation
Byte Address
Word Address
Data
1
Write
Bank Address
Bank Address
00B0h
The following is a C source code example of using the erase suspend function. Refer to the
Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.
/* Example: Erase suspend command */
*( (UINT16 *)bank_addr + 0x000 ) = 0x00B0;
/* write suspend command
*/
Table 8.17 Erase Resume
(LLD Function = lld_EraseResumeCmd)
Cycle
Operation
Byte Address
Word Address
Bank Address
Data
1
Write
Bank Address
0030h
The following is a C source code example of using the erase resume function. Refer to the
Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.
/* Example: Erase resume command */
*( (UINT16 *)bank_addr + 0x000 ) = 0x0030;
/* write resume command
*/
/* The flash needs adequate time in the resume state */
8.5.6
Program Suspend/Program Resume Commands
The Program Suspend command allows the system to interrupt an embedded programming op-
eration or a Write to Buffer programming operation so that data can read from any non-
suspended sector. When the Program Suspend command is written during a programming pro-
cess, the device halts the programming operation within tPSL (program suspend latency) and
updates the status bits. Addresses are don't-cares when writing the Program Suspend command.
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After the programming operation has been suspended, the system can read array data from any
non-suspended sector. The Program Suspend command may also be issued during a program-
ming operation while an erase is suspended. In this case, data may be read from any addresses
not in Erase Suspend or Program Suspend. If a read is needed from the Secured Silicon Sector
area, then user must use the proper command sequences to enter and exit this region.
The system may also write the Autoselect command sequence when the device is in Program Sus-
pend mode. The device allows reading Autoselect codes in the suspended sectors, since the codes
are not stored in the memory array. When the device exits the Autoselect mode, the device re-
verts to Program Suspend mode, and is ready for another valid operation. See Autoselect for more
information.
After the Program Resume command is written, the device reverts to programming. The system
can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in
the standard program operation. See Write Operation Status for more information.
The system must write the Program Resume command (address bits are don't care) to exit the
Program Suspend mode and continue the programming operation. Further writes of the Program
Resume command are ignored. Another Program Suspend command can be written after the de-
vice has resumed programming.
Software Functions and Sample Code
Table 8.18 Program Suspend
(LLD Function = lld_ProgramSuspendCmd)
Cycle
Operation
Byte Address
Word Address
Data
1
Write
Bank Address
Bank Address
00B0h
The following is a C source code example of using the program suspend function. Refer to the
Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.
/* Example: Program suspend command */
*( (UINT16 *)base_addr + 0x000 ) = 0x00B0;
/* write suspend command
*/
Table 8.19 Program Resume
(LLD Function = lld_ProgramResumeCmd)
Cycle
Operation
Byte Address
Word Address
Bank Address
Data
1
Write
Bank Address
0030h
The following is a C source code example of using the program resume function. Refer to the
Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.
/* Example: Program resume command */
*( (UINT16 *)base_addr + 0x000 ) = 0x0030;
/* write resume command
*/
8.5.7
Accelerated Program/Chip Erase
Accelerated single word programming, write buffer programming, sector erase, and chip erase
operations are enabled through the ACC function. This method is faster than the standard chip
program and erase command sequences.
The accelerated chip program and erase functions must not be used more than 10 times
per sector. In addition, accelerated chip program and erase should be performed at room tem-
perature (25°C ±10°C).
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If the system asserts VHH on this input, the device automatically enters the aforementioned Un-
lock Bypass mode and uses the higher voltage on the input to reduce the time required for
program and erase operations. The system can then use the Write Buffer Load command se-
quence provided by the Unlock Bypass mode. Note that if a Write-to-Buffer-Abort Reset is
required while in Unlock Bypass mode, the full 3-cycle RESET command sequence must be used
to reset the device. Removing VHH from the ACC input, upon completion of the embedded pro-
gram or erase operation, returns the device to normal operation.
Sectors must be unlocked prior to raising ACC to VHH
.
The ACC pin must not be at VHH for operations other than accelerated programming and ac-
celerated chip erase, or device damage may result.
The ACC pin must not be left floating or unconnected; inconsistent behavior of the device may
result.
ACC locks all sector if set to VIL. ACC should be set to VIH for all other conditions.
8.5.8
Unlock Bypass
The device features an Unlock Bypass mode to facilitate faster word programming. Once the de-
vice enters the Unlock Bypass mode, only two write cycles are required to program data, instead
of the normal four cycles.
This mode dispenses with the initial two unlock cycles required in the standard program command
sequence, resulting in faster total programming time. See the Appendix for the requirements for
the unlock bypass command sequences.
During the unlock bypass mode, only the Read, Unlock Bypass Program and Unlock Bypass Reset
commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock
bypass reset command sequence. The first cycle must contain the bank address and the data 90h.
The second cycle need only contain the data 00h. The bank then returns to the read mode.
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Software Functions and Sample Code
The following are C source code examples of using the unlock bypass entry, program, and exit
functions. Refer to the Spansion Low Level Driver User’s Guide (available soon on www.amd.com
and www.fujitsu.com) for general information on Spansion Flash “memory software development
guidelines.
Table 8.20 Unlock Bypass Entry
(LLD Function = lld_UnlockBypassEntryCmd)
Cycle
Description
Unlock
Operation
Write
Write
Write
*/
Byte Address
Base + AAAh
Base + 554h
Base + AAAh
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Data
1
2
3
00AAh
0055h
0020h
Unlock
Entry Command
/* Example: Unlock Bypass Entry Command
*( (UINT16 *)bank_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)bank_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)bank_addr + 0x555 ) = 0x0020;
/* write unlock cycle 1
/* write unlock cycle 2
/* write unlock bypass command
*/
*/
*/
/* At this point, programming only takes two write cycles.
/* Once you enter Unlock Bypass Mode, do a series of like
/* operations (programming or sector erase) and then exit
/* Unlock Bypass Mode before beginning a different type of
/* operations.
*/
*/
*/
*/
*/
Table 8.21 Unlock Bypass Program
(LLD Function = lld_UnlockBypassProgramCmd)
Cycle
Description
Operation
Write
Byte Address
Base + xxxh
Word Address
Data
00A0h
1
2
Program Setup Command
Program Command
Base +xxxh
Write
Program Address
Program Address
Program Data
/* Example: Unlock Bypass Program Command */
/* Do while in Unlock Bypass Entry Mode! */
*( (UINT16 *)bank_addr + 0x555 ) = 0x00A0;
/* write program setup command
/* write data to be programmed
*/
*/
*( (UINT16 *)pa )
= data;
*/
/* Poll until done or error.
/* If done and more to program, */
/* do above two cycles again. */
Table 8.22 Unlock Bypass Reset
(LLD Function = lld_UnlockBypassResetCmd)
Cycle
Description
Reset Cycle 1
Reset Cycle 2
Operation
Write
Byte Address
Base + xxxh
Base + xxxh
Word Address
Data
1
2
Base +xxxh
Base +xxxh
0090h
0000h
Write
/* Example: Unlock Bypass Exit Command */
*( (UINT16 *)base_addr + 0x000 ) = 0x0090;
*( (UINT16 *)base_addr + 0x000 ) = 0x0000;
8.5.9
Write Operation Status
The device provides several bits to determine the status of a program or erase operation. The
following subsections describe the function of DQ1, DQ2, DQ3, DQ5, DQ6, and DQ7.
DQ7: Data# Polling. The Data# Polling bit, DQ7, indicates to the host system whether an Em-
bedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase
Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command se-
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quence. Note that the Data# Polling is valid only for the last word being programmed in the write-
buffer-page during Write Buffer Programming. Reading Data# Polling status on any word other
than the last word to be programmed in the write-buffer-page returns false status information.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the
datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend.
When the Embedded Program algorithm is complete, the device outputs the datum programmed
to DQ7. The system must provide the program address to read valid status information on DQ7.
If a program address falls within a protected sector, Data# polling on DQ7 is active for approxi-
mately tPSP, then that bank returns to the read mode.
During the Embedded Erase Algorithm, Data# polling produces a 0 on DQ7. When the Embedded
Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling pro-
duces a 1 on DQ7. The system must provide an address within any of the sectors selected for
erasure to read valid status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected,
Data# Polling on DQ7 is active for approximately tASP, then the bank returns to the read mode.
If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7
at an address within a protected sector, the status may not be valid.
Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asyn-
chronously with DQ6-DQ0 while Output Enable (OE#) is asserted low. That is, the device may
change from providing status information to valid data on DQ7. Depending on when the system
samples the DQ7 output, it may read the status or valid data. Even if the device has completed
the program or erase operation and DQ7 has valid data, the data outputs on DQ6-DQ0 may be
still invalid. Valid data on DQ7-D00 appears on successive read cycles.
See the following for more information: Table 8.23, Write Operation Status, shows the outputs
for Data# Polling on DQ7. Figure 8.6, Write Operation Status Flowchart, shows the Data# Polling
algorithm; and Figure 12.17, Data# Polling Timings (During Embedded Algorithm), shows the
Data# Polling timing diagram.
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START
Read 1
(Note 6)
YES
Erase
Operation
Complete
DQ7=valid
data?
NO
YES
YES
Read 2
Read 1
DQ5=1?
Read3=
valid data?
NO
NO
Read 3
Read 2
Read 3
Program
Operation
Failed
YES
Write Buffer
Programming?
YES
Programming
NO
Operation?
NO
Device BUSY,
Re-Poll
(Note 3)
(Note 5)
(Note 1)
YES
(Note 1)
(Note 2)
YES
YES
DQ6
toggling?
DQ6
DEVICE
ERROR
TIMEOUT
toggling?
NO
(Note 4)
NO
YES
Read3
DQ1=1?
NO
Device BUSY,
Re-Poll
DQ2
toggling?
NO
Read 2
Read 3
Device BUSY,
Re-Poll
Erase
Device in
Erase/Suspend
Mode
Operation
Complete
Read3
DQ1=1
YES
Write Buffer
AND DQ7 ≠
Valid Data?
Operation
Failed
NO
Notes:
1) DQ6 is toggling if Read2 DQ6 does not equal Read3 DQ6.
2) DQ2 is toggling if Read2 DQ2 does not equal Read3 DQ2.
3) May be due to an attempt to program a 0 to 1. Use the RESET
command to exit operation.
Device BUSY,
Re-Poll
4) Write buffer error if DQ1 of last read =1.
5) Invalid state, use RESET command to exit operation.
6) Valid data is the data that is intended to be programmed or all 1's for
an erase operation.
7) Data polling algorithm valid for all operations except advanced sector
protection.
Figure 8.6 Write Operation Status Flowchart
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DQ6: Toggle Bit I . Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algo-
rithm is in progress or complete, or whether the device has entered the Erase Suspend mode.
Toggle Bit I may be read at any address in the same bank, and is valid after the rising edge of
the final WE# pulse in the command sequence (prior to the program or erase operation), and dur-
ing the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any ad-
dress cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6
toggles for approximately tASP [all sectors protected toggle time], then returns to reading array
data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unpro-
tected sectors, and ignores the selected sectors that are protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or
is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm
is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops tog-
gling. However, the system must also use DQ2 to determine which sectors are erasing or erase-
suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling).
If a program address falls within a protected sector, DQ6 toggles for approximately tPAP after the
program command sequence is written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embed-
ded Program Algorithm is complete.
See the following for additional information: Figure 8.6, Write Operation Status Flowchart;
Figure 12.18, Toggle Bit Timings (During Embedded Algorithm), and Table 8.23 and Table 8.24.
Toggle Bit I on DQ6 requires either OE# or CE# to be de-asserted and reasserted to show the
change in state.
DQ2: Toggle Bit II . The Toggle Bit II on DQ2, when used with DQ6, indicates whether a partic-
ular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether
that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse
in the command sequence. DQ2 toggles when the system reads at addresses within those sectors
that have been selected for erasure. But DQ2 cannot distinguish whether the sector is actively
erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively eras-
ing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus,
both status bits are required for sector and mode information. Refer to Table 8.23 to compare
outputs for DQ2 and DQ6. See the following for additional information: Figure 8.6, the DQ6: Tog-
gle Bit I section, and Figures 12.17–12.20.
Reading Toggle Bits DQ6/DQ2. Whenever the system initially begins reading toggle bit status,
it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typ-
ically, the system would note and store the value of the toggle bit after the first read. After the
second read, the system would compare the new value of the toggle bit with the first. If the toggle
bit is not toggling, the device has completed the program or erases operation. The system can
read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read
cycles, the system determines that the toggle bit is still toggling, the system also should note
whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then deter-
mine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just
as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed
the program or erases operation. If it is still toggling, the device did not complete the operation
successfully, and the system must write the reset command to return to reading array data. The
remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5
has not gone high. The system may continue to monitor the toggle bit and DQ5 through succes-
sive read cycles, determining the status as described in the previous paragraph. Alternatively, it
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may choose to perform other system tasks. In this case, the system must start at the beginning
of the algorithm when it returns to determine the status of the operation. Refer to Figure 8.6 for
more details.
DQ5: Exceeded Timing Limits. DQ5 indicates whether the program or erase time has exceeded
a specified internal pulse count limit. Under these conditions DQ5 produces a 1, indicating that
the program or erase cycle was not successfully completed. The device may output a 1 on DQ5 if
the system tries to program a 1 to a location that was previously programmed to 0 Only an erase
operation can change a 0 back to a 1. Under this condition, the device halts the operation, and
when the timing limit has been exceeded, DQ5 produces a 1. Under both these conditions, the
system must write the reset command to return to the read mode (or to the erase-suspend-read
mode if a bank was previously in the erase-suspend-program mode).
DQ3: Sector Erase Timeout State Indicator. After writing a sector erase command sequence,
the system may read DQ3 to determine whether or not erasure has begun. (The sector erase
timer does not apply to the chip erase command.) If additional sectors are selected for erasure,
the entire time-out also applies after each additional sector erase command. When the time-out
period is complete, DQ3 switches from a 0 to a 1. If the time between additional sector erase
commands from the system can be assumed to be less than tSEA, the system need not monitor
DQ3. See Sector Erase Command Sequence for more details.
After the sector erase command is written, the system should read the status of DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and
then read DQ3. If DQ3 is 1, the Embedded Erase algorithm has begun; all further commands (ex-
cept Erase Suspend) are ignored until the erase operation is complete. If DQ3 is 0 the device
accepts additional sector erase commands. To ensure the command has been accepted, the sys-
tem software should check the status of DQ3 prior to and following each sub-sequent sector erase
command. If DQ3 is high on the second status check, the last command might not have been
accepted. Table 8.23 shows the status of DQ3 relative to the other status bits.
DQ1: Write to Buffer Abort. DQ1 indicates whether a Write to Buffer operation was aborted.
Under these conditions DQ1 produces a 1. The system must issue the Write to Buffer Abort Reset
command sequence to return the device to reading array data. See Write Buffer Programming
Operation for more details.
Table 8.23 Write Operation Status
INVALID
INVALID
INVALID
INVALID
INVALID
INVALID
Program
Suspend
Mode
Reading within Program Suspended Sector
(Not
Allowed)
(Not
Allowed)
(Not
Allowed)
(Not
Allowed)
(Not
Allowed)
(Not
Allowed)
Reading within Non-Program Suspended
Sector
(Note 3)
Data
Data
Data
Data
Data
Data
BUSY State
DQ7#
DQ7#
DQ7#
Toggle
Toggle
Toggle
0
1
0
N/A
N/A
N/A
N/A
N/A
N/A
0
0
1
Write to
Buffer
(Note 5)
Exceeded Timing Limits
ABORT State
Notes:
1. DQ5 switches to 1 when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the
section on DQ5 for more information.
2. DQ7 a valid address when reading status information. Refer to the appropriate subsection for further details.
3. Data are invalid for addresses in a Program Suspended sector.
4. DQ1 indicates the Write to Buffer ABORT status during Write Buffer Programming operations.
5. The data-bar polling algorithm should be used for Write Buffer Programming operations. Note that DQ7# during Write Buffer Programming
indicates the data-bar for DQ7 data for the Last Loaded Write-buffer Address location.
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8.6 Simultaneous Read/Write
The simultaneous read/write feature allows the host system to read data from one bank of mem-
ory while programming or erasing another bank of memory. An erase operation may also be
suspended to read from or program another location within the same bank (except the sector
being erased). Figure 12.24, Back-to-Back Read/Write Cycle Timings, shows how read and write
cycles may be initiated for simultaneous operation with zero latency. Refer to the DC Character-
istics table for read-while-program and read-while-erase current specification.
8.7 Writing Commands/Command Sequences
When the device is configured for Asynchronous read, only Asynchronous write operations are
allowed, and CLK is ignored. When in the Synchronous read mode configuration, the device is able
to perform both Asynchronous and Synchronous write operations. CLK and AVD# induced address
latches are supported in the Synchronous programming mode. During a synchronous write oper-
ation, to write a command or command sequence (which includes programming data to the
device and erasing sectors of memory), the system must drive AVD# and CE# to VIL, and OE#
to VIH when providing an address to the device, and drive WE# and CE# to VIL, and OE# to VIH
when writing commands or data. During an asynchronous write operation, the system must drive
CE# and WE# to VIL and OE# to VIH when providing an address, command, and data. Addresses
are latched on the last falling edge of WE# or CE#, while data is latched on the 1st rising edge of
WE# or CE#. An erase operation can erase one sector, multiple sectors, or the entire device.
Tables 7.1–7.3 indicate the address space that each sector occupies. The device address space is
divided into sixteen banks: Banks 1 through 14 contain only 64 Kword sectors, while Banks 0 and
15 contain both 16 Kword boot sectors in addition to 64 Kword sectors. A bank address is the set
of address bits required to uniquely select a bank. Similarly, a sector address is the address bits
required to uniquely select a sector. ICC2 in DC Characteristics represents the active current spec-
ification for the write mode. AC Characteristics—Synchronous and AC Characteristics—
Asynchronous Read contain timing specification tables and timing diagrams for write operations.
8.8 Handshaking
The handshaking feature allows the host system to detect when data is ready to be read by simply
monitoring the RDY (Ready) pin, which is a dedicated output and controlled by CE#.
When the device is configured to operate in synchronous mode, and OE# is low (active), the initial
word of burst data becomes available after either the falling or rising edge of the RDY pin (de-
pending on the setting for bit 10 in the Configuration Register). It is recommended that the host
system set CR13–CR11 in the Configuration Register to the appropriate number of wait states to
ensure optimal burst mode operation (see Table 8.8, Configuration Register).
Bit 8 in the Configuration Register allows the host to specify whether RDY is active at the same
time that data is ready, or one cycle before data is ready.
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8.9 Hardware Reset
The RESET# input provides a hardware method of resetting the device to reading array data.
When RESET# is driven low for at least a period of tRP, the device immediately terminates any
operation in progress, tristates all outputs, resets the configuration register, and ignores all read/
write commands for the duration of the RESET# pulse. The device also resets the internal state
machine to reading array data.
To ensure data integrity the operation that was interrupted should be reinitiated once the device
is ready to accept another command sequence.
When RESET# is held at VSS, the device draws CMOS standby current (ICC4). If RESET# is held
at VIL, but not at VSS, the standby current is greater.
RESET# may be tied to the system reset circuitry which enables the system to read the boot-up
firmware from the Flash memory upon a system reset.
See Figures 12.5 and 12.12 for timing diagrams.
8.10 Software Reset
Software reset is part of the command set (see Table 13.1) that also returns the device to array
read mode and must be used for the following conditions:
1. to exit Autoselect mode
2. when DQ5 goes high during write status operation that indicates program or erase cycle was
not successfully completed
3. exit sector lock/unlock operation.
4. to return to erase-suspend-read mode if the device was previously in Erase Suspend mode.
5. after any aborted operations
Software Functions and Sample Code
Table 8.24 Reset
(LLD Function = lld_ResetCmd)
Cycle
Operation
Byte Address
Word Address
Data
Reset Command
Write
Base + xxxh
Base + xxxh
00F0h
Note: Base = Base Address.
The following is a C source code example of using the reset function. Refer to the Spansion
Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for general
information on Spansion Flash memory software development guidelines.
/* Example: Reset (software reset of Flash state machine) */
*( (UINT16 *)base_addr + 0x000 ) = 0x00F0;
The following are additional points to consider when using the reset command:
This command resets the banks to the read and address bits are ignored.
Reset commands are ignored once erasure has begun until the operation is complete.
Once programming begins, the device ignores reset commands until the operation is com-
plete
The reset command may be written between the cycles in a program command sequence be-
fore programming begins (prior to the third cycle). This resets the bank to which the system
was writing to the read mode.
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If the program command sequence is written to a bank that is in the Erase Suspend mode,
writing the reset command returns that bank to the erase-suspend-read mode.
The reset command may be also written during an Autoselect command sequence.
If a bank has entered the Autoselect mode while in the Erase Suspend mode, writing the reset
command returns that bank to the erase-suspend-read mode.
If DQ1 goes high during a Write Buffer Programming operation, the system must write the
Write to Buffer Abort Reset command sequence to RESET the device to reading array data.
The standard RESET command does not work during this condition.
To exit the unlock bypass mode, the system must issue a two-cycle unlock bypass reset com-
mand sequence [see command table for details].
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9 Advanced Sector Protection/Unprotection
The Advanced Sector Protection/Unprotection feature disables or enables programming or erase
operations in any or all sectors and can be implemented through software and/or hardware meth-
ods, which are independent of each other. This section describes the various methods of
protecting data stored in the memory array. An overview of these methods in shown in Figure 9.1.
Hardware Methods
Software Methods
Lock Register
(One Time Programmable)
ACC = V
IL
All sectors locked)
Persistent Method
Password Method
(
(DQ1)
(DQ2)
WP# = V
IL
(All boot
sectors locked)
64-bit Password
(One Time Protect)
1. Bit is volatile, and defaults to “1” on
reset.
PPB Lock Bit1,2,3
2. Programming to “0” locks all PPBs to
their current state.
0 = PPBs Locked
1 = PPBs Unlocked
3. Once programmed to “0”, requires
hardware reset to unlock.
Persistent
Protection Bit
(PPB)4,5
Dynamic
Protection Bit
(PPB)6,7,8
Memory Array
Sector 0
Sector 1
Sector 2
PPB 0
PPB 1
PPB 2
DYB 0
DYB 1
DYB 2
Sector N-2
Sector N-1
PPB N-2
PPB N-1
PPB N
DYB N-2
DYB N-1
DYB N
Sector N3
3. N = Highest Address Sector.
4. 0 = Sector Protected,
1 = Sector Unprotected.
6. 0 = Sector Protected,
1 = Sector Unprotected.
5. PPBs programmed individually,
but cleared collectively
7. Protect effective only if PPB Lock Bit
is unlocked and corresponding PPB
is “1” (unprotected).
8. Volatile Bits: defaults to user choice
upon power-up (see ordering
options).
Figure 9.1 Advanced Sector Protection/Unprotection
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9.1
Lock Register
As shipped from the factory, all devices default to the persistent mode when power is applied, and
all sectors are unprotected, unless otherwise chosen through the DYB ordering option. The device
programmer or host system must then choose which sector protection method to use. Program-
ming (setting to 0) any one of the following two one-time programmable, non-volatile bits locks
the part permanently in that mode:
Lock Register Persistent Protection Mode Lock Bit (DQ1)
Lock Register Password Protection Mode Lock Bit (DQ2)
Table 9.1 Lock Register
Device
DQ15-05
DQ4
DQ3
DQ2
DQ1
DQ0
Customer
Secured Silicon
Sector
Password
Protection
Mode Lock Bit
Persistent
Protection
Mode Lock Bit
S29WS256N
1
1
1
Protection Bit
DYB Lock Boot Bit
PPB One-Time
0 = sectors
power up
protected
Programmable Bit
Password
Protection
Mode Lock Bit
Persistent
Protection
Mode Lock Bit
Secured Silicon
Sector
Protection Bit
S29WS128N/
S29WS064N
0 = All PPB erase
command disabled
Undefined
1 = sectors
power up
unprotected
1 = All PPB Erase
command enabled
For programming lock register bits refer to Table 13.2.
Notes
1. If the password mode is chosen, the password must be programmed before setting the cor-
responding lock register bit.
2. After the Lock Register Bits Command Set Entry command sequence is written, reads and
writes for Bank 0 are disabled, while reads from other banks are allowed until exiting this
mode.
3. If both lock bits are selected to be programmed (to zeros) at the same time, the operation
aborts.
4. Once the Password Mode Lock Bit is programmed, the Persistent Mode Lock Bit is permanently
disabled, and no changes to the protection scheme are allowed. Similarly, if the Persistent
Mode Lock Bit is programmed, the Password Mode is permanently disabled.
After selecting a sector protection method, each sector can operate in any of the following three
states:
1. Constantly locked. The selected sectors are protected and can not be reprogrammed unless
PPB lock bit is cleared via a password, hardware reset, or power cycle.
2. Dynamically locked. The selected sectors are protected and can be altered via software
commands.
3. Unlocked. The sectors are unprotected and can be erased and/or programmed.
These states are controlled by the bit types described in Sections 9.2–9.6.
9.2 Persistent Protection Bits
The Persistent Protection Bits are unique and nonvolatile for each sector and have the same en-
durances as the Flash memory. Preprogramming and verification prior to erasure are handled by
the device, and therefore do not require system monitoring.
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Notes
1. Each PPB is individually programmed and all are erased in parallel.
2. While programming PPB for a sector, array data can be read from any other bank, except
Bank 0 (used for Data# Polling) and the bank in which sector PPB is being programmed.
3. Entry command disables reads and writes for the bank selected.
4. Reads within that bank return the PPB status for that sector.
5. Reads from other banks are allowed while writes are not allowed.
6. All Reads must be performed using the Asynchronous mode.
7. The specific sector address (A23-A14 WS256N, A22-A14 WS128N, A21-A14 WS064N) are
written at the same time as the program command.
8. If the PPB Lock Bit is set, the PPB Program or erase command does not execute and times-
out without programming or erasing the PPB.
9. There are no means for individually erasing a specific PPB and no specific sector address is
required for this operation.
10. Exit command must be issued after the execution which resets the device to read mode and
re-enables reads and writes for Bank 0
11. The programming state of the PPB for a given sector can be verified by writing a PPB
Status Read Command to the device as described by the flow chart shown in Figure 9.2.
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Enter PPB
Command Set.
Addr = BA
Program PPB Bit.
Addr = SA
Read Byte Twice
Addr = SA0
No
DQ6 =
Toggle?
Yes
No
DQ5 = 1?
Yes
Wait 500 µs
Read Byte Twice
Addr = SA0
No
Read Byte.
Addr = SA
DQ6 =
Toggle?
Yes
DQ0 =
No
'1' (Erase)
'0' (Pgm.)?
FAIL
Yes
Issue Reset
Command
PASS
Exit PPB
Command Set
Figure 9.2 PPB Program/Erase Algorithm
9.3 Dynamic Protection Bits
Dynamic Protection Bits are volatile and unique for each sector and can be individually modified.
DYBs only control the protection scheme for unprotected sectors that have their PPBs cleared
(erased to 1). By issuing the DYB Set or Clear command sequences, the DYBs are set (pro-
grammed to 0) or cleared (erased to 1), thus placing each sector in the protected or unprotected
state respectively. This feature allows software to easily protect sectors against inadvertent
changes yet does not prevent the easy removal of protection when changes are needed.
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Notes
1. The DYBs can be set (programmed to 0) or cleared (erased to 1) as often as needed.
When the parts are first shipped, the PPBs are cleared (erased to 1) and upon power up or reset,
the DYBs can be set or cleared depending upon the ordering option chosen.
2. If the option to clear the DYBs after power up is chosen, (erased to 1), then the sectorsmay
be modified depending upon the PPB state of that sector (see Table 9.2).
3. The sectors would be in the protected state If the option to set the DYBs after power up is
chosen (programmed to 0).
4. It is possible to have sectors that are persistently locked with sectors that are left in the
dynamic state.
5. The DYB Set or Clear commands for the dynamic sectors signify protected or unprotected
state of the sectors respectively. However, if there is a need to change the status of the per-
sistently locked sectors, a few more steps are required. First, the PPB Lock Bit must be
cleared by either putting the device through a power-cycle, or hardware reset. The PPBs can
then be changed to reflect the desired settings. Setting the PPB Lock Bit once again locks
the PPBs, and the device operates normally again.
6. To achieve the best protection, it is recommended to execute the PPB Lock Bit Set command
early in the boot code and protect the boot code by holding WP# = VIL. Note that the PPB
and DYB bits have the same function when ACC = VHH as they do when ACC =VIH.
9.4 Persistent Protection Bit Lock Bit
The Persistent Protection Bit Lock Bit is a global volatile bit for all sectors. When set (programmed
to 0), it locks all PPBs and when cleared (programmed to 1), allows the PPBs to be changed. There
is only one PPB Lock Bit per device.
Notes
1. No software command sequence unlocks this bit unless the device is in the password pro-
tection mode; only a hardware reset or a power-up clears this bit.
2. The PPB Lock Bit must be set (programmed to 0) only after all PPBs are configured to the
desired settings.
9.5 Password Protection Method
The Password Protection Method allows an even higher level of security than the Persistent Sector
Protection Mode by requiring a 64 bit password for unlocking the device PPB Lock Bit. In addition
to this password requirement, after power up and reset, the PPB Lock Bit is set 0 to maintain the
password mode of operation. Successful execution of the Password Unlock command by entering
the entire password clears the PPB Lock Bit, allowing for sector PPBs modifications.
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Notes
1. There is no special addressing order required for programming the password. Once the
Password is written and verified, the Password Mode Locking Bit must be set in order to pre-
vent access.
2. The Password Program Command is only capable of programming 0s. Programming a 1 after
a cell is programmed as a 0 results in a time-out with the cell as a 0.
3. The password is all 1s when shipped from the factory.
4. All 64-bit password combinations are valid as a password.
5. There is no means to verify what the password is after it is set.
6. The Password Mode Lock Bit, once set, prevents reading the 64-bit password on the data
bus and further password programming.
7. The Password Mode Lock Bit is not erasable.
8. The lower two address bits (A1–A0) are valid during the Password Read, Password Program,
and Password Unlock.
9. The exact password must be entered in order for the unlocking function to occur.
10. The Password Unlock command cannot be issued any faster than 1 µs at a time to prevent
a hacker from running through all the 64-bit combinations in an attempt to correctly match
a password.
11. Approximately 1 µs is required for unlocking the device after the valid 64-bit password is
given to the device.
12. Password verification is only allowed during the password programming operation.
13. All further commands to the password region are disabled and all operations are ignored.
14. If the password is lost after setting the Password Mode Lock Bit, there is no way to clear the
PPB Lock Bit.
15. Entry command sequence must be issued prior to any of any operation and it disables reads
and writes for Bank 0. Reads and writes for other banks excluding Bank 0 are allowed.
16. If the user attempts to program or erase a protected sector, the device ignores the com-
mand and returns to read mode.
17. A program or erase command to a protected sector enables status polling and returns to
read mode without having modified the contents of the protected sector.
18. The programming of the DYB, PPB, and PPB Lock for a given sector can be verified by writing
individual status read commands DYB Status, PPB Status, and PPB Lock Status to the
device.
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Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write
Enter Lock Register Command:
Address 555h, Data 40h
XXXh = Address don’t care
* Not on future devices
Program Lock Register Data
Address XXXh, Data A0h
Address 77h*, Data PD
Program Data (PD): See text for Lock Register
definitions
Caution: Lock register can only be progammed
once.
Wait 4 µs
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Yes
Done?
No
No
DQ5 = 1?
Yes
Error condition (Exceeded Timing Limits)
PASS. Write Lock Register
Exit Command:
FAIL. Write rest command
to return to reading array.
Address XXXh, Data 90h
Address XXXh, Data 00h
Device returns to reading array.
Figure 9.3 Lock Register Program Algorithm
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9.6 Advanced Sector Protection Software Examples
Table 9.2
Unique Device PPB Lock Bit
0 = locked
Sector PPB
0 = protected
1 = unprotected
Sector DYB
0 = protected
1 = unprotected
1 = unlocked
Sector Protection Status
Protected through PPB
Protected through PPB
Unprotected
Any Sector
Any Sector
Any Sector
Any Sector
Any Sector
Any Sector
Any Sector
Any Sector
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
x
x
1
0
x
x
0
1
Protected through DYB
Protected through PPB
Protected through PPB
Protected through DYB
Unprotected
Table 9.2 contains all possible combinations of the DYB, PPB, and PPB Lock Bit relating to the sta-
tus of the sector. In summary, if the PPB Lock Bit is locked (set to 0), no changes to the PPBs are
allowed. The PPB Lock Bit can only be unlocked (reset to 1) through a hardware reset or power
cycle. See also Figure 9.1 for an overview of the Advanced Sector Protection feature.
9.7 Hardware Data Protection Methods
The device offers two main types of data protection at the sector level via hardware control:
When WP# is at VIL, the four outermost sectors are locked (device specific).
When ACC is at VIL, all sectors are locked.
There are additional methods by which intended or accidental erasure of any sectors can be pre-
vented via hardware means. The following subsections describes these methods:
9.7.1
WP# Method
The Write Protect feature provides a hardware method of protecting the four outermost sectors.
This function is provided by the WP# pin and overrides the previously discussed Sector Protec-
tion/Unprotection method.
If the system asserts VIL on the WP# pin, the device disables program and erase functions in the
outermost boot sectors. The outermost boot sectors are the sectors containing both the lower and
upper set of sectors in a dual-boot-configured device.
If the system asserts VIH on the WP# pin, the device reverts to whether the boot sectors were
last set to be protected or unprotected. That is, sector protection or unprotection for these sectors
depends on whether they were last protected or unprotected.
Note that the WP# pin must not be left floating or unconnected as inconsistent behavior of the
device may result.
The WP# pin must be held stable during a command sequence execution
9.7.2
9.7.3
ACC Method
This method is similar to above, except it protects all sectors. Once ACC input is set to VIL, all
program and erase functions are disabled and hence all sectors are protected.
Low V
Write Inhibit
CC
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during
VCC power-up and power-down.
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The command register and all internal program/erase circuits are disabled, and the device resets
to reading array data. Subsequent writes are ignored until VCC is greater than VLKO. The system
must provide the proper signals to the control inputs to prevent unintentional writes when VCC is
greater than VLKO
.
9.7.4
9.7.5
Write Pulse Glitch Protection
Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Power-Up Write Inhibit
If WE# = CE# = RESET# = VIL and OE# = VIH during power up, the device does not accept com-
mands on the rising edge of WE#. The internal state machine is automatically reset to the read
mode on power-up.
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10 Power Conservation Modes
10.1 Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby
mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the
high impedance state, independent of the OE# input. The device enters the CMOS standby mode
when the CE# and RESET# inputs are both held at VCC ± 0.2 V. The device requires standard
access time (tCE) for read access, before it is ready to read data. If the device is deselected during
erasure or programming, the device draws active current until the operation is completed. ICC3 in
DC Characteristics represents the standby current specification
10.2 Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption while in asynchronous
mode. the device automatically enables this mode when addresses remain stable for tACC + 20
ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Stan-
dard address access timings provide new data when addresses are changed. While in sleep mode,
output data is latched and always available to the system. While in synchronous mode, the auto-
matic sleep mode is disabled. Note that a new burst operation is required to provide new data.
ICC6 in DC Characteristics represents the automatic sleep mode current specification.
10.3 Hardware RESET# Input Operation
The RESET# input provides a hardware method of resetting the device to reading array data.
When RESET# is driven low for at least a period of tRP, the device immediately terminates any
operation in progress, tristates all outputs, resets the configuration register, and ignores all read/
write commands for the duration of the RESET# pulse. The device also resets the internal state
machine to reading array data. The operation that was interrupted should be reinitiated once the
device is ready to accept another command sequence to ensure data integrity.
When RESET# is held at VSS ± 0.2 V, the device draws CMOS standby current (ICC4). If RESET#
is held at VIL but not within VSS ± 0.2 V, the standby current is greater.
RESET# may be tied to the system reset circuitry and thus, a system reset would also reset the
Flash memory, enabling the system to read the boot-up firmware from the Flash memory.
10.4 Output Disable (OE#)
When the OE# input is at VIH, output from the device is disabled. The outputs are placed in the
high impedance state.
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11 Secured Silicon Sector Flash Memory Region
The Secured Silicon Sector provides an extra Flash memory region that enables permanent part
identification through an Electronic Serial Number (ESN). The Secured Silicon Sector is 256 words
in length that consists of 128 words for factory data and 128 words for customer-secured areas.
All Secured Silicon reads outside of the 256-word address range returns invalid data. The Factory
Indicator Bit, DQ7, (at Autoselect address 03h) is used to indicate whether or not the Factory Se-
cured Silicon Sector is locked when shipped from the factory. The Customer Indicator Bit (DQ6)
is used to indicate whether or not the Customer Secured Silicon Sector is locked when shipped
from the factory.
Please note the following general conditions:
While Secured Silicon Sector access is enabled, simultaneous operations are allowed except
for Bank 0.
On power-up, or following a hardware reset, the device reverts to sending commands to the
normal address space.
Reads can be performed in the Asynchronous or Synchronous mode.
Burst mode reads within Secured Silicon Sector wrap from address FFh back to address 00h.
Reads outside of sector 0 return memory array data.
Continuous burst read past the maximum address is undefined.
Sector 0 is remapped from memory array to Secured Silicon Sector array.
Once the Secured Silicon Sector Entry Command is issued, the Secured Silicon Sector Exit
command must be issued to exit Secured Silicon Sector Mode.
The Secured Silicon Sector is not accessible when the device is executing an Embedded Pro-
gram or Embedded Erase algorithm.
Table 11.1 Addresses
Sector
Customer
Factory
Sector Size
128 words
128 words
Address Range
000080h-0000FFh
000000h-00007Fh
11.1 Factory Secured SiliconSector
The Factory Secured Silicon Sector is always protected when shipped from the factory and has
the Factory Indicator Bit (DQ7) permanently set to a 1. This prevents cloning of a factory locked
part and ensures the security of the ESN and customer code once the product is shipped to the
field.
These devices are available pre programmed with one of the following:
A random, 8 Word secure ESN only within the Factory Secured Silicon Sector
Customer code within the Customer Secured Silicon Sector through the SpansionTM program-
ming service.
Both a random, secure ESN and customer code through the Spansion programming service.
Customers may opt to have their code programmed through the Spansion programming services.
Spansion programs the customer's code, with or without the random ESN. The devices are then
shipped from the Spansion factory with the Factory Secured Silicon Sector and Customer Secured
Silicon Sector permanently locked. Contact your local representative for details on using Spansion
programming services.
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11.2 Customer Secured Silicon Sector
The Customer Secured Silicon Sector is typically shipped unprotected (DQ6 set to 0), allowing
customers to utilize that sector in any manner they choose. If the security feature is not required,
the Customer Secured Silicon Sector can be treated as an additional Flash memory space.
Please note the following:
Once the Customer Secured Silicon Sector area is protected, the Customer Indicator Bit is
permanently set to 1.
The Customer Secured Silicon Sector can be read any number of times, but can be pro-
grammed and locked only once. The Customer Secured Silicon Sector lock must be used with
caution as once locked, there is no procedure available for unlocking the Customer Secured
Silicon Sector area and none of the bits in the Customer Secured Silicon Sector memory space
can be modified in any way.
The accelerated programming (ACC) and unlock bypass functions are not available when pro-
gramming the Customer Secured Silicon Sector, but reading in Banks 1 through 15 is avail-
able.
Once the Customer Secured Silicon Sector is locked and verified, the system must write the
Exit Secured Silicon Sector Region command sequence which return the device to the mem-
ory array at sector 0.
11.3
Secured Silicon Sector Entry and Secured Silicon Sector Exit Command Sequences
The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured
Silicon Sector command sequence. The device continues to access the Secured Silicon Sector re-
gion until the system issues the four-cycle Exit Secured Silicon Sector command sequence.
See Command Definition Table [Secured Silicon Sector Command Table, Appendix
Table 13.1 for address and data requirements for both command sequences.
The Secured Silicon Sector Entry Command allows the following commands to be executed
Read customer and factory Secured Silicon areas
Program the customer Secured Silicon Sector
After the system has written the Enter Secured Silicon Sector command sequence, it may read
the Secured Silicon Sector by using the addresses normally occupied by sector SA0 within the
memory array. This mode of operation continues until the system issues the Exit Secured Silicon
Sector command sequence, or until power is removed from the device.
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Software Functions and Sample Code
The following are C functions and source code examples of using the Secured Silicon Sector
Entry, Program, and exit commands. Refer to the Spansion Low Level Driver User’s Guide
(available soon on www.amd.com and www.fujitsu.com) for general information on Spansion
Flash memory software development guidelines.
Table 11.2 Secured Silicon Sector Entry
(LLD Function = lld_SecSiSectorEntryCmd)
Cycle
Operation
Write
Byte Address
Base + AAAh
Base + 554h
Base + AAAh
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Data
Unlock Cycle 1
Unlock Cycle 2
00AAh
0055h
0088h
Write
Entry Cycle
Write
Note: Base = Base Address.
/* Example: SecSi Sector Entry Command */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0088;
/* write unlock cycle 1
/* write unlock cycle 2
/* write Secsi Sector Entry Cmd
*/
*/
*/
Table 11.3 Secured Silicon Sector Program
(LLD Function = lld_ProgramCmd)
Cycle
Operation
Write
Byte Address
Base + AAAh
Base + 554h
Base + AAAh
Word Address
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Word Address
Data
00AAh
Unlock Cycle 1
Unlock Cycle 2
Program Setup
Write
0055h
Write
00A0h
Program
Write
Data Word
Note: Base = Base Address.
/* Once in the SecSi Sector mode, you program */
/* words using the programming algorithm. */
Table 11.4 Secured Silicon Sector Exit
(LLD Function = lld_SecSiSectorExitCmd)
Cycle
Operation
Write
Byte Address
Base + AAAh
Base + 554h
Base + AAAh
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Data
Unlock Cycle 1
Unlock Cycle 2
00AAh
0055h
0090h
Write
Exit Cycle
Write
Note: Base = Base Address.
/* Example: SecSi Sector Exit Command */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0090;
*( (UINT16 *)base_addr + 0x000 ) = 0x0000;
/* write unlock cycle 1
/* write unlock cycle 2
/* write SecSi Sector Exit cycle 3 */
/* write SecSi Sector Exit cycle 4 */
*/
*/
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12 Electrical Specifications
12.1 Absolute Maximum Ratings
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C
Voltage with Respect to Ground:
All Inputs and I/Os except
as noted below (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VIO + 0.5 V
VCC (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +2.5 V
VIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +2.5 V
ACC (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +9.5 V
Output Short Circuit Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Notes:
1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs or I/Os may undershoot V to –2.0 V
SS
for periods of up to 20 ns. See Figure 12.1. Maximum DC voltage on input or I/Os is V + 0.5 V. During voltage
CC
transitions outputs may overshoot to V + 2.0 V for periods up to 20 ns. See Figure 12.2.
CC
2. Minimum DC input voltage on pin ACC is -0.5V. During voltage transitions, ACC may overshoot V to –2.0 V for periods
SS
of up to 20 ns. See Figure 12.1. Maximum DC voltage on pin ACC is +9.5 V, which may overshoot to 10.5 V for periods
up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than
one second.
4. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these or any other conditions above those indicated in the
operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for
extended periods may affect device reliability.
20 ns
20 ns
20 ns
VCC
+0.8 V
+2.0 V
VCC
+0.5 V
–0.5 V
–2.0 V
1.0 V
20 ns
20 ns
20 ns
Figure 12.1 Maximum Negative
Overshoot Waveform
Figure 12.2 Maximum Positive
Overshoot Waveform
Note: The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document is
Preliminary for the S29W256N.
12.2 Operating Ranges
Wireless (W) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25°C to +85°C
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Supply Voltages
VCC Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+1.70 V to +1.95 V
VIO Supply Voltages: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.70 V to +1.95 V
(Contact local sales office for VIO = 1.35 to +1.70 V.)
Note: Operating ranges define those limits between which the device functionality is guaranteed.
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12.3 Test Conditions
Device
Under
Test
C
L
Figure 12.3 Test Setup
Table 12.1 Test Specifications
Test Condition
Output Load Capacitance, CL
All Speed Options
Unit
30
pF
(including jig capacitance)
3.0 @ 54, 66 MHz
2.5 @ 80 MHz
Input Rise and Fall Times
ns
Input Pulse Levels
0.0–VIO
VIO/2
V
V
V
Input timing measurement reference levels
Output timing measurement reference levels
VIO/2
Note: The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document
is Preliminary for the S29W256N.
12.4 Key to Switching Waveforms
Waveform
Inputs
Outputs
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State
(High Z)
Note: The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document
is Preliminary for the S29W256N.
12.5 Switching Waveforms
VIO
All Inputs and Outputs
VIO/2
VIO/2
Input
Measurement Level
Output
0.0 V
Figure 12.4 Input Waveforms and Measurement Levels
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12.6 V
Power-up
CC
Parameter
Description
Test Setup
Speed
Unit
tVCS
VCC Setup Time
Min
1
ms
Notes:
1.
V
>= V - 100mV and V ramp rate is > 1V / 100µs
IO CC
CC
2.
V
ramp rate <1V / 100µs, a Hardware Reset is required.
CC
3. The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document
is Preliminary for the S29W256N.
tVCS
VCC
VIO
RESET#
Figure 12.5
V
Power-up Diagram
CC
February 17, 2005 S75WS-N-00_A0
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67
A d v a n c e I n f o r m a t i o n
12.7 DC Characteristics
(CMOS Compatible)
Parameter
Description (Notes)
Test Conditions (Notes 1, 2, 9)
= V to V , V = V max
Min
Typ
Max
±1
±1
54
60
66
48
54
60
42
48
54
36
42
48
30
36
18
4
Unit
µA
I
Input Load Current
V
V
LI
IN
SS
CC
CC
CC
I
Output Leakage Current (3)
= V to V , V = V max
µA
LO
OUT
SS
CC
CC
CC
54 MHz
66 MHz
80 MHz
54 MHz
66 MHz
80 MHz
54 MHz
66 MHz
80 MHz
54 MHz
66 MHz
80 MHz
27
28
30
28
30
32
29
32
34
32
35
38
20
27
13
3
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
CE# = V , OE# = V , WE#
IL
IH
= V , burst length = 8
IH
CE# = V , OE# = V , WE#
IL
IH
= V , burst length = 16
IH
I
V
Active burst Read Current
CCB
CC
CE# = V , OE# = V , WE#
IL
IH
= V , burst length = 32
IH
CE# = V , OE# = V , WE#
IL
IH
= V , burst length =
IH
Continuous
I
V
V
Non-active Output
OE# = V
IH
IO1
IO
10 MHz
5 MHz
1 MHz
mA
mA
mA
µA
Active Asynchronous
Read Current (4)
CE# = V , OE# = V , WE#
CC
IL
IH
I
CC1
= V
IH
V
1
5
ACC
CE# = V , OE# = V , ACC
IL
IH
I
I
V
V
Active Write Current (5)
Standby Current (6, 7)
CC2
CC3
CC
CC
= V
IH
V
19
1
52.5
5
mA
µA
CC
V
ACC
CE# = RESET# =
± 0.2 V
V
CC
V
20
70
40
150
µA
CC
I
I
I
V
V
Reset Current (7)
Active Current
RESET# = V CLK = V
IL
µA
CC4
CC5
CC6
CC
CC
IL,
CE# = V , OE# = V , ACC = V
@
IL
IH
IH
50
60
mA
5 MHz
(Read While Write) (7)
V
Sleep Current (7)
CE# = V , OE# = V
IL
2
6
40
20
µA
mA
mA
V
CC
IH
V
CE# = V , OE# = V
IL
ACC
IH,
I
Accelerated Program Current (8)
ACC
V
= 9.5 V
ACC
V
14
20
CC
V
Input Low Voltage
V
V
= 1.8 V
= 1.8 V
–0.5
0.4
IL
IO
V
Input High Voltage
V
V
– 0.4
V
+ 0.4
V
IH
IO
IO
IO
V
Output Low Voltage
I
I
= 100 µA, V = V
= V
IO
0.1
V
OL
OH
HH
OL
OH
CC
CC min
V
V
Output High Voltage
Voltage for Accelerated Program
= –100 µA, V = V
= V
IO
– 0.1
8.5
1.0
V
CC
CC min
IO
9.5
1.4
V
V
Low V Lock-out Voltage
V
LKO
CC
Notes:
1. Maximum I specifications are tested with V = V max.
CC
CC
CC
2.
3. CE# must be set high when measuring the RDY pin.
4. The I current listed is typically less than 3 mA/MHz, with OE# at V
V
= V .
CC IO
.
IH
CC
5.
I
active while Embedded Erase or Embedded Program is in progress.
CC
6. Device enters automatic sleep mode when addresses are stable for t
+ 20 ns. Typical sleep mode current is equal to
ACC
I
.
CC3
7.
V
= V ± 0.2 V and V > –0.1 V.
IH CC IL
8. Total current during accelerated programming is the sum of V
and V currents.
ACC
CC
9.
V
= V
on ACC input.
HH
ACC
10. The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document
is Preliminary for the S29W256N.
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A d v a n c e I n f o r m a t i o n
12.8 AC Characteristics
12.8.1 CLK Characterization
Parameter
fCLK
Description
CLK Frequency
54 MHz
54
66 MHz
66
80 MHz
80
Unit
MHz
ns
Max
Min
tCLK
tCH
CLK Period
18.5
15.1
12.5
CLK High Time
CLK Low Time
CLK Rise Time
CLK Fall Time
Min
7.4
3
6.1
3
5.0
2.5
ns
ns
tCL
tCR
Max
tCF
Note: The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document
is Preliminary for the S29W256N.
t
CLK
t
t
CL
CH
CLK
t
t
CF
CR
Figure 12.6 CLK Characterization
12.8.2 Synchronous/Burst Read
Parameter
JEDEC
Standard
tIACC
tBACC
tACS
tACH
tBDH
tCR
Description
54 MHz
66 MHz
80
80 MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Latency
Max
Burst Access Time Valid Clock to Output Delay Max
13.5
5
11.2
9
Address Setup Time to CLK (Note 1)
Address Hold Time from CLK (Note 1)
Data Hold Time from Next Clock Cycle
Chip Enable to RDY Valid
Min
Min
Min
Max
Max
Max
Max
Min
Min
Max
Min
Min
Min
Max
4
6
3
7
4
13.5
13.5
11.2
9
tOE
Output Enable to Output Valid
Chip Enable to High Z (Note 2)
Output Enable to High Z (Note 2)
CE# Setup Time to CLK
11.2
tCEZ
10
10
4
tOEZ
tCES
tRDYS
tRACC
tCAS
tAVC
RDY Setup Time to CLK
5
4
3.5
9
Ready Access Time from CLK
CE# Setup Time to AVD#
AVD# Low to CLK
13.5
11.2
0
4
tAVD
tAOE
AVD# Pulse
8
AVD Low to OE# Low
38.4
Notes:
1. Addresses are latched on the first rising edge of CLK.
2. Not 100% tested.
3. The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document
is Preliminary for the S29W256N.
February 17, 2005 S75WS-N-00_A0
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69
A d v a n c e I n f o r m a t i o n
12.8.3 Timing Diagrams
5 cycles for initial access shown.
18.5 ns typ. (54 MHz)
tCEZ
tCES
CE#
1
2
3
4
5
6
7
CLK
tAVC
AVD#
tAVD
tACS
Addresses
Data (n)
Aa
tBACC
tACH
Hi-Z
tIACC
Da
Da + 1
Da + 2
Da + n
tOEZ
Da + 3
tAOE
tBDH
OE#
tRACC
tOE
Hi-Z
Hi-Z
RDY (n)
tCR
tRDYS
Hi-Z
Hi-Z
Data (n + 1)
RDY (n + 1)
Da
Da + 1
Da + 2
Da + n
Da + 2
Hi-Z
Hi-Z
Hi-Z
Data (n + 2)
RDY (n + 2)
Da
Da + 1
Da + 1
Da + n
Da + 1
Hi-Z
Hi-Z
Hi-Z
Data (n + 3)
Da
Da
Da
Da + n
Da
Hi-Z
RDY (n + 3)
Notes:
1. Figure shows total number of wait states set to five cycles. The total number of wait states can be programmed from two
cycles to seven cycles.
2. If any burst address occurs at address + 1 , address + 2, or address + 3, additional clock delay cycles are inserted, and
are indicated by RDY.
3. The device is in synchronous mode.
Figure 12.7 CLK Synchronous Burst Mode Read
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A d v a n c e I n f o r m a t i o n
7 cycles for initial access shown.
tCES
CE#
CLK
1
2
3
4
5
6
7
tAVC
AVD#
tAVD
tACS
Ac
Addresses
Data
tBACC
tACH
tIACC
DC
DD
DE
DF
D8
DB
tBDH
tAOE
OE#
RDY
tCR
tRACC
tRACC
tOE
Hi-Z
tRDYS
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from
two cycles to seven cycles.
2. If any burst address occurs at address + 1 , address + 2, or address + 3, additional clock delay cycles are inserted, and
are indicated by RDY.
3. The device is in synchronous mode with wrap around.
4. D8–DF in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting
address in figure is the 4th address in range (0-F).
Figure 12.8 8-word Linear Burst with Wrap Around
7 cycles for initial access shown.
tCES
CE#
1
2
3
4
5
6
7
CLK
tAVC
AVD#
tAVD
tACS
Ac
Addresses
Data
tBACC
tACH
tIACC
DC
DD
DE
DF
D10
D13
tAOE
tBDH
OE#
RDY
tCR
tRACC
tRACC
tOE
Hi-Z
tRDYS
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from
two cycles to seven cycles. Clock is set for active rising edge.
2. If any burst address occurs at address + 1 , address + 2, or address + 3, additional clock delay cycles are inserted, and
are indicated by RDY.
3. The device is in asynchronous mode with out wrap around.
4. DC–D13 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest.
Starting address in figure is the 1st address in range (c-13).
Figure 12.9 8-word Linear Burst without Wrap Around
February 17, 2005 S75WS-N-00_A0
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71
A d v a n c e I n f o r m a t i o n
tCEZ
6 wait cycles for initial access shown.
tCES
CE#
CLK
1
2
3
4
5
6
tAVC
AVD#
tAVD
tACS
Aa
Addresses
Data
tBACC
tACH
Hi-Z
tIACC
Da
Da+1
Da+2
Da+3
Da + n
tBDH
tAOE
tOEZ
tRACC
OE#
RDY
tCR
tOE
Hi-Z
Hi-Z
tRDYS
Notes:
1. Figure assumes 6 wait states for initial access and synchronous read.
2. The Set Configuration Register command sequence has been written with CR8=0; device outputs RDY one cycle before
valid data.
Figure 12.10 Linear Burst with RDY Set One Cycle Before Data
12.8.4 AC Characteristics—Asynchronous Read
Parameter
Description
54 MHz 66 MHz 80 MHz Unit
JEDEC Standard
tCE
tACC
Access Time from CE# Low
Max
Max
Min
Min
Min
Max
Min
Min
Max
Min
80
80
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Asynchronous Access Time
tAVDP
tAAVDS
tAAVDH
tOE
AVD# Low Time
Address Setup Time to Rising Edge of AVD#
Address Hold Time from Rising Edge of AVD#
Output Enable to Output Valid
4
7
6
13.5
0
Read
Output Enable Hold Time
Data# Polling
tOEH
10
10
0
tOEZ
tCAS
Output Enable to High Z (see Note)
CE# Setup Time to AVD#
Notes:
1. Not 100% tested.
2. The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document
is Preliminary for the S29W256N.
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A d v a n c e I n f o r m a t i o n
CE#
tOE
OE#
tOEH
WE#
Data
tCE
tOEZ
Valid RD
tACC
RA
Addresses
AVD#
tAAVDH
tCAS
tAVDP
tAAVDS
Note: RA = Read Address, RD = Read Data.
Figure 12.11 Asynchronous Mode Read
12.8.5 Hardware Reset (RESET#)
Parameter
JEDEC
Std.
Description
All Speed Options
Unit
µs
tRP
tRH
RESET# Pulse Width
Reset High Time Before Read (See Note)
Min
Min
30
200
ns
Notes:
1. Not 100% tested.
2. The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document
is Preliminary for the S29W256N.
CE#, OE#
tRH
RESET#
tRP
Figure 12.12 Reset Timings
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73
A d v a n c e I n f o r m a t i o n
12.8.6 Erase/Program Timing
Parameter
Description
54 MHz 66 MHz 80 MHz Unit
JEDEC Standard
t
t
Write Cycle Time (Note 1)
Min
80
5
ns
ns
ns
AVAV
WC
Synchronous
Asynchronous
Synchronous
Asynchronous
t
t
Address Setup Time (Notes 2, 3)
Address Hold Time (Notes 2, 3)
Min
Min
AVWL
AS
0
9
t
t
ns
WLAX
AH
20
8
t
AVD# Low Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Max
Max
Max
Max
Typ
Typ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
µs
AVDP
t
t
t
Data Setup Time
45
20
DVWH
DS
DH
t
Data Hold Time
0
0
WHDX
t
t
Read Recovery Time Before Write
CE# Setup Time to AVD#
CE# Hold Time
GHWL
GHWL
t
0
CAS
t
t
0
WHEH
WLWH
WHWL
CH
t
t
t
Write Pulse Width
30
20
0
WP
t
Write Pulse Width High
WPH
t
Latency Between Read and Write Operations
SR/W
t
V
V
V
Rise and Fall Time
500
1
VID
ACC
ACC
t
Setup Time (During Accelerated Programming)
VIDS
t
Setup Time
CC
50
5
VCS
t
t
CE# Setup Time to WE#
ELWL
CS
t
AVD# Setup Time to WE#
5
AVSW
AVHW
t
AVD# Hold Time to WE#
5
t
AVD# Setup Time to CLK
5
AVSC
AVHC
t
AVD# Hold Time to CLK
5
t
Clock Setup Time to WE#
5
CSW
t
Noise Pulse Margin on WE#
Sector Erase Accept Time-out
Erase Suspend Latency
3
WEP
t
50
20
20
100
1
SEA
t
ESL
PSL
ASP
t
Program Suspend Latency
t
Toggle Time During Sector Protection
Toggle Time During Programming Within a Protected Sector
t
PSP
Notes:
1. Not 100% tested.
2. Asynchronous read mode allows Asynchronous program operation only. Synchronous read mode allows both
Asynchronous and Synchronous program operation.
3. In asynchronous program operation timing, addresses are latched on the falling edge of WE#. In synchronous program
operation timing, addresses are latched on the rising edge of CLK.
4. See the Erase and Programming Performance section for more information.
5. Does not include the preprogramming time.
6. The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document
is Preliminary for the S29W256N.
74
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Erase Command Sequence (last two cycles)
Read Status Data
V
IH
CLK
V
IL
tAVDP
AVD#
tAH
tAS
SA
VA
VA
Addresses
Data
2AAh
555h for
chip erase
10h for
chip erase
In
Complete
55h
30h
Progress
tDS
tDH
CE#
tCH
OE#
WE#
tWP
tWHWH2
tCS
tWPH
tWC
tVCS
VCC
Figure 12.13 Chip/Sector Erase Operation Timings
February 17, 2005 S75WS-N-00_A0
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75
A d v a n c e I n f o r m a t i o n
Program Command Sequence (last two cycles)
Read Status Data
V
IH
CLK
AVD
V
IL
tAVSW
tAVHW
tAVDP
tAS
tAH
Addresses
Data
555h
PA
VA
VA
In
Progress
A0h
tDS
Complete
PD
tCAS
tDH
CE#
tCH
OE#
WE#
tWP
tWHWH1
tCS
tWPH
tWC
tVCS
VCC
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. In progress and complete refer to status of program operation.
3. A23–A14 for the WS256N (A22–A14 for the WS128N, A21–A14 for the WS064N) are don’t care during command
sequence unlock cycles.
4. CLK can be either V or V
.
IH
IL
5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Configuration Register.
Figure 12.14 Asynchronous Program Operation Timings
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A d v a n c e I n f o r m a t i o n
Program Command Sequence (last two cycles)
Read Status Data
tAVCH
CLK
tAS
tAH
tAVSC
AVD#
tAVDP
Addresses
Data
PA
VA
VA
555h
In
Progress
Complete
A0h
PD
tDS
tDH
tCAS
CE#
tCH
OE#
WE#
tCSW
tWP
tWHWH1
tWPH
tWC
tVCS
VCC
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. In progress and complete refer to status of program operation.
3. A23–A14 for the WS256N (A22–A14 for the WS128N, A21–A14 for the WS064N) are don’t care during command
sequence unlock cycles.
4. Addresses are latched on the first rising edge of CLK.
5. Either CE# or AVD# is required to go from low to high in between programming command sequences.
6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register.
The Configuration Register must be set to the Synchronous Read Mode.
Figure 12.15 Synchronous Program Operation Timings
CE#
AVD#
WE#
Addresses
Data
PA
Don't Care
A0h
Don't Care
PD
Don't Care
OE#
ACC
tVIDS
V
V
ID
tVID
or V
IH
IL
Note: Use setup and hold times from conventional program operation.
Figure 12.16 Accelerated Unlock Bypass Programming Timing
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77
A d v a n c e I n f o r m a t i o n
AVD#
CE#
tCEZ
tCE
tOEZ
tCH
tOE
OE#
WE#
tOEH
tACC
VA
High Z
High Z
Addresses
VA
Status Data
Status Data
Data
Notes:
1. Status reads in figure are shown as asynchronous.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is
completeData# Polling outputs true data.
Figure 12.17 Data# Polling Timings (During Embedded Algorithm)
AVD#
tCEZ
tCE
CE#
tOEZ
tCH
tOE
OE#
WE#
tOEH
tACC
VA
High Z
Addresses
VA
High Z
Data
Status Data
Status Data
Notes:
1. Status reads in figure are shown as asynchronous.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is
complete, .
Figure 12.18 Toggle Bit Timings (During Embedded Algorithm)
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A d v a n c e I n f o r m a t i o n
CE#
CLK
AVD#
Addresses
OE#
VA
VA
tIACC
tIACC
Data
Status Data
Status Data
RDY
Notes:
1. The timings are similar to synchronous read timings.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is
complete, .
3. RDY is active with data (D8 = 1 in the Configuration Register). When D8 = 0 in the Configuration Register, RDY is active
one clock cycle before data.
Figure 12.19 Synchronous Data Polling Timings/Toggle Bit Timings
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to
toggle DQ2 and DQ6
Figure 12.20 DQ2 vs. DQ6
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79
A d v a n c e I n f o r m a t i o n
Address boundary occurs every 128 words, beginning at address
00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.
C124
C125
7D
C126
7E
C127
7F
C127
7F
C128
80
C129
81
C130
82
C131
83
CLK
7C
Address (hex)
(stays high)
AVD#
tRACC
tRACC
RDY(1)
latency
tRACC
tRACC
RDY(2)
Data
latency
D124
D125
D126
D127
D128
D129
D130
OE#,
CE#
(stays low)
Notes:
1. RDY(1) active with data (D8 = 1 in the Configuration Register).
2. RDY(2) active one clock cycle before data (D8 = 0 in the Configuration Register).
3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60.
4. Figure shows the device not crossing a bank in the process of performing an erase or program.
5. RDY does not go low and no additional wait states are required if the Burst frequency is <=66 MHz and the Boundary
Crossing bit (D14) in the Configuration Register is set to 0
Figure 12.21 Latency with Boundary Crossing when Frequency > 66 MHz
80
S75WS256Nxx Based MCPs
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A d v a n c e I n f o r m a t i o n
Address boundary occurs every 128 words, beginning at address
00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.
C124
C125
7D
C126
7E
C127
7F
C127
7F
CLK
7C
Address (hex)
(stays high)
AVD#
tRACC
tRACC
RDY(1)
latency
tRACC
tRACC
RDY(2)
Data
latency
D124
D125
D126
D127
Read Status
OE#,
CE#
(stays low)
Notes:
1. RDY(1) active with data (D8 = 1 in the Configuration Register).
2. RDY(2) active one clock cycle before data (D8 = 0 in the Configuration Register).
3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60.
4. Figure shows the device crossing a bank in the process of performing an erase or program.
5. RDY does not go low and no additional wait states are required if the Burst frequency is < 66 MHz and the Boundary
Crossing bit (D14) in the Configuration Register is set to 0.
Figure 12.22 Latency with Boundary Crossing into Program/Erase Bank
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A d v a n c e I n f o r m a t i o n
Data
D0
D1
Rising edge of next clock cycle
following last wait state triggers
next burst data
AVD#
OE#
total number of clock cycles
following addresses being latched
1
2
0
3
1
4
5
6
4
7
5
CLK
2
3
number of clock cycles
programmed
Wait State Configuration Register Setup:
D13, D12, D11 = 111 ⇒ Reserved
D13, D12, D11 = 110 ⇒ Reserved
D13, D12, D11 = 101 ⇒ 5 programmed, 7 total
D13, D12, D11 = 100 ⇒ 4 programmed, 6 total
D13, D12, D11 = 011 ⇒ 3 programmed, 5 total
D13, D12, D11 = 010 ⇒ 2 programmed, 4 total
D13, D12, D11 = 001 ⇒ 1 programmed, 3 total
D13, D12, D11 = 000 ⇒ 0 programmed, 2 total
Note: 6.Figure assumes address D0 is not at an address boundary, and wait state is set to 101
Figure 12.23 Example of Wait State Insertion
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A d v a n c e I n f o r m a t i o n
Last Cycle in
Program or
Sector Erase
Read status (at least two cycles) in same bank
and/or array data from other bank
Begin another
write or program
command sequence
Command Sequence
tWC
tRC
tRC
tWC
CE#
OE#
tOE
tGHWL
tOEH
WE#
Data
tWPH
tOEZ
tWP
tDS
tACC
tOEH
tDH
PD/30h
RD
RD
AAh
tSR/W
RA
Addresses
AVD#
PA/SA
tAS
RA
555h
tAH
Note: Breakpoints in waveforms indicate that system may alternately read array data from the non-busy bank while check-
ing the status of the program or erase operation in the busy bank. The system should read status twice to ensure
valid information.
Figure 12.24 Back-to-Back Read/Write Cycle Timings
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A d v a n c e I n f o r m a t i o n
12.8.7 Erase and Programming Performance
Parameter
Typ (Note 1)
0.6
Max (Note 2)
Unit
Comments
64 Kword
16 Kword
VCC
VCC
3.5
2
Sector Erase Time
s
<0.15
153.6 (WS256N)
77.4 (WS128N)
39.3 (WS064N)
308 (WS256N)
154 (WS128N)
78 (WS064N)
Excludes 00h
programming prior
to erasure (Note 4)
VCC
Chip Erase Time
s
130.6 (WS256N)
65.8 (WS128N)
33.4 (WS064N)
262 (WS256N)
132 (WS128N)
66 (WS064N)
ACC
VCC
ACC
VCC
ACC
VCC
ACC
40
24
400
240
94
Single Word Programming Time
(Note 8)
µs
µs
µs
9.4
6
Effective Word Programming Time
utilizing Program Write Buffer
60
300
192
3000
1920
Total 32-Word Buffer Programming
Time
157.3 (WS256N)
78.6 (WS128N)
39.3 (WS064N)
314.6 (WS256N)
157.3 (WS128N)
78.6 (WS064N)
VCC
Excludes system
level overhead
(Note 5)
Chip Programming Time (Note 3)
s
100.7 (WS256N)
50.3 (WS128N)
25.2 (WS064N)
201.3 (WS256N)
100.7 (WS128N)
50.3 (WS064N)
ACC
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 1.8 V V , 10,000 cycles; checkerboard data
CC
pattern.
2. Under worst case conditions of 90°C, V = 1.70 V, 100,000 cycles.
CC
3. Typical chip programming time is considerably less than the maximum chip programming time listed, and is based on
utilizing the Write Buffer.
4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command.
See the Appendix for further information about command definitions.
6. Contact the local sales office for minimum cycling endurance values in specific applications and operating conditions.
7. Refer to Application Note Erase Suspend/Resume Timing for more details.
8. Word programming specification is based upon a single word programming operation not utilizing the write buffer.
9. The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document
is Preliminary for the S29W256N.
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12.8.8 BGA Ball Capacitance
Parameter Symbol
Parameter Description
Input Capacitance
Test Set up
Typ.
5.3
5.8
6.3
Max
6.3
6.8
7.3
Unit
pF
C
V
= 0
= 0
= 0
IN
IN
C
Output Capacitance
Control Pin Capacitance
V
pF
OUT
OUT
C
V
pF
IN2
IN
Notes:
1. Sampled, not 100% tested.
2. Test conditions T = 25°C; f = 1.0 MHz.
A
3. The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document
is Preliminary for the S29W256N.
February 17, 2005 S75WS-N-00_A0
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A d v a n c e I n f o r m a t i o n
13 Appendix
This section contains information relating to software control or interfacing with the Flash device.
For additional information and assistance regarding software, see the Additional Resources on
page 19, or explore the Web at www.amd.com and www.fujitsu.com.
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Table 13.1 Memory Array Commands
Bus Cycles (Notes 1–5)
Third Fourth
Addr Addr Data
First
Addr
Second
Fifth
Addr
Sixth
Addr Data
Command Sequence
(Notes)
Data
RD
Addr
Data
Data
Data
Asynchronous Read (6)
Reset (7)
Manufacturer ID
1
1
4
6
RA
XXX
555
555
F0
AA
2AA
2AA
55
55
[BA]555
[BA]555
90
90
[BA]X00 0001
[BA]X01 227E
Device ID (9)
AA
BA+X0E
PA
Data
PD
BA+X0F 2200
Indicator Bits (10)
4
555
AA
2AA
55
[BA]555
90
[BA]X03
Data
Program
4
6
1
3
6
6
1
1
4
4
1
3
2
1
555
555
SA
555
555
555
BA
AA
AA
29
AA
AA
AA
B0
30
AA
AA
98
AA
A0
98
2AA
2AA
55
55
555
PA
A0
25
PA
PA
PD
Write to Buffer (11)
Program Buffer to Flash
Write to Buffer Abort Reset (12)
Chip Erase
WC
WBL
PD
2AA
2AA
2AA
55
55
55
555
555
555
F0
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
Sector Erase
Erase/Program Suspend (13)
Erase/Program Resume (14)
Set Configuration Register (18)
Read Configuration Register
CFI Query (15)
BA
555
555
[BA]555
555
XXX
XXX
2AA
2AA
55
55
555
555
D0
C6
X00
X00
CR
CR
Entry
Program (16)
2AA
PA
55
PD
555
20
CFI (16)
Reset
2
XXX
90
XXX
00
Entry
3
4
1
555
555
00
AA
AA
Data
2AA
2AA
55
55
555
555
88
A0
Program (17)
Read (17)
PA
PD
00
Exit (17)
4
555
AA
2AA
55
555
90
XXX
Legend:
X = Don’t care.
RA = Read Address.
RD = Read Data.
PA = Program Address. Addresses latch on the rising edge of the
AVD# pulse or active edge of CLK, whichever occurs first.
SA = Sector Address. WS256N = A23–A14; WS128N = A22–A14;
WS064N = A21–A14.
BA = Bank Address. WS256N = A23–A20; WS128N = A22–A20;
WS064N = A21–A18.
CR = Configuration Register data bits D15–D0.
WBL = Write Buffer Location. Address must be within the same write
buffer page as PA.
PD = Program Data. Data latches on the rising edge of WE# or CE#
pulse, whichever occurs first.
WC = Word Count. Number of write buffer locations to load minus 1.
Notes:
1. See Table 8.1 for description of bus operations.
2. All values are in hexadecimal.
11. Total number of cycles in the command sequence is determined
by the number of words written to the write buffer.
12. Command sequence resets device for next command after write-
to-buffer operation.
13. System may read and program in non-erasing sectors, or enter
the autoselect mode, when in the Erase Suspend mode. The
Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
14. Erase Resume command is valid only during the Erase Suspend
mode, and requires the bank address.
15. Command is valid when device is ready to read array data or
when device is in autoselect mode. Address equals 55h on all
future devices, but 555h for WS256N/128N/064N.
3. Shaded cells indicate read cycles.
4. Address and data bits not specified in table, legend, or notes are
don’t cares (each hex digit implies 4 bits of data).
5. Writing incorrect address and data values or writing them in the
improper sequence may place the device in an unknown state.
The system must write the reset command to return the device
to reading array data.
6. No unlock or command cycles required when bank is reading
array data.
7. Reset command is required to return to reading array data (or to
the erase-suspend-read mode if previously in Erase Suspend)
when a bank is in the autoselect mode, or if DQ5 goes high
(while the bank is providing status information) or performing
sector lock/unlock.
16. Requires Entry command sequence prior to execution. Unlock
Bypass Reset command is required to return to reading array
data.
17. Requires Entry command sequence prior to execution. Secured
Silicon Sector Exit Reset command is required to exit this mode;
device may otherwise be placed in an unknown state.
8. The system must provide the bank address. See Autoselect
section for more information.
9. Data in cycle 5 is 2230 (WS256N), 2232 (WS064N), or 2231
(WS128N).
18. Requires reset command to configure the Configuration Register.
10. See Table 8.9 for indicator bit values.
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A d v a n c e I n f o r m a t i o n
Table 13.2 Sector Protection Commands
Bus Cycles (Notes 1–4)
First
Second
Third
Fourth
Fifth
Sixth
Seventh
Command Sequence
(Notes)
Addr
Data
AA
Addr
Data
55
Addr
Data
Addr Data Addr Data Addr Data Addr Data
Command Set Entry (5)
3
2
1
2
3
2
4
7
2
3
2
2
1
2
3
2
1
555
XX
2AA
555
40
Lock
Register
Bits
Program (6, 12)
Read (6)
A0
77/00
data
77
data
90
Command Set Exit (7)
Command Set Entry (5)
Program [0-3] (8)
Read (9)
XX
XX
2AA
00
00
55
PWD[0-3]
PWD1
03
555
XX
AA
A0
555
60
Password
Protection
0...00 PWD0 0...01
0...02
00
PWD2 0...03 PWD3
Unlock
00
XX
555
XX
XX
SA
XX
555
XX
BA
25
90
00
XX
PWD0
01
PWD1
02
PWD2
03
PWD3
00
29
Command Set Exit (7)
Command Set Entry (5)
PPB Program (10)
All PPB Erase (10, 11)
PPB Status Read
00
AA
2AA
SA
55
[BA]555
C0
A0
80
00
Non-Volatile
Sector
Protection (PPB)
00
30
RD(0)
90
Command Set Exit (7)
Command Set Entry (5)
PPB Lock Bit Set
XX
2AA
XX
00
55
00
Global
Volatile Sector
Protection
Freeze
AA
[BA]555
[BA]555
50
E0
A0
PPB Lock Bit Status Read
RD(0)
Command Set Exit (7)
2
XX
90
XX
00
(PPB Lock)
Command Set Entry (5)
DYB Set
3
2
2
1
2
555
XX
XX
SA
XX
AA
A0
2AA
SA
55
00
01
Volatile Sector
Protection
(DYB)
DYB Clear
DYB Status Read
Command Set Exit (7)
A0
SA
RD(0)
90
XX
00
Legend:
X = Don’t care.
RA = Address of the memory location to be read.
PD(0) = Secured Silicon Sector Lock Bit. PD(0), or bit[0].
PD(1) = Persistent Protection Mode Lock Bit. PD(1), or bit[1], must
be set to ‘0’ for protection while PD(2), bit[2] must be left as ‘1’.
PD(2) = Password Protection Mode Lock Bit. PD(2), or bit[2], must
be set to ‘0’ for protection while PD(1), bit[1] must be left as ‘1’.
BA = Bank Address. WS256N = A23–A20; WS128N = A22–A20;
WS064N = A21–A18.
PWD3–PWD0 = Password Data. PD3–PD0 present four 16 bit
combinations that represent the 64-bit Password
PWA = Password Address. Address bits A1 and A0 are used to select
each 16-bit portion of the 64-bit entity.
PWD = Password Data.
RD(0), RD(1), RD(2) = DQ0, DQ1, or DQ2 protection indicator bit. If
protected, DQ0, DQ1, or DQ2 = 0. If unprotected, DQ0, DQ1,
DQ2 = 1.
PD(3) = Protection Mode OTP Bit. PD(3) or bit[3].
SA = Sector Address. WS256N = A23–A14; WS128N = A22–A14;
WS064N = A21–A14.
Notes:
1. All values are in hexadecimal.
2. Shaded cells indicate read cycles.
currently 77h for the WS256N only. See Table 9.1 and Table 9.2
for explanation of lock bits.
7. Exit command must be issued to reset the device into read
mode; device may otherwise be placed in an unknown state.
3. Address and data bits not specified in table, legend, or notes are
don’t cares (each hex digit implies 4 bits of data).
4. Writing incorrect address and data values or writing them in the
improper sequence may place the device in an unknown state.
The system must write the reset command to return the device
to reading array data.
5. Entry commands are required to enter a specific mode to enable
instructions only available within that mode.
6. If both the Persistent Protection Mode Locking Bit and the
Password Protection Mode Locking Bit are set at the same time,
the command operation aborts and returns the device to the
default Persistent Sector Protection Mode during 2nd bus cycle.
Note that on all future devices, addresses equal 00h, but is
8. Entire two bus-cycle sequence must be entered for each portion
of the password.
9. Full address range is required for reading password.
10. See Figure 9.2 for details.
11. The All PPB Erase command pre-programs all PPBs before
erasure to prevent over-erasure.
12. The second cycle address for the lock register program operation
is 77 for S29Ws256N; however, for WS128N and Ws064N this
address is 00.
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A d v a n c e I n f o r m a t i o n
13.1 Common Flash Memory Interface
The Common Flash Interface (CFI) specification outlines device and host system software inter-
rogation handshake, which allows specific vendor-specified soft-ware algorithms to be used for
entire families of devices. Software support can then be device-independent, JEDEC ID-indepen-
dent, and forward- and back-ward-compatible for the specified flash device families. Flash
vendors can standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to
address (BA)555h any time the device is ready to read array data. The system can read CFI in-
formation at the addresses given in Tables 13.3–13.6) within that bank. All reads outside of the
CFI address range, within the bank, returns non-valid data. Reads from other banks are allowed,
writes are not. To terminate reading CFI data, the system must write the reset command.
The following is a C source code example of using the CFI Entry and Exit functions. Refer to
the Spansion Low Level Driver User’s Guide (available on www.amd.com and
www.fujitsu.com) for general information on Spansion Flash memory software development
guidelines.
/* Example: CFI Entry command */
*( (UINT16 *)bank_addr + 0x555 ) = 0x0098;
/* write CFI entry command
/* write cfi exit command
*/
*/
/* Example: CFI Exit command */
*( (UINT16 *)bank_addr + 0x000 ) = 0x00F0;
For further information, please refer to the CFI Specification (see JEDEC publications JEP137-A
and JESD68.01and CFI Publication 100). Please contact your sales office for copies of these
documents.
Table 13.3 CFI Query Identification String
Addresses
Data
Description
10h
11h
12h
0051h
0052h
0059h
Query Unique ASCII string QRY
13h
14h
0002h
0000h
Primary OEM Command Set
15h
16h
0040h
0000h
Address for Primary Extended Table
17h
18h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
0000h
0000h
Table 13.4 System Interface String
Addresses
Data
Description
V
Min. (write/erase)
CC
1Bh
0017h
D7–D4: volt, D3–D0: 100 millivolt
V
Max. (write/erase)
CC
1Ch
0019h
D7–D4: volt, D3–D0: 100 millivolt
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
0000h
0000h
0006h
0009h
000Ah
0000h
0004h
0004h
0003h
0000h
V
V
Min. voltage (00h = no V pin present)
PP
PP
Max. voltage (00h = no V pin present)
PP
PP
Typical timeout per single byte/word write 2N µs
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for byte/word write 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
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A d v a n c e I n f o r m a t i o n
Table 13.5 Device Geometry Definition
Addresses
Data
Description
0019h (WS256N)
0018h (WS128N)
0017h (WS064N)
Device Size = 2N byte
27h
28h
29h
0001h
0000h
Flash Device Interface description (refer to CFI publication 100)
Max. number of bytes in multi-byte write = 2N
(00h = not supported)
2Ah
2Bh
0006h
0000h
2Ch
0003h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
0003h
0000h
0080h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
00FDh (WS256N)
007Dh (WS128N)
003Dh (WS064N)
31h
Erase Block Region 2 Information
32h
33h
34h
0000h
0000h
0002h
35h
36h
37h
38h
0003h
0000h
0080h
0000h
Erase Block Region 3 Information
Erase Block Region 4 Information
39h
3Ah
3Bh
3Ch
0000h
0000h
0000h
0000h
Table 13.6 Primary Vendor-Specific Extended Query
Addresses
Data
Description
40h
41h
42h
0050h
0052h
0049h
Query-unique ASCII string PRI
43h
44h
0031h
0034h
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock (Bits 1-0), 0 = Required, 1 = Not Required
Silicon Technology (Bits 5-2) 0100 = 0.11 µm
45h
46h
47h
48h
49h
0100h
0002h
0001h
0000h
0008h
Erase Suspend,
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect,
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
08 = Advanced Sector Protection
00F3h (WS256N)
007Bh (WS128N)
003Fh (WS064N)
Simultaneous Operation
Number of Sectors in all banks except boot bank
4Ah
Burst Mode Type
00 = Not Supported, 01 = Supported
4Bh
4Ch
4Dh
0001h
0000h
0085h
Page Mode Type,
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page, 04 = 16 Word Page
ACC (Acceleration) Supply Minimum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
4Eh
0095h
4Fh
50h
0001h
0001h
0001h = Dual Boot Device
Program Suspend. 00h = not supported
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A d v a n c e I n f o r m a t i o n
Table 13.6 Primary Vendor-Specific Extended Query (Continued)
Addresses
51h
Data
0001h
0007h
Description
Unlock Bypass, 00 = Not Supported, 01=Supported
Secured Silicon Sector (Customer OTP Area) Size 2N bytes
52h
Hardware Reset Low Time-out during an embedded
algorithm to read mode Maximum 2N ns
53h
54h
0014h
0014h
Hardware Reset Low Time-out not during an embedded
algorithm to read mode Maximum 2N ns
55h
56h
57h
0005h
0005h
Erase Suspend Time-out Maximum 2N ns
Program Suspend Time-out Maximum 2N ns
Bank Organization: X = Number of banks
0010h
0013h (WS256N)
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
60h
61h
62h
63h
64h
65h
66h
67h
000Bh (WS128N) Bank 0 Region Information. X = Number of sectors in bank
0007h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
Bank 1 Region Information. X = Number of sectors in bank
Bank 2 Region Information. X = Number of sectors in bank
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N) Bank 3 Region Information. X = Number of sectors in bank
0004h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
Bank 4 Region Information. X = Number of sectors in bank
Bank 5 Region Information. X = Number of sectors in bank
Bank 6 Region Information. X = Number of sectors in bank
Bank 7 Region Information. X = Number of sectors in bank
Bank 8 Region Information. X = Number of sectors in bank
Bank 9 Region Information. X = Number of sectors in bank
Bank 10 Region Information. X = Number of sectors in bank
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N) Bank 11 Region Information. X = Number of sectors in bank
0004h (WS064N)
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
Bank 12 Region Information. X = Number of sectors in bank
Bank 13 Region Information. X = Number of sectors in bank
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
0010h (WS256N)
0008h (WS128N) Bank 14 Region Information. X = Number of sectors in bank
0004h (WS064N)
0013h (WS256N)
000Bh (WS128N)
0007h (WS064N)
Bank 15 Region Information. X = Number of sectors in bank
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14 Commonly Used Terms
Ter m
D efi nit i on
ACCelerate. A special purpose input signal which allows for faster programming or
erase operation when raised to a specified voltage above VCC. In some devices ACC
may protect all sectors when at a low voltage.
ACC
Most significant bit of the address input [A23 for 256Mbit, A22 for128Mbit, A21 for
64Mbit]
Amax
Amin
Least significant bit of the address input signals (A0 for all devices in this document).
Operation where signal relationships are based only on propagation delays and are
unrelated to synchronous control (clock) signal.
Asynchronous
Read mode for obtaining manufacturer and device information as well as sector
protection status.
Autoselect
Bank
Section of the memory array consisting of multiple consecutive sectors. A read
operation in one bank, can be independent of a program or erase operation in a
different bank for devices that offer simultaneous read and write feature.
Smaller size sectors located at the top and or bottom of Flash device address space.
The smaller sector size allows for finer granularity control of erase and protection for
code or parameters used to initiate system operation after power-on or reset.
Boot sector
Boundary
Burst Read
Byte
Location at the beginning or end of series of memory locations.
See synchronous read.
8 bits
Common Flash Interface. A Flash memory industry standard specification [JEDEC 137-
A and JESD68.01] designed to allow a system to interrogate the Flash to determine its
size, type and other performance parameters.
CFI
Clear
Zero (Logic Low Level)
Special purpose register which must be programmed to enable synchronous read
mode
Configuration Register
Synchronous method of burst read whereby the device reads continuously until it is
stopped by the host, or it has reached the highest address of the memory array, after
which the read address wraps around to the lowest memory array address
Continuous Read
Erase
Returns bits of a Flash memory array to their default state of a logical One (High Level).
Halts an erase operation to allow reading or programming in any sector that is not
selected for erasure
Erase Suspend/Erase Resume
Ball Grid Array package. Spansion LLC offers two variations: Fortified Ball Grid Array
and Fine-pitch Ball Grid Array. See the specific package drawing or connection diagram
for further details.
BGA
Synchronous (burst) read operation in which 8, 16, or 32 words of sequential data with
Linear Read
or without wraparound before requiring a new initial address
.
Multi-Chip Package. A method of combining integrated circuits in a single package by
stacking multiple die of the same or different devices.
MCP
Memory Array
MirrorBit™ Technology
The programmable area of the product available for data storage.
Spansion™ trademarked technology for storing multiple bits of data in the same
transistor.
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Group of words that may be accessed more rapidly as a group than if the words were
accessed individually.
Page
Asynchronous read operation of several words in which the first word of the group
takes a longer initial access time and subsequent words in the group take less page
access time to be read. Different words in the group are accessed by changing only the
least significant address lines.
Page Read
Sector protection method which uses a programmable password, in addition to the
Password Protection
Persistent Protection
Program
Persistent Protection method, for protection of sectors in the Flash memory device
.
Sector protection method that uses commands and only the standard core voltage
supply to control protection of sectors in the Flash memory device. This method
replaces a prior technique of requiring a 12V supply to control the protection method.
Stores data into a Flash memory by selectively clearing bits of the memory array in
order to leave a data pattern of ones and zeros.
Program Suspend/Program
Resume
Halts a programming operation to read data from any location that is not selected for
programming or erase.
Read
Host bus cycle that causes the Flash to output data onto the data bus.
Dynamic storage bits for holding device control information or tracking the status of
an operation.
Registers
Secured Silicon. An area consisting of 256 bytes in which any word may be
programmed once, and the entire area may be protected once from any future
programming. Information in this area may be programmed at the factory or by the
user. Once programmed and protected there is no way to change the secured
information. This area is often used to store a software readable identification such as
a serial number.
Secured Silicon
Use of one or more control bits per sector to indicate whether each sector may be
programmed or erased. If the Protection bit for a sector is set the embedded
algorithms for program or erase ignores program or erase commands related to that
sector.
Sector Protection
Sector
An Area of the memory array in which all bits must be erased together by an erase
operation.
Mode of operation in which a host system may issue a program or erase command to
one bank, that embedded algorithm operation may then proceed while the host
immediately follows the embedded algorithm command with reading from another
bank. Reading may continue concurrently in any bank other than the one executing
the embedded algorithm operation.
Simultaneous Operation
Synchronous Operation
Operation that progresses only when a timing signal, known as a clock, transitions
between logic levels (that is, at a clock edge).
Separate power supply or voltage reference signal that allows the host system to set
the voltage levels that the device generates at its data outputs and the voltages
tolerated at its data inputs.
VersatileIO™ (VIO
Unlock Bypass
Word
)
Mode that facilitates faster program times by reducing the number of command bus
cycles required to issue a write operation command. In this mode the initial two Unlock
write cycles, of the usual 4 cycle Program command, are not required – reducing all
Program commands to two bus cycles while in this mode.
Two contiguous bytes (16 bits) located at an even byte boundary. A double word is two
contiguous words located on a two word boundary. A quad word is four contiguous
words located on a four word boundary.
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Special burst read mode where the read address wraps or returns back to the lowest
address boundary in the selected range of words, after reading the last Byte or Word
in the range, e.g. for a 4 word range of 0 to 3, a read beginning at word 2 would read
words in the sequence 2, 3, 0, 1.
Wraparound
Interchangeable term for a program/erase operation where the content of a register
and or memory location is being altered. The term write is often associated with writing
command cycles to enter or exit a particular mode of operation.
Write
Multi-word area in which multiple words may be programmed as a single operation. A
Write Buffer
Write Buffer may be 16 to 32 words long and is located on a 16 or 32 word boundary
respectively.
Method of writing multiple words, up to the maximum size of the Write Buffer, in one
Write Buffer Programming
Write Operation Status
operation. Using Write Buffer Programming results in
time than by using single word at a time programming commands.
≥
8 times faster programming
Allows the host system to determine the status of a program or erase operation by
reading several special purpose register bits
.
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S29RS512N
512 Megabit (32 M x 16-Bit) CMOS 1.8 Volt-only
Read/Write, Burst Mode, Mass Storage Flash Memory
for Multi-Chip Products (MCP)
DATA SHEET
Distinctive Characteristics
Architectural Advantages
Single 1.8 volt read, program and erase (1.65
Hardware Features
Sector Protection
to 1.95 volt)
Manufactured on 0.11 µm MirrorBitTM process
—
Dynamic Protection Bits (DYB) are assigned to every
sector
Read/Write operation
—
A command sector protection to lock/unlock
combinations of individual sectors to prevent/allow
program or erase operations within that sector.
—
Zero latency between read and write operations
Programable Burst Interface
Handshaking feature available
—
—
2 Modes of Burst Read Operation
Linear Burst: 8, 16, and 32 words with or without
wrap-around
—
Provides host system with minimum possible latency
by monitoring RDY
—
Continuous Sequential Burst
ACC input: Acceleration function reduces
Sector Architecture
programming time in a factory setting
—
one-hundred-twenty-eight 256 Kword sectors
Low VCC write inhibit
100,000 erase cycle per sector typical
20-year data retention typical
Software Features
Software command set compatible with
JEDEC 42.4 standards
Data# Polling and toggle bits
Performance Charcteristics
Read access times at 80/66/54 MHz
—
Provides a software method of detecting program and
erase operation completion
—
—
—
Burst access times of 9.1/11.2/13.5 ns
Synchronous latency of 148 ns
Asynchronous random access times of 143 ns
Erase Suspend/Resume
—
Suspends an erase operation to read data from, or
program data to, a sector that is not being erased,
then resumes the erase operation
High Performance
—
—
Typical word programming time of 40 µs
Typical effective word programming time of 9.4 µs
utilizing a 32-Word Write Buffer at Vcc Level
Typical effective word programming time of 6 µs
utilizing a 32-Word Write Buffer at ACC Level
Typical 2 s sector erase time for 256 Kword sectors
Program Suspend/Resume
—
—
—
Suspends a programming operation to read data from
a sector other than the one being programmed, then
resume the programming operation
Power dissipation (typical values, CL = 30 pF)
Unlock Bypass Program command
@ 80 MHz
—
Reduces overall programming time when issuing
multiple program command sequences
—
—
—
—
Continuous Burst Mode Read: 35 mA
Program: 19 mA
Erase: 19 mA
Additional Features
Program Operation
Standby mode: 20 µA
—
Ability to perform synchronous and asynchronous
write operation independent of burst control register
setting
Publication Number S75WS-N-00 Revision A Amendment 0 Issue Date February 17, 2005
D a t a S h e e t
General Description
The S29RS512N is a 512 Mbit, 1.8 Volt-only, simultaneous Read/Write, Burst Mode Flash memory
device, organized as 33,554,432words of 16 bits each. This device uses a single VCC of 1.65 to
1.95 V to read, program, and erase the memory array. A 9.0-volt VHH on ACC may be used for
faster program performance in a factory setting environment.
The device uses Chip Enable (CE#), Write Enable (WE#), Address Valid (AVD#) and Output En-
able (OE#) to control asynchronous read and write operations. For burst operations, the device
additionally requires Ready (RDY), and Clock (CLK). This implementation allows easy interface
with minimal glue logic to a wide range of microprocessors/microcontrollers for high performance
read operations.
The burst read mode feature gives system designers flexibility in the interface to the device. The
user can preset the burst length and then wrap or non-wrap through the same memory space, or
read the currently addressable flash array block in continuous mode.
The rising clock edge initiates burst accesses and determines when data will be output.
The device is entirely command set compatible with the JEDEC 42.4 single-power-supply
Flash standard. Commands are written to the command register using standard microprocessor
write timing. Register contents serve as inputs to an internal state-machine that controls the
erase and programming circuitry. Write cycles also internally latch addresses and data needed for
the programming and erase operations. Reading data out of the device is similar to reading from
other Flash or EPROM devices.
Device programming occurs by executing the program command sequence. This initiates the Em-
bedded Program algorithm - an internal algorithm that automatically times the program pulse
widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster program times
by requiring only two write cycles to program data instead of four. Additionally, Write Buffer Pro-
gramming is available on this family of devices. This feature provides superior programming
performance by grouping locations being programmed.
Device erasure occurs by executing the erase command sequence. This initiates the Embedded
Erase algorithm - an internal algorithm that automatically preprograms the array (if it is not al-
ready programmed) before executing the erase operation. During erase, the device automatically
times the erase pulse widths and verifies proper cell margin.
The Program Suspend/Program Resume feature enables the user to put program on hold to
read data from any sector that is not selected for programming. If a read is needed from the Dy-
namic Protection area after a program suspend, then the user must use the proper command
sequence to enter and exit this region. The program suspend/resume functionality is also avail-
able when programming in erase suspend (1 level depth only).
The Erase Suspend/Erase Resume feature enables the user to put erase on hold to read data
from, or program data to, any sector that is not selected for erasure. True background erase can
thus be achieved. If a read is needed from the Dynamic Protection area, after an erase suspend,
then the user must use the proper command sequence to enter and exit this region.
The hardware RESET# pin terminates any operation in progress and resets the internal state
machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A sys-
tem reset would thus also reset the device, enabling the system microprocessor to read boot-up
firmware from the Flash memory device.
The host system can detect whether a memory array program or erase operation is complete by
using the device status bit DQ7 (Data# Polling), DQ6/DQ2 (toggle bits), DQ5 (exceeded timing
limit), DQ3 (sector erase start timeout state indicator), and DQ1 (write to buffer abort). After a
program or erase cycle has been completed, the device automatically returns to reading array
data.
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The sector erase architecture allows memory sectors to be erased and reprogrammed without
affecting the data contents of other sectors [The device is fully erased when shipped from the
factory].
Hardware data protection measures include a low VCC detector that automatically inhibits write
operations during power transitions.
When the ACC pin = VIL, the entire flash memory array is protected.
The device offers two power-saving features. When addresses have been stable for a specified
amount of time, the device enters the automatic sleep mode. The system can also place the
device into the standby mode. Power consumption is greatly reduced in both modes.
Spansion’s Flash technology combines years of Flash memory manufacturing experience to pro-
duce the highest levels of quality, reliability and cost effectiveness. The device electrically erases
all bits within a sector. The data is programmed using hot electron injection.
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15 Product Selector Guide
S29RS512N
Synchronous/Burst
Speed Option
80 MHz
66 MHz
54 MHz
Asynchronous
Max Access Time,
Max Latency,
ns (tIACC
148
160
160
143
)
ns (tACC
)
Max CE# Access,
Max Burst Access Time, ns (tBACC
Max OE# Access, ns (tOE
)
9.1
9.1
11.2
11.2
13.5
13.5
148
9.1
ns (tCE
)
)
Max OE# Access, ns (tOE
)
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16 Block Diagram
VCC
VSS
DQ15–DQ0
RDY
Buffer
RDY
Erase Voltage
Generator
Input/Output
Buffers
WE#
RESET#
ACC
State
Control
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
CE#
OE#
Y-Decoder
Y-Gating
VCC
Detector
Timer
Cell Matrix
X-Decoder
Burst
State
Control
Burst
Address
Counter
AVD#
CLK
Amax–A0*
Amax = A24
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17 Logic Symbol
25 or 24
Amax–
CLK
16
DQ15–DQ0
ACC
CE#
OE#
WE#
RDY
RESET#
AVD#
Note: Amax = A24 for 512Mb.
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18 Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated
through the internal command register. The command register itself does not occupy any addres-
sable memory location. The register is composed of latches that store the commands, along with
the address and data information needed to execute the command. The contents of the register
serve as inputs to the internal state machine. The state machine outputs dictate the function of
the device. Table 18.1 lists the device bus operations, the inputs and control levels they require,
and the resulting output. The following subsections describe each of these operations in further
detail.
Table 18.1 Device Bus Operations
Operation
CE#
L
OE#
L
WE#
Addresses
Addr In
Addr In
Addr In
Addr In
X
DQ15–0
I/O
RESET#
CLK
X
AVD#
Asynchronous Read - Addresses Latched
Asynchronous Read - Addresses Steady State
Asynchronous Write
H
H
L
H
H
H
H
H
L
L
L
I/O
X
L
L
L
H
I/O
X
Synchronous Write
L
H
L
I/O
Standby (CE#)
H
X
X
X
X
HIGH Z
HIGH Z
X
X
X
X
Hardware Reset
X
X
Burst Read Operations
Load Starting Burst Address
L
L
X
L
H
H
Addr In
X
X
H
H
Advance Burst to next address with
appropriate Data presented on the Data Bus
Burst
Data Out
H
Terminate current Burst read cycle
H
X
X
X
H
H
X
X
HIGH Z
HIGH Z
H
L
X
X
Terminate current Burst read cycle via RESET#
X
Terminate current Burst read cycle and start
new Burst read cycle
L
X
H
Addr In
I/O
H
Legend: L = Logic 0, H = Logic 1, X = Don’t Care.
18.1 Requirements for Asynchronous Read Operation (Non-Burst)
To read data from the memory array, the system must first assert a valid address on Amax–A0,
while driving AVD# and CE# to VIL. WE# should remain at VIH. The rising edge of AVD# latches
the address. The data will appear on DQ15–DQ0.
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The
chip enable access time (tCE) is the delay from the stable CE# to valid data at the outputs. The
output enable access time (tOE) is the delay from the falling edge of OE# to valid data at the
output.
The internal state machine is set for reading array data in asynchronous mode upon device
power-up, or after a hardware reset. This ensures that no spurious alteration of the memory con-
tent occurs during the power transition.
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18.2 Requirements for Synchronous (Burst) Read Operation
The device is capable of continuous sequential burst operation and linear burst operation of a pre-
set length. When the device first powers up, it is enabled for asynchronous read operation.
Prior to entering burst mode, the system should determine how many wait states are desired for
the initial word (tIACC) of each burst access, what mode of burst operation is desired and how the
RDY signal will transition with valid data. The system would then write the configuration register
command sequence. See Set Configuration Register Command Sequence for further details.
Table 2-4 shows the address latency scheme for varying frequencies.
Table 18.2 Address Latency Scheme for < 56Mhz
Cycle
Add ws
Initial
Addr
X
X+1
D1
D2
D3
X+2
D2
X+3
D3
X+4
D4
X+5
D5
X+6
D6
00
01
10
11
D0
D1
D2
D3
0ws
0ws
0ws
0ws
D3
1ws
1ws
1ws
D4
D5
D6
1ws
1ws
D4
D5
D6
1ws
D4
D5
D6
Table 18.3 Address Latency Scheme for < 70Mhz
Cycle
Initial
Addr
X
X+1
D1
D2
D3
X+2
D2
X+3
D3
Add ws
1ws
X+4
D4
X+5
D5
X+6
D6
00
01
10
11
D0
D1
D2
D3
D3
1ws
1ws
1ws
1ws
D4
D5
D6
1ws
1ws
1ws
D4
D5
D6
1ws
1ws
D4
D5
D6
Table 18.4 Address Latency Scheme for < 84Mhz
Cycle
Initial
Addrs
X
X+1
D1
D2
D3
X+2
D2
X+3
D3
Add ws
2ws
X+4
D4
X+5
D5
X+6
D6
00
01
10
11
D0
D1
D2
D3
D3
1ws
1ws
1ws
2ws
D4
D5
D6
1ws
1ws
2ws
D4
D5
D6
1ws
2ws
D4
D5
D6
Address Latency Scheme for < 84Mhz
The initial word is output tIACC after the rising edge of the first CLK cycle. Subsequent words are
output tBACC after the rising edge of each successive clock cycle, which automatically increments
the internal address counter. Note that the device has a fixed internal address boundary that oc-
curs every 512 words and there is a boundary crossing latency of 4/8 wait states, when
the device is operating at frequencies lower than 56/80Mhz respectively.
During the time the device is outputting data with the starting burst address not divisible by four,
additional waits are required. For example, if the device is operating at frequency of 80Mhz and
if the starting burst address is divisible by four A1:0 = 00, two additional wait state is required.
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If the starting burst address is at address A1:0 = 01, 10, 11 then three, four or five wait states
are required, respectively, until data D4 is read and burst sequence becomes linear. Please refer
to Table 18.4 for further details. The RDY output indicates this condition to the system by
deasserting.
18.2.1 Continuous Burst
The device will continue to output sequential burst data, wrapping around to address 000000h
after it reaches the highest addressable memory location, until the system drives CE# high, RE-
SET# low, or AVD# low in conjunction with a new address. See Table 18.1.
18.2.2 8-, 16-, and 32-Word Linear Burst with Wrap Around
The remaining three modes are of the linear wrap around design, in which a fixed number of
words are read from consecutive addresses. In each of these modes, the burst addresses read
are determined by the group within which the starting address falls. The groups are sized accord-
ing to the number of words read in a single burst sequence for a given mode (see Table 18.5.).
Table 18.5 Burst Address Groups
Mode
Group Size
8 words
Group Address Ranges
0-7h, 8-Fh, 10-17h,...
0-Fh, 10-1Fh, 20-2Fh,...
00-1Fh, 20-3Fh, 40-5Fh,...
8-word
16-word
32-word
16 words
32 words
As an example: if the starting address in the 8-word mode is 3ch, the address range to be read
would be 38-3Fh, and the burst sequence would be 3C, 3D, 3E, 3F, 38, 39, 3A, 3Bh. if wrap around
is enable. The burst sequence begins with the starting address written to the device, but wraps
back to the first address in the selected group and stops at the group size, terminating the burst
read. In a similar fashion, the 16-word and 32-word Linear Wrap modes begin their burst se-
quence on the starting address written to the device, and then wrap back to the first address in
the selected address group. Note that in these three burst read modes the address pointer
does not cross the boundary that occurs every 512 words; thus, no wait states are in-
serted (except during the initial access). (see Figure 25.4)
18.2.3 8-, 16-, and 32-Word Linear Burst without Wrap Around
If wrap around is not enabled, 8-word, 16-word, or 32-word burst will execute linearly up to word
boundary. The burst will stop after 8, 16, or 32 addresses and will not wrap around to the first
address of the selected group. As an example: if the starting address in the 8-word mode is 3ch,
the address range to be read would be 39-40h, and the burst sequence would be 3C, 3D-3E-3F-
40-41-42-43h if wrap around is not enabled. The next address to be read will require a new ad-
dress and AVD# pulse. The address range would stay within the address block, causing address
FFFFh to be followed by 0000h. Note that in this burst mode, the address pointer may cross the
boundary that occurs every 128 words.
18.3 Configuration Register
The device uses a configuration register to set the various burst parameters: number of wait
states, burst read mode, RDY configuration, and synchronous mode active.
18.4 RDY: Ready
The RDY is a dedicated output that, when the device is configured in the Synchronous mode, in-
dicates (when at logic low) the system should wait 1 clock cycle before expecting the next word
of data. The RDY pin is only controlled by CE#. Using the RDY Configuration Command Sequence,
RDY can be set so that a logic low indicates the system should wait 2 clock cycles before expecting
valid data.
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The following conditions cause the RDY output to be low: during the initial access (in burst mode),
and at the boundary crossing, that occurs every 512 words beginning with address 1FFh.
18.5 Handshaking
The device is equipped with a handshaking feature that allows the host system to simply monitor
the RDY signal from the device to determine when the burst data is ready to be read. The host
system should use the programmable wait state configuration to set the number of wait states
for optimal burst mode operation. The initial word of burst data is indicated by the rising edge of
RDY after OE# goes low.
For optimal burst mode performance, the host system must set the appropriate number of wait
states in the flash device depending on clock frequency. See Set Configuration Register Command
Sequence and Requirements for Synchronous (Burst) Read Operation for more information.
18.6 Writing Commands/Command Sequences
The device has the capability of performing an asynchronous or synchronous write operation.
While the device is configured in Asynchronous read it is able to perform Asynchronous write op-
erations only. CLK is ignored when the device is configured in the Asynchronous mode. When in
the Synchronous read mode configuration, the device is able to perform both Asynchronous and
Synchronous write operations. CLK and AVD# address latch is supported in the Synchronous pro-
gramming mode. During a synchronous write operation, to write a command or command
sequence (which includes programming data to the device and erasing sectors of memory), the
system must drive AVD# and CE# to VIL, and OE# to VIH when providing an address to the de-
vice, and drive WE# and CE# to VIL, and OE# to VIH. when writing commands or data. During an
asynchronous write operation, the system must drive CE# and WE# to VIL and OE# to VIH when
providing an address, command, and data. Addresses are latched on the last falling edge of WE#
or CE#, while data is latched on the 1st rising edge of WE# or CE# (see ).
The device features an Unlock Bypass mode to facilitate faster programming. Once the device en-
ters the Unlock Bypass mode, only two write cycles are required to program a word, instead of
four.
An erase operation can erase one sector, multiple sectors or the entire device. Table 19.6 indicates
the address space that each sector occupies. A sector address is the address bits required to
uniquely select a sector.
ICC2 in the DC Characteristics section represents the active current specification for the write
mode. The AC Characteristics section contains timing specification tables and timing diagrams for
write operations.
18.7 Accelerated Program/Chip Erase Operations
The device offers accelerated program and accelerated chip erase operations through the ACC
functionACC is intended to allow faster manufacturing throughput at the factory and not to be
used in system operations.
The system can use the Write Buffer Load command sequence. Note that if a Write-to-Buffer-
Abort Reset is required, the full 3-cycle RESET command sequence must be used to reset
the device. Removing VHH from the ACC input, upon completion of the embedded program or
erase operation, returns the device to normal operation. Note that sectors must be unlocked prior
to raising ACC to VHH. When at VIL, ACC locks all sectors. ACC should be at VIH for all other
conditions.
number loaded = the number of locations to program minus 1. For example, if the system will
program 6 address locations, then 05h should be written to the device.)
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The system then writes the starting address/data combination. This starting address is the first
address/data pair to be programmed, and selects the write-buffer-page address. All subsequent
address/data pairs must fall within the selected-write-buffer-page where Amax = 24 for RS512N.
The write-buffer-page is selected by addresses Amax - A5.
The write-buffer-page addresses must be the same for all address/data pairs loaded into
the write buffer. (This means Write Buffer Programming cannot be performed across multiple
write-buffer-pages. This also means that Write Buffer Programming cannot be performed across
multiple sectors. If the system attempts to load programming data outside of the selected write-
buffer-page, the operation will ABORT.)
After writing the Starting Address/Data pair, the system then writes the remaining address/data
paris into the write buffer. Write buffer locations may be loaded in any order.
Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter
will be decremented for every data load operation. Also, the last data loaded at a location
before the Program Buffer to Flash confirm command will be programmed into the device. It is
the software’s responsibility to comprehend ramifications of loading a write-buffer location more
than once. The counter decrements for each data load operation, not for each unique write-
buffer-address location.
Once the specified number of write buffer locations have been loaded, the system must then write
the Program Buffer to Flash command at the Sector Address. Any other address/data write com-
binations will abort the Write Buffer Programming operation. The device then goes busy. The Data
Bar polling techniques should be used while monitoring the last address location loaded into
the write buffer. This eliminates the need to store an address in memory because the system
can load the last address location, issue the program confirm command at the last loaded address
location, and then data bar poll at that same address. DQ7, DQ6, DQ5, DQ2, and DQ1 should be
monitored to determine the device status during Write Buffer Programming.
The write-buffer embedded programming operation can be suspended using the standard sus-
pend/resume commands. Upon successful completion of the Write Buffer Programming operation,
the device will return to READ mode.
The Write Buffer Programming Sequence can be ABORTED in the following ways:
Load a value that is greater than the page buffer size during the Number of Locations to Pro-
gram step.
Write to an address in a sector different than the one specified during the Write-Buffer-Load
command.
Write an Address/Data pair to a different write-buffer-page than the one selected by the
Starting Address during the write buffer data loading stage of the operation.
Write data other than the Confirm Command after the specified number of data load cycles.
The ABORT condition is indicated by DQ1 = 1, DQ7 = Data# (for the last address location loaded),
DQ6 = TOGGLE, DQ5 = 0. This indicates that the Write Buffer Programming Operation was
ABORTED. A Write-to-Buffer-Abort reset command sequence is required when using the Write-
Buffer-Programming features in Unlock Bypass mode. [Use of the write buffer is strongly rec-
ommended for programming when multiple words are to be programmed.]
from the internal register (which is separate from the memory array)
18.8 Dynamic Sector Protection
The device offers data protection at the sector level and the DYB associated command sequences
disables or re-enables both program and erase operations in any sector or sector group.
Dynamically Locked—The sector is protected and can be changed by a simple command
Unlocked—The sector is unprotected and can be changed by a simple command
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18.8.1 Dynamic Protection Bit (DYB)
A volatile protection bit is assigned for each sector. After power-up or hardware reset, the con-
tents of all DYBs is cleared erased to 1. In other words, the DYB powers-up in an unprotected
state. Each DYB is individually modifiable through the DYB Write Command.
The Protection State for each sector is determined by the DYB related to that sector. The DYBs
control whether or not the sector is protected or unprotected. By issuing the DYB Write com-
mand sequences, the DYBs will be set (programmed to 0) or cleared (erased to 1), thus placing
each sector in the protected or unprotected state. These are the so-called Dynamic Locked or
Unlocked states. They are called dynamic states because it is very easy to switch back and forth
between the protected and unprotected conditions. This allows software to easily protect sectors
against inadvertent changes yet does not prevent the easy removal of protection when changes
are needed. The DYBs maybe set or cleared as often as needed.
18.9 Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby
mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the
high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# inputs are both held at
VCC. The device requires standard access time (tCE) for read access, before it is ready to read
data.
If the device is deselected during erasure or programming, the device draws active current until
the operation is completed.
ICC3 in the DC Characteristics section represents the standby current specification.
18.10 Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. While in asynchronous
mode, the device automatically enables this mode when addresses remain stable for tACC + 20
ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Stan-
dard address access timings provide new data when addresses are changed. While in sleep mode,
output data is latched and always available to the system. While in synchronous mode, the Auto-
matic Sleep Mode is disabled. Note that a new burst operation is required to provide new data.
ICC6 in the DC Characteristics section represents the automatic sleep mode current specification.
18.11 RESET#: Hardware Reset Input
The RESET# input provides a hardware method of resetting the device to reading array data.
When RESET# is driven low for at least a period of tRP, the device immediately terminates any
operation in progress, tristates all outputs, resets the configuration register, and ignores all read/
write commands for the duration of the RESET# pulse. The device also resets the internal state
machine to reading array data. The operation that was interrupted should be reinitiated once the
device is ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS, the device
draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS, the standby cur-
rent will be greater.
RESET# may be tied to the system reset circuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is asserted tRP operation, the device requires a time of tRH + tRP before the device is
ready to read data again. If RESET# is asserted when a program or erase operation is not exe-
cuting, the reset operation is completed within a time of tRP (not during Embedded Algorithms).
The system can read data tRH after RESET# returns to VIH.
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Refer to the Synchronous/Burst Read section for RESET# parameters and to Figure 25.9 for the
timing diagram.
18.12 Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The outputs are placed in the
high impedance state.
18.13 Hardware Data Protection
The following hardware data protection measures prevent accidental erasure or programming,
which might otherwise be caused by spurious system level signals during VCC power-up and
power-down transitions, or from system noise.
18.13.1 Low V
Write Inhibit
CC
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during
VCC power-up and power-down. The command register and all internal program/erase circuits are
disabled, and the device resets to reading array data. Subsequent writes are ignored until VCC is
greater than VLKO. The system must provide the proper signals to the control inputs to prevent
unintentional writes when VCC is greater than VLKO
.
18.13.2 Write Pulse Glitch Protection
Noise pulses do not initiate a write cycle.
18.13.3 Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate
a write cycle, CE# and WE# must be a logical zero while OE# is a logical one.
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19 Sector Address / Memory Address Map
Table 19.6 Sector Address / Memory Address Map for the RS512N
(A24-A0)
(A24-A0)
Sector
SA0
Sector Size
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
Address Range
Sector
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
Sector Size
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
Address Range
0000000h-003FFFFh
0040000h-007FFFFh
0080000h-00BFFFFh
00C0000h-00FFFFFh
0100000h-013FFFFh
0140000h-017FFFFh
0180000h-01BFFFFh
01C0000h-01FFFFFh
0200000h-023FFFFh
0240000h-027FFFFh
0280000h-02BFFFFh
02C0000h-02FFFFFh
0300000h-033FFFFh
0340000h-037FFFFh
0380000h-03BFFFFh
03C0000h-03FFFFFh
0400000h-043FFFFh
0440000h-047FFFFh
0480000h-04BFFFFh
04C0000h-04FFFFFh
0500000h-053FFFFh
0540000h-057FFFFh
0580000h-05BFFFFh
05C0000h-05FFFFFh
0600000h-063FFFFh
0640000h-067FFFFh
0680000h-06BFFFFh
06C0000h-06FFFFFh
0700000h-073FFFFh
0740000h-077FFFFh
0780000h-07BFFFFh
07C0000h-07FFFFFh
0800000h-083FFFFh
0840000h-087FFFFh
0880000h-08BFFFFh
08C0000h-08FFFFFh
0900000h-093FFFFh
0940000h-097FFFFh
0980000h-09BFFFFh
09C0000h-09FFFFFh
1000000h-103FFFFh
1040000h-107FFFFh
1080000h-10BFFFFh
10C0000h-10FFFFFh
1100000h-113FFFFh
1140000h-117FFFFh
1180000h-11BFFFFh
11C0000h-11FFFFFh
1200000h-123FFFFh
1240000h-127FFFFh
1280000h-12BFFFFh
12C0000h-12FFFFFh
1300000h-133FFFFh
1340000h-137FFFFh
1380000h-13BFFFFh
13C0000h-13FFFFFh
1400000h-143FFFFh
1440000h-147FFFFh
1480000h-14BFFFFh
14C0000h-14FFFFFh
1500000h-153FFFFh
1540000h-157FFFFh
1580000h-15BFFFFh
15C0000h-15FFFFFh
1600000h-163FFFFh
1640000h-167FFFFh
1680000h-16BFFFFh
16C0000h-16FFFFFh
1700000h-173FFFFh
1740000h-177FFFFh
1780000h-17BFFFFh
17C0000h-17FFFFFh
1800000h-183FFFFh
1840000h-187FFFFh
1880000h-18BFFFFh
18C0000h-18FFFFFh
1900000h-193FFFFh
1940000h-197FFFFh
1980000h-19BFFFFh
19C0000h-19FFFFFh
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
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Table 19.6 Sector Address / Memory Address Map for the RS512N (Continued)
(A24-A0)
(A24-A0)
Sector
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
Sector Size
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
Address Range
Sector
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
Sector Size
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
256 Kwords
Address Range
0A00000h-0A3FFFFh
0A40000h-0A7FFFFh
0A80000h-0ABFFFFh
0AC0000h-0AFFFFFh
0B00000h-0B3FFFFh
0B40000h-0B7FFFFh
0B80000h-0BBFFFFh
0BC0000h-0BFFFFFh
0C00000h-0C3FFFFh
0C40000h-0C7FFFFh
0C80000h-0CBFFFFh
0CC0000h-0CFFFFFh
0D00000h-0D3FFFFh
0D40000h-0D7FFFFh
0D80000h-0DBFFFFh
0DC0000h-0DFFFFFh
0E00000h-0E3FFFFh
0E40000h-0E7FFFFh
0E80000h-0EBFFFFh
0EC0000h-0EFFFFFh
0F00000h-0F3FFFFh
0F40000h-0F7FFFFh
0F80000h-0FBFFFFh
0FC0000h-0FFFFFFh
1A00000h-1A3FFFFh
1A40000h-1A7FFFFh
1A80000h-1ABFFFFh
1AC0000h-1AFFFFFh
1B00000h-1B3FFFFh
1B40000h-1B7FFFFh
1B80000h-1BBFFFFh
1BC0000h-1BFFFFFh
1C00000h-1C3FFFFh
1C40000h-1C7FFFFh
1C80000h-1CBFFFFh
1CC0000h-1CFFFFFh
1D00000h-1D3FFFFh
1D40000h-1D7FFFFh
1D80000h-1DBFFFFh
1DC0000h-1DFFFFFh
1E00000h-1E3FFFFh
1E40000h-1E7FFFFh
1E80000h-1EBFFFFh
1EC0000h-1EFFFFFh
1F00000h-1F3FFFFh
1F40000h-1F7FFFFh
1F80000h-1FBFFFFh
1FC0000h-1FFFFFFh
19.1 Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are
required to retrieve data in asynchronous mode. The device is ready to read array data after com-
pleting an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the erase-suspend-read
mode, after which the system can read data from any non-erase-suspended sector within the
same device. After completing a programming operation in the Erase Suspend mode, the system
may once again read array data from any non-erase-suspended sector within the same device.
See the Erase Suspend/Erase Resume Commands section for more information.
After the device accepts a Program Suspend command, the device enters the program-suspend-
read mode, after which the system can read data from any non-program-suspended sector within
the device. See Program Suspend/Program Resume Commands for more information.
The system must issue the reset command to return device to the read (or erase-suspend-read)
mode if DQ5 goes high during an active program or erase operation, or if the device is in the au-
toselect mode. See the Reset Command section for more information. If DQ1 goes high during
Write Buffer Programming, the system must issue the Write Buffer Abort Reset command.
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See also the Requirements for Asynchronous Read Operation (Non-Burst) and the Requirements
for Synchronous (Burst) Read Operation sections for more information. The Asynchronous Read
and Synchronous/Burst Read tables provide the read parameters, Figure 25.2, Figure 25.3, and
Figure 25.7 show the timings.
19.2 Set Configuration Register Command Sequence
The device uses a configuration register to set the various burst parameters: number of wait
states, burst read mode, RDY configuration, and synchronous mode active. The configuration reg-
ister must be set before the device will enter burst mode.
The configuration register is loaded with a four-cycle command sequence. The first two cycles are
standard unlock sequences. On the third cycle, the data should be D0h and address bits should
be 555h. During the fourth cycle, the configuration code should be entered onto the data bus with
the address bus set to address 000h or 001h. Once the data has been programmed into the con-
figuration register, a software reset command is required to set the device into the correct state.
The device will power up or after a hardware reset with the default setting, which is in asynchro-
nous mode. The register must be set before the device can enter synchronous mode. The
configuration register can not be changed during device operations (program, erase, or sector
lock).
19.3 Read Configuration Register Command Sequence
The configuration register can be read with a four-cycle command sequence. The first two cycles
are standard unlock sequences. On the third cycle, the data should be C6h and address bits
should be 555h. During the fourth cycle, the configuration code should be read out of the data
bus with the address bus set to address 000h or 001h. Once the data has been read from the
configuration register, a software reset command is required to set the device into array read
mode.
Power-up/
Hardware Reset
Asynchronous Read
Mode Only
Set Burst Mode
Configuration Register
Command for
Set Burst Mode
Configuration Register
Command for
Synchronous Mode
(D15 = 0)
Asynchronous Mode
(D15 = 1)
Synchronous Read
Mode Only
Figure 19.1 Synchronous/Asynchronous State Diagram
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19.3.1 Read Mode Setting
On power-up or hardware reset, the device is set to be in asynchronous read mode. This setting
allows the system to enable or disable burst mode during system operations. Configuration Bit
CR0.15 determines this setting: 1 for asynchronous mode, 0 for synchronous mode.
19.3.2 Programmable Wait State Configuration
The programmable wait state feature informs the device of the number of clock cycles that must
elapse after AVD# is driven active before data will be available. This value is determined by the
input frequency of the device. Configuration Bit CR1.0 & CR0.13–CR0.11 determine the set-
ting (see Table 19.7).
The wait state command sequence instructs the device to set a particular number of clock cycles
for the initial access in burst mode. The number of wait states that should be programmed into
the device is directly related to the clock frequency.
Table 19.7 Programmable Wait State Settings
CR1.0
0
CR0.13
CR0.12
CR0.11
Total Initial Access Cycles
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Reserved
0
3
0
4
0
5
0
6
0
7
Reserved
Reserved
8
0
0
1
1
9
1
10
1
11
1
12 (default)
13
1
1
Reserved
Reserved
1
Notes:
1. Upon power-up or hardware reset, the default setting is twelve wait states.
2. All other but setting are reserved.
It is recommended that the wait state command sequence be written, even if the default wait
state value is desired, to ensure the device is set as expected. A hardware reset will set the wait
state to the default setting.
19.3.3 Programmable Wait State
The host system should set CR1.0 & CR0.13-CR0.11 to 1100/1010/1000 for a clock frequency
of 80/66/54 MHz for the system/device to execute at maximum speed.
19.3.4 Boundary Crossing Latency
Additional wait states must be inserted to account for boundary crossing latency. This is done by
setting CR0.14 to a ‘1’ (default). If required, CR0.14 can be changed to a ‘0’ to remove the
boundary crossing latency.
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19.3.5 Handshaking
For optimal burst mode performance, the host system must set the appropriate number of wait
states in the flash device depending on the clock frequency.
The autoselect function allows the host system to determine whether the flash device is enabled
for handshaking. See the Autoselect Command Sequence for more information.
19.3.6 Burst Length Configuration
The device supports four different read modes: continuous mode, and 8, 16, and 32 word linear
with or without wrap around modes. A continuous sequence (default) begins at the starting ad-
dress and advances the address pointer until the burst operation is complete. If the highest
address in the device is reached during the continuous burst read mode, the address pointer
wraps around to the lowest address.
For example, an eight-word linear read with wrap around begins on the starting address written
to the device and then advances to the next 8 word boundary. The address pointer then returns
to the 1st word after the previous eight word boundary, wrapping through the starting location.
The sixteen- and thirty-two linear wrap around modes operate in a fashion similar to the eight-
word mode.
Table 19.8 shows the CR0.2-CR0.0 and settings for the four read modes.
Table 19.8 Burst Length Configuration
Address Bits
Burst Modes
Continuous
CR0.2
CR0.1
CR0.0
0
0
0
1
0
1
1
0
0
0
1
0
8-word linear
16-word linear
32-word linear
Note: Upon power-up or hardware reset the default setting is continuous.
19.3.7 Burst Wrap Around
By default, the device will perform burst wrap around with CR0.3 set to a ‘1’. Changing the CR0.3
to a ‘0’ disables burst wrap around.
19.3.8 RDY Configuration
By default, the device is set so that the RDY pin will output VOH whenever there is valid data on
the outputs. The device can be set so that RDY goes active one data cycle before active data.
CR0.8 determines this setting; 1 for RDY active (default) with data, 0 for RDY active one clock
cycle before valid data.
19.3.9 RDY Polarity
By default, the RDY pin will always indicate that the device is ready to handle a new transaction
with CR0.10 set to a ‘1’. In this case, the RDY pin is active high. Changing the CR0.10 to a ‘0’
sets the RDY pin to be active low. In this case, the RDY pin will always indicate that the device is
ready to handle a new transaction when low.
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19.4 Configuration Register
Table 19.9 shows the address bits that determine the configuration register settings for various
device functions.
Table 19.9 Configuration Register
CR0. Bit
Function
Settings (Binary)
0 = Synchronous Read (Burst Mode) Enabled
1 = Asynchronous Mode (default)
CR0.15 Set Device Read Mode
0 = No extra boundary crossing latency
1 = With extra boundary crossing latency (default)
CR0.14
Boundary Crossing
0000 = Reserved
0001 = Data is valid on the 4th active CLK edge after addresses are latched
0010 = Data is valid on the 5th active CLK edge after addresses are latched
0011 = Data is valid on the 6th active CLK edge after addresses are latched
0100 = Data is valid on the 7th active CLK edge after addresses are latched
0101 = Data is valid on the 8th active CLK edge after addresses are latched
0110 = Reserved
0111 = Reserved
CR1.0
1000 = Data is valid on the 9th active CLK edge after addresses are latched
1001 = Data is valid on the 10th active CLK edge after addresses are latched
1010 = Data is valid on the 11th active CLK edge after addresses are latched
1011 = Data is valid on the 12th active CLK edge after addresses are latched
1100 = Data is valid on the 13th active CLK edge after addresses are latched (default)
1101 = Data is valid on the 14th active CLK edge after addresses are latched
1110 = Reserved
Programmable
Wait State
1111 = Reserved
CR0.13
CR0.12
CR0.11
0 = RDY signal is active low
1 = RDY signal is active high (default)
CR0.10
CR0.9
CR0.8
RDY Polarity
Reserved
RDY
1 = default
0 = RDY active one clock cycle before data
1 = RDY active with data (default)
CR0.7
CR0.6
CR0.5
CR0.4
Reserved
Reserved
Reserved
Reserved
1 = default
1 = default
0 = default
0 = default
0 = No Wrap Around Burst
1 = Wrap Around Burst (default)
CR0.3
Burst Wrap Around
000 = Continuous (default)
010 = 8-Word Linear Burst
011 = 16-Word Linear Burst
100 = 32-Word Linear Burst
(All other bit settings are reserved)
CR0.2
Burst Length
CR0.1
CR0.0
Note: 3.Device will be in the default state upon power-up or hardware reset.
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19.5 Reset Command
Writing the reset command resets the device to the read or erase-suspend-read mode. Address
bits are don’t cares for this command.
The reset command may be written between the sequence cycles in an erase command sequence
before erasing begins. This resets the device to which the system was writing to the read mode.
[Once erasure begins, however, the device ignores reset commands until the operation is
complete].
The reset command may be written between the sequence cycles in a program command se-
quence before programming begins (prior to the third cycle). This resets the device to which the
system was writing to the read mode. If the program command sequence is written to the device
that is in the Erase Suspend mode, writing the reset command returns the device to the erase-
suspend-read mode. Once programming begins, however, the device ignores reset commands
until the operation is complete.
The reset command may be written between the sequence cycles in an autoselect command se-
quence. Once in the autoselect mode, the reset command must be written to return to the read
mode. If a device entered the autoselect mode while in the Erase Suspend mode, writing the reset
command returns that device to the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation, writing the reset command returns the
device to the read mode (or erase-suspend-read mode if the device was in Erase Suspend and
program-suspend-read mode if the device was in Program Suspend).
Note: If DQ1 goes high during a Write Buffer Programming operation, the system must
write the Write to Buffer Abort Reset command sequence to RESET the device to read-
ing array data. The standard RESET command will not work. See Table 19.9 for details
on this command sequence.
19.6 Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and device
codes, and determine whether or not a sector is protected. The Command Definitions table shows
the address and data requirements. The autoselect command sequence may be written to an ad-
dress within the device that is either in the read or erase-suspend-read mode. The autoselect
command may not be written while the device is actively programming or erasing.
The autoselect command sequence is initiated by first writing two unlock cycles. This is followed
by a third write cycle that contains the autoselect command. The device then enters the autose-
lect mode. No subsequent data will be made available if the autoselect data is read in synchronous
mode. The system may read at any address within the device any number of times without initi-
ating another autoselect command sequence. The following table describes the address
requirements for the various autoselect functions, and the resulting data. The device ID is read
in three cycles.
Table 19.10 Autoselect Addresses
Description
Address
00h
Read Data
01h
Manufacturer ID
Device ID, Word 1
Device ID, Word 2
Device ID, Word 3
01h
227Eh
0Eh
2229 (RS512N)
2201 (RS512N)
0Fh
DQ15 - DQ5 = 0
DQ4 & DQ3 = 11
DQ2 - DQ0 = 0
Indicator Bits
03h
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The system must write the reset command to return to the read mode (or erase-suspend-read
mode if the device was previously in Erase Suspend).
19.7 Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writ-
ing two unlock write cycles, followed by the program set-up command. The program address and
data are written next, which in turn initiate the Embedded Program algorithm. The system is not
required to provide further controls or timings. The device automatically provides internally gen-
erated program pulses and verifies the programmed cell margin. The Command Definitions table
shows the address and data requirements for the program command sequence.
When the Embedded Program algorithm is complete, the device then returns to the read mode
and addresses are no longer latched. The system can determine the status of the program oper-
ation by monitoring DQ7 or DQ6/DQ2. Refer to the “Write Operation Status” section for
information on these status bits.
Any commands written to the device during the Embedded Program Algorithm are ignored. Note
that a hardware reset immediately terminates the program operation. The program command se-
quence should be reinitiated once the device has returned to the read mode, to ensure data
integrity.
Programming is allowed in any sequence and across sector boundaries. A bit cannot be pro-
grammed from 0 back to a 1. Only erase operations can convert a 0 back to a 1.
Attempting to program a 1 over a 0 will result in a programming failure.
Note: See the Command Definitions table for program command sequence.
Figure 19.2 Program Word Operation
19.8 Write Buffer Programming Command Sequence
Write Buffer Programming Sequence allows for faster programming as compared to the standard
Program Command Sequence. See the Write Buffer Programming Operation section for the pro-
gram command sequence.
Table 19.11 Write Buffer Command Sequence
Sequence
Unlock Command 1
Address
555
Data
00AA
0055
0025h
Comment
Not required in the Unlock Bypass mode
Same as above
Unlock Command 2
Write Buffer Load
2AA
Sector Address
Specify the Number of Program
Locations
Starting Address
Starting Address
Word Count Number of locations to program minus 1
All addresses must be within write-buffer-
Program Data page boundaries, but do not have to be
loaded in any order
Load 1st data word
Load next data word
...
Write Buffer Location Program Data Same as above
... ... Same as above
Write Buffer Location Program Data Same as above
This command must follow the last write
Load last data word
Write Buffer Program Confirm
Device goes busy
Sector Address
0029h
buffer location loaded, or the operation will
ABORT
Status monitoring through DQ pins
(Perform Data Bar Polling on the Last
Loaded Address)
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Write “Write to Buffer”
command and
Sector Address
Part of “Write to Buffer”
Command Sequence
Write number of addresses
to program minus 1
and Sector Address
Write first address/data
Yes
WC = 0 ?
No
Write to a different
sector address
Abort Write to
Buffer Operation?
Yes
Write to buffer ABORTED.
Must write “Write-to-buffer
Abort Reset” command
sequence to return
No
Write next address/data pair
to read mode.
WC = WC - 1
Write program buffer to
flash sector address
Read DQ15 - DQ0 at
Last Loaded Address
Yes
DQ7 = Data?
No
No
No
DQ1 = 1?
Yes
DQ5 = 1?
Yes
Read DQ15 - DQ0 with
address = Last Loaded
Address
Yes
DQ7 = Data?
No
FAIL or ABORT
PASS
Figure 19.3 Write Buffer Programming Operation
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19.8.1 Unlock Bypass Command Sequence
The unlock bypass feature allows the system to primarily program to the device faster than using
the standard word program command sequence. The unlock bypass command sequence is initi-
ated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock
bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock by-
pass program command sequence is all that is required to program in this mode. The first cycle
in this sequence contains the unlock bypass program command, A0h; the second cycle contains
the program address and data. Additional data is programmed in the same manner. This mode
dispenses with the initial two unlock cycles required in the standard program command sequence,
resulting in faster total programming time.
During the unlock bypass mode, only the Unlock Bypass Program command is valid. To exit the
unlock bypass mode, the system must issue the two-cycle unlock bypass reset command se-
quence. The first cycle must contain the data 90h. The second cycle need only contain the data
00h. The device then returns to the read mode.
19.9 Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing
two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then
followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The
device does not require the system to preprogram prior to erase. The Embedded Erase algorithm
automatically preprograms and verifies the entire memory for an all zero data pattern prior to
electrical erase. The system is not required to provide any controls or timings during these oper-
ations. The Command Definitions table shows the address and data requirements for the chip
erase command sequence.
When the Embedded Erase algorithm is complete, the device returns to the read mode and ad-
dresses are no longer latched. The system can determine the status of the erase operation by
using DQ7 or DQ6/DQ2. Refer to the Write Operation Status section for information on these sta-
tus bits.
Any commands written during the chip erase operation are ignored. However, note that a hard-
ware reset immediately terminates the erase operation. If that occurs, the chip erase command
sequence should be reinitiated once the device has returned to reading array data, to ensure data
integrity.
Figure 20.4 illustrates the algorithm for the erase operation. Refer to the Erase/Program Opera-
tions table in the AC Characteristics section for parameters and timing diagrams.
19.10 Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writ-
ing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written,
and are then followed by the address of the sector to be erased, and the sector erase command.
The Command Definitions table shows the address and data requirements for the sector erase
command sequence.
The device does not require the system to preprogram prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the entire memory for an all zero data pattern prior to
electrical erase. The system is not required to provide any controls or timings during these
operations.
After the command sequence is written, a sector erase time-out of no less than 50 µs occurs.
During the time-out period, additional sector addresses and sector erase commands may be writ-
ten. Loading the sector erase buffer may be done in any sequence, and the number of sectors
may be from one sector to all sectors. The time between these additional cycles must be less than
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tSEA. Any sector erase address and command following the exceeded time-out may or may not
be accepted. Any command other than Sector Erase or Erase Suspend during the time-out period
resets the device to the read mode.
The system can monitor DQ3 to determine if the sector erase timer has timed out (See DQ3: Sec-
tor Erase Timer.) The time-out begins from the rising edge of the final WE# pulse in the command
sequence.
When the Embedded Erase algorithm is complete, the device returns to reading array data and
addresses are no longer latched. The system can determine the status of the erase operation by
reading DQ7 or DQ6/DQ2. Refer to the Write Operation Status section for information on these
status bits.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other
commands are ignored. However, note that a hardware reset immediately terminates the erase
operation. If that occurs, the sector erase command sequence should be reinitiated once the de-
vice has returned to reading array data, to ensure data integrity.
Figure 20.4 illustrates the algorithm for the erase operation. Refer to the Erase/Program Opera-
tions table in the Erase/Program Operations section for parameters and timing diagrams.
19.10.1 Accelerated Sector Erase
Under certain conditions, the device can erase sectors in parallel. This method of erasing sectors
is faster than the standard sector erase command sequence. Table 19.6lists the sectors.
The accelerated sector erase function must not be used more than 100 times per sector.
In addition, accelerated sector erase should be performed at room temperature 30°C (+/-) 5°C.
Use the following procedure to perform accelerated sector erase:
1. Unlock all sectors in a sector to be erased using the sector lock/unlock command sequence.
All sectors that remain locked will not be erased.
2. Apply 9 V to the ACC input. This voltage must be applied at least 1 µs before executing
step 3.
3. Write 80h to any address within a sector to be erased.
4. Write 30h to any address within a sector to be erased.
5. Monitor status bits DQ2/DQ6 or DQ7 to determine when erasure is complete, just as in the
standard erase operation. See the Write Operation Status section for further details.
6. Lower ACC from 9 V to VCC
7. Relock sectors as required.
.
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20 Erase Suspend/Erase Resume Commands
Notes:
1.See the Command Definitions table for erase command sequence.
2.See the section on DQ3 for information on the sector erase timer.
Figure 20.4 Erase Operation
The Erase Suspend command allows the system to interrupt a sector erase operation and then
read data from, or program data to, any sector not selected for erasure. This command is valid
only during the sector erase operation, including the minimum tSEA time-out period during the
sector erase command sequence. The Erase Suspend command is ignored if written during the
chip erase operation or Embedded Program algorithm.
When the Erase Suspend command is written during the sector erase operation, the device re-
quires a maximum of tESL (Erase Suspend Latency) to suspend the erase operation. However,
when the Erase Suspend command is written during the sector erase time-out, the device imme-
diately terminates the time-out period and suspends the erase operation.
After the erase operation has been suspended, the device enters the erase-suspend-read mode.
The system can read data from or program data to any sector not selected for erasure. (The de-
vice erase suspends all sectors selected for erasure.) Reading at any address within erase-
suspended sectors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6
and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See Write
Operation Status for information on these status bits.
After an erase-suspended program operation is complete, the device returns to the erase-sus-
pend-read mode. The system can determine the status of the program operation using the DQ7
or DQ6 status bits, just as in the standard program operation. See Write Operation Status for
more information.
In the erase-suspend-read mode, the system can also issue the autoselect command sequence.
See Write Buffer Programming Operation and Autoselect Command Sequence for details. To re-
sume the sector erase operation, the system must write the Erase Resume command. Further
writes of the Resume command are ignored. Another Erase Suspend command can be written
after the chip has resumed erasing.
20.1 Program Suspend/Program Resume Commands
The Program Suspend command allows the system to interrupt a embedded programming oper-
ation or a Write to Buffer programming operation so that data can read from any non-suspended
sector. When the Program Suspend command is written during a programming process, the de-
vice halts the programming operation within tPSL (Program Suspend Latency) and updates the
status bits. Addresses are don’t-cares when writing the Program Suspend command.
After the programming operation has been suspended, the system can read array data from any
non-suspended sector. The Program Suspend command may also be issued during a program-
ming operation while an erase is suspended. In this case, data may be read from any addresses
not in Erase Suspend or Program Suspend. If a read is needed from the SecSi Sector area (One
Time Program area), then user must use the proper command sequences to enter and exit this
region. The system may also write the autoselect command sequence when the device is in Pro-
gram Suspend mode. The device allows reading autoselect codes in the suspended sectors, since
the codes are not stored in the memory array. When the device exits the autoselect mode, the
device reverts to Program Suspend mode, and is ready for another valid operation. See Autoselect
Command Sequence for more information.
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After the Program Resume command is written, the device reverts to programming. The system
can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in
the standard program operation. See Write Operation Status for more information. The system
must write the Program Resume command (address bits are don’t care) to exit the Program Sus-
pend mode and continue the programming operation. Further writes of the Program Resume
command are ignored. Another Program Suspend command can be written after the device has
resume programming.
20.2 Volatile Sector Protection Command Set
The Volatile Sector Protection Command Set permits the user to set the Dynamic Protection Bit
(DYB), clear the Dynamic Protection Bit (DYB), and read the logic state of the Dynamic Protection
Bit (DYB).
The Volatile Sector Protection Command Set Entry command sequence must be issued prior
to any of the commands listed following to enable proper command execution. Note that issuing
the Volatile Sector Protection Command Set Entry command disables reads and writes for
the device with the command.
DYB Set Command
DYB Clear Command
DYB Status Read Command
The DYB Set/Clear command is used to set or clear a DYB for a given sector. The address bits
are issued at the same time as the code 00h or 01h on DQ7-DQ0. All other DQ data bus pins are
ignored during the data write cycle. The DYBs are modifiable at any time, regardless of the state
of the PPB or PPB Lock Bit. The DYBs are cleared (erased to ‘1’) at power-up or hardware reset
and are thus in an unprotected state.
The programming state of the DYB for a given sector can be verified by writing a DYB Status
Read Command to the device.
The Volatile Sector Protection Command Set Exit command must be issued after the execu-
tion of the commands listed previously to reset the device to read mode. Otherwise the device
will hang.
Note that issuing the Volatile Sector Protection Command Set Exit command re-enables
reads and writes for the device.
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21 Command Definitions
Bus Cycles (Notes 1–6)
Third Fourth
Addr
Command Sequence
(Note 1)
First
Second
Fifth
Sixth
Addr
Data
RD
F0
Addr Data Addr Data
Data
Addr Data Addr Data
Asynchronous Read (7)
1
1
4
6
4
4
6
1
3
6
6
1
1
4
4
3
2
2
RA
XXX
555
555
555
555
555
SA
555
555
555
XXX
XXX
555
555
555
XX
Reset (8)
Manufacturer ID
Device ID (10)
Indicator Bits
AA
AA
AA
AA
AA
29
AA
AA
AA
B0
30
AA
AA
AA
A0
90
2AA
2AA
2AA
2AA
2AA
55
55
55
55
55
555
555
555
555
SA
90
90
90
A0
25
X00
X01
X03
PA
0001
(11)
(11)
Data
WC
Autoselect
(9)
X0E (10) X0F (10)
Program
Write to Buffer (18)
PA
PA
PD
WBL
PD
Program Buffer to Flash
Write to Buffer Abort Reset (22)
Chip Erase
2AA
2AA
2AA
55
55
55
555
555
555
F0
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
Sector Erase
Erase Suspend (15)
Erase Resume (15)
Set Configuration Register (16)
Read Configuration Register (17)
2AA
2AA
2AA
PA
55
55
55
PD
00
555
555
555
D0
C6
20
X00 or X01
X00 or X01
CR
CR
Unlock Bypass Entry (21)
Unlock Bypass Program (12, 13)
Unlock Bypass Reset
Unlock
Bypass
Mode
XX
XXX
Volatile Sector Protection Command Set Definitions
Volatile Sector Protection
Command Set Entry
3
555
AA
2AA
55
555
E0
DYB Set
DYB Clear
DYB Status Read
2
2
1
XX
XX
SA
A0
A0
RD(0)
SA
SA
00
01
DYB
Volatile Sector Protection
Command Set Exit
2
XX
90
XX
00
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the rising edge of the AVD# pulse or active edge of CLK which ever
comes first.
PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A24–A14 for the RS512N uniquely select any sector.
CR = Configuration Register data bits D15–D0.
WBL = Write Buffer Location. Address must be within the same write buffer page as PA.
WC = Word Count. Number of write buffer locations to load minus 1.
Notes:
1. See Table 18.1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the following, all bus cycles are write cycle: read cycle, fourth through sixth cycles of the Autoselect commands, fourth cycle of
the configuration register verify command, and any cycle reading at RD(0) and RD(1).
4. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD, PD, and WD.
5. Unless otherwise noted, address bits Amax–A12 are don’t cares.
6. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system
must write the reset command to return the device to reading array data.
7. No unlock or command cycles required when device is reading array data.
8. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when
device is in the autoselect mode, or if DQ5 goes high (while the device is providing status information) or performing sector lock/unlock.
9. The fourth cycle of the autoselect command sequence is a read cycle. See the Autoselect Command Sequence section.
10. 512 Mb: 0Eh = 29h and 0Fh = 01h.
11. See the Autoselect Command Sequence section.
12. The Unlock Bypass command sequence is required prior to this command sequence.
13. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode.
14. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase
Suspend command is valid only during a sector erase operation.
15. The Erase Resume command is valid only during the Erase Suspend mode
16. See the Set Configuration Register Command Sequence section.
17. See the Read Configuration Register Command Sequence section which further provides information on Reset Command to Configure the
Configuration Register.
18. The total number of cycles in the command sequence is determined by the number of words written to the write buffer. The maximum
number of cycles in the command sequence is 37.
19. ACC must be at V
during the entire operation of this command
HH
20. Command sequence resets device for next command after write-to-buffer operation.
21. Entry commands are needed to enter a specific mode to enable instructions only available within that mode.
22. Write Buffer Programming can be initiated after Unlock Bypass Entry.
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22 Write Operation Status
The device provides several bits to determine the status of a program or erase operation: DQ1,
DQ2, DQ3, DQ5, DQ6, and DQ7. Table 22.13 and the following subsections describe the function
of these bits. DQ7 and DQ6 each offers a method for determining whether a program or erase
operation is complete or in progress.
22.1 DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase
algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling
is valid after the rising edge of the final WE# pulse in the command sequence. Note that the
Data# Polling is valid only for the last word being programmed in the write-buffer-page
during Write Buffer Programming. Reading Data# Polling status on any word other
than the last word to be programmed in the write-buffer-page will return false status
information.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the
datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend.
When the Embedded Program algorithm is complete, the device outputs the datum programmed
to DQ7. The system must provide the program address to read valid status information on DQ7.
If a program address falls within a protected sector, Data# Polling on DQ7 is active for approxi-
mately tPSP, then the device returns to the read mode.
During the Embedded Erase algorithm, Data# Polling produces a 0 on DQ7. When the Embedded
Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling pro-
duces a 1 on DQ7. The system must provide an address within any of the sectors selected for
erasure to read valid status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected,
Data# Polling on DQ7 is active for approximately tASP, then the device returns to the read mode.
If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7
at an address within a protected sector, the status may not be valid.
Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asyn-
chronously with DQ6–DQ0 while Output Enable (OE#) is asserted low. That is, the device may
change from providing status information to valid data on DQ7. Depending on when the system
samples the DQ7 output, it may read the status or valid data. Even if the device has completed
the program or erase operation and DQ7 has valid data, the data outputs on DQ6-DQ0 may be
still invalid. Valid data on DQ7-D00 will appear on successive read cycles.
Table 22.13 shows the outputs for Data# Polling on DQ7. Figure 22.5 shows the Data# Polling
algorithm. Figure 25.13 in the AC Characteristics section shows the Data# Polling timing diagram.
Notes:
1. VA = Valid adntsbdress for programming. During a sector erase operation, a valid address is any sector address within
the sector being erased. During chip erase, a valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5.
Figure 22.5 Data# Polling Algorithm
22.2 DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or
complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read
at any address in the device, and is valid after the rising edge of the final WE# pulse in the com-
mand sequence (prior to the program or erase operation), and during the sector erase time-out.
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During an Embedded Program or Erase algorithm operation, successive read cycles to any ad-
dress cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6
toggles for approximately tASP (All Sectors Protected toggle time), then returns to reading array
data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unpro-
tected sectors, and ignores the selected sectors that are protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or
is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm
is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops tog-
gling. However, the system must also use DQ2 to determine which sectors are erasing or erase-
suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling).
If a program address falls within a protected sector, DQ6 toggles for approximately tPSP after the
program command sequence is written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embed-
ded Program algorithm is complete.
See the following for additional information: Figure 22.6, Figure 25.14 (toggle bit timing dia-
gram), and Table 22.12.
Toggle Bit I on DQ6 requires either OE# or CE# to be deasserted and reasserted to show the
change in state.
Note: The system should recheck the toggle bit even if DQ5 = 1 because the toggle bit may stop toggling as DQ5 changes
to 1. See the subsections on DQ6 and DQ2 for more information.
Figure 22.6 Toggle Bit Algorithm
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DQ2: Toggle Bit II
The Toggle Bit II on DQ2, when used with DQ6, indicates whether a particular sector is actively
erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-
suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command
sequence.
DQ2 toggles when the system reads at addresses within those sectors that have been selected
for erasure. But DQ2 by itself cannot distinguish whether the sector is actively erasing or is erase-
suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase
Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are
required for sector and mode information. Refer to Table 22.12 to compare outputs for DQ2 and
DQ6.
See Figure 22.6 and Figure 25.14 for additional information.
22.3 Reading Toggle Bits DQ6/DQ2
Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least
twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and
store the value of the toggle bit after the first read. After the second read, the system would com-
pare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system can read array data on DQ7–DQ0 on the
following read cycle. (See Figure 22.6)
However, if after the initial two read cycles, the system determines that the toggle bit is still tog-
gling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If
it is, the system should then determine again whether the toggle bit is toggling, since the toggle
bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the
device has successfully completed the program or erase operation. If it is still toggling, the device
did not completed the operation successfully, and the system must write the reset command to
return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and
DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through suc-
cessive read cycles, determining the status as described in the previous paragraph. Alternatively,
it may choose to perform other system tasks. In this case, the system must start at the beginning
of the algorithm when it returns to determine the status of the operation.
22.4 DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count
limit. Under these conditions DQ5 produces a 1, indicating that the program or erase cycle was
not successfully completed.
The device may output a 1 on DQ5 if the system tries to program a 1 to a location that was pre-
viously programmed to 0 Only an erase operation can change a 0 back to a 1. Under this
condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 pro-
duces a 1.
Under both these conditions, the system must write the reset command to return to the read
mode (or to the erase-suspend-read mode if the device was previously in the erase-suspend-pro-
gram mode).
22.5 DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether
or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If
additional sectors are selected for erasure, the entire time-out also applies after each additional
sector erase command. When the time-out period is complete, DQ3 switches from a 0 to a 1. If
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the time between additional sector erase commands from the system can be assumed to be less
than tSEA, the system need not monitor DQ3. See also the Sector Erase Command Sequence
section.
After the sector erase command is written, the system should read the status of DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and
then read DQ3. If DQ3 is 1, the Embedded Erase algorithm has begun; all further commands (ex-
cept Erase Suspend) are ignored until the erase operation is complete. If DQ3 is 00 the device
will accept additional sector erase commands. To ensure the command has been accepted, the
system software should check the status of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status check, the last command might not have
been accepted.
Table 22.13 shows the status of DQ3 relative to the other status bits.
22.6 DQ1: Write to Buffer Abort
DQ1 indicates whether a Write to Buffer operation was aborted. Under these conditions DQ1 pro-
duces a ‘1’. The system must issue the Write to Buffer Abort Reset command sequence to return
the device to reading array data. See the Write Buffer Programming Operation section for more
details.
3.
4. DQ1 indicates the Write to Buffer ABORT status during Write Buffer Programming operations.
5. The data-bar polling algorithm should be used for Write Buffer Programming operations. Note that DQ7# during Write
Buffer Programming indicates the data-bar for DQ7 data for the LAST LOADED WRITE-BUFFER ADDRESS location.
ACC (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +9.5 V
6. Minimum DC input voltage on pin ACC is -0.5V. During voltage transitions, ACC may overshoot
20 ns
20 ns
+0.8 V
–0.5 V
–2.0 V
20 ns
Table 22.1 Maximum Negative Overshoot Waveform
20 ns
V
CC
+2.0 V
V
CC
+0.5 V
1.0 V
20 ns
20 ns
Figure 22.7 Maximum Positive Overshoot Waveform
February 17, 2005 S75WS-N-00_00_A0
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23 DC Characteristics
23.1 CMOS Compatible
Typ
(Note 7)
Parameter
Description
Test Conditions (Note 1)
Min
Max
Unit
I
Input Load Current
V
V
= V to V , V = V max
±1
±1
66
µA
µA
LI
IN
SS
CC
CC
CC
I
Output Leakage Current
= V to V , V = V max
OUT SS CC CC CC
LO
80 MHz
30
28
27
32
30
28
34
32
29
38
35
22
27
13
3
CE# = V , OE# = V
WE# = V , burst length = 66 MHz
8
,
IH
IL
60
mA
mA
mA
mA
IH
54 MHz
54
80 MHz
60
CE# = V , OE# = V
,
IH
IL
WE# = V , burst length = 66 MHz
54
IH
16
54 MHz
48
V
Active burst
CC
I
CCB
Read Current
80 MHz
54
CE# = V , OE# = V
,
IH
IL
WE# = V , burst length = 66 MHz
48
IH
32
54 MHz
42
80 MHz
48
CE# = V , OE# = V
WE# = V , burst length = 66 MHz
Continuous
54 MHz
,
IH
IL
42
IH
36
10 MHz
36
mA
mA
mA
mA
µA
µA
µA
µA
µA
mA
mA
V
V
Active Asynchronous
CE# = V , OE# = V ,
IL IH
WE# = V
CC
I
5 MHz
1 MHz
18
CC1
Read Current (Note 2)
IH
4
V
<35
20
20
10
70
20
<30
<15
<50
30
CC
V
Active Write Current
CE# = V ,
IL
OE# = V , ACC = V
CC
I
I
CC2
CC3
(Note 3)
IH
IH
V
ACC
V
40
CC
CE# = RESET# =
V
Standby Current
CC
(Note 6)
V
± 0.2 V
CC
V
15
ACC
I
I
V
V
Reset Current
Sleep Current
RESET# = V CLK = V
IL
150
40
CC4
CC6
CC
CC
IL,
CE# = V , OE# = V
IL
IH
V
<40
<20
0.4
CC
Accelerated Program Current CE# = V , OE# = V
(Note 5)
IL
IH,
I
ACC
V
= 9.5 V
ACC
V
ACC
V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
–0.5
IL
V
V
V
– 0.4
V
+ 0.4
IH
CC
CC
V
I
I
= 100 µA, V = V min
0.1
V
V
OL
OH
OL
CC
CC
V
V
= –100 µA, V = V min
– 0.1
OH
CC
CC
CC
Voltage for
Accelerated Program
8.5
1.0
9.5
1.4
V
V
HH
V
Low V Lock-out Voltage
CC
LKO
Notes:
1. Maximum I specifications are tested with V = V max.
CC
CC
CC
2. The I current listed is typically less than 2-3 mA/MHz, with OE# at V
.
IH
CC
3.
I
active while Embedded Erase or Embedded Program is in progress.
CC
4. Device enters automatic sleep mode when addresses are stable for t
+ 20 ns. Typical sleep mode current is equal to
ACC
I
.
CC3
5. Total current during accelerated programming is the sum of V
and V currents.
CC
ACC
6.
U
= V
± 0.2 V and VIL > -.1 V
CC
IH
7. Typical test conditions of room temperature and 1.8 V V
.
CC
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24 Test Conditions
Device
Under
Test
C
L
Figure 24.1 Test Setup
Table 24.1 Test Specifications
Test Condition
All Speed Options
Unit
pF
ns
V
Output Load Capacitance, C (including jig capacitance)
L
30
Input Rise and Fall Times
2.5
Input Pulse Levels
0.0–V
CC
Input timing measurement reference levels
Output timing measurement reference levels
V
V
/2
V
CC
CC
/2
V
Figure 24.2 Input Waveforms and Measurement Levels
Waveform
Inputs
Outputs
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
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25 AC Characteristics
25.1 V
Power-up
CC
Parameter
Description
Setup Time
CC
Test Setup
Speed
Unit
t
V
Min
1
ms
VCS
Notes:
1.
V
>= V - 100mV and V ramp rate is > 1V / 100µs
IO CC
CC
2.
V
ramp rate <1V / 100µs, a Hardware Reset will be required.
CC
tVCS
VCC
RESET#
Figure 25.1
V
Power-up Diagram
CC
25.2 CLK Characterization
Parameter
Description
80 MHz
80
66 MHz
54 MHz
Unit
f
CLK Frequency
CLK Period
Max
Min
66
54
MHz
ns
CLK
CLK
t
12.5
15.1
18.5
t
CLK High Time
CLK Low Time
CLK Rise Time
CLK Fall Time
CH
Min
3.5
2
6.1
3
7.40
3
ns
ns
t
CL
t
CR
Max
t
CF
t
CLK
t
CF
t
t
CL
CH
t
CR
CLK
Figure 25.2 CLK Characterization
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25.3 Synchronous/Burst Read
Parameter
JEDEC Standard
Description
80 MHz
66 MHz
54 MHz
Unit
t
Latency
Max
Max
148
ns
ns
IACC
Burst Access Time Valid
Clock to Output Delay
t
9.1
11.2
13.5
BACC
t
Address Setup Time to CLK (Note 1)
Address Hold Time from CLK (Note 1)
Data Hold Time from Next Clock Cycle
Chip Enable to RDY Valid
Min
Min
Min
Max
Max
Max
Max
Min
Min
Max
Min
Min
Min
Min
Min
4
2
4
2
5
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ACS
ACH
BDH
t
t
4
4
5
t
t
9.1
9.1
10
10
4
11.2
11.2
10
10
4
13.5
13.5
10
10
4
CR
Output Enable to Output Valid
Chip Enable to High Z (Note 2)
Output Enable to High Z (Note 2)
CE# Setup Time to CLK
OE
t
CEZ
OEZ
t
t
CES
t
t
RDY Setup Time to CLK
4
4
5
RDYS
RACC
Ready Access Time from CLK
Address Setup Time to AVD# (Note 1)
Address Hold Time to AVD# (Note 1)
CE# Setup Time to AVD#
9.1
4
11.2
4
13.5
5
t
AAS
t
2
2
3
AAH
t
t
0
0
0
CAS
AVC
AVD
AVD# Low to CLK
4
4
4
t
AVD# Pulse
8
8
8
Notes:
1. Addresses are latched on the first rising edge of CLK.
2. Not 100% tested.
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D a t a S h e e t
10 cycles for initial access shown.
18.5 ns typ. (54 MHz)
tCEZ
tCES
CE#
CLK
1
2
3
9
10
11
12
tAVC
AVD#
tAVD
tACS
Addresses
Data (n)
Aa
tBACC
tACH
Hi-Z
tIACC
Da
Da + 1
Da + 2
Da + n
tOEZ
tBDH
OE#
tRACC
tOE
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
RDY (n)
tCR
tRDYS
Hi-Z
Hi-Z
Data (n + 1)
RDY (n + 1)
Da
Da + 1
Da + 1
Da
Da + 2
Da + 1
Da
Da + n
Da + n
Da + n
Hi-Z
Hi-Z
Data (n + 2)
RDY (n + 2)
Da
Hi-Z
Hi-Z
Data (n + 3)
Da
RDY (n + 3)
Notes:
1. Figure shows total number of wait states set to ten cycles. The total number of wait states can be programmed from
three cycles to thirteen cycles.
2. If any burst address occurs at address + 1, address + 2, ..., or address + 7, additional clock delay cycles are inserted,
and are indicated by RDY.
3. The device is in synchronous mode.
4. In order for the device to operate at 80Mhz/66Mhz/54Mhz, there is an additional wait state latency of 2/1/0 accordingly,
every 4 clock cycles with the first data being read.
Figure 25.3 CLK Synchronous Burst Mode Read
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12 cycles for initial access shown.
tCES
CE#
CLK
1
2
3
9
10
11
12
tAVC
AVD#
tAVD
tACS
Ac
Addresses
Data
tBACC
tACH
tIACC
DC
DD
DE
DF
D8
DB
tBDH
OE#
RDY
tCR
tRACC
tOE
tRACC
Hi-Z
tRDYS
Notes:
1. Figure shows total number of wait states set to twelve cycles. The total number of wait states can be programmed from
three cycles to thirteen cycles. Clock is set for active rising edge.
2. If any burst address occurs at address + 1, address + 2, ..., or address + 7, additional clock delay cycles are inserted,
and are indicated by RDY. The device is in synchronous mode with wrap around.
3. In order for the device to operate at 80Mhz/66Mhz/54Mhz, there is an additional wait state latency of 2/1/0 accordingly,
every 4 clock cycles with the first data being read.
4. D8–DF in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting
address in figure is the 4th address in range (O-F).
Figure 25.4 8-word Linear Burst with Wrap Around
12 cycles for initial access shown.
tCES
CE#
1
2
3
9
10
11
12
CLK
tAVC
AVD#
tAVD
tACS
AC
Addresses
Data
tBACC
tACH
tIACC
DC
DD
DE
DF
D10
D13
tBDH
OE#
RDY
tCR
tRACC
tRACC
tOE
Hi-Z
tRDYS
Notes:
1. Figure shows total number of wait states set to twelve cycles. The total number of wait states can be programmed from
three cycles to thirteen cycles. Clock is set for active rising edge.
2. If any burst address occurs at address + 1, address + 2, ..., or address + 7, additional clock delay cycles are inserted,
and are indicated by RDY.
3. In order for the device to operate at 80Mhz/66Mhz/54Mhz, there is an additional wait state latency of 2/1/0 accordingly,
every 4 clock cycles with the first data being read.
4. DC–D13 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest.
Starting address in figure is the 4th address in range (C-13).
Figure 25.5 8-word Linear Burst without Wrap Around
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D a t a S h e e t
tCEZ
12 wait cycles for initial access shown.
tCES
CE#
CLK
1
2
3
4
10
11
tAVC
AVD#
tAVD
tACS
Aa
Addresses
Data
tBACC
tACH
Hi-Z
tIACC
Da
Da+1
Da+2
Da+3
Da + n
tBDH
tOEZ
tRACC
OE#
tCR
tOE
Hi-Z
Hi-Z
RDY
tRDYS
Notes:
1. Figure assumes eleven wait states for initial access and synchronous read.
2. The Set Configuration Register command sequence has been written with A18=0; device will output RDY one cycle
before valid data.
Figure 25.6 Burst with RDY Set One Cycle Before Data
25.4 Asynchronous Mode Read @ VIO = 1.8 V
Parameter
Description
80 MHz 66 MHz 54 MHz Unit
JEDEC Standard
t
Access Time from CE# Low
Max
Max
Min
Min
Min
Max
Min
Min
Max
Min
148
143
8
ns
CE
t
Asynchronous Access Time (Note 1)
AVD# Low Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ACC
t
8
4
10
5
AVDP
t
Address Setup Time to Rising Edge of AVD#
Address Hold Time from Rising Edge of AVD#
Output Enable to Output Valid
4
AAVDS
AAVDH
t
2
2
3
t
9.1
0
11.2
0
13.5
0
OE
Read
Output Enable Hold Time
Data# Polling
t
OEH
10
10
0
10
10
0
10
10
0
t
Output Enable to High Z (Note 2)
CE# Setup Time to AVD#
OEZ
CAS
t
Notes:
1. Asynchronous Access Time is from the last of either stable addresses or the falling edge of AVD#.
2. Not 100% tested.
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25.5 Timing Diagrams
CE#
tOE
OE#
tOEH
WE#
Data
tCE
tOEZ
Valid RD
tACC
RA
Addresses
AVD#
tAAVDH
tCAS
tAVDP
tAAVDS
Note: RA = Read Address, RD = Read Data.
Figure 25.7 Asynchronous Mode Read with Latched Addresses
CE#
OE#
tOE
tOEH
WE#
Data
tCE
tOEZ
Valid RD
tACC
RA
Addresses
AVD#
Note: RA = Read Address, RD = Read Data.
Figure 25.8 Asynchronous Mode Read
25.6 Hardware Reset (RESET#)
Parameter
Description
All Speeds
Unit
JEDEC
Std
t
RESET# Pulse Width
Min
Min
Min
30
300
20
µs
µs
µs
RP
t
Reset High Time Before Read to Read Mode
RESET# Low to Standby Mode
RH
t
RPD
Note: Not 100% tested.
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D a t a S h e e t
CE#, OE#
RESET#
tRH
tRP
Reset Timings
Figure 25.9 Reset Timings
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25.7 Erase/Program Operations
Parameter
JEDEC Standard
Description
80 MHz 66 MHz 54 MHz Unit
t
t
Write Cycle Time (Note 1)
Min
Min
70
5
ns
ns
AVAV
WC
Synchronous
Asynchronous
Synchronous
Asynchronous
t
t
Address Setup Time (Notes 2, 3)
Address Hold Time (Notes 2, 3)
AVWL
AS
0
2
0
0
3
2
t
t
Min
ns
WLAX
AH
0
0
0
t
AVD# Low Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Max
Max
Max
Max
Typ
Typ
8
8
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
µs
AVDP
t
t
t
Data Setup Time
20
0
20
0
25
0
DVWH
WHDX
DS
DH
t
Data Hold Time
t
t
Read Recovery Time Before Write
CE# Setup Time to AVD#
CE# Hold Time
0
0
0
GHWL
GHWL
t
0
0
0
CAS
t
t
0
0
0
WHEH
WLWH
WHWL
CH
WP
t
t
t
Write Pulse Width
30
20
0
t
Write Pulse Width Highs
20
0
25
0
WPH
t
Latency Between Read and Write Operations
SR/W
t
V
V
V
Rise and Fall Time
500
1
VID
ACC
ACC
t
Setup Time (During Accelerated Programming)
VIDS
t
Setup Time
CC
50
5
VCS
t
t
CE# Setup Time to WE#
ELWL
CS
t
AVD# Setup Time to WE#
5
AVSW
AVHW
t
AVD# Hold Time to WE#
2
2
2
3
3
t
AVD# Setup Time to CLK
5
AVSC
t
AVD# Hold Time to CLK
2
AVHC
t
Clock Setup Time to WE#
5
CSW
t
Noise Pulse Margin on WE#
Sector Erase Accept Time-out
Erase Suspend Latency
3
WEP
t
50
20
20
100
1
SEA
t
ESL
PSL
ASP
t
Program Suspend Latency
t
Toggle Time During Sector Protection
Toggle Time During Programming Within a Protected Sector
t
PSP
Notes:
1. Not 100% tested.
2. Asynchronous read mode allows Asynchronous program operation only. Synchronous read mode allows both
Asynchronous and Synchronous program operation.
3. In asynchronous program operation timing, addresses are latched on the falling edge of WE#. In synchronous program
operation timing, addresses are latched on the rising edge of CLK.
4. See the Erase and Programming Performance section for more information. Does not include the preprogramming time.
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D a t a S h e e t
Program Command Sequence (last two cycles)
Read Status Data
V
IH
CLK
V
IL
tAVSW
tAVHW
tAVDP
AVD#
tAS
tAH
Addresses
Data
555h
PA
VA
VA
In
A0h
tDS
Complete
PD
Progress
tCAS
tDH
CE#
tCH
OE#
WE#
tWP
tWHWH1
tCS
tWPH
tWC
tVCS
VCC
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. In progress and complete refer to status of program operation.
3. Amax–A14 are don’t care during command sequence unlock cycles.
4. CLK can be either V or V
.
IH
IL
5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Configuration Register.
Figure 25.10 Asynchronous Program Operation Timings: WE# Latched Addresses
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D a t a S h e e t
Program Command Sequence (last two cycles)
tAVCH
Read Status Data
CLK
tAS
tAH
tAVSC
AVD#
tAVDP
Addresses
Data
PA
VA
VA
555h
In
Complete
A0h
PD
tDS
Progress
tCAS
tDH
CE#
tCH
OE#
WE#
tCSW
tWP
tWHWH1
tWPH
tWC
tVCS
VCC
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. In progress and complete refer to status of program operation.
3. Amax9–A14 are don’t care during command sequence unlock cycles.
4. Addresses are latched on the rising edge of CLK.
5. Either CE# or AVD# is required to go from low to high in between programming command sequences.
6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register.
The Configuration Register must be set to the Synchronous Read Mode.
Figure 25.11 Synchronous Program Operation Timings: CLK Latched Addresses
CE#
AVD#
WE#
Addresses
Data
PA
Don't Care
A0h
Don't Care
PD
Don't Care
OE#
ACC
tVIDS
V
V
ID
tVID
or V
IL
IH
Note: Use setup and hold times from conventional program operation.
Figure 25.12 Accelerated Unlock Bypass Programming Timing
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D a t a S h e e t
AVD#
CE#
tCEZ
tCE
tOEZ
tCH
tOE
OE#
WE#
tOEH
tACC
VA
High Z
High Z
Addresses
VA
Status Data
Status Data
Data
Notes:
1. Status reads in figure are shown as asynchronous.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is
completeData# Polling will output true data.
Figure 25.13 Data# Polling Timings (During Embedded Algorithm)
AVD#
tCEZ
tCE
CE#
tOEZ
tCH
tOE
OE#
WE#
tOEH
tACC
High Z
High Z
Addresses
VA
VA
Data
Status Data
Status Data
Notes:
1. Status reads in figure are shown as asynchronous.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is
complete, .
Figure 25.14 Toggle Bit Timings (During Embedded Algorithm)
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D a t a S h e e t
CE#
CLK
AVD#
Addresses
OE#
VA
VA
tIACC
tIACC
Data
Status Data
Status Data
RDY
Notes:
1. The timings are similar to synchronous read timings.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is
complete, .
3. RDY is active with data (D8 = 0 in the Configuration Register). When D8 = 1 in the Configuration Register, RDY is active
one clock cycle before data.
Figure 25.15 Synchronous Data Polling Timings/Toggle Bit Timings
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to
toggle DQ2 and DQ6.
Figure 25.16 DQ2 vs. DQ6
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D a t a S h e e t
Address boundary occurs every 512 words, beginning at address
0001FFh: (0002FFh, 0003FFh, etc.) Address 000000h is also a boundary crossing.
C508
C509
C510
C511
1FF
C511
1FF
C512
200
C513
201
C514
202
C515
203
CLK
1FC
(stays high)
1FD
1FE
Address (hex)
AVD#
RDY(1)
RDY(2)
tRACC
tRACC
latency
tRACC
tRACC
latency
Data
D508
D509
D510
D511
D512
D513
D514
OE#,
CE#
(stays low)
Notes:
1. RDY active with data (D8 = 0 in the Configuration Register).
2. RDY active one clock cycle before data (D8 = 1 in the Configuration Register).
3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60.
4. There will be an additional 4/8 wait state latency for 54/80 Mhz respectively.
Figure 25.17 Latency with Boundary Crossing
Data
D0
D1
Rising edge of next clock cycle
following last wait state triggers
AVD#
next burst data
total number of clock cycles
following AVD# falling edge
OE#
1
2
3
4
5
6
7
8
0
9
1
10
2
11
3
12
4
13
5
14
CLK
number of clock cycles
programmed
Wait State Configuration Register Setup
CR1.0, CR0.13, CR0.12, CR0.11= 1101
CR1.0, CR0.13, CR0.12, CR0.11= 1100
CR1.0, CR0.13, CR0.12, CR0.11= 1011
CR1.0, CR0.13, CR0.12, CR0.11= 1010
CR1.0, CR0.13, CR0.12, CR0.11= 1001
CR1.0, CR0.13, CR0.12, CR0.11= 1000
CR1.0, CR0.13, CR0.12, CR0.11= 0101
CR1.0, CR0.13, CR0.12, CR0.11= 0100
CR1.0, CR0.13, CR0.12, CR0.11= 0011
CR1.0, CR0.13, CR0.12, CR0.11= 0010
CR1.0, CR0.13, CR0.12, CR0.11= 0001
⇒
⇒
⇒
⇒
⇒
⇒
⇒
⇒
⇒
⇒
⇒
13 total
12 total
11 total
10 total
9 total
8 total
7 total
6 total
5 total
4 total
3 total
Note: Figure assumes address D0 is not at an address boundary.
Figure 25.18 Example of Wait States Insertion
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D a t a S h e e t
Last Cycle in
Program or
Sector Erase
Read status (at least two cycles) in same bank
and/or array data from other bank
Begin another
write or program
command sequence
Command Sequence
tWC
tRC
tRC
tWC
CE#
OE#
tOE
tOEH
tGHWL
WE#
Data
tOEZ
tWPH
tWP
tDS
tACC
tOEH
tDH
PD/30h
RD
RD
AAh
tSR/W
RA
Addresses
AVD#
PA/SA
tAS
RA
555h
tAH
Note: Breakpoints in waveforms indicate that system may alternately read the status of the program or erase operation in
the device. The system should read status twice to ensure valid information.
Figure 25.19 Back-to-Back Read/Write Cycle Timings
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D a t a S h e e t
26 Erase and Programming Performance
Typ
(Note 1)
Max
(Note 2)
Parameter
Unit
Comments
V
2
1
20
10
CC
Sector Erase Time
Chip Erase Time
256 Kword
s
ACC
Excludes 00h programming prior to
erasure (Note 4)
V
308
616
CC
s
ACC
262
524
V
<40
<400
<240
<94
CC
Excludes system level overhead
(Note 5)
Word Programming Time
µs
µs
µs
s
ACC
<24
V
<9.4
<6
CC
Effective Word Programming
Time utilizing Program Write Buffer
ACC
<60
V
<300
<192
<314.6
<201.4
<3000
<1920
<629.2
<402.6
CC
Total 32-Word BufferProgramming Time
ACC
V
CC
Excludes system level overhead
(Note 5)
Chip Programming Time (Note 3)
ACC
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 1.8 V V , 100,000 cycles typical. Additionally,
CC
programming typically assumes a checkerboard pattern.
2. Under worst case conditions of 90°C, V = 1.65 V, 100,000 cycles.
CC
3. The typical chip programming time is considerably less than the maximum chip programming time listed.
4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command.
See the Command Definitions table for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 100,000 cycles.
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CellularRAM
128/64/32 Megabit
Burst CellularRAM
Features
Single device supports asynchronous, page,
Low-Power Consumption
and burst operations
—
—
—
—
—
—
Asynchronous Read < 25mA
Intrapage Read < 15mA
Initial access, burst Read < 35mA
Continuous burst Read < 11mA
Standby: 180µA
VCC Voltages
—
1.70V–1.95V VCC
Random Access Time: 70ns
Burst Mode Write Access
Deep power-down < 10µA
—
Continuous burst
Low-Power Features
Burst Mode Read Access
—
Temperature Compensated Refresh (TCR) On-chip
sensor control
—
4, 8, or 16 words, or continuous burst
—
—
Partial Array Refresh (PAR)
Deep Power-Down (DPD) Mode
Page Mode Read Access
—
—
—
Sixteen-word page size
Interpage Read access: 70ns
Intrapage Read access: 20ns
General Description
CellularRAM™ products are High-speed, CMOS dynamic random access memories developed for low-
power, portable applications. These devices include an industry standard burst mode Flash interface that
dramatically increases Read/Write bandwidth compared with other low-power SRAM or Pseudo SRAM
offerings.
To operate seamlessly on a burst Flash bus, CellularRAM products incorporate a transparent self-refresh
mechanism. The hidden refresh requires no additional support from the system memory controller and
has no significant impact on device Read/Write performance.
Two user-accessible control registers define device operation. The bus configuration register (BCR) de-
fines how the CellularRAM device interacts with the system memory bus and is nearly identical to its
counterpart on burst mode Flash devices. The refresh configuration register (RCR) is used to control how
refresh is performed on the DRAM array. These registers are automatically loaded with default settings
during power-up and can be updated anytime during normal operation.
Special attention has been focused on standby current consumption during self refresh. CellularRAM prod-
ucts include three mechanisms to minimize standby current. Partial array refresh (PAR) enables the
system to limit refresh to only that part of the DRAM array that contains essential data. Temperature com-
pensated refresh (TCR) adjusts the refresh rate to match the device temperature—the refresh rate
decreases at lower temperatures to minimize current consumption during standby. Deep power-down
(DPD) enables the system to halt the refresh operation altogether when no vital information is stored in
the device. The system-configurable refresh mechanisms are accessed through the RCR.
Publication Number S75WS-N-00 Revision A Amendment 0 Issue Date February 17, 2005
A d v a n c e I n f o r m a t i o n
27 Functional Block Diagram
128M: A[22:0]
64M: A[21:0]
32M: A[20:0]
Address Decode
Logic
Input/
Output
MUX
and
Buffers
DQ[7:0]
DRAM
MEMORY
ARRAY
DQ[15:8]
Refresh Configuration
Register (RCR)
Bus Configuration
Register (BCR)
CE#
WE#
OE#
CLK
Control
Logic
ADV#
CRE
WAIT
LB#
UB#
Note: Functional block diagrams illustrate simplified device operation. See truth table, ball descriptions, and timing di-
agrams for detailed information.
Figure 27.1 Functional Block Diagram
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Table 27.1 Signal Descriptions
Symbol
Type
Description
128M: A[22:0]
64M: A[21:0]
32M: A[20:0]
Address Inputs: Inputs for addresses during Read and Write operations. Addresses are
internally latched during Read and Write cycles. The address lines are also used to define
the value to be loaded into the BCR or the RCR.
Input
Clock: Synchronizes the memory to the system operating frequency during synchronous
operations. When configured for synchronous operation, the address is latched on the first
rising CLK edge when ADV# is active. CLK is static (High or Low) during asynchronous
access Read and Write operations and during Page Read Access operations.
CLK
Input
Input
Address Valid: Indicates that a valid address is present on the address inputs. Addresses
can be latched on the rising edge of ADV# during asynchronous Read and Write operations.
ADV# can be held Low during asynchronous Read and Write operations.
ADV#
CRE
CE#
Input
Input
Configuration Register Enable: When CRE is High, Write operations load the RCR or BCR.
Chip Enable: Activates the device when Low. When CE# is High, the device is disabled and
goes into standby or deep power-down mode.
Output Enable: Enables the output buffers when Low. When OE# is High, the output buffers
are disabled.
OE#
WE#
Input
Input
Write Enable: Determines if a given cycle is a Write cycle. If WE# is Low, the cycle is a Write
to either a configuration register or to the memory array.
LB#
UB#
Input
Input
Lower Byte Enable. DQ[7:0]
Upper Byte Enable. DQ[15:8]
Input/
Output
DQ[15:0]
Data Inputs/Outputs.
Wait: Provides data-valid feedback during burst Read and Write operations. The signal is
gated by CE#. Wait is used to arbitrate collisions between refresh and Read/Write
operations. Wait is asserted when a burst crosses a row boundary. Wait is also used to mask
the delay associated with opening a new internal page. Wait is asserted and should be
ignored during asynchronous and page mode operations. Wait is High-Z when CE# is High.
Wait
VCC
Output
Supply
Supply
Supply
Supply
Device Power Supply: (1.7V–1.95V) Power supply for device core operation.
I/O Power Supply: (1.7V–1.95V) Power supply for input/output buffers.
VSS must be connected to ground.
VCC
VSS
SSQ
Q
V
VSSQ must be connected to ground.
Note: The CLK and ADV# inputs can be tied to V if the device is always operating in asynchronous or page mode.
SS
Wait will be asserted but should be ignored during asynchronous and page mode operations.
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A d v a n c e I n f o r m a t i o n
Table 27.2 Bus Operations—Asynchronous Mode
Clk
LB#/
UB#
Wait
(Note 2)
DQ[15:0]
(Note 3)
Mode
Read
Power
Active
Active
Standby
Idle
(Note 1) ADV#
CE#
L
OE#
L
WE#
CRE
Notes
4
X
X
X
X
L
L
H
L
L
L
L
L
L
L
Low-Z
Low-Z
High-Z
Low-Z
Data-Out
Data-In
High-Z
X
Write
L
X
4
Standby
No Operation
X
X
H
X
X
X
X
X
5, 6
4, 6
L
X
Configuration
Register
Active
X
X
L
L
H
X
L
H
X
X
X
Low-Z
High-Z
High-Z
High-Z
Deep
Power-down
DPD
X
H
X
7
Notes:
1. CLK may be High or Low, but must be static during synchronous Read, synchronous Write, burst suspend, and DPD modes; and to achieve
standby power during standby and active modes.
2. The Wait polarity is configured through the bus configuration register (BCR[10]).
3. When LB# and UB# are in select mode (Low), DQ[15:0] are affected. When only LB# is in select mode, DQ[7:0] are affected. When only
UB# is in the select mode, DQ[15:8] are affected.
4. The device will consume active power in this mode whenever addresses are changed.
5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence.
6.
V
= V Q or 0V; all device balls must be static (unswitched) to achieve standby current.
IN CC
7. DPD is maintained until RCR is reconfigured.
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Table 27.3 Bus Operations—Burst Mode
CLK
(Note 1) ADV#
LB#/
UB#
Wait
(Note 2)
DQ[15:0]
(Note 3)
Mode
Power
Active
Active
Standby
Idle
CE#
L
OE#
L
WE#
CRE
Notes
4
Async Read
Async Write
Standby
X
X
X
X
L
L
H
L
L
L
L
L
L
Low-Z
Low-Z
High-Z
Low-Z
Data-Out
Data-In
High-Z
X
L
X
L
4
X
X
H
X
X
X
X
5, 6
4, 6
No Operation
L
X
X
Initial Burst Read
Initial Burst Write
Active
Active
L
L
L
L
X
H
H
L
L
L
L
Low-Z
Low-Z
Data-Out
Data-In
4, 8
4, 8
X
Data-In or
Data-Out
Burst Continue
Burst Suspend
Active
Active
Active
H
X
L
L
L
L
X
H
H
X
X
L
L
L
X
X
X
Low-Z
Low-Z
Low-Z
4, 8
4, 8
8
X
X
High-Z
High-Z
Configuration
Register
H
Deep
Power-Down
DPD
X
H
X
X
X
X
High-Z
High-Z
7
Notes:
1. CLK may be High or Low, but must be static during asynchronous Read, synchronous Write, burst suspend, and DPD modes; and to achieve
standby power during standby and active modes.
2. The Wait polarity is configured through the bus configuration register (BCR[10]).
3. When LB# and UB# are in select mode (Low), DQ[15:0] are affected. When only LB# is in select mode, DQ[7:0] are affected. When only
UB# is in the select mode, DQ[15:8] are affected.
4. The device will consume active power in this mode whenever addresses are changed.
5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence.
6.
V
= V Q or 0V; all device balls must be static (unswitched) to achieve standby current.
IN CC
7. DPD is maintained until RCR is reconfigured.
8. Burst mode operation is initialized through the bus configuration register (BCR[15]).
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A d v a n c e I n f o r m a t i o n
28 Functional Description
The CellularRAM bus interface supports both asynchronous and burst mode transfers. Page mode
accesses are also included as a bandwidth-enhancing extension to the asynchronous Read
protocol.
28.1 Power-Up Initialization
CellularRAM products include an on-chip voltage sensor used to launch the power-up initialization
process. Initialization will configure the BCR and the RCR with their default settings (see
Table 31.1 and Table 31.5). VCC and VCCQ must be applied simultaneously. When they reach a sta-
ble level at or above 1.7V, the device will require 150 µs to complete its self-initialization process.
During the initialization period, CE# should remain High. When initialization is complete, the de-
vice is Ready for normal operation.
>
150 μs
VCC = 1.7 V
tPU
Device ready for
normal operation
VCC
VCCQ
Device Initialization
Figure 28.2 Power-Up Initialization Timing
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A d v a n c e I n f o r m a t i o n
29 Bus Operating Modes
CellularRAM products incorporate a burst mode interface found on Flash products targeting low-
power, wireless applications. This bus interface supports asynchronous, page mode, and burst
mode Read and Write transfers. The specific interface supported is defined by the value loaded
into the BCR. Page mode is controlled by the refresh configuration register (RCR[7]).
29.1 Asynchronous Mode
CellularRAM products power up in the asynchronous operating mode. This mode uses the industry
standard SRAM control bus (CE#, OE#, WE#, LB#/ UB#). Read operations (Figure 29.1) are ini-
tiated by bringing CE#, OE#, and LB#/UB# Low while keeping WE# High. Valid data will be driven
out of the I/Os after the specified access time has elapsed. Write operations (Figure 29.2) occur
when CE#, WE#, and LB#/ UB# are driven Low. During asynchronous Write operations, the OE#
level is a don't care, and WE# will override OE#. The data to be written is latched on the rising
edge of CE#, WE#, or LB#/UB# (whichever occurs first). Asynchronous operations (page mode
disabled) can either use the ADV input to latch the address, or ADV can be driven Low during the
entire Read/Write operation.
During asynchronous operation, the CLK input must be held static (High or Low, no transitions).
Wait will be driven while the device is enabled and its state should be ignored.
CE#
OE#
WE#
ADDRESS
Address Valid
Data Valid
DATA
LB#/UB#
t
RC
= READ Cycle Time
Don't Care
Note: ADV must remain Low for page mode operation.
Figure 29.1 Read Operation (ADV# Low)
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A d v a n c e I n f o r m a t i o n
CE#
OE#
WE#
ADDRESS
Address Valid
Data Valid
DATA
LB#/UB#
t
= WRITE Cycle Time
WC
Don't Care
Figure 29.2 Write Operation (ADV# Low)
29.2 Page Mode Read Operation
Page mode is a performance-enhancing extension to the legacy asynchronous Read operation. In
page mode-capable products, an initial asynchronous Read access is performed, then adjacent
addresses can be Read quickly by simply changing the low-order address. Addresses A[3:0] are
used to determine the members of the 16-address CellularRAM page. Addresses A[4] and higher
must remain fixed during the entire page mode access. Figure 29.3 shows the timing for a page
mode access. Page mode takes advantage of the fact that adjacent addresses can be Read in a
shorter period of time than random addresses. Write operations do not include comparable page
mode functionality.
During asynchronous page mode operation, the CLK input must be held Low. CE# must be driven
High upon completion of a page mode access. Wait will be driven while the device is enabled and
its state should be ignored. Page mode is enabled by setting RCR[7] to High. Write operations do
not include comparable page mode functionality. ADV must be driven Low during all page mode
Read accesses.
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A d v a n c e I n f o r m a t i o n
CE#
OE#
WE#
ADDRESS
ADD[0]
ADD[1] ADD[2] ADD[3]
t
AA
t
t
t
APA
APA
APA
D[0]
D[1]
D[2]
D[3]
DATA
LB#/UB#
Don't Care
Figure 29.3 Page Mode Read Operation (ADV# Low)
29.3 Burst Mode Operation
Burst mode operations enable High-speed synchronous Read and Write operations. Burst opera-
tions consist of a multi-clock sequence that must be performed in an ordered fashion. After CE#
goes Low, the address to access is latched on the rising edge of the next clock that ADV# is Low.
During this first clock rising edge, WE# indicates whether the operation is going to be a Read
(WE# = High, Figure 29.4) or Write (WE# = Low, Figure 29.5).
The size of a burst can be specified in the BCR either as a fixed length or continuous. Fixed-length
bursts consist of four, eight, or sixteen words. Continuous bursts have the ability to start at a
specified address and burst through the entire memory.
The latency count stored in the BCR defines the number of clock cycles that elapse before the
initial data value is transferred between the processor and CellularRAM device.
The Wait output asserts as soon as a burst is initiated, and de-asserts to indicate when data is to
be transferred into (or out of) the memory. Wait will again be asserted if the burst crosses a row
boundary. Once the CellularRAM device has restored the previous row's data and accessed the
next row, Wait will be deasserted and the burst can continue (see Figure 34.9).
To access other devices on the same bus without the timing penalty of the initial latency for a new
burst, burst mode can be suspended. Bursts are suspended by stopping CLK. CLK can be stopped
High or Low. If another device will use the data bus while the burst is suspended, OE# should be
taken High to disable the CellularRAM outputs; otherwise, OE# can remain Low. Note that the
Wait output will continue to be active, and as a result no other devices should directly share the
Wait connection to the controller. To continue the burst sequence, OE# is taken Low, then CLK is
restarted after valid data is available on the bus.
See How Extended Timings Impact CellularRAM™ Operation for restrictions on the maximum CE#
Low time during burst operations. If a burst suspension will cause CE# to remain Low for longer
than tCEM, CE# should be taken High and the burst restarted with a new CE# Low/ADV# low
cycle.
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A d v a n c e I n f o r m a t i o n
CLK
A[22:0]
ADV#
Address
Valid
Latency Code 2 (3 clocks), variable
CE#
OE#
WE#
WAIT
DQ[15:0]
LB#/UB#
D[0]
D[1]
D[2]
D[3]
Legend:
READ Burst Identified
(WE# = HIGH)
Don't care
Undefined
Note: Non-default BCR settings: Variable latency; latency code two (three clocks); Wait active Low; Wait asserted dur-
ing delay.
Figure 29.4 Burst Mode Read (4-word burst)
CLK
Address
Valid
A[22:0]
ADV#
Latency Code 2 (3 clocks), variable
CE#
OE#
WE#
WAIT
DQ[15:0]
LB#/UB#
D[0]
D[1]
D[2]
D[3]
Legend:
Don't care
WRITE Burst Identified
(WE# = LOW)
Note: Non-default BCR settings: Variable latency; latency code two (three clocks); Wait active Low; Wait asserted dur-
ing delay.
Figure 29.5 Burst Mode Write (4-word burst)
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29.4 Mixed-Mode Operation
The device can support a combination of synchronous Read and asynchronous Write operations
when the BCR is configured for synchronous operation. The asynchronous Write operation re-
quires that the clock (CLK) remain static (High or Low) during the entire sequence. The ADV#
signal can be used to latch the target address, or it can remain Low during the entire Write oper-
ation. CE# can remain Low when transitioning between mixed-mode operations with fixed latency
enabled. Note that the tCKA period is the same as a Read or Write cycle. This time is required to
ensure adequate refresh. Mixed-mode operation facilitates a seamless interface to legacy burst
mode Flash memory controllers. See Figure 34.18, Asynchronous Write Followed by Burst Read
(timing diagram).
29.5 Wait Operation
The Wait output on a CellularRAM device is typically connected to a shared, system-level Wait sig-
nal (Figure 29.6). The shared Wait signal is used by the processor to coordinate transactions with
multiple memories on the synchronous bus.
External
Pull-Up/
Pull-Down
Resistor
CellularRAM
WAIT
READY
WAIT
WAIT
Other
Other
Device
Device
Processor
Figure 29.6 Wired or Wait Configuration
Once a Read or Write operation has been initiated, Wait goes active to indicate that the Cellular-
RAM device requires additional time before data can be transferred. For Read operations, Wait will
remain active until valid data is output from the device. For Write operations, Wait will indicate to
the memory controller when data will be accepted into the CellularRAM device. When Wait tran-
sitions to an inactive state, the data burst will progress on successive clock edges.
CE# must remain asserted during Wait cycles (Wait asserted and Wait configuration BCR[8] = 1).
Bringing CE# High during Wait cycles may cause data corruption. (Note that for BCR[8] = 0, the
actual Wait cycles end one cycle after Wait de-asserts, and for row boundary crossings, start one
cycle after the Wait signal asserts.)
When using variable initial access latency (BCR[14] = 0), the Wait output performs an arbitration
role for Read or Write operations launched while an on-chip refresh is in progress. If a collision
occurs, the Wait pin is asserted for additional clock cycles until the refresh has completed
(Figure 29.7 and Figure 29.8). When the refresh operation has completed, the Read or Write op-
eration will continue normally.
Wait is also asserted when a continuous Read or Write burst crosses the boundary between 128-
word rows. The Wait assertion allows time for the new row to be accessed, and permits any pend-
ing refresh operations to be performed.
Wait will be asserted but should be ignored during asynchronous Read and Write, and page Read
operations.
29.6 LB#/UB# Operation
The LB# enable and UB# enable signals support byte-wide data transfers. During Read opera-
tions, the enabled byte(s) are driven onto the DQs. The DQs associated with a disabled byte are
put into a High-Z state during a Read operation. During Write operations, any disabled bytes will
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not be transferred to the RAM array and the internal value will remain unchanged. During an asyn-
chronous Write cycle, the data to be written is latched on the rising edge of CE#, WE#, LB#, or
UB#, whichever occurs first.
When both the LB# and UB# are disabled (High) during an operation, the device will disable the
data bus from receiving or transmitting data. Although the device will seem to be deselected, it
remains in an active mode as long as CE# remains Low.
V
V
IH
IL
CLK
A[22:0]
ADV#
V
V
IH
IL
Address
Valid
V
V
IH
IL
V
V
IH
IL
CE#
OE#
V
V
IH
IL
V
V
IH
IL
WE#
V
V
IH
IL
LB#/UB#
High-Z
V
V
OH
OL
WAIT
V
V
OH
OL
DQ[15:0]
D[0]
D[1]
D[2]
D[3]
Additional WAIT states inserted to allow refresh completion.
Legend:
Don't care
Undefined
Note: Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay.
Figure 29.7 Refresh Collision During Read Operation
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V
V
IH
IL
CLK
A[22:0]
ADV#
V
V
IH
IL
Address
Valid
V
V
IH
IL
V
V
IH
IL
CE#
OE#
V
V
IH
IL
V
V
IH
IL
WE#
V
V
IH
IL
LB#/UB#
High-Z
V
V
OH
OL
WAIT
V
V
OH
OL
DQ[15:0]
D[0]
D[1]
D[2]
D[3]
Additional WAIT states inserted to allow refresh completion.
Legend:
Don't care
Note: Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay.
Figure 29.8 Refresh Collision During Write Operation
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30 Low-Power Operation
30.1 Standby Mode Operation
During standby, the device current consumption is reduced to the level necessary to perform the
DRAM refresh operation. Standby operation occurs when CE# is High.
The device will enter a reduced power state upon completion of a Read or Write operation, or
when the address and control inputs remain static for an extended period of time. This mode will
continue until a change occurs to the address or control inputs.
30.2 Temperature Compensated Refresh
Temperature compensated refresh (TCR) is used to adjust the refresh rate depending on the de-
vice operating temperature. DRAM technology requires increasingly frequent refresh operation to
maintain data integrity as temperatures increase. More frequent refresh is required due to in-
creased leakage of the DRAM capacitive storage elements as temperatures rise. A decreased
refresh rate at lower temperatures will facilitate a savings in standby current.
TCR allows for adequate refresh at four different temperature thresholds (+15°C, +45°C, +70°C,
and +85°C). The setting selected must be for a temperature higher than the case temperature
of the CellularRAM device. For example, if the case temperature is 50°C, the system can minimize
self refresh current consumption by selecting the +7°0C setting. The +15°C and +45°C settings
would result in inadequate refreshing and cause data corruption.
30.3 Partial Array Refresh
Partial array refresh (PAR) restricts refresh operation to a portion of the total memory array. This
feature enables the device to reduce standby current by refreshing only that part of the memory
array required by the host system. The refresh options are full array, one-half array, one-quarter
array, three-quarter array, or none of the array. The mapping of these partitions can start at either
the beginning or the end of the address map (Table 31.6). Read and Write operations to address
ranges receiving refresh will not be affected. Data stored in addresses not receiving refresh will
become corrupted. When re-enabling additional portions of the array, the new portions are avail-
able immediately upon writing to the RCR.
30.4 Deep Power-Down Operation
Deep power-down (DPD) operation disables all refresh-related activity. This mode is used if the
system does not require the storage provided by the CellularRAM device. Any stored data will be-
come corrupted when DPD is enabled. When refresh activity has been re-enabled by rewriting the
RCR, the CellularRAM device will require 150µs to perform an initialization procedure before nor-
mal operations can resume. During this 150µs period, the current consumption will be higher than
the specified standby levels, but considerably lower than the active current specification.
DPD cannot be enabled or disabled by writing to the RCR using the software access sequence;
the RCR should be accessed using CRE instead.
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31 Configuration Registers
Two user-accessible configuration registers define the device operation. The bus configuration
register (BCR) defines how the CellularRAM interacts with the system memory bus and is nearly
identical to its counterpart on burst mode Flash devices. The refresh configuration register (RCR)
is used to control how refresh is performed on the DRAM array. These registers are automatically
loaded with default settings during power-up, and can be updated any time the devices are op-
erating in a standby state.
31.1 Access Using CRE
The configuration registers can be written to using either a synchronous or an asynchronous op-
eration when the configuration register enable (CRE) input is High (see Figure 31.1 and
Figure 31.2). When CRE is Low, a Read or Write operation will access the memory array. The reg-
ister values are written via address pins A[21:0]. In an asynchronous Write, the values are
latched into the configuration register on the rising edge of ADV#, CE#, or WE#, whichever oc-
curs first; LB# and UB# are Don’t Care. The BCR is accessed when A[19] is High; the RCR is
accessed when A[19] is Low. For Reads, address inputs other than A[19] are Don’t Care, and reg-
ister bits 15:0 are output on DQ[15:0].
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A[22:0]
(except A19)
ADDRESS
ADDRESS
OPCODE
t
t
AVH
AVS
Select Control Register
A19
(Note)
CRE
t
AVS
t
AVH
t
VPH
ADV#
t
VP
t
CBPH
Initiate Control Register Access
CE#
OE#
t
CW
t
WP
Write Address
Bus Value to
Control Register
WE#
LB#/UB#
DQ[15:0]
DATA VALID
Legend:
Don't care
Note: A[19] = Low to load RCR; A[19] = High to load BCR.
Figure 31.1 Configuration Register Write, Asynchronous Mode Followed by Read
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CLK
Latch Control Register Value
OPCODE
A[22:0]
(except A19)
ADDRESS
ADDRESS
t
HD
Latch Control Register Address
t
SP
SP
A19
(Note 2)
t
CRE
t
t
HD
t
SP
ADV#
HD
t
CBPH
(Note 3)
t
CSP
CE#
OE#
t
SP
WE#
t
HD
LB#/UB#
t
CEW
WAIT
High-Z
High-Z
DATA
VALID
DQ[15:0]
Legend:
Don't care
Notes:
1. Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay.
2. A[19] = Low to load RCR; A[19] = High to load BCR.
3. CE# must remain Low to complete a burst-of-one Write. Wait must be monitored—additional Wait cycles caused by refresh collisions
require a corresponding number of additional CE# Low cycles.
Figure 31.2 Configuration Register Write, Synchronous Mode Followed by Read0
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31.2 Bus Configuration Register
The BCR defines how the CellularRAM device interacts with the system memory bus. Page mode
operation is enabled by a bit contained in the RCR. Table 31.1 below describes the control bits in
the BCR. At powerup, the BCR is set to 9D4Fh.
The BCR is accessed using CRE and A[19] High.
Table 31.1 Bus Configuration Register Definition
A[22:20]
A19
A[18:16]
A15
A14
A13 A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2 A1 A0
22–20
19
18–16
15
14
13 12
11
10
9
8
7
6
5
4
3
2
1
0
Burst
Wrap
Impedance (BW)
(Note)
Burst
Length
(BL)
WAIT
Register
Select
Operating
Mode
Initial
Latency
Latency
Counter
WAIT
Polarity
Output
Reserved
Reserved
Reserved Configuration Reserved Reserved
(WC)
(Note)
All must be set to "0"
Must be set to "0"
Must be set to "0"
Must be set to "0"
Must be set to "0"
Setting is ignored
Output Impedance
BCR[5] BCR[4]
0
0
1
1
0
1
0
1
Full Drive (default)
1/2 Drive
1/4 Drive
Reserved
BCR[13] BCR[12] BCR[11]
Latency Counter
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Code 0–Reserved
Code 1–Reserved
Code 2
BCR[3]
Burst Wrap (Note)
0
1
Burst wraps within the burst length
Burst no wrap (default)
Code 3 (Default)
Code 4
Code 5
Code 6
Code 7–Reserved
BCR[8]
WAIT Configuration
Asserted during delay
0
1
Asserted one data cycle before delay (default)
BCR[10] WAIT Polarity
0
1
Active LOW
Active HIGH (default)
BCR[15]
Operating Mode
Burst Length (Note)
BCR[2] BCR[1] BCR[0]
0
1
Synchronous burst access mode
Asynchronous access mode (default)
0
0
0
1
0
1
0
1
1
4 words
1
8 words
1
16 words
Register Select
BCR[19]
1
Continuous burst (default)
0
1
Select RCR
Select BCR
Others
Reserved
Note: Burst wrap and length apply to Read operations only.
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Table 31.2 Sequence and Burst Length
4-word
Burst
Address Length 8-word Burst Length
Starting
Burst Wrap
16-word Burst Length
Continuous Burst
BCR[3] Wrap (Decimal) Linear
Linear
Linear
Linear
0
1
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15
1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0
2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1
3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2
4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3
5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4
6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5
7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6
…
0-1-2-3-4-5-6-…
1-2-3-4-5-6-7-…
2-3-4-5-6-7-8-…
3-4-5-6-7-8-9-…
4-5-6-7-8-9-10-…
5-6-7-8-9-10-11-…
6-7-8-9-10-11-12-…
7-8-9-10-11-12-13-…
…
2
3
4
5
0
Yes
6
7
…
14
15
0
14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13
15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15
1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16
2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-17
3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18
4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-19
5-6-7-8-9-10-11-12-13-…-15-16-17-18-19-20
14-15-16-17-18-19-20-…
15-16-17-18-19-20-21…
0-1-2-3-4-5-6-…
1-2-3-4-5-6-7-…
2-3-4-5-6-7-8-…
3-4-5-6-7-8-9-…
4-5-6-7-8-9-10-…
5-6-7-8-9-10-11…
6-7-8-9-10-11-12…
7-8-9-10-11-12-13…
…
0-1-2-3
1-2-3-4
2-3-4-5
3-4-5-6
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-8
2-3-4-5-6-7-8-9
3-4-5-6-7-8-9-10
4-5-6-7-8-9-10-11
5-6-7-8-9-10-11-12
1
2
3
4
5
1
No
6
6-7-8-9-10-11-12-13 6-7-8-9-10-11-12-13-14-…-16-17-18-19-20-21
7
7-8-9-10-11-12-13-14
7-8-9-10-11-12-13-14-…-17-18-19-20-21-22
…
…
14
15
14-15-16-17-18-19-…-23-24-25-26-27-28-29
5-16-17-18-19-20-…-24-25-26-27-28-29-30
14-15-16-17-18-19-20-…
15-16-17-18-19-20-21-…
31.2.1 Burst Length (BCR[2:0]): Default = Continuous Burst
Burst lengths define the number of words the device outputs during burst Read operations. The
device supports a burst length of 4, 8, or 16 words. The device can also be set in continuous burst
mode where data is accessed sequentially without regard to address boundaries. Enabling burst
no-wrap with BCR[3] = 1 overrides the burst-length setting.
31.2.2 Burst Wrap (BCR[3]): Default = No Wrap
The burst-wrap option determines if a 4-, 8-, or 16-word Read burst wraps within the burst length
or steps through sequential addresses. If the wrap option is not enabled, the device accesses data
from sequential addresses without regard to burst boundaries. When continuous burst operation
is selected, the internal address wraps to 000000h if the burst goes past the last address. En-
abling burst nowrap (BCR[3] = 1) overrides the burst-length setting.
31.2.3 Output Impedance (BCR[5:4]): Default = Outputs Use Full Drive
Strength
The output driver strength can be altered to full, one-half, or one-quarter strength to adjust for
different data bus loading scenarios. The reduced-strength options are intended for stacked chip
(Flash + CellularRAM) environments when there is a dedicated memory bus. The reduced-drive-
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strength option minimizes the noise generated on the data bus during Read operations. Normal
output drive strength should be selected when using a discrete CellularRAM device in a more
heavily loaded data bus environment. Outputs are configured at full drive strength during testing.
Table 31.3 Output Impedance
BCR[5]
BCR[4]
DRIVE STRENGTH
0
0
1
1
0
1
0
1
Full
1/2
1/4
Reserved
31.2.4 Wait Configuration (BCR[8]): Default = Wait Transitions One
Clock Before Data Valid/Invalid
The Wait configuration bit is used to determine when Wait transitions between the asserted and
the de-asserted state with respect to valid data presented on the data bus. The memory controller
will use the Wait signal to coordinate data transfer during synchronous Read and Write operations.
When BCR[8] = 0, data will be valid or invalid on the clock edge immediately after Wait transitions
to the de-asserted or asserted state, respectively (Figure 31.3 and Figure 31.5). When A8 = 1,
the Wait signal transitions one clock period prior to the data bus going valid or invalid
(Figure 31.4).
31.2.5 Wait Polarity (BCR[10]): Default = Wait Active High
The Wait polarity bit indicates whether an asserted Wait output should be High or Low. This bit
will determine whether the Wait signal requires a pull-up or pull-down resistor to maintain the de-
asserted state.
CLK
WAIT
High-Z
DQ[15:0]
Data[0]
Data[1]
Data immediately valid (or invalid)
Note: Data valid/invalid immediately after Wait transitions (BCR[8] = 0). See Figure 31.5.
Figure 31.3 Wait Configuration (BCR[8] = 0)
CLK
WAIT
High-Z
DQ[15:0]
Data[0]
Data valid (or invalid) after one clock delay
Note: Valid/invalid data delayed for one clock after Wait transitions (BCR[8] = 1). See Figure 31.5.
Figure 31.4 Wait Configuration (BCR[8] = 1)
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CLK
BCR[8]
= 0
WAIT
DATA VALID IN CURRENT CYCLE
BCR[8]
= 1
WAIT
DATA VALID IN NEXT CYCLE
DQ[15:0]
D[0]
D[1]
D[2]
D[3]
D[4]
Legend:
Don't care
Note: Non-default BCR setting: Wait active Low.
Figure 31.5 Wait Configuration During Burst Operation
31.2.6 Latency Counter (BCR[13:11]): Default = Three-Clock Latency
The latency counter bits determine how many clocks occur between the beginning of a Read or
Write operation and the first data value transferred. Latency codes from two (three clocks) to six
(seven clocks) are allowed (see Table 31.4 and Figure 31.6 below).
Table 31.4 Variable Latency Configuration Codes
Latency (Note)
Max Input Clk Frequency (MHz)
Latency Configuration
Code
BCR[13:11]
010
Normal
Refresh Collision
70 ns/80 MHz
85 ns/66 MHz
2 (3 clocks)
3 (4 clocks)—default
4 (5 clocks)
2
3
4
4
6
8
75 (13.0 ns)
44 (22.7 ns)
011
80 (12.5 ns)
66 (15.2 ns)
100
Note: Latency is the number of clock cycles from the initiation of a burst operation until data appears. Data is trans-
ferred on the next clock cycle.
V
IH
CLK
V
IL
V
IH
A[21:0]
Valid Address
V
IL
V
IH
ADV#
A/DQ[15:0]
A/DQ[15:0]
A/DQ[15:0]
V
IL
Code 2
Code 3
Code 4
V
V
OH
OL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
(Default)
V
V
OH
OL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
V
OH
Valid
Output
Valid
Output
Valid
Output
V
OL
Legend:
Don't care
Undefined
Figure 31.6 Latency Counter (Variable Initial Latency, No Refresh Collision)
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31.2.7 Operating Mode (BCR[15]): Default = Asynchronous Operation
The operating mode bit selects either synchronous burst operation or the default asynchronous
mode of operation.
31.3 Refresh Configuration Register
The refresh configuration register (RCR) defines how the CellularRAM device performs its trans-
parent self refresh. Altering the refresh parameters can dramatically reduce current consumption
during standby mode. Page mode control is also embedded into the RCR. Table 31.5 below de-
scribes the control bits used in the RCR. At power-up, the RCR is set to 0070h. The RCR is
accessed using CRE and A[19] Low.
Table 31.5 Refresh Configuration Register Mapping
A[22:20]
A19
A[18:8]
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus
22–20
Reserved
19
18–8
Reserved
7
6
5
4
3
2
1
0
Read Configuration
Register
Register
Select
Page
TCR
DPD
Reserved
PAR
Must be set to "0"
All must be set to "0"
All must be set to "0"
RCR[19] Register Select
RCR[2] RCR[1] RCR[0] Refresh Coverage
0
1
Select RCR
Select BCR
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Full array (default)
Bottom 1/2 array
Bottom 1/4 array
Bottom 1/8 array
None of array
RCR[7]
Page Mode Enable/Disable
Page Mode Disabled (default)
Page Mode Enable
0
1
Top 1/2 array
Top 1/4 array
Maximum Case Temp
RCR[6]
RCR[5]
Top 3/4 array
1
1
0
1
0
+85ºC (default)
+70ºC
0
0
1
RCR[4]
Deep Power-Down
DPD Enable
+45ºC
0
1
+15ºC
DPD Disable (default)
31.3.1 Partial Array Refresh (RCR[2:0]): Default = Full Array Refresh
The PAR bits restrict refresh operation to a portion of the total memory array. This feature allows
the device to reduce standby current by refreshing only that part of the memory array required
by the host system. The refresh options are full array, one-half array, one-quarter array, three-
quarters array, or none of the array. The mapping of these partitions can start at either the be-
ginning or the end of the address map (see Table 31.6 through Table 31.8).
Table 31.6 128Mb Address Patterns for PAR (RCR[4] = 1)
RCR[2]
RCR[1]
RCR[0]
Active Section
Full die
Address Space
000000h–7FFFFFh
000000h–3FFFFFh
000000h–1FFFFFh
000000h–0FFFFFh
0
Size
Density
128Mb
64Mb
32Mb
16Mb
0Mb
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
8 Meg x 16
4 Meg x 16
2 Meg x 16
1 Meg x 16
0 Meg x 16
4 Meg x 16
One-half of die
One-quarter of die
One-eighth of die
None of die
One-half of die
400000h–7FFFFFh
64Mb
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Table 31.6 128Mb Address Patterns for PAR (RCR[4] = 1) (Continued)
RCR[2]
RCR[1]
RCR[0]
Active Section
One-quarter of die
One-eighth of die
Address Space
Size
Density
32Mb
16Mb
1
1
1
1
0
1
600000h–7FFFFFh
700000h–7FFFFFh
2 Meg x 16
1 Meg x 16
Table 31.7 64Mb Address Patterns for PAR (RCR[4] = 1)
RCR[2]
RCR[1]
RCR[0]
Active Section
Full die
Address Space
000000h–3FFFFFh
000000h–2FFFFFh
000000h–1FFFFFh
000000h–0FFFFFh
0
Size
Density
64Mb
48Mb
32Mb
16Mb
0Mb
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4 Meg x 16
3 Meg x 16
2 Meg x 16
1 Meg x 16
0 Meg x 16
3 Meg x 16
2 Meg x 16
1 Meg x 16
One-half of die
One-quarter of die
One-eighth of die
None of die
One-half of die
One-quarter of die
One-eighth of die
100000h–3FFFFFh
200000h–3FFFFFh
300000h–3FFFFFh
48Mb
32Mb
16Mb
Table 31.8 32Mb Address Patterns for PAR (RCR[4] = 1)
RCR[2]
RCR[1]
RCR[0]
ACTIVE SECTION
Full die
ADDRESS SPACE
000000h–1FFFFFh
000000h–17FFFFh
000000h–0FFFFFh
000000h–07FFFFh
0
SIZE
DENSITY
32Mb
24Mb
16Mb
8Mb
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2 Meg x 16
1.5 Meg x 16
1 Meg x 16
512K x 16
0 Meg x 16
1.5 Meg x 16
1 Meg x 16
512K x 16
One-half of die
One-quarter of die
One-eighth of die
None of die
0Mb
One-half of die
One-quarter of die
One-eighth of die
080000h–1FFFFFh
100000h–1FFFFFh
180000h–1FFFFFh
24Mb
16Mb
8Mb
31.3.2 Deep Power-Down (RCR[4]): Default = DPD Disabled
The deep power-down bit enables and disables all refresh-related activity. This mode is used if
the system does not require the storage provided by the CellularRAM device. Any stored data will
become corrupted when DPD is enabled. When refresh activity has been re-enabled, the Cellular-
RAM device will require 150µs to perform an initialization procedure before normal operations can
resume.
Deep power-down is enabled when RCR[4] = 0, and remains enabled until RCR[4] is set to 1.
31.3.3 Temperature Compensated Refresh (RCR[6:5]): Default = +85ºC
Operation
The TCR bits allow for adequate refresh at four different temperature thresholds (+15ºC, +45ºC,
+70ºC, and +85ºC). The setting selected must be for a temperature higher than the case tem-
perature of the CellurlarRAM device. If the case temperature is +50ºC, the system can minimize
self refresh current consumption by selecting the +70ºC setting. The +15ºC and +45ºC settings
would result in inadequate refreshing and cause data corruption.
February 17, 2005 S75WS-N-00_A0
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31.3.4 Page Mode Operation (RCR[7]): Default = Disabled
The page mode operation bit determines whether page mode is enabled for asynchronous Read
operations. In the power-up default state, page mode is disabled.
166
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32 Absolute Maximum Ratings
Voltage to Any Ball Except VCC, VCC
Q
. . . . . . . . . . . . . . . . . . . . . . . . . . . . Relative to VSS-0.50V to (4.0V or VCCQ + 0.3V, whichever is less)
Voltage on VCC Supply Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2V to +2.45V
Voltage on VCCQ Supply Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2V to +2.45V
Storage Temperature (plastic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55ºC to +150ºC
Operating Temperature (case)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wireless-25ºC to +85ºC
Note: *Stresses greater than those listed may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at these or any other conditions above those indi-
cated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
February 17, 2005 S75WS-N-00_A0
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A d v a n c e I n f o r m a t i o n
33 DC Characteristics
Table 33.1 Electrical Characteristics and Operating Conditions
Description
Conditions
Symbol
Min
1.70
Max
1.95
Units
V
Notes
Supply Voltage
VCC
W: 1.8V
J: 1.5V
1.70
1.95
V
I/O Supply Voltage
VCCQ
1.35
1.65
V
Input High Voltage
Input Low Voltage
VIH
VIL
VCCQ - 0.4
-0.20
VCCQ + 0.2
0.4
V
2
3
4
4
V
Output High Voltage
Output Low Voltage
Input Leakage Current
IOH = -0.2mA
IOL = +0.2mA
VOH
VOL
ILI
0.80 VCC
Q
V
0.20 VCC
Q
V
VIN = 0 to VCC
Q
1
µA
OE# = VIH or
Chip Disabled
Output Leakage Current
ILO
1
µA
Operating Current
-70
-85
25
20
Asynchronous Random Read
Asynchronous Page Read
Initial Access, Burst Read
Continuous Burst Read
V
IN = VCCQ or 0V
Chip Enabled,
IOUT = 0
ICC
1
mA
5
5
-70
-85
15
12
80 MHz
66 MHz
80 MHz
66 MHz
-70
35
V
IN = VCCQ or 0V
Chip Enabled,
IOUT = 0
30
ICC1
mA
18
15
25
VIN = VCCQ or 0V
Chip Enabled
Write Operating Current
ICC2
mA
µA
-85
20
128 M
64 M
180
120
110
VIN = VCCQ or 0V
Standby Current
ISB
6
CE# = VCC
Q
32 M
Notes:
1. Wireless Temperature (-25ºC < TC < +85ºC); Industrial Temperature (-40ºC < TC < +85ºC).
2. Input signals may overshoot to V Q + 1.0V for periods less than 2ns during transitions.
CC
3. Input signals may undershoot to V - 1.0V for periods less than 2ns during transitions.
SS
4. BCR[5:4] = 00b.
5. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add the current required to drive
output capacitance expected in the actual system.
6. ISB (MAX) values measured with PAR set to FULL ARRAY and TCR set to +85°C. To achieve Low standby current, all inputs must be driven
to either V Q or V
.
CC
SS
168
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A d v a n c e I n f o r m a t i o n
Table 33.2 Temperature Compensated Refresh Specifications and Conditions
Standard
Power
Tem pe r ature (No Desig.)
Max Case
Description
Conditions
Symbol
Density
Units
+85
+70
+45
+15
+85
+70
+45
+15
°
°
°
°
°
°
°
°
C
C
C
C
C
C
C
C
120
105
85
64 Mb
70
Temperature Compensated
Refresh Standby Current
VIN = VCCQ or 0V,
ITCR
µA
CE# = VCC
Q
110
95
32 Mb
80
70
Note: I
(MAX) values measured with TCR set to 85°C.
PAR
Table 33.3 Partial Array Refresh Specifications and Conditions
Standard
Power
Array
Description
Conditions
Symbol
Density
Partition
Full
1/2
1/4
1/8
0
(No Desig.)
Units
120
115
110
105
70
64 Mb
Full
1/2
1/4
1/8
0
110
105
100
95
Partially Array Refresh Standby
Current
VIN = VCCQ or 0V,
IPAR
µA
CE# = VCC
Q
32 Mb
70
Full
0
180
50
128 Mb
Note:IPAR (MAX) values measured with TCR set to 85°C.
Table 33.4 Deep Power-Down Specifications
Description
Conditions
Symbol
Typ
Units
µA
Deep Power-down
VIN = VCCQ or 0V; +25°C; VCC = 1.8V
IZZ
10
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A d v a n c e I n f o r m a t i o n
34 AC Characteristics
V
CC
Q
V
Q
/2
V
Q/2
CC
(Note 2)
CC
Input
(Note 1)
Output
Test Points
(Note 3)
V
SS
Notes:
1. AC test inputs are driven at V Q for a logic 1 and V for a logic 0. Input rise and fall times (10% to 90%) < 1.6ns.
CC
SS
2. Input timing begins at V Q/2.
CC
3. Output timing ends at V Q/2.
CC
Figure 34.1 AC Input/Output Reference Waveform
V
Q
CC
R1
Test Point
DUT
30pF
R2
Note: All tests are performed with the outputs configured for full drive strength (BCR[5] = 0).
Figure 34.2 Output Load Circuit
Table 34.1 Output Load Circuit
V
Q
R1/R2
2.7K
CC
1.8V
Ω
170
S75WS256Nxx Based MCPs
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Table 34.2 Asynchronous Read Cycle Timing Requirements
85ns/66 MHz
70ns/80 MHz
Units
Notes
Parameter
Address Access Time
Symbol
tAA
Min
Max
85
Min
Max
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADV# Access Time
tAADV
tAPA
tAVH
tAVS
tBA
85
70
Page Access Time
25
20
Address Hold from ADV# High
Address Setup to ADV# High
LB#/UB# Access Time
5
5
10
10
85
8
70
8
LB#/UB# Disable to DQ High-Z Output
LB#/UB# Enable to Low-Z Output
CE# High between Subsequent Mixed-Mode Operations
Maximum CE# Pulse Width
CE# Low to Wait Valid
tBHZ
tBLZ
tCBPH
tCEM
tCEW
tCO
4
3
10
5
10
5
4
4
2
1
10
10
5
7.5
85
1
10
10
5
7.5
70
Chip Select Access Time
CE# Low to ADV# High
tCVS
tHZ
Chip Disable to DQ and Wait High-Z Output
Chip Enable to Low-Z Output
Output Enable to Valid Output
Output Hold from Address Change
Output Disable to DQ High-Z Output
Output Enable to Low-Z Output
Page Cycle Time
8
20
8
8
20
8
4
3
tLZ
tOE
tOH
tOHZ
tOLZ
tPC
4
3
5
5
25
85
10
10
20
70
10
10
Read Cycle Time
tRC
ADV# Pulse Width Low
tVP
ADV# Pulse Width High
tVPH
Notes:
1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0).
2. See How Extended Timings Impact CellularRAM™ Operation below.
3. High-Z to Low-Z timings are tested with the circuit shown in Figure 34.2. The Low-Z timings measure a
4. 100mV transition away from the High-Z (V Q/2) level toward either V or V
.
OL
CC
OH
5. Low-Z to High-Z timings are tested with the circuit shown in Figure 34.2. The High-Z timings measure a 100mV transition from either V
OH
or V toward V Q/2.
OL
CC
February 17, 2005 S75WS-N-00_A0
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A d v a n c e I n f o r m a t i o n
Table 34.3 Burst Read Cycle Timing Requirements
70ns/80 MHz
85ns/66 MHz
Parameter
Burst to Read Access Time (Variable Latency)
CLK to Output Delay
Symbol
tABA
tACLK
tAVS
tBOE
tCBPH
tCEW
tCLK
tCSP
tHD
Min
Max
35
9
Min
Max
55
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
11
Address Setup to ADV# High
Burst OE# Low to Output Delay
CE# High between Subsequent Mixed-Mode Operations
CE# Low to Wait Valid
10
10
20
20
5
1
5
1
7.5
7.5
CLK Period
12.5
4
15
5
CE# Setup Time to Active CLK Edge
Hold Time from Active CLK Edge
Chip Disable to DQ and Wait High-Z Output
CLK Rise or Fall Time
2
2
tHZ
8
1.6
9
8
1.6
11
8
2
tKHKL
tKHTL
tKHZ
tKLZ
tKOH
tKP
CLK to Wait Valid
CLK to DQ High-Z Output
3
2
2
3
8
3
2
2
3
CLK to Low-Z Output
5
5
Output Hold from CLK
CLK High or Low Time
Output Disable to DQ High-Z Output
Output Enable to Low-Z Output
Setup Time to Active CLK Edge
tOHZ
tOLZ
tSP
8
8
2
3
5
3
5
3
Notes:
1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0).
2. Low-Z to High-Z timings are tested with the circuit shown in Figure 34.2. The High-Z timings measure a 100mV transition from either V
OH
or V toward V Q/2.
OL
CC
3. High-Z to Low-Z timings are tested with the circuit shown in Figure 34.2. The Low-Z timings measure a 100mV transition away from the
High-Z (V Q/2) level toward either V or V
.
OL
CC
OH
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Table 34.4 Asynchronous Write Cycle Timing Requirements
70 ns/80 MHz
85 ns/66 MHz
Parameter
Address and ADV# Low Setup Time
Address Hold from ADV# Going High
Address Setup to ADV# Going High
Address Valid to End of Write
LB#/UB# Select to End of Write
Maximum CE# Pulse Width
CE# Low to Wait Valid
Symbol
tAS
Min
0
Max
Min
0
Max
Units
ns
Notes
tAVH
tAVS
tAW
5
5
ns
10
70
70
10
85
85
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tBW
tCEM
tCEW
tCKA
tCVS
tCW
tDH
4
4
1
1
7.5
1
7.5
Async Address-to-Burst Transition Time
CE# Low to ADV# High
70
10
70
0
85
10
85
0
Chip Enable to End of Write
Data Hold from Write Time
Data Write Setup Time
tDW
tHZ
23
23
1
Chip Disable to Wait High-Z Output
Chip Enable to Low-Z Output
End Write to Low-Z Output
ADV# Pulse Width
8
8
tLZ
10
5
10
5
3
3
tOW
tVP
tVPH
tVS
10
10
70
70
10
10
85
85
ADV# Pulse Width High
ADV# Setup to End of Write
Write Cycle Time
tWC
tWHZ
tWP
Write to DQ High-Z Output
Write Pulse Width
8
8
2
1
46
10
0
55
10
0
Write Pulse Width High
tWPH
tWR
Write Recovery Time
Notes:
1. See How Extended Timings Impact CellularRAM™ Operation below.
2. Low-Z to High-Z timings are tested with the circuit shown in Figure 34.2. The High-Z timings measure a 100mV transition from either V
OH
or V toward V Q/2.
OL
CC
3. High-Z to Low-Z timings are tested with the circuit shown in Figure 34.2. The Low-Z timings measure a 100mV transition away from the
High-Z (V Q/2) level toward either V
or V
.
CC
OH
OL
February 17, 2005 S75WS-N-00_A0
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A d v a n c e I n f o r m a t i o n
Table 34.5 Burst Write Cycle Timing Requirements
70ns/80 MHz
85ns/66 MHz
Parameter
CE# High between Subsequent Mixed-Mode Operations
CE# Low to Wait Valid
Symbol
tCBPH
tCEW
tCLK
tCSP
tHD
Min
5
Max
Min
5
Max
Units
ns
Notes
1
7.5
1
7.5
ns
Clock Period
12.5
4
15
5
ns
CE# Setup to CLK Active Edge
Hold Time from Active CLK Edge
Chip Disable to Wait High-Z Output
CLK Rise or Fall Time
ns
2
2
ns
tHZ
8
1.6
9
8
ns
tKHKL
tKHTL
tKP
1.6
11
ns
Clock to Wait Valid
ns
CLK High or Low Time
3
3
3
3
ns
Setup Time to Activate CLK Edge
tSP
ns
34.1 Timing Diagrams
V
(MIN)
CC
V
, V Q = 1.7V
CC CC
t
PU
Device ready for
normal operation
Figure 34.3 Initialization Period
Table 34.1 Initialization Timing Parameters
70ns/80 MHz
85ns/66 MHz
Parameter
Symbol
Min
Max
Min
Max
Units
Notes
Initialization Period (required before normal operations)
tPU
150
150
µs
174
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A d v a n c e I n f o r m a t i o n
t
RC
V
V
IH
IL
VALID ADDRESS
A[22:0]
t
AA
V
V
IH
IL
ADV#
CE#
t
t
CBPH
HZ
V
V
IH
IL
t
CO
t
t
BHZ
BA
V
V
IH
IL
LB#/UB#
t
t
OHZ
OE
V
V
V
V
IH
IL
IH
IL
OE#
WE#
t
OLZ
t
BLZ
t
LZ
V
V
OH
OL
High-Z
DQ[15:0]
VALID OUTPUT
t
t
HZ
CEW
V
V
IH
IL
High-Z
High-Z
WAIT
Legend:
Don't Care
Undefined
Figure 34.4 Asynchronous Read
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A d v a n c e I n f o r m a t i o n
Table 34.2 Asynchronous Read Timing Parameters
70ns/80 MHz
85ns/66 MHz
Symbol
tAA
Min
Max
70
70
8
Min
Max
85
85
8
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tBA
tBHZ
tBLZ
tCBPH
tCEW
tCO
10
5
10
5
1
7.5
70
8
1
7.5
8
tHZ
tLZ
10
10
tOE
20
8
20
8
tOHZ
tOLZ
tRC
5
5
70
85
176
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A d v a n c e I n f o r m a t i o n
V
V
IH
IL
A[22:0]
VALID ADDRESS
t
AA
t
t
AVH
AVS
t
VPH
V
V
IH
IL
ADV#
t
AADV
t
VP
t
t
CVS
t
CBPH
HZ
V
V
IH
IL
CE#
t
CO
t
t
BHZ
BA
V
V
IH
IL
LB#/UB#
t
t
OHZ
OE
V
V
V
V
IH
IL
IH
IL
OE#
WE#
t
OLZ
t
BLZ
t
LZ
V
V
OH
OL
High-Z
DQ[15:0]
VALID OUTPUT
t
t
HZ
CEW
V
V
IH
IL
High-Z
High-Z
WAIT
Legend:
Don't Care
Undefined
Figure 34.5 Asynchronous Read Using ADV#
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A d v a n c e I n f o r m a t i o n
Table 34.3 Asynchronous Read Timing Parameters Using ADV#
70ns/80 MHz
85ns/66 MHz
Symbol
tAA
Min
Max
70
Min
Max
85
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAADV
tCVS
tAVH
tAVS
tBA
70
85
10
5
10
5
10
10
70
8
85
8
tBHZ
tBLZ
tCBPH
tCEW
tCO
10
5
10
5
1
7.5
70
1
7.5
85
tCVS
tHZ
10
10
10
10
8
8
tLZ
tOE
20
8
20
8
tOHZ
tOLZ
tVP
5
5
10
10
10
10
tVPH
178
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A d v a n c e I n f o r m a t i o n
t
RC
V
V
IH
IL
A[22:0]
A[3:0]
VALID ADDRESS
V
V
IH
IL
VALID
VALID
VALID
ADDRESS
VALID ADDRESS
ADDRESS
ADDRESS
t
t
PC
AA
V
V
IH
IL
ADV#
t
t
CEM
CBPH
t
t
t
CBPH
CO
HZ
V
V
IH
IL
CE#
t
t
BHZ
BA
V
V
IH
IL
LB#/UB#
t
t
OHZ
OE
V
V
V
V
IH
IL
IH
IL
OE#
WE#
t
OLZ
t
t
APA
BLZ
t
t
OH
LZ
V
V
OH
OL
High-Z
t
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
DQ[15:0]
t
HZ
CEW
V
V
IH
IL
High-Z
High-Z
WAIT
Legend:
Don't Care
Undefined
Figure 34.6 Page Mode Read
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A d v a n c e I n f o r m a t i o n
Table 34.4 Asynchronous Read Timing Parameters—Page Mode Operation
70ns/80 MHz
85ns/66 MHz
Symbol
tAA
Min
Max
70
20
70
8
Min
Max
85
25
85
8
Units
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAPA
tBA
tBHZ
tBLZ
tCBPH
tCEM
tCEW
tCO
10
5
10
5
4
7.5
70
8
4
7.5
85
8
1
1
tHZ
tLZ
10
5
10
5
tOE
20
8
20
8
tOH
tOHZ
tOLZ
tPC
5
5
20
70
25
85
tRC
180
S75WS256Nxx Based MCPs
S75WS-N-00_A0 February 17, 2005
A d v a n c e I n f o r m a t i o n
t
t
KP
t
KP
CLK
V
V
IH
IL
CLK
t
KHKL
t
t
SP
HD
V
V
IH
IL
A[22:0]
ADV#
VALID ADDRESS
t
t
SP
HD
V
V
IH
IL
t
HD
t
t
HZ
t
ABA
CSP
V
V
IH
IL
CE#
OE#
t
t
OHZ
BOE
V
V
IH
IL
t
OLZ
t
t
SP
SP
HD
V
V
IH
IL
WE#
t
t
HD
V
V
IH
IL
LB#/UB#
t
CEW
t
KHTL
V
V
OH
OL
High-Z
High-Z
WAIT
t
t
KOH
ACLK
V
V
OH
OL
High-Z
DQ[15:0]
VALID OUTPUT
Legend:
Don't Care
Undefined
READ Burst Identified
(WE# = HIGH)
Note: Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay.
Figure 34.7 Single-Access Burst Read Operation—Variable Latency
February 17, 2005 S75WS-N-00_A0
S75WS256Nxx Based MCPs
181
A d v a n c e I n f o r m a t i o n
Table 34.5 Burst Read Timing Parameters—Single Access, Variable Latency
70ns/80 MHz
85ns/66 MHz
Symbol
tABA
tACLK
tBOE
tCEW
tCLK
tCSP
tHD
Min
Max
35
9
Min
Max
55
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11
20
7.5
20
1
12.5
4
1
15
5
7.5
2
2
tHZ
8
1.6
9
8
tKHKL
tKHTL
tKOH
tKP
1.6
11
2
3
2
3
tOHZ
tOLZ
tSP
8
8
5
3
5
3
182
S75WS256Nxx Based MCPs
S75WS-N-00_A0 February 17, 2005
A d v a n c e I n f o r m a t i o n
t
CLK
t
t
t
KP
KHKL
KP
V
V
IH
IL
CLK
t
t
SP
HD
V
V
IH
IL
Valid
Address
A[22:0]
ADV#
CE#
t
t
SP
HD
V
V
IH
IL
t
t
t
t
HD
CSP
ABA
CBPH
V
V
IH
IL
t
HZ
t
t
OHZ
BOE
V
V
IH
IL
OE#
t
OLZ
t
t
t
SP
HD
HD
V
V
IH
IL
WE#
t
SP
V
V
IH
IL
LB#/UB#
t
t
CEW
KHTL
V
V
OH
OL
High-Z
High-Z
WAIT
t
KOH
t
ACLK
V
V
OH
OL
High-Z
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
DQ[15:0]
Legend:
READ Burst Identified
(WE# = HIGH)
Don't Care
Undefined
Note: Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay.
Figure 34.8 Four-word Burst Read Operation—Variable Latency
February 17, 2005 S75WS-N-00_A0
S75WS256Nxx Based MCPs
183
A d v a n c e I n f o r m a t i o n
Table 34.6 Burst Read Timing Parameters—4-word Burst
70ns/80 MHz
85ns/66 MHz
Symbol
tABA
tACLK
tBOE
tCBPH
tCEW
tCLK
tCSP
tHD
Min
Max
35
9
Min
Max
55
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11
20
20
5
1
5
1
7.5
7.5
12.5
4
15
5
2
2
tHZ
8
1.6
9
8
tKHKL
tKHTL
tKOH
tKP
1.6
11
2
3
2
3
tOHZ
tOLZ
tSP
8
8
5
3
5
3
184
S75WS256Nxx Based MCPs
S75WS-N-00_A0 February 17, 2005
A d v a n c e I n f o r m a t i o n
t
CLK
V
V
IH
IL
CLK
t
t
SP
HD
V
V
IH
IL
Valid
Address
A[22:0]
ADV#
CE#
t
t
SP
HD
V
V
IH
IL
t
t
t
HD
CSP
CBPH
V
V
IH
IL
t
HZ
t
t
OHZ
BOE
V
V
IH
IL
OE#
t
OLZ
t
t
t
SP
HD
HD
V
V
IH
IL
WE#
t
SP
V
V
IH
IL
LB#/UB#
t
t
CEW
KHTL
V
V
OH
OL
High-Z
High-Z
WAIT
t
KOH
t
ACLK
t
t
t
KHTL
KHTL
KHTL
V
V
OH
OL
High-Z
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
DQ[15:0]
High-Z
Legend:
READ Burst Identified
(WE# = HIGH)
Don't Care
Undefined
Note: Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay.
Figure 34.9 Four-word Burst Read Operation (with LB#/UB#)
February 17, 2005 S75WS-N-00_A0
S75WS256Nxx Based MCPs
185
A d v a n c e I n f o r m a t i o n
Table 34.7 Burst Read Timing Parameters—4-word Burst with LB#/UB#
70ns/80 MHz
85ns/66 MHz
Symbol
tACLK
tBOE
tCBPH
tCEW
tCLK
tCSP
tHD
Min
Max
9
Min
Max
11
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
20
5
1
5
1
7.5
7.5
12.5
4
15
5
2
2
tHZ
8
9
8
5
8
11
8
tKHTL
tKHZ
tKLZ
3
2
2
3
2
2
5
tKOH
tOHZ
tOLZ
tSP
8
8
5
3
5
3
186
S75WS256Nxx Based MCPs
S75WS-N-00_A0 February 17, 2005
A d v a n c e I n f o r m a t i o n
t
CLK
V
V
IH
IL
CLK
t
t
SP
HD
V
V
IH
IL
Valid
Address
Valid
Address
A[22:0]
t
t
HD
SP
V
V
IH
IL
ADV#
t
CBPH
t
t
t
CSP
HZ
V
V
IH
IL
CE#
OE#
t
OHZ
OHZ
(Note 2)
V
V
IH
IL
t
t
t
SP
HD
HD
V
V
IH
IL
WE#
t
SP
V
V
IH
IL
LB#/UB#
t
t
CEW
BOE
t
OLZ
High-Z
V
V
High-Z
IH
IL
WAIT
t
KOH
t
BOE
t
ACLK
t
OLZ
V
V
OH
OL
High-Z
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
DQ[15:0]
Legend:
Don't Care
Undefined
Notes:
1. Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay.
2. OE# can stay Low during burst suspend. If OE# is Low, DQ[15:0] will continue to output valid data.
Figure 34.10 Refresh Collision During Write Operation
Table 34.8 Burst Read Timing Parameters—Burst Suspend
70ns/80 MHz
85ns/66 MHz
Symbol
tACLK
tBOE
tCBPH
tCLK
Min
Max
9
Min
Max
11
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
20
5
12.5
4
5
15
5
tCSP
tHD
2
2
tHZ
8
8
8
8
tKOH
tOHZ
tOLZ
2
5
2
5
February 17, 2005 S75WS-N-00_A0
S75WS256Nxx Based MCPs
187
A d v a n c e I n f o r m a t i o n
Table 34.8 Burst Read Timing Parameters—Burst Suspend (Continued)
70ns/80 MHz
85ns/66 MHz
Symbol
Min
Max
Min
Max
Units
tSP
3
3
ns
V
CLK
V
IH
IL
t
CLK
V
IH
IL
A[22:0]
V
V
V
IH
IL
ADV#
V
V
IH
IL
LB#/UB#
V
V
IH
IL
CE#
OE#
WE#
V
V
IH
IL
V
V
IH
IL
t
t
KHTL
KHTL
V
V
OH
OL
(Note 2)
WAIT
t
t
KOH
ACLK
V
V
OH
OL
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
DQ[15:0]
Legend:
Don't Care
Notes:
1. Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay.
2. Wait will assert LC + 1 or 2LC + 1 cycles for variable latency (depending upon refresh status).
Figure 34.9. Continuous Burst Read Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition
Table 34.10 Burst Read Timing Parameters—BCR[8] = 0
70ns/80 MHz
85ns/66 MHz
Symbol
tACLK
tCLK
Min
12.5
2
Max
Min
15
2
Max
Units
ns
9
11
ns
tKHTL
tKOH
9
11
ns
ns
188
S75WS256Nxx Based MCPs
S75WS-N-00_A0 February 17, 2005
A d v a n c e I n f o r m a t i o n
t
AA
V
V
IH
IL
A[22:0]
VALID ADDRESS
t
AW
t
t
AS
WR
V
V
IH
IL
ADV#
t
CEM
t
CW
V
V
IH
IL
CE#
t
BW
V
V
IH
IL
LB#/UB#
OE#
V
V
IH
IL
t
t
WP
WPH
V
V
IH
IL
WE#
t
t
DH
DW
High-Z
V
V
IH
IL
DQ[15:0]
IN
VALID
INPUT
t
t
WHZ
LZ
V
V
OH
OL
DQ[15:0]
OUT
t
HZ
t
CEW
High-Z
V
V
IH
IL
High-Z
WAIT
Legend:
Don't Care
Figure 34.11 CE#-Controlled Asynchronous Write
February 17, 2005 S75WS-N-00_A0
S75WS256Nxx Based MCPs
189
A d v a n c e I n f o r m a t i o n
Table 34.11 Asynchronous Write Timing Parameters—CE#-Controlled
70ns/80 MHz
85ns/66 MHz
Symbol
tAS
Min
0
Max
Min
0
Max
Units
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAW
70
70
85
85
tBW
tCEM
tCEW
tCW
tDH
4
4
1
70
0
7.5
1
85
0
7.5
tDW
tHZ
23
23
8
8
8
8
tLZ
10
70
10
85
tWC
tWHZ
tWP
tWPH
tWR
46
10
0
55
10
0
190
S75WS256Nxx Based MCPs
S75WS-N-00_A0 February 17, 2005
A d v a n c e I n f o r m a t i o n
t
WC
V
V
IH
IL
A[22:0]
VALID ADDRESS
t
AW
t
t
AS
WR
V
V
IH
IL
ADV#
t
CEM
t
CW
V
V
IH
IL
CE#
t
BW
V
V
IH
IL
LB#/UB#
OE#
V
V
IH
IL
t
t
WP
WPH
V
V
IH
IL
WE#
t
t
DH
DW
High-Z
V
V
IH
IL
DQ[15:0]
IN
VALID
INPUT
t
t
WHZ
LZ
V
V
OH
OL
DQ[15:0]
OUT
t
HZ
t
CEW
High-Z
V
V
IH
IL
High-Z
WAIT
Legend:
Don't Care
Figure 34.12 LB#/UB#-Controlled Asynchronous Write
February 17, 2005 S75WS-N-00_A0
S75WS256Nxx Based MCPs
191
A d v a n c e I n f o r m a t i o n
Table 34.12 Asynchronous Write Timing Parameters—LB#/UB#-Controlled
70ns/80 MHz
85ns/66 MHz
Symbol
tAS
Min
0
Max
Min
0
Max
Units
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAW
70
70
85
85
tBW
tCEM
tCEW
tCW
tDH
4
4
1
70
0
7.5
1
85
0
7.5
tDW
tHZ
23
23
8
8
8
8
tLZ
10
70
10
85
tWC
tWHZ
tWP
tWPH
tWR
46
10
0
55
10
0
192
S75WS256Nxx Based MCPs
S75WS-N-00_A0 February 17, 2005
A d v a n c e I n f o r m a t i o n
t
WC
V
V
IH
IL
A[22:0]
VALID ADDRESS
t
AW
t
WR
V
V
IH
IL
ADV#
t
CEM
t
CW
V
V
IH
IL
CE#
t
BW
V
V
IH
IL
LB#/UB#
OE#
V
V
IH
IL
t
AS
t
t
WP
WPH
V
V
IH
IL
WE#
t
t
DH
DW
High-Z
V
V
IH
IL
DQ[15:0]
IN
VALID
INPUT
t
t
t
OW
LZ
WHZ
V
V
OH
OL
DQ[15:0]
OUT
t
t
CEW
HZ
V
V
IH
IL
High-Z
High-Z
WAIT
Legend:
Don't Care
Figure 34.13 WE#-Controlled Asynchronous Write
February 17, 2005 S75WS-N-00_A0
S75WS256Nxx Based MCPs
193
A d v a n c e I n f o r m a t i o n
Table 34.13 Asynchronous Write Timing Parameters—WE#-Controlled
70ns/80 MHz
85ns/66 MHz
Symbol
tAS
Min
0
Max
Min
0
Max
Units
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAW
70
70
85
85
tBW
tCEM
tCEW
tCW
tDH
4
4
1
70
0
7.5
1
85
0
7.5
tDW
tHZ
23
23
8
8
8
8
tLZ
10
5
10
5
tOW
tWC
tWHZ
tWP
70
85
46
10
0
55
10
0
tWPH
tWR
194
S75WS256Nxx Based MCPs
S75WS-N-00_A0 February 17, 2005
A d v a n c e I n f o r m a t i o n
V
V
IH
IL
A[22:0]
VALID ADDRESS
t
t
AVH
AVS
t
VS
t
t
VP
VPH
t
AS
V
V
IH
IL
ADV#
t
AS
t
AW
t
CEM
t
CW
V
V
IH
IL
CE#
t
BW
V
V
IH
IL
LB#/UB#
OE#
V
V
IH
IL
t
t
WPH
WP
V
V
IH
IL
WE#
t
t
DH
DW
High-Z
V
V
IH
IL
DQ[15:0]
IN
VALID
INPUT
t
t
t
OW
LZ
WHZ
V
V
OH
OL
DQ[15:0]
OUT
t
t
CEW
HZ
V
V
IH
IL
High-Z
High-Z
WAIT
Legend:
Don't Care
Figure 34.14 Asynchronous Write Using ADV#
February 17, 2005 S75WS-N-00_A0
S75WS256Nxx Based MCPs
195
A d v a n c e I n f o r m a t i o n
Table 34.14 Asynchronous Write Timing Parameters Using ADV#
70ns/80 MHz
85ns/66 MHz
Symbol
tAS
Min
0
Max
Min
0
Max
Units
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVH
tAVS
tAW
tBW
tCEM
tCEW
tCW
tDH
5
5
10
70
70
10
85
85
4
4
1
70
0
7.5
1
85
0
7.5
tDW
tHZ
23
23
8
8
tLZ
10
5
10
5
tOW
tAS
0
0
tVP
10
10
70
10
10
85
tVPH
tVS
tWHZ
tWP
8
8
46
10
55
10
tWPH
196
S75WS256Nxx Based MCPs
S75WS-N-00_A0 February 17, 2005
A d v a n c e I n f o r m a t i o n
t
KHKL
t
t
KP
t
KP
CLK
V
V
IH
IL
CLK
t
t
SP
HD
V
V
IH
IL
Valid
Address
A[22:0]
ADV#
t
t
SP
HD
V
V
IH
IL
t
SP
t
HD
V
V
IH
IL
LB#/UB#
t
t
CSP
t
HD
CBPH
V
V
IH
IL
CE#
OE#
V
V
IH
IL
t
t
SP
HD
V
V
IH
IL
WE#
t
HZ
t
t
CEW
KHTL
High-Z
V
V
(Note 2)
IH
IL
High-Z
WAIT
t
t
HD
SP
V
V
OH
OL
DQ[15:0]
D[1]
D[2]
D[3]
D[0]
Legend:
READ Burst Identified
(WE# = LOW)
Don't Care
Notes:
1. Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay; burst length four; burst wrap
enabled.
Figure 34.15 Burst Write Operation
February 17, 2005 S75WS-N-00_A0
S75WS256Nxx Based MCPs
197
A d v a n c e I n f o r m a t i o n
Table 34.15 Burst Write Timing Parameters
70ns/80 MHz
85ns/66 MHz
Symbol
tCBPH
tCEW
tCLK
tCSP
tHD
Min
5
Max
Min
5
Max
Units
ns
1
7.5
1
7.5
ns
12.5
4
15
5
ns
ns
2
2
ns
tHZ
8
1.6
9
8
ns
tKHKL
tKHTL
tKP
1.6
11
ns
ns
3
3
3
3
ns
tSP
ns
V
CLK
V
IH
IL
t
CLK
V
IH
IL
A[22:0]
V
V
V
IH
IL
ADV#
V
V
IH
IL
LB#/UB#
V
V
IH
IL
CE#
V
V
IH
IL
WE#
V
V
IH
IL
OE#
t
t
KHTL
KHTL
(Note 2)
V
V
OH
OL
WAIT
t
t
HD
SP
V
V
OH
OL
Valid Input
D[n+3]
Valid Input
D[n+2]
Valid Input Valid Input
D[n] D[n+1]
DQ[15:0]
Legend:
Don't Care
END OF ROW
Notes:
1. Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay.
2. Wait will assert LC + 1 or 2LC + 1 cycles for variable latency (depending upon refresh status).
Figure 34.16 Continuous Burst Write Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition
198
S75WS256Nxx Based MCPs
S75WS-N-00_A0 February 17, 2005
A d v a n c e I n f o r m a t i o n
Table 34.16 Burst Write Timing Parameters—BCR[8] = 0
70ns/80 MHz
85ns/66 MHz
Symbol
tCLK
Min
12.5
2
Max
Min
15
2
Max
Units
ns
tHD
ns
tKHTL
tSP
8
3
11
3
ns
ns
t
CLK
V
V
IH
IL
CLK
t
t
t
t
t
t
HD
SP
SP
HD
V
V
IH
IL
Valid
Address
Valid
Address
A[22:0]
SP
t
t
HD
SP
HD
V
V
IH
IL
ADV#
t
t
HD
SP
V
V
IH
IL
LB#/UB#
CE#
t
t
t
HD
CSP
CBPH
V
V
IH
IL
(Note 2)
t
CSP
t
OHZ
V
V
IH
IL
OE#
t
SP
t
t
HD
t
SP
HD
V
V
IH
IL
WE#
t
BOE
V
V
High-Z
High-Z
OH
OL
WAIT
t
t
t
t
HD
ACLK
KOH
SP
V
V
V
High-Z
IH
IL
High-Z
OH
OL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
DQ[15:0]
D[0]
D[1]
D[2]
D[3]
V
Legend:
Don't Care
Undefined
Notes:
1. Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay.
1. To allow self-refresh operations to occur between transactions, CE# must remain High for at least 5ns (t
) to schedule the appropriate
CBPH
internal refresh operation. CE# can stay Low between burst Read and burst Write operations. See How Extended Timings Impact
CellularRAM™ Operation for restrictions on the maximum CE# Low time (t ).
CEM
Figure 34.17 Burst Write Followed by Burst Read
Table 34.17 Write Timing Parameters—Burst Write Followed by Burst Read
70ns/80 MHz
85ns/66 MHz
Symbol
tCBPH
tCLK
Min
5
Max
Min
5
Max
Units
ns
12.5
4
20
20
15
5
20
20
ns
tCSP
ns
tHD
2
2
ns
tSP
3
3
ns
February 17, 2005 S75WS-N-00_A0
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199
A d v a n c e I n f o r m a t i o n
Table 34.18 Read Timing Parameters—Burst Write Followed by Burst Read
70ns/80 MHz
85ns/66 MHz
Symbol
tACLK
tBOE
tCLK
Min
Max
Min
Max
ns
Units
9
11
20
20
ns
ns
ns
ns
ns
ns
ns
12.5
15
5
tCSP
tHD
4
2
2
2
tKOH
tOHZ
tSP
2
8
8
3
3
t
CLK
V
V
IH
IL
CLK
t
t
t
t
t
HD
WC
WC
CKA
SP
V
V
IH
IL
Valid
Address
Valid
Address
Valid
Address
A[22:0]
t
t
t
t
WR
AVS
AVH
AW
t
t
HD
t
SP
VPH
V
V
IH
IL
ADV#
t
t
t
VP
VS
t
t
t
BW
SP
HD
CVS
V
V
IH
IL
LB#/UB#
CE#
t
t
t
CSP
CW
CBPH
V
V
IH
IL
(Note 2)
t
OHZ
V
V
IH
IL
OE#
t
WC
t
t
WP
t
AS
WPH
t
t
HD
SP
V
V
IH
IL
WE#
t
t
BOE
CEW
V
V
High-Z
OH
OL
WAIT
t
WHZ
t
ACLK
V
V
High-Z
V
V
High-Z
IH
IL
OH
OL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
DQ[15:0]
DATA
DATA
t
t
t
DH
DW
KOH
Legend:
Don't Care
Undefined
Notes:
1. Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay.
1. When transitioning between asynchronous and variable-latency burst operations, CE# must go High. If CE# goes High, it must remain High
for at least 5ns (t ) to schedule the appropriate internal refresh operation. See How Extended Timings Impact CellularRAM™ Operation
CBPH
for restrictions on the maximum CE# Low time (t
).
CEM
Figure 34.18 Asynchronous Write Followed by Burst Read
200
S75WS256Nxx Based MCPs
S75WS-N-00_A0 February 17, 2005
A d v a n c e I n f o r m a t i o n
Table 34.19 Write Timing Parameters—Asynchronous Write Followed by Burst Read
70ns/80 MHz
85ns/66 MHz
Symbol
tAVH
tAS
Min
5
Max
Min
5
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
0
tAVS
tAW
10
70
70
70
10
70
0
10
85
85
85
10
85
0
tBW
tCKA
tCVS
tCW
tDH
tDW
tVP
tVPH
tVS
20
10
10
70
70
23
10
10
85
85
tWC
tWHZ
tWP
tWPH
tWR
8
8
46
10
0
55
10
0
Table 34.20 Read Timing Parameters—Asynchronous Write Followed by Burst Read
70ns/80 MHz
85ns/66 MHz
Symbol
tACLK
tBOE
tCBPH
tCEW
tCLK
Min
Max
9
Min
Max
11
Units
ns
20
20
ns
5
1
5
1
ns
7.5
7.5
ns
12.5
4
15
5
ns
tCSP
ns
tHD
2
2
ns
tKOH
tOHZ
tSP
2
2
ns
8
8
ns
3
3
ns
February 17, 2005 S75WS-N-00_A0
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201
A d v a n c e I n f o r m a t i o n
t
CLK
V
V
IH
IL
CLK
t
t
t
t
t
HD
WC
WC
CKA
SP
V
V
IH
IL
Valid
Address
Valid
Address
Valid
Address
A[22:0]
t
t
WR
AW
t
t
HD
SP
V
V
IH
IL
ADV#
t
t
SP
t
BW
HD
V
V
IH
IL
LB#/UB#
CE#
t
t
t
CSP
CW
CSP
V
V
IH
IL
(Note 2)
t
OHZ
V
V
IH
IL
OE#
t
WC
t
t
t
t
HD
WP
WPH
SP
V
V
IH
IL
WE#
t
t
BOE
CEW
V
V
High-Z
OH
OL
WAIT
t
t
WHZ
t
t
KOH
DW
ACLK
V
V
High-Z
V
V
High-Z
IH
IL
OH
OL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
DQ[15:0]
DATA
DATA
t
DH
Legend:
Don't Care
Undefined
Notes:
1. Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay.
2. When transitioning between asynchronous and variable-latency burst operations, CE# must go High. If CE# goes High, it must remain High
for at least 5ns (t ) to schedule the appropriate internal refresh operation. See How Extended Timings Impact CellularRAM™ Operation
CBPH
for restrictions on the maximum CE# Low time (t
).
CEM
Figure 34.19 Asynchronous Write (ADV# Low) Followed By Burst Read
202
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A d v a n c e I n f o r m a t i o n
Table 34.21 Asynchronous Write Timing Parameters—ADV# Low
70ns/80 MHz
85ns/66 MHz
Symbol
tAW
Min
70
70
70
70
0
Max
Min
85
85
85
85
0
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tBW
tCKA
tCW
tDH
tDW
23
70
23
85
tWC
tWHZ
tWP
tWPH
tWR
8
8
46
10
0
55
10
0
Table 34.22 Burst Read Timing Parameters
70ns/80 MHz
85ns/66 MHz
Symbol
tACLK
tBOE
tCBPH
tCEW
tCLK
Min
Max
9
Min
Max
11
Units
ns
20
20
ns
5
1
5
1
ns
7.5
7.5
ns
12.5
4
15
5
ns
tCSP
ns
tHD
2
2
ns
tKOH
tOHZ
tSP
2
2
ns
8
8
ns
3
3
ns
February 17, 2005 S75WS-N-00_A0
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203
A d v a n c e I n f o r m a t i o n
t
CLK
V
V
IH
IL
CLK
t
t
t
WC
SP
HD
V
V
IH
IL
Valid
Address
Valid
Address
A[22:0]
t
t
AW
SP
t
WR
t
HD
V
V
IH
IL
ADV#
t
CBPH
t
t
CEM
HD
t
t
t
CSP
CW
HZ
V
V
IH
IL
CE#
OE#
(Note 2)
t
t
OHZ
BOE
V
V
IH
IL
t
AS
t
OLZ
t
t
t
t
t
WPH
SP
SP
HD
WP
V
V
IH
IL
WE#
t
t
BW
HD
V
V
IH
IL
LB#/UB#
t
t
CEW
CEW
t
t
KHTL
HZ
High-Z
V
V
High-Z
OH
OL
WAIT
t
DW
t
DH
t
t
KOH
ACLK
High-Z
V
V
IH
IL
Valid
Output
DQ[15:0]
Valid
Input
Legend:
Don't Care
Undefined
READ Burst Identified
(WE# = HIGH)
Notes:
1. Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay.
2. When transitioning between asynchronous and variable-latency burst operations, CE# must go High. If CE# goes High, it must remain High
for at least 5ns (t ) to schedule the appropriate internal refresh operation. See How Extended Timings Impact CellularRAM™ Operation
CBPH
for restrictions on the maximum CE# Low time (t
).
CEM
Figure 34.23. Burst Read Followed by Asynchronous Write (WE#-Controlled)
204
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A d v a n c e I n f o r m a t i o n
Table 34.24 Burst Read Timing Parameters
70ns/80 MHz
85ns/66 MHz
Symbol
tACLK
tBOE
tCBPH
tCEW
tCLK
Min
Max
9
Min
Max
11
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
20
5
1
5
1
7.5
7.5
12.5
4
15
5
tCSP
tHD
2
2
tHZ
8
1.6
9
8
tKHKL
tKHTL
tKOH
tKP
1.6
11
2
3
2
3
tOHZ
8
8
Table 34.25 Asynchronous Write Timing Parameters—WE# Controlled
70ns/80 MHz
85ns/66 MHz
Symbol
tAS
Min
0
Max
Min
Max
Units
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
0
tAW
70
70
85
85
tBW
tCEM
tCW
tDH
4
4
8
70
0
85
0
tDW
tHZ
tWC
tWP
tWPH
tWR
23
23
8
70
46
10
0
85
55
10
0
February 17, 2005 S75WS-N-00_A0
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205
A d v a n c e I n f o r m a t i o n
t
CLK
V
V
IH
IL
CLK
t
t
HD
SP
V
V
IH
IL
Valid
Address
Valid
Address
A[22:0]
t
t
AVS
AVH
t
t
t
VPH
VS
SP
t
t
HD
VP
V
V
IH
IL
ADV#
t
AW
t
t
AS
CBPH
t
t
CEM
HD
t
t
t
CSP
CW
HZ
V
V
IH
IL
CE#
OE#
(Note 2)
t
t
OHZ
BOE
V
V
IH
IL
t
AS
t
OLZ
t
t
t
t
t
WPH
SP
SP
HD
WP
V
V
IH
IL
WE#
t
t
BW
HD
V
V
IH
IL
LB#/UB#
t
t
CEW
CEW
t
t
KHTL
HZ
High-Z
V
V
High-Z
OH
OL
WAIT
t
DW
t
DH
t
t
KOH
ACLK
High-Z
V
V
OH
OL
Valid
Output
DQ[15:0]
Valid
Input
Legend:
Don't Care
Undefined
READ Burst Identified
(WE# = HIGH)
Notes:
1. Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay.
2. When transitioning between asynchronous and variable-latency burst operations, CE# must go High. If CE# goes High, it must remain High
for at least 5ns (t ) to schedule the appropriate internal refresh operation. See How Extended Timings Impact CellularRAM™ Operation
CBPH
for restrictions on the maximum CE# Low time (t
).
CEM
Figure 34.26. Burst Read Followed by Asynchronous Write Using ADV#
206
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A d v a n c e I n f o r m a t i o n
Table 34.27 Burst Read Timing Parameters
70ns/80 MHz
85ns/66 MHz
Symbol
tACLK
tBOE
tCBPH
tCEW
tCLK
Min
Max
9
Min
Max
11
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
20
5
1
5
1
7.5
7.5
12.5
4
15
5
tCSP
tHD
2
2
tHZ
8
1.6
9
8
tKHKL
tKHTL
tKOH
tKP
1.6
11
2
3
2
3
tOHZ
8
8
Table 34.28 Asynchronous Write Timing Parameters Using ADV#
70ns/80 MHz
85ns/66 MHz
Symbol
tAS
Min
0
Max
Min
0
Max
Units
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVH
tAVS
tAW
5
5
10
70
70
10
85
85
tBW
tCEM
tCEW
tCW
tDH
4
4
1
70
0
7.5
1
85
0
7.5
tDW
tHZ
23
23
8
8
tVP
10
10
70
46
10
0
10
10
85
55
10
0
tVPH
tVS
tWP
tWPH
tWR
February 17, 2005 S75WS-N-00_A0
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207
A d v a n c e I n f o r m a t i o n
V
V
IH
IL
Valid
Address
Valid
Valid
Address
A[22:0]
ADV#
Address
t
t
t
AW
WR
AA
V
V
IH
IL
t
BHZ
t
t
BW
BLZ
V
V
IH
IL
LB#/UB#
CE#
t
t
CEM
t
CBPH
t
HZ
CW
V
V
IH
IL
(Note)
t
LZ
t
t
OHZ
OE
V
V
IH
IL
OE#
t
WC
t
t
WP
t
AS
WPH
V
V
IH
IL
WE#
t
t
HZ
HZ
V
V
OH
OL
WAIT
t
WHZ
t
OLZ
High-Z
High-Z
V
V
V
V
IH
IL
OH
OL
Valid
Output
DQ[15:0]
DATA
DATA
t
t
DW
DH
Legend:
Don't Care
Undefined
Note: CE# can stay Low when transitioning between asynchronous operations. If CE# goes High, it must remain High
for at least 5ns (t ) to schedule the appropriate internal refresh operation. See How Extended Timings Impact Cel-
CBPH
lularRAM™ Operation for restrictions on the maximum CE# Low time (t
).
CEM
Figure 34.29. Asynchronous Write Followed by Asynchronous Read—ADV# Low
208
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A d v a n c e I n f o r m a t i o n
Table 34.30 Write Timing Parameters—ADV# Low
70ns/80 MHz
85ns/66 MHz
Symbol
tAS
Min
0
Max
Min
0
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAW
70
70
70
0
85
85
85
0
tBW
tCW
tDH
tDW
tHZ
23
23
8
8
8
8
tWC
tWHZ
tWP
70
85
46
10
0
55
10
0
tWPH
tWR
Table 34.31 Read Timing Parameters—ADV# Low
70ns/80 MHz
85ns/66 MHz
Symbol
tAA
Min
Max
70
8
Min
Max
85
8
Units
ns
tBHZ
tBLZ
tCBPH
tCEM
tHZ
ns
10
5
10
5
ns
ns
4
8
4
8
µs
ns
tLZ
10
5
10
5
ns
tOE
20
8
20
8
ns
tOHZ
tOLZ
ns
ns
February 17, 2005 S75WS-N-00_A0
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A d v a n c e I n f o r m a t i o n
V
V
IH
IL
Valid
Address
Valid
Address
Valid
Address
A[22:0]
t
t
t
t
t
AA
AVS
AVH
AW
WR
t
t
t
VPH VP
VS
V
V
IH
IL
ADV#
t
t
t
BHZ
t
BW
BLZ
CVS
V
V
IH
IL
LB#/UB#
t
t
t
CBPH
CEM
t
HZ
CW
V
V
IH
IL
CE#
OE#
(Note)
t
t
LZ
AS
t
OHZ
V
V
IH
IL
t
WC
t
t
WP
t
AS
WPH
t
OLZ
V
V
IH
IL
WE#
V
V
OH
OL
WAIT
t
WHZ
t
OE
High-Z
High-Z
V
V
V
V
IH
IL
OH
OL
Valid
Output
DQ[15:0]
DATA
DATA
t
t
DW
DH
Legend:
Don't Care
Undefined
Note: CE# can stay Low when transitioning between asynchronous operations. If CE# goes High, it must remain High
for at least 5ns (t ) to schedule the appropriate internal refresh operation. See How Extended Timings Impact Cel-
CBPH
lularRAM™ Operation for restrictions on the maximum CE# Low time (t
).
CEM
Figure 34.32. Asynchronous Write Followed by Asynchronous Read
210
S75WS256Nxx Based MCPs
S75WS-N-00_A0 February 17, 2005
A d v a n c e I n f o r m a t i o n
Table 34.33 Write Timing Parameters—Asynchronous Write Followed by Asynchronous Read
70ns/80 MHz
85ns/66 MHz
Symbol
tAS
Min
0
Max
Min
0
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVH
tAVS
tAW
5
5
10
70
70
10
70
0
10
85
85
10
85
0
tBW
tCVS
tCW
tDH
tDW
tVP
tVPH
tVS
23
10
10
70
70
23
10
10
85
85
tWC
tWHZ
tWP
8
8
46
10
0
55
10
0
tWPH
tWR
Table 34.34 Read Timing Parameters—Asynchronous Write Followed by Asynchronous Read
70ns/80 MHz
85ns/66 MHz
Symbol
tAA
Min
Max
70
8
Min
Max
85
8
Units
ns
tBHZ
tBLZ
tCBPH
tCEM
tHZ
ns
10
5
10
5
ns
ns
4
8
4
8
µs
ns
tLZ
10
5
10
5
ns
tOE
20
8
20
8
ns
tOHZ
tOLZ
ns
ns
February 17, 2005 S75WS-N-00_A0
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211
A d v a n c e I n f o r m a t i o n
35 How Extended Timings Impact CellularRAM™ Operation
35.1 Introduction
This section describes CellularRAM™ timing requirements in systems that perform extended
operations.
CellularRAM products use a DRAM technology that periodically requires refresh to ensure against
data corruption. CellularRAM devices include on-chip circuitry that performs the required refresh
in a manner that is completely transparent in systems with normal bus timings. The refresh cir-
cuitry imposes constraints on timings in systems that take longer than 4µs to complete an
operation. Write operations are affected if the device is configured for asynchronous operation.
Both Read and Write operations are affected if the device is configured for page or burst-mode
operation.
35.2 Asynchronous Write Operation
The timing parameters provided in Figure 34.4 require that all Write operations must be com-
pleted within 4µs. After completing a Write operation, the device must either enter standby (by
transitioning CE# High), or else perform a second operation (Read or Write) using a new address.
Figure 35.1 and Figure 35.2 demonstrate these constraints as they apply during an asynchronous
(page-mode-disabled) operation. Either the CE# active period (tCEM in Figure 35.1) or the ad-
dress valid period (tTM in Figure 35.2) must be less than 4µs during any Write operation,
otherwise, the extended Write timings must be used.
t
< 4 μs
CEM
CE#
ADDRESS
Figure 35.1 Extended Timing for t
CEM
CE#
t
<
TM 4μs
ADDRESS
Figure 35.2 Extended Timing for t
TM
Table 35.1 Extended Cycle Impact on Read and Write Cycles
Page Mode
Timing Constraint
Read Cycle
Write Cycle
tCEM and tTM > 4µs
(See Figure 35.1 and
Figure 35.2.)
Must use extended Write
timing.
Asynchronous
Page Mode Disabled
No impact.
(See Figure 35.2)
Must use extended Write
timing.
Asynchronous
Page Mode Enabled
tCEM > 4µs
(See Figure 35.1.)
All following intrapage Read
access times are tAA (not tAPA).
(See Figure 35.3)
Burst
tCEM > 4µs (See Figure 35.1.)
Burst must cross a row boundary within 4µs.
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35.2.1 Extended Write Timing— Asynchronous Write Operation
Modified timings are required during extended Write operations (see Figure 35.3). An extended
Write operation requires that both the Write pulse width (tWP) and the data valid period (tDW) be
lengthened to at least the minimum Write cycle time (tWC [MIN]). These increased timings ensure
that time is available for both a refresh operation and a successful completion of the Write
operation.
t
or t
> 4μs
TM
CEM
ADDRESS
CE#
LB#/UB#
t
t
> t
(MIN)
(MIN)
WP
DW
WC
WC
WE#
> t
DATA-IN
Figure 35.3 Extended Write Operation
35.3 Page Mode Read Operation
When a CellularRAM device is configured for page mode operation, the address inputs are used
to accelerate Read accesses and cannot be used by the on-chip circuitry to schedule refresh. If
CE# is Low longer than the tCEM maximum time of 4µs during a Read operation, the system must
allow tAA (not tAPA, as would otherwise be expected) for all subsequent intrapage accesses until
CE# goes High.
35.4 Burst-Mode Operation
When configured for burst-mode operation, it is necessary to allow the device to perform a refresh
within any 4µs window. One of two conditions will enable the device to schedule a refresh within
4µs. The first condition is when all burst operations complete within 4µs. A burst completes when
the CE# signal is registered High on a rising clock edge. The second condition that allows a refresh
is when a burst access crosses a row boundary. The row-boundary crossing causes Wait to be
asserted while the next row is accessed and enables the scheduling of refresh.
35.5 Summary
CellularRAM products are designed to ensure that any possible asynchronous timings do not
cause data corruption due to lack of refresh. Slow bus timings on asynchronous Write operations
require that tWP and tDW be lengthened. Slow bus timings during asynchronous page Read oper-
ations cause the next intrapage Read data to be delayed to tAA.
Burst mode timings must allow the device to perform a refresh within any 4µs period. A burst
operation must either complete (CE# registered High) or cross a row boundary within 4µs to en-
sure successful refresh scheduling. These timing requirements are likely to have little or no impact
when interfacing a CellularRAM device with a low-speed memory bus.
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36 Revisions
Revision A0 (February 17, 2005)
Initial Release
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