W219B_技术文档

W219B

Frequency Generator for Integrated Core Logic with 133MHz FSB

Features

Table 1. Frequency Selections

FS4 FS3 FS2 FS1 FS0 CPU SDRAM 3V66 PCI APIC

SS

OFF

• Maximized EMI suppression using Cypress’s Spread

Spectrum technology

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

75.3

95.0

113.0

95.0

75.3 37.6 18.8

63.3 31.6 15.8

86.0 43.0 21.5

75.3 37.6 18.8

75.0 37.5 18.7

73.0 36.6 18.3

70.0 35.0 17.5

72.0 36.0 18.0

68.3 34.1 17.0

70.0 35.0 17.5

69.0 34.5 17.0

70.0 35.0 17.5

66.8 33.4 16.7

78.6 39.3 19.6

80.0 40.0 20.0

73.3 36.6 18.3

61.0 30.5 15.2

84.6 42.3 21.1

81.3 40.6 20.3

78.0 39.0 19.5

76.0 38.0 19.0

80.0 40.0 20.0

78.0 39.0 19.5

83.0 41.5 20.7

89.0 44.5 22.2

66.6 33.3 16.6

–0.6%

OFF

• Low jitter and tightly controlled clock skew

129.0 129.0

150.0 113.0

150.0 150.0

• Highly integrated device providing clocks required for

CPU, core logic, and SDRAM

OFF

• Two copies of CPU clock

110.0

OFF

• Nine copies of SDRAM clock

140.0 140.0

144.0 108.0

OFF

• Seven copies of PCI clock

OFF

68.3

102.5

OFF

• One copy of synchronous APIC clock

• Three copies of 66-MHz outputs

• Two copies of 48-MHz outputs

• One copy of selectable 24- or 48-MHz clock

105.0 105.0

138.0 138.0

140.0 105.0

OFF

66.8

100.2

0.45%

OFF

100.2 100.2

133.6 133.6

133.6 100.2

157.3 118.0

160.0 120.0

146.6 110.0

• One copy of double strength 14.31818-MHz reference

clock

• Power-down control

• SMBus interface for turning off unused clocks

OFF

Key Specifications

122.0

91.5

–0.6%

OFF

CPU, SDRAM Outputs Cycle-to-Cycle Jitter: .............250 ps

127.0 127.0

122.0 122.0

APIC, 48-MHz, 3V66, PCI Outputs

Cycle-to-Cycle Jitter: ...................................................500 ps

–0.6%

OFF

117.0

114.0

80.0

117.0

114.0

120.0

117.0

CPU, 3V66 Output Skew:............................................175 ps

SDRAM, APIC, 48-MHz Output Skew:........................250 ps

PCI Output Skew:........................................................500 ps

CPU to SDRAM Skew (@ 133 MHz) ....................... 0.5 ns

CPU to SDRAM Skew (@ 100 MHz) .................4.5 to 5.5 ns

CPU to 3V66 Skew (@ 66 MHz)........................7.0 to 8.0 ns

3V66 to PCI Skew (3V66 lead)...........................1.5 to 3.5 ns

PCI to APIC Skew ..................................................... 0.5 ns

OFF

78.0

OFF

166.0 124.5

133.6 133.6

OFF

66.6

100.0

–0.6%

100.0 100.0

133.3 133.3

133.3 100.0

VDDQ3

Pin Configuration^[1]

Block Diagram

REF2X/FS3*

X1

X2

XTAL

OSC

VDDQ2

APIC

VDDQ2

CPU0

CPU1

REF2x/FS3*

VDDQ3

X1

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

PLL REF FREQ

VDDQ2

CPU0:1

X2

GND

VDDQ3

3V66_0

3V66_1

3V66_2

GND

FS0*/PCI0

FS1*/PCI1

FS2*/PCI2

GND

PCI3

PCI4

VDDQ3

PCI5

PCI6

GND

Divider,

Delay,

and

Phase

Con-

trol

GND

2

SDATA

SCLK

SMBus

Logic

VDDQ3

SDRAM0

SDRAM1

SDRAM2

GND

SDRAM3

SDRAM4

SDRAM5

VDDQ3

SDRAM6

SDRAM7

SDRAM8

GND

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

APIC

(FS0:4*)

VDDQ3

3V66_0:2

Logic

2

PCI0/FS0*

PLL 1

PCI1/FS1*

PCI2/FS2*

PCI3:6

5

9

PWR_DWN#

SCLK

VDDQ3

GND

SDATA

^

SDRAM0:8

48MHz_0

PWR_DWN#

FS4*/48MHz_1

SI0/24_48#MHz*

VDDQ3

48MHz_0

48MHz_1/FS4*

PLL2

Note:

1. Internal 250K pull-down or pull up resistors present on inputs marked

with * or ^ respectively. Design should not rely solely on internal

pull-up or pull down resistor to set I/O pins HIGH or LOW respectively.

SI0/24_48#MHz*

/2

Rev 1.0, November 20, 2006

2200 Laurelwood Road, Santa Clara, CA 95054

Page 1 of 14

Tel:(408) 855-0555 Fax:(408) 855-0550

www.SpectraLinear.com

W219B

I

Pin Definitions

Type

Pin Name

Pin No.

Pin Description

REF2x/FS3

1

I/O

Reference Clock with 2x Drive/Frequency Select 3: 3.3V 14.318-MHz clock

output. This pin also serves as the select strap to determine device operating

frequency as described in Table 1.

X1

3

4

I

Crystal Input: This pin has dual functions. It can be used as an external

14.318-MHz crystal connection or as an external reference frequency input.

X2

Crystal Output: An input connection for an external 14.318-MHz crystal

connection. If using an external reference, this pin must be left unconnected.

PCI0/FS0

11

I/O

PCI Clock 0/Frequency Selection 0: 3.3V 33-MHz PCI clock outputs. This pin also

serves as the select strap to determine device operating frequency as described in

Table 1.

PCI1/FS1

PCI2/FS2

12

13

I/O

PCI Clock 1/Frequency Selection 1: 3.3V 33-MHz PCI clock outputs. This pin also

serves as the select strap to determine device operating frequency as described in

Table 1.

PCI Clock 2/Frequency Selection 2: 3.3V 33-MHz PCI clock outputs. This pin also

serves as the select strap to determine device operating frequency as described in

Table 1.

PCI3:6

15, 16, 18, 19

7, 8, 9

O

PCI Clock 3 through 6: 3.3V 33-MHz PCI clock outputs. PCI0:6 can be individually

turned off via SMBus interface.

3V66_0:2

66-MHz Clock Output: 3.3V output clocks. The operating frequency is controlled

by FS0:4 (see Table 1).

48MHz_0

21

22

O

48-MHz Clock Output: 3.3V fixed 48-MHz, non-spread spectrum clock output.

48MHz_1/

FS4

I/O

48-MHz Clock Output/Frequency Selection 4: 3.3V fixed 48-MHz, non-spread

spectrum clock output. This pin also serves as the select strap to determine device

operating frequency as described in Table 1.

SIO/

24_48#MHz

23

I/O

Clock Output for Super I/O: This is the input clock for a Super I/O (SIO) device.

During power-up, it also serves as a selection strap. If it is sampled HIGH, the output

frequency for SIO is 24 MHz. If the input is sampled LOW, the output is 48 MHz.

PWR_DWN#

CPU0:1

29

I

Power Down Control: LVTTL-compatible input that places the device in

power-down mode when held LOW.

45, 44

O

CPU Clock Outputs: Clock outputs for the host bus interface. Output frequencies

depending on the configuration of FS0:4. Voltage swing is set by VDDQ2.

SDRAM0:8

41, 40, 39, 37,

36, 35, 33, 32,

31

SDRAM Clock Outputs: 3.3V outputs for SDRAM. The operating frequency is

controlled by FS0:4 (see Table 1).

APIC

47

O

Synchronous APIC Clock Outputs: Clock outputs running synchronous with the

PCI clock outputs. Voltage swing set by VDDQ2.

SDATA

SCLK

25

28

I/O

I

Data pin for SMBus circuitry.

Clock pin for SMBus circuitry.

VDDQ3

2, 6, 17, 24, 27,

34, 42

P

3.3V Power Connection: Power supply for SDRAM output buffers, PCI output

buffers, reference output buffers and 48-MHz output buffers. Connect to 3.3V.

VDDQ2

GND

46, 48

P

2.5V Power Connection: Power supply for IOAPIC and CPU output buffers.

Connect to 2.5V or 3.3V.

5,10,14,20,26,

30, 38, 43,

G

Ground Connections: Connect all ground pins to the common system ground

plane.

Rev 1.0,November 20, 2006

Page 2 of 14

W219B

Output Strapping Resistor

Series Termination Resistor

Clock Load

W219B

Output

Buffer

Power-on

Reset

Timer

Hold

Output

Low

Output Three-state

10k:

Q

D

Data

Latch

Figure 1. Input Logic Selection Through Resistor Load Option

is delivered on the pins. If the power supply has not yet

reached full value, output frequency initially may be below

target but will increase to target once supply voltage has stabi-

lized. In either case, a short output clock cycle may be

produced from the CPU clock outputs when the outputs are

enabled.

Overview

The W219B is a highly integrated frequency timing generator,

supplying all the required clock sources for an Intel® archi-

tecture platform using graphics integrated core logic.

Functional Description

Offsets Among Clock Signal Groups

I/O Pin Operation

Figure 2 and Figure 3 represent the phase relationship among

the different groups of clock outputs from W219B when it is

providing a 66-MHz CPU clock and a 100-MHz CPU clock,

respectively. It should be noted that when CPU clock is

operating at 100 MHz, CPU clock output is 180 degrees out of

phase with SDRAM clock outputs.

Pin # 1, 11, 12, 13, 22, and 23 are dual-purpose l/O pins. Upon

power-up the pin acts as a logic input. An external 10-k:

strapping resistor should be used. Figure 1 shows a suggested

method for strapping resistor connections.

After 2 ms, the pin becomes an output. Assuming the power

supply has stabilized by then, the specified output frequency

10 ns

20 ns

30 ns

40 ns

0 ns

CPU 66 Period

CPU 66-MHz

SDRAM 100 Period

SDRAM 100-MHz

Hub-PC

3V66 66-MHz

PCI 33-MHz

REF 14.318-MHz

USB 48-MHz

APIC

Figure 2. Group Offset Waveforms (66.8 CPU Clock, 100.2 SDRAM Clock)

Rev 1.0,November 20, 2006

Page 3 of 14

W219B

0 ns

10 ns

20 ns

30 ns

40 ns

CPU 100 Period

CPU 100-MHz

SDRAM 100 Period

SDRAM 100-MHz

3V66 66-MHz

Hub-PC

PCI 33-MHz

REF 14.318-MHz

USB 48-MHz

APIC

Figure 3. Group Offset Waveforms (100.2 CPU Clock, 100.2 SDRAM Clock)

Power-Down Control

W219B provides one PWRDWN# signal to place the device in low-power mode. In low-power mode, the PLLs are turned off and

all clock outputs are driven LOW.

0 ns

25 ns

50 ns

75 ns

Center

1

2

VCO Internal

CPU 100MHz

3V66 66MHz

APIC 33MHz

PCI 33MHz

PwrDwn

SDRAM 100MHz

REF 14.318MHz

USB 48MHz

Figure 4. PWRDWN# Timing Diagram^{[2, 3, 4, 5]}

Notes:

2. Once the PWRDWN# signal is sampled LOW for two consecutive rising edges of CPU, clocks of interest will be held LOW on the next HIGH-to-LOW transition.

3. PWRDWN# is an asynchronous input and metastable conditions could exist. This signal is synchronized inside W219B.

4. The shaded sections on the SDRAM, REF, and USB clocks indicate “Don’t Care” states.

5. Diagrams shown with respect to 100 MHz. Similar operation when CPU is 66 MHz.

Rev 1.0,November 20, 2006

Page 4 of 14

W219B

Where P is the percentage of deviation and F is the frequency

in MHz where the reduction is measured.

Spread Spectrum Frequency Timing Generator

The device generates a clock that is frequency modulated in

order to increase the bandwidth that it occupies. By increasing

the bandwidth of the fundamental and its harmonics, the ampli-

tudes of the radiated electromagnetic emissions are reduced.

This effect is depicted in Figure 5.

The output clock is modulated with a waveform depicted in

Figure 6. This waveform, as discussed in “Spread Spectrum

Clock Generation for the Reduction of Radiated Emissions” by

Bush, Fessler, and Hardin produces the maximum reduction

in the amplitude of radiated electromagnetic emissions. The

deviation selected for this chip is 0.45% or –0.6% of the

selected frequency. Figure 6 details the Cypress spreading

pattern. Cypress does offer options with more spread and

greater EMI reduction. Contact your local Sales representative

for details on these devices.

As shown in Figure 5, a harmonic of a modulated clock has a

much lower amplitude than that of an unmodulated signal. The

reduction in amplitude is dependent on the harmonic number

and the frequency deviation or spread. The equation for the

reduction is:

dB = 6.5 + 9*log₁₀(P) + 9*log₁₀(F)

SSFTG

EMI Reduction

Typical Clock

Spread

Spectrum

Enabled

Non-

Spread

Spectrum

Frequency Span (MHz)

Center Spread

Frequency Span (MHz)

Figure 5. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation

MAX.

MIN.

Figure 6. Typical Modulation Profile

Rev 1.0,November 20, 2006

Page 5 of 14

W219B

1 bit

7 bits

1

8 bits

1

Start bit

Slave Address

R/W

Ack

Command Code

Ack

Byte Count = N

Ack

1 bit

Data Byte 1

8 bits

Ack

Data Byte 2

8 bits

Ack

1

...

Data Byte N

8 bits

Ack

1

Stop

1

Figure 7. An Example of a Block Write^[6]

Serial Data Interface

transfer a maximum of 32 data bytes. The slave receiver

address for W219B is 11010010. Figure 7 shows an example

of a block write.

The W219B features a two-pin, serial data interface that can

be used to configure internal register settings that control

particular device functions.

The command code and the byte count bytes are required as

the first two bytes of any transfer. W219B expects a command

code of 0000 0000. The byte count byte is the number of

additional bytes required for the transfer, not counting the

command code and byte count bytes. Additionally, the byte

count byte is required to be a minimum of 1 byte and a

maximum of 32 bytes to satisfy the above requirement. Table

2 shows an example of a possible byte count value.

Data Protocol

The clock driver serial protocol accepts only block writes from

the controller. The bytes must be accessed in sequential order

from lowest to highest byte with the ability to stop after any

complete byte has been transferred. Indexed bytes are not

allowed.

A transfer is considered valid after the acknowledge bit corre-

sponding to the byte count is read by the controller. The

command code and byte count bytes are ignored by the

W219B. However, these bytes must be included in the data

write sequence to maintain proper byte allocation.

A block write begins with a slave address and a write condition.

After the command code the core logic issues a byte count

which describes how many more bytes will follow in the

message. If the host had 20 bytes to send, the first byte would

be the number 20 (14h), followed by the 20 bytes of data. The

byte count may not be 0. A block write command is allowed to

Table 2. Example of Possible Byte Count Value

Byte Count Byte

Notes

MSB

0000

0010

LSB

0000

0001

0010

0011

0100

0101

0110

0111

0000

Not allowed. Must have at least one byte.

Data for functional and frequency select register (currently byte 0 in spec)

Reads first two bytes of data. (byte 0 then byte1)

Reads first three bytes (byte 0, 1, 2 in order)

Reads first four bytes (byte 0, 1, 2, 3 in order)

Reads first five bytes (byte 0, 1, 2, 3, 4 in order)^[7]

Reads first six bytes (byte 0, 1, 2, 3, 4, 5 in order)^[7]

Reads first seven bytes (byte 0, 1, 2, 3, 4, 5, 6 in order)

Max. byte count supported = 32

Table 3. Serial Data Interface Control Functions Summary

Control Function

Description

Common Application

Output Disable

Any individual clock output(s) can be disabled.

Disabled outputs are actively held LOW.

Unused outputs are disabled to reduce EMI and

system power. Examples are clock outputs to unused

PCI slots.

(Reserved)

Reserved function for future device revision or

production device testing.

No user application. Register bit must be written as 0.

Notes:

6. The acknowledgment bit is returned by the slave/receiver (W219B).

7. Bytes 6 and 7 are not defined for W219B.

Rev 1.0,November 20, 2006

Page 6 of 14

W219B

2. All unused register bits (reserved and N/A) should be

written to a “0” level.

Serial Configuration Map

1. The serial bits will be read by the clock driver in the following

order:

3. All register bits labeled “Initialize to 0" must be written to

zero during initialization. Failure to do so may result in

higher than normal operating current. The controller will

read back the written value.

Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0

Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0

Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0

Byte 0: Control Register (1 = Enable, 0 = Disable)^[8]

Bit

Pin#

Name

Reserved

Default

Pin Function

Pin Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

-

0

1

0

Reserved

-

Reserved

24/48 MHz

48 MHz

Reserved

-

Reserved

-

Reserved

-

23

Reserved

(Active/Inactive)

Reserved

21, 22

-

Reserved

Byte 1: Control Register (1 = Enable, 0 = Disable)^[8]

Bit

Pin#

32

Name

SDRAM7

Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1

(Active/Inactive)

33

SDRAM6

SDRAM5

SDRAM4

SDRAM3

SDRAM2

SDRAM1

SDRAM0

35

36

37

39

40

41

Byte 2: Control Register (1 = Enable, 0 = Disable)^[8]

Bit

Pin#

--

Name

Reserved

PCI6

Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

0

1

Reserved

19

18

16

15

13

12

11

(Active/Inactive)

PCI5

PCI4

PCI3

PCI2

PCI1

Bit 0

PCI0

Note:

8. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be

configured during the normal modes of operation.

Rev 1.0,November 20, 2006

Page 7 of 14

W219B

Byte 3: Reserved Register (1 = Enable, 0 = Disable)

Bit

Pin#

Name

SDRAM8

Default

Pin Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

31

-

1

0

1

0

1

0

(Active/Inactive)

Reserved

APIC

-

Reserved

-

Reserved

47

-

(Active/Inactive)

Reserved

-

Reserved

-

Reserved

Byte 4: Reserved Register (1 = Enable, 0 = Disable)

Bit

Pin#

Name

Default

Pin Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

-

SEL3

SEL2

SEL1

SEL0

0

See Table 4

FS(0:4) Override

0 = Select operating frequency by FS(0:4) strapping

1 = Select operating frequency by SEL(0:4) bit settings

Bit 2

Bit 1

Bit 0

-

SEL4

0

See Table 4

Reserved

Test Mode

Reserved

0 = All output enable

1 = All output three-stated

Byte 5: Reserved Register (1 = Enable, 0 = Disable)

Bit

Pin#

Name

Reserved

Default

Pin Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

-

0

Reserved

Byte 6: Reserved Register (1 = Enable, 0 = Disable)

Bit

Pin#

Name

Reserved

Default

Pin Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

-

0

1

Reserved

Rev 1.0,November 20, 2006

Page 8 of 14

W219B

Byte 6: Reserved Register (1 = Enable, 0 = Disable)

Bit

Pin#

Name

Default

Pin Description

Bit 0

-

Reserved

0

Reserved

Table 4. Additional Frequency Selections through Serial Data Interface Data Bytes

Input Conditions

Output Frequency

Data Byte 4, Bit 3 = 1

Bit 2

SEL_4

Bit 7

SEL_3

Bit 6

SEL_2

Bit 5

SEL_1

Bit 4

SEL_0

Spread

Spectrum

CPU

75.3

SDRAM

113.0

95.0

3V66

75.3

63.3

86.0

75.3

75.0

73.0

70.0

72.0

68.3

70.0

69.0

70.0

66.8

78.6

80.0

73.3

61.0

84.6

81.3

78.0

76.0

80.0

78.0

83.0

89.0

66.6

PCI

37.6

31.6

43.0

37.6

37.5

36.6

35.0

36.0

34.1

35.0

34.5

35.0

33.4

39.3

40.0

36.6

30.5

42.3

40.6

39.0

38.0

40.0

39.0

41.5

44.5

33.3

APIC

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

18.8

15.8

21.5

18.8

18.7

18.3

17.5

18.0

17.0

17.5

17.0

17.5

16.7

19.6

20.0

18.3

15.2

21.1

20.3

19.5

19.0

20.0

19.5

20.7

22.2

16.6

OFF

–0.6%

OFF

95.0

129.0

150.0

110.0

140.0

144.0

68.3

129.0

113.0

150.0

110.0

140.0

108.0

102.5

105.0

138.0

105.0

100.2

133.6

100.2

118.0

120.0

110.0

91.5

OFF

105.0

138.0

140.0

66.8

OFF

0.45%

OFF

100.2

133.6

157.3

160.0

146.6

122.0

127.0

122.0

117.0

114.0

80.0

OFF

–0.6%

OFF

127.0

122.0

117.0

114.0

120.0

117.0

124.5

133.6

100.0

133.3

100.0

–0.6%

OFF

78.0

OFF

166.0

133.6

66.6

OFF

–0.6%

100.0

133.3

Rev 1.0,November 20, 2006

Page 9 of 14

W219B

DC Electrical Characteristics^[9]

DC parameters must be sustainable under steady state (DC) conditions.

Absolute Maximum DC Power Supply

Parameter

V_DDQ3

V_DDQ2

T_S

Description

3.3V Core Supply Voltage

Min.

–0.5

–65

Max.

4.6

Unit

V

2.5V I/O Supply Voltage

Storage Temperature

3.6

V

150

°C

Absolute Maximum DC I/O

Parameter

Description

Min.

–0.5

2000

Max.

4.6

Unit

V

V_i/o3

3.3V Core Supply Voltage

2.5V I/O Supply Voltage

Input ESD Protection

V_i/o3

3.6

V

ESD prot.

V

DC Operating Requirements

Parameter

Description

Condition

3.3V 5%

2.5V 5%

Min.

Max.

Unit

V

V_DD3

3.3V Core Supply Voltage

3.3V I/O Supply Voltage

2.5V I/O Supply Voltage

3.135

2.375

3.465

2.625

V_DDQ3

V

V_DDQ2

V

V_DD3= 3.3V 5%

V_ih3

3.3V Input High Voltage

3.3V Input Low Voltage

Input Leakage Current^[10]

V_DD3

2.0

GND – 0.3

–5

V_DD+ 0.3

0.8

V

V_il3

I_il

0<V_in<V_DDQ3

+5

µA

V_DDQ2= 2.5V 5%

V_oh2

2.5V Output High Voltage

2.5V Output Low Voltage

I_oh=(–1 mA)

I_ol=(1 mA)

2.0

2.4

V

V_ol2

0.4

V_DDQ3= 3.3V 5%

V_oh3

3.3V Output High Voltage

3.3V Output Low Voltage

I_oh=(–1 mA)

I_ol=(1 mA)

V

V_ol3

V_DDQ3= 3.3V 5%

V_poh3

PCI Bus Output High Voltage

PCI Bus Output Low Voltage

I_oh=(–1 mA)

I_ol=(1 mA)

V

V_pol3

0.55

C_in

Input Pin Capacitance

Xtal Pin Capacitance

Output Pin Capacitance

Pin Inductance

5

22.5

6

pF

nH

°C

C_xtal

C_out

L_pin

13.5

0

7

T_a

Ambient Temperature

No Airflow

70

Note:

9. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.

10. Input Leakage Current does not include inputs with pull-up or pull-down resistors.

Rev 1.0,November 20, 2006

Page 10 of 14

W219B

AC Electrical Characteristics^[9]

T_A= 0°C to +70°C, V_DDQ3= 3.3V 5ꢀ, V_DDQ2= 2.5V 5ꢀ

f

_XTL= 14.31818 MHz

66.6-MHz Host

100-MHz Host

133-MHz Host

Parameter

Description

Min.

15.0

5.2

Max.

15.5

N/A

1.6

Min.

10.0

3.0

Max.

10.5

N/A

1.6

Min.

7.5

Max.

8.0

Unit

Notes

11

T_Period

T_HIGH

T_LOW

T_RISE

T_FALL

Host/CPUCLK Period

ns

Host/CPUCLK High Time

Host/CPUCLK Low Time

Host/CPUCLK Rise Time

Host/CPUCLK Fall Time

1.87

1.67

0.4

N/A

1.6

14

5.0

2.8

0.4

15

0.4

1.6

0.4

1.6

0.4

1.6

T_Period

T_HIGH

T_LOW

T_RISE

T_FALL

SDRAM CLK Period

10.0

3.0

2.8

0.4

10.5

N/A

1.6

10.0

3.0

2.8

0.4

10.5

N/A

1.6

10.0

3.0

2.8

0.4

10.5

N/A

1.6

ns

11

14

SDRAM CLK High Time

SDRAM CLK Low Time

SDRAM CLK Rise Time

SDRAM CLK Fall Time

15

1.6

T_Period

T_HIGH

T_LOW

T_RISE

T_FALL

APIC CLK Period

60.0

25.5

25.3

0.4

64.0

N/A

1.6

60.0

25.5

25.30

0.4

N/A

1.6

60.0

25.5

25.30

0.4

64.0

N/A

1.6

ns

11

14

APIC CLK High Time

APIC CLK Low Time

APIC CLK Rise Time

APIC CLK Fall Time

15

0.4

1.6

0.4

1.6

0.4

1.6

T_Period

T_HIGH

T_LOW

T_RISE

T_FALL

3V66 CLK Period

30.0

12.0

0.4

N/A

1.6

30.0

12.0

0.4

N/A

1.6

30.0

12.0

0.4

N/A

1.6

ns

11, 13

14

3V66 CLK High Time

3V66 CLK Low Time

3V66 CLK Rise Time

3V66 CLK Fall Time

15

0.4

1.6

0.4

1.6

0.4

1.6

T_Period

T_HIGH

T_LOW

T_RISE

T_FALL

PCI CLK Period

15.0

5.25

5.05

0.5

16.0

N/A

2.0

15.0

5.25

5.05

0.5

16.0

N/A

2.0

15.0

5.25

5.05

0.5

16.0

N/A

2.0

ns

11, 12

14

PCI CLK High Time

PCI CLK Low Time

PCI CLK Rise Time

PCI CLK Fall Time

15

0.5

2.0

0.5

2.0

0.5

2.0

tp_ZL, tp_ZH

tp_LZ, tp_ZH

Output Enable Delay (All outputs)

30.0

12.0

N/A

30.0

12.0

N/A

30.0

12.0

N/A

ns

Output Disable Delay

(All outputs)

15

t_stable

All Clock Stabilization from

Power-Up

12.0

N/A

12.0

N/A

12.0

N/A

ms

Notes:

11. Period, jitter, offset, and skew measured on rising edge at 1.25 for 2.5V clocks and at 1.5V for 3.3V clocks.

12. T

13. T

14. The time specified is measured from when V

is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs.

is measured at 0.4V for all outputs.

HIGH

LOW

achieves its nominal operating level (typical condition V

= 3.3V) until the frequency output is stable and

DDQ3

operating within specification.

15. T and T

RISE

and V = 2.4V for 3.3V.

are measured as a transition through the threshold region V = 0.4V and V = 2.0V (1 mA) JEDEC specification for 2.5V outputs, and V = 0.4V

FALL

ol

oh

ol

oh

Rev 1.0,November 20, 2006

Page 11 of 14

W219B

Group Skew and Jitter Limits

Skew, Jitter

Output Group

CPU

Pin-Pin Skew Max.

Cycle-Cycle Jitter

250 ps

Duty Cycle

45/55

Nom Vdd

2.5V

Measure Point

1.25V

1.5V

175 ps

250 ps

175 ps

500 ps

N/A

SDRAM

APIC

250 ps

45/55

3.3V

500 ps

45/55

2.5V

1.25V

1.5V

48MHz

3V66

500 ps

45/55

3.3V

500 ps

45/55

3.3V

1.5V

PCI

500 ps

45/55

3.3V

1.5V

REF

1000 ps

45/55

3.3V

1.5V

Test Point

Output

Buffer

Test Load

Clock Output Wave

T

PERIOD

Duty Cycle

T

HIGH

2.0

1.25

2.5V Clocking

Interface

0.4

T

LOW

T

RISE

FALL

T

PERIOD

Duty Cycle

T

HIGH

2.4

1.5

0.4

3.3V Clocking

Interface

T

LOW

T

RISE

FALL

Figure 8. Output Buffer

Rev 1.0,November 20, 2006

Page 12 of 14

W219B

Layout Example

+2.5V Supply

FB

+3.3V Supply

FB

VDDQ2

VDDQ3

0.005 PF

G

10 PF

0.005 PF

C1

C2

C3

C4

G

V

G

1

2

3

4

48

G

V

G

47

46

45

G

V

G

V

5

6

7

8

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

G

V

G

9

10

11

12

G

13

14

15

16

17

G

V

G

V

18 ^G

19

G

20

21

22

23

_G28

V

VDDQ3

(Core)

G

27

26

3.3V

G

5:

G

24

25

0.1PF

20PF

C5

C6

G

FB = Dale ILB1206 - 300 (300: @ 100 MHz) or TDK ACB2012L-120

PF C6 = 0.1 PF

µF C2 & C4 = 0.005

Ceramic Caps

C1 & C3, C5 = 10 – 22

= VIA to GND plane layer V =VIA to respective supply plane trace

G

Note: Each supply plane or strip should have a ferrite bead and capacitors

All VDD by pass capacitors = 0.1 PF

Rev 1.0,November 20, 2006

Page 13 of 14

W219B

Ordering Information

Ordering Code

Package Name

Package Type

48-pin SSOP (300 mils)

W219B

H

Package Drawing and Dimensions

48-Lead Shrunk Small Outline Package O48

While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir-

cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in

normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other applica-

tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional

processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any

circuitry or specification without notice.

Rev 1.0, November 20, 2006

Page 14 of 14


型号：	W219B
厂家：	SPECTRALINEAR INC
描述：	Frequency Generator for Integrated Core Logic with 133MHz FSB 频率发生器集成的核心逻辑与133MHz外频外围集成电路光电二极管
文件：	总14页 (文件大小：232K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

W219B [SPECTRALINEAR]

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