MN5920 [SPECTRUM]
ADC, Flash Method, 8-Bit, 1 Func, 1 Channel, Parallel, 8 Bits Access, ECL, CDIP42, CERAMIC, DIP-42;
| 型号： | MN5920 |
| 厂家： | 
SPECTRUM MICROWAVE, INC. |
| 描述： | ADC, Flash Method, 8-Bit, 1 Func, 1 Channel, Parallel, 8 Bits Access, ECL, CDIP42, CERAMIC, DIP-42 CD 转换器 |
| 文件： | 总6页 (文件大小：57K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MN5920/21
8-Bit, 150MHz
Flash A/D Converters
DESCRIPTION
FEATURES
The MN5920/21 are monolithic 8-bit, 150MHz
flash A/D converters. These converters are ECL-
compatible and are clocked from a single
sampling clock.
·
·
·
8-Bit Resolution
150MHz Sampling Rate
They feature a unique comparator design with
input and clock buffers. The analog input buffers
stabilize the comparators input capacitance over
changing input frequencies making these
devices easier to drive than typical flash A/D
converters.
335MHz Input
Bandwidth
·
·
·
·
Low 10pF Input
Capacitance
Comparator Input and
Clock Buffers
The devices are packaged in a 42-pin ceramic
DIP packages and operate from a single -5.2V
supply.
Single -5.2V Supply
Operation
Devices are available for commercial and
industrial applications and are specified for 0°C
to +70°C applications.
ECL-Compatible Digital
Inputs/Outputs
·
·
0°C to +70°C Operation
APPLICATIONS
42-Pin Ceramic DIP
Package
Video Digitizer
RADAR
Pulse Measurement
Systems
Infrared Imaging
IF Digitizer
Imaging
Communications
Medical Imaging
m ic ro ne tworks
324 Clark Street Worcester MA 01606-1293
Phone: (508) 852-5400 FAX (508) 853-8296
Email: sales@mnc.com
Web Site: http://www.mnc.com
MN5920/21 8-Bit 150MHz Flash A/D Converters
ABSOLUTE MAXIMUM RATINGS
ORDERING INFORMATION
PART NUMBER
Operating Temperature Range
Specified Temperature Range
Storage Temperature Range
Power Supplies
Digital Inputs
Analog Input
0°C to +70°C
MN5920/21
0°C to +70°C
-65°C to +150°C
-7.0 to +0.5Volts
-VEE to +0.5Volts
-VEE to +0.5Volts
25mA
Standard model is specified for
0°C to +70°C operation.
Reference Current VRTF to VRBF
Digital Output Current
0 to -30mA
SPECIFICATIONS Typical at +25°C, -V =-5.2V, V = 0 to -2V, fS= 150MSPS, fCLK= 150MHz, VRTF
=
EE
IN
0.0V, VRBF= -2.0V, unless otherwise specified.
SPECIFICATIONS
ANALOG INPUT
MIN.
TYP.
MAX.
UNITS
Input Voltage Range
Input Capacitance
Input Resistance
-2
0
Volts
pF
kW
MHz
10
15
335
Input Bandwidth (Vin=500mVp-p)
DIGITAL INPUTS
Logic Levels: Logic “1”
Logic “0”
Logic Currents: Logic “1”
Logic “0”
-1.1
-2
-0.7
-1.5
Volts
Volts
uA
40
40
uA
DIGITAL OUTPUTS
-1.1
Volts
Volts
Logic Levels: Logic “1” (50W to -2V)
Logic “0” (50W to -2V)
-1.5
TRANSFER CHARACTERISTICS
Integral Nonlinearity Error (@ fCLK=100kHz)
Differential Nonlinearity Error (@ fCLK=100kHz)
Offset Error
-0.75
-0.75
+0.75
-0.75
+/-30
+/-30
LSB
LSB
mV
Gain Error
mV
No Missing Codes
Guaranteed
DYNAMIC CHARACTERISTICS
Conversion Rate
Clock to Data Delay
Acquisition Time
Aperture Jitter
125
150
2.4
1.5
5
MHz
nsec
nsec
psec-
Signal-to-Noise Ratio (SNR) (MN5920/5921)
fIN = 3.58MHz
46/45
42/40
48/47
46/44
dB
dB
fIN = 50MHz
Total Harmonic Distortion (THD) (MN5920/5921)
fIN = 3.58MHz
fIN = 50MHz
-48/-46
-40/-39
-52/-50
-44/-43
dB
dB
Signal-to-(Noise + Distortion) (SINAD) (MN5920/5921)
fIN = 3.58MHz
fIN = 50MHz
45/43
39/37
48/46
42/40
dB
dB
REFERENCE INPUT
Resistance
Bandwidth
100
200
10
300
W
MHz
m ic ro ne tworks 324 Clark Street, Worcester, MA 01606-1293 Phone: (508)852-5400; FAX (508) 853-8296
SPECIFICATIONS
MIN.
TYP.
MAX.
UNITS
POWER SUPPLY REQUIREMENTS
Power Supply
Supply Current
Power Consumption
-5.2
425
2.2
Volts
mA
Watts
550
2.9
PIN DESIGNATIONS
1. Power Supply (-V )
2. N.C.
3. LINV
42. N.C.
41. VRTF
40. N.C.
EE
1
28
4. Power Supply (-V )
39. Power Supply (-V )
EE
EE
5. AGND
6. DGND
7. D0 (LSB)
8. D1
9. D2
10. D3
38. Power Supply (-V )
37. N.C.
36. N.C.
35. AGND
34. Analog Input
33. AGND
32. VRF/2
EE
11. D4
12. D5
13. D6
14. D7 (MSB)
15. DGND
16. AGND
31. AGND
30. Analog Input
29. AGND
28. N.C.
27. N.C.
17. Power Supply (-V )
26. Power Supply (-V )
EE
EE
18. MINV
19. N.C.
20. CLK
21. CLK
25. Power Supply (-V )
EE
24. N.C.
23. VRFB
22. N.C.
21
22
PACKAGE OUTLINE
INCHES
MILLIMETERS
DIM
A
MINIMUM
0.081
MAXIMUM
0.099
MINIMUM
2.06
MAXIMUM
2.51
B
0.016
0.020
0.41
0.51
C
D
E
0.095
0.105
2.41
2.67
1.27
1.27
6.99
0.050 (typ)
0.050 (typ)
0.275
F
G
H
I
2.080
0.585
0.008
0.600
2.120
0.605
0.015
0.620
52.83
14.86
0.20
53.85
15.37
0.38
J
15.24
15.75
m ic ro ne tworks 324 Clark Street, Worcester, MA 01606-1293 Phone: (508)852-5400; FAX (508) 853-8296
will give the best performance. The
converter is bonded-out to place the digital
pins on the left side of the package with
the analog pins located on the right side of
the package. Additionally, an RF bead
connection through a single point from the
analog to digital ground planes will reduce
ground noise pickup.
APPLICATIONS INFORMATION - The
MN5920 and MN5921 are fast monolithic
8-bit parallel flash A/D converters. The
nominal conversion rate for these two
devices is 150MSPS with an analog input
bandwidth in excess of 200MHz.
The devices are designed with input
preamplifiers
inserted
between
the
reference ladder and input comparators
facilitating a reduction in the level of clock
transient kickback into the input and
POWER SUPPLIES AND GROUNDING
- The -VEE connections are the device’s
power supply with respect to analog
ground and is nominally -5.2V. The power
supply pins should be bypassed as close
to the device as possible with at least a
0.01uF ceramic capacitor. A 1uF tantalum
capacitor should also be employed for low
frequency noise suppression. The device’s
digital ground connection is the reference
for the ECL outputs and is to be referenced
reference
ladder
circuitry.
These
preamplifiers act as buffers and stabilize
the input capacitance so that it remains
constant for varying input frequencies and,
therefore, making the devices easier to
drive than other flash A/D converters. In
addition the MN5920 and MN5921
incorporate proprietary decoding scheme
that reduces metastable errors (sometimes
referred to as sparkle codes or flyers) to a
maximum of 1 LSB.
to
the
output
pulldown
voltage
appropriately bypassed as shown in the
applications diagram.
These devices are designed with true
differential analog and digital paths from
the preamplifiers to the output buffers
(Current Mode Logic) for reducing potential
missing codes while rejecting common
mode noise.
ANALOG INPUT - There are two analog
input pins tied internally to the same point.
Either one may be used as an analog input
sense and the other one for input force
connections. This is convenient for testing
the source signal when ensuring sufficient
drive capability. The pins can also be tied
together and driven single-ended. The
Signature errors are also reduced by
careful layout of the analog circuitry. Every
comparator also has a clock buffer to
reduce differential delays and to improve
signal-to-noise ratio. The output drive
capability of the device can provide full
ECL swings into 50W loads.
TYPICAL INTERFACE CIRCUIT - The
typical interface circuit is shown below.
The MN5920/21 is relatively easy to apply
depending on the accuracy needed in the
intended application. Wire-wrap may be
employed with careful point-to-point ground
connections if desired, but to achieve best
operation, a double-sided PC board with a
ground plane on the component side
separated into digital and analog sections
m ic ro ne tworks 324 Clark Street, Worcester, MA 01606-1293 Phone: (508)852-5400; FAX (508) 853-8296
MN5920 and MN5921 offer superior
performance compared to similar devices
due to their internal comparator design.
Each comparator circuit is preceded with a
preamplifier stage making the devices
easier to drive because of a constant
capacitance presented to the driving
source. This constant capacitance results
in less slew rate distortion.
devices
(straight
binary
,
two’s
complement, etc.). See the following table
for additional information. Both MINV and
LINV are in the logic “low” state when left
open. The high state can be obtained by
tying these inputs to analog ground
through a diode or 3.9KW resistor.
DIGITAL OUTPUTS - The device’s digital
outputs can drive ECL levels into 50W
when pulled down to -2V. When pulled
down to -5.2V, the output can drive 150W
to 1KW loads.
CLOCK INPUTS - The clock inputs are
designed to be driven differentially with
ECL levels. The clock may be driven
single-ended since CLK is internally biased
to-1.3V. CLK may be left open, however, it
is recommended that a 0.01uF capacitor
be connected from CLK to analog ground.
Please note that overall performance may
be degraded due to increased clock noise
and or jitter in this configuration.
REFERENCE INPUTS - The device’s
have two reference input connections and
one external reference tap. The reference
bottom force connection is typically
connected to a -2V reference source
(please see the applications diagram) and
a reference top force connection typically
tied to analog ground. The reference mid
tap should be bypassed to analog ground
for further noise suppression.
OUTPUT LOGIC CONTROL (MINV,
LINV) - The are ECL-compatible digital
control lines designed to accommodate
changing the output coding of these
m ic ro ne tworks 324 Clark Street, Worcester, MA 01606-1293 Phone: (508)852-5400; FAX (508) 853-8296
DIGITAL OUTPUT CODING
MINV
LINV
0V
0
0
0
1
1
0
1
1
1111 1111
1111 1110
1000 0000
1000 0001
0111 1111
0111 1110
0000 0000
0000 0001
1000 0000
0111 1111
1111 1111
0000 0000
0000 0000
1111 1111
0111 1111
1000 0000
0000 0001
0000 0000
0111 1110
0111 1111
1000 0001
1000 0000
1111 1110
1111 1111
-2V
TIMING DIAGRAM
m ic ro ne tworks 324 Clark Street, Worcester, MA 01606-1293 Phone: (508)852-5400; FAX (508) 853-8296
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