SSM20N03P [SSC]

N-CHANNEL ENHANCEMENT-MODE POWER MOSFET; N沟道增强模式功率MOSFET
SSM20N03P
型号: SSM20N03P
厂家: SILICON STANDARD CORP.    SILICON STANDARD CORP.
描述:

N-CHANNEL ENHANCEMENT-MODE POWER MOSFET
N沟道增强模式功率MOSFET

文件: 总6页 (文件大小:443K)
中文:  中文翻译
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SSM20N03S,P  
N-CHANNEL ENHANCEMENT-MODE  
POWER MOSFET  
Dynamic dv/dt rating  
Repetitive-avalanche rated  
Fast switching  
BVDSS  
RDS(ON)  
ID  
30V  
52mΩ  
20A  
D
S
G
Simple drive requirement  
Description  
Power MOSFETs from Silicon Standard provide the  
designer with the best combination of fast switching,  
G
D
S
TO-263  
ruggedized device design, low on-resistance and cost-effectiveness.  
The TO-263 package is widely preferred for commercial and  
industrial surface mount applications and suited for low voltage  
applications such as DC/DC converters. The through-hole version  
(SSM20N03P) is available for low-footprint applications.  
G
TO-220  
D
S
Absolute Maximum Ratings  
Symbol  
Parameter  
Rating  
30  
Units  
V
VDS  
VGS  
Drain-Source Voltage  
Gate-Source Voltage  
V
± 20  
20  
Continuous Drain Current, VGS @ 10V  
ID@TC=25  
ID@TC=100℃  
IDM  
A
Continuous Drain Current, VGS @ 10V  
Pulsed Drain Current1  
13  
A
58  
31  
A
PD@TC=25℃  
Total Power Dissipation  
W
Linear Derating Factor  
0.25  
W/℃  
TSTG  
TJ  
Storage Temperature Range  
Operating Junction Temperature Range  
-55 to 150  
-55 to 150  
Thermal Data  
Symbol  
Parameter  
Value  
4.0  
Unit  
/W  
/W  
Rthj-case  
Thermal Resistance Junction-case  
Thermal Resistance Junction-ambient  
Max.  
Max.  
Rthj-amb  
62  
Rev.2.01 6/26/2003  
www.SiliconStandard.com  
1 of 6  
SSM20N03S,P  
Electrical Characteristics @ T=25oC (unless otherwise specified)  
j
Symbol  
BVDSS  
Parameter  
Drain-Source Breakdown Voltage  
Breakdown Voltage Temperature Coefficient Reference to 25, ID=1mA  
Test Conditions  
Min. Typ. Max. Units  
VGS=0V, ID=250uA  
30  
-
-
0.037  
-
-
-
V
ΔBVDSS/ΔTj  
V/℃  
mΩ  
RDS(ON)  
Static Drain-Source On-Resistance  
VGS=10V, ID=10A  
-
52  
VGS=4.5V, ID=8A  
VDS=VGS, ID=250uA  
VDS=10V, ID=10A  
VDS=30V, VGS=0V  
VDS=24V, VGS=0V  
-
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
85  
3
mΩ  
V
VGS(th)  
gfs  
Gate Threshold Voltage  
Forward Transconductance  
Drain-Source Leakage Current (T=25oC)  
3
-
S
IDSS  
uA  
uA  
nA  
nC  
nC  
nC  
ns  
ns  
ns  
ns  
pF  
pF  
pF  
j
-
1
Drain-Source Leakage Current (T=150oC)  
-
100  
j
IGSS  
Qg  
Gate-Source Leakage  
Total Gate Charge2  
Gate-Source Charge  
Gate-Drain ("Miller") Charge  
Turn-on Delay Time2  
Rise Time  
VGS=  
-
± 20V  
±100  
ID=10A  
6.1  
1.4  
4
-
-
-
-
-
-
Qgs  
Qgd  
td(on)  
tr  
VDS=24V  
VGS=5V  
VDS=15V  
ID=20A  
4.9  
29  
14.3  
3.6  
290  
160  
45  
td(off)  
tf  
Turn-off Delay Time  
Fall Time  
RG=3.3Ω,VGS=10V  
RD=0.75Ω  
VGS=0V  
-
-
-
-
Ciss  
Coss  
Crss  
Input Capacitance  
Output Capacitance  
Reverse Transfer Capacitance  
VDS=25V  
f=1.0MHz  
Source-Drain Diode  
Symbol  
Parameter  
Test Conditions  
Min. Typ. Max. Units  
A
A
V
IS  
Continuous Source Current ( Body Diode )  
Pulsed Source Current ( Body Diode )1  
Forward On Voltage2  
VD=VG=0V , VS=1.3V  
-
-
-
-
-
-
20  
58  
ISM  
VSD  
Tj=25, IS=20A, VGS=0V  
1.3  
Notes:  
1.Pulse width limited by safe operating area.  
2.Pulse width <300us , duty cycle <2%.  
Rev.2.01 6/26/2003  
www.SiliconStandard.com  
2 of 6  
SSM20N03S,P  
50  
40  
30  
20  
10  
0
70  
60  
50  
40  
30  
20  
10  
0
T C =150 o C  
T C =25 o C  
V G =10V  
G =8.0V  
V
G =10V  
V
V G =8.0V  
V G =6.0V  
V G =6.0V  
V
V
G =4.0V  
G =3.0V  
V G =4.0V  
V G =3.0V  
8
0
1
2
3
4
5
6
7
9
0
1
2
3
4
5
6
7
V DS , Drain-to-Source Voltage (V)  
V DS , Drain-to-Source Voltage (V)  
Fig 1. Typical Output Characteristics  
Fig 2. Typical Output Characteristics  
85  
80  
75  
70  
65  
60  
55  
50  
45  
40  
35  
1.80  
1.60  
1.40  
1.20  
1.00  
0.80  
0.60  
I D =10A  
V G =10V  
I
D =10A  
T C =25 o C  
Ω
Ω
Ω
Ω
-50  
0
50  
100  
150  
3
4
5
6
7
8
9
10  
11  
T j , Junction Temperature ( o C)  
V GS (V)  
Fig 3. On-Resistance v.s. Gate Voltage  
Fig 4. Normalized On-Resistance  
v.s. Junction Temperature  
Rev.2.01 6/26/2003  
www.SiliconStandard.com  
3 of 6  
SSM20N03S,P  
25  
20  
15  
10  
5
40  
30  
20  
10  
0
0
25  
50  
75  
100  
125  
150  
0
50  
100  
150  
T c , Case Temperature ( o C)  
T c ,Case Temperature( o C)  
Fig 5. Maximum Drain Current v.s.  
Case Temperature  
Fig 6. Typical Power Dissipation  
10  
100  
10  
1
10us  
1
DUTY=0.5  
100us  
0.2  
0.1  
PDM  
0.1  
t
SINGLE PULSE  
1ms  
0.05  
T
0.02  
0.01  
Duty factor = t/T  
Peak Tj = PDM x Rthjc + TC  
10ms  
D=0.01 T c =25 o C  
100ms  
0.01  
1
10  
100  
0.00001  
0.0001  
0.001  
0.01  
0.1  
1
10  
V DS (V)  
t , Pulse Width (s)  
Fig 7. Maximum Safe Operating Area  
Fig 8. Effective Transient Thermal Impedance  
Rev.2.01 6/26/2003  
www.SiliconStandard.com  
4 of 6  
SSM20N03S,P  
f=1.0MHz  
1000  
100  
10  
12  
10  
8
Id=10A  
V D =16V  
V D =20V  
V D =24V  
Ciss  
Coss  
6
Crss  
4
2
0
0
2
4
6
8
10  
12  
1
6
11  
16  
21  
26  
31  
V DS (V)  
Q G , Total Gate Charge (nC)  
Fig 9. Gate Charge Characteristics  
Fig 10. Typical Capacitance Characteristics  
3
2
1
0
100  
10  
T j = 150 o C  
T j = 25 o C  
1
0.1  
0.01  
-50  
0
50  
100  
150  
0.1  
0.3  
0.5  
0.7  
0.9  
1.1  
1.3  
1.5  
T j , Junction Temperature( o C)  
V SD (V)  
Fig 11. Forward Characteristic of  
Reverse Diode  
Fig 12. Gate Threshold Voltage v.s.  
Junction Temperature  
Rev.2.01 6/26/2003  
www.SiliconStandard.com  
5 of 6  
SSM20N03S,P  
VDS  
RD  
90%  
VDS  
TO THE  
OSCILLOSCOPE  
D
S
0.5x RATED VDS  
RG  
G
10%  
VGS  
+
-
10V  
VGS  
tr  
td(off)  
td(on)  
tf  
Fig 13. Switching Time Circuit  
Fig 14. Switching Time Waveform  
VG  
VDS  
QG  
TO THE  
OSCILLOSCOPE  
D
S
5V  
0.8 x RATED VDS  
QGD  
G
QGS  
VGS  
+
1~ 3 mA  
IG  
-
ID  
Q
Charge  
Fig 15. Gate Charge Circuit  
Fig 16. Gate Charge Waveform  
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no  
guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no  
responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its  
use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including  
without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to  
the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of  
Silicon Standard Corporation or any third parties.  
Rev.2.01 6/26/2003  
www.SiliconStandard.com  
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