SSM2603GY [SSC]

P-CHANNEL ENHANCEMENT MODE POWER MOSFET; P沟道增强型功率MOSFET
SSM2603GY
型号: SSM2603GY
厂家: SILICON STANDARD CORP.    SILICON STANDARD CORP.
描述:

P-CHANNEL ENHANCEMENT MODE POWER MOSFET
P沟道增强型功率MOSFET

文件: 总5页 (文件大小:307K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
SSM2603GY  
P-CHANNEL ENHANCEMENT MODE  
POWER MOSFET  
PRODUCT SUMMARY  
S
BVDSS  
RDS(ON)  
ID  
-20V  
65mΩ  
-5.0A  
Simple Drive Requirement  
Small Package Outline  
Surface Mount Device  
D
D
G
D
SOT-26  
D
DESCRIPTION  
D
S
Advanced Power MOSFETs utilized advanced processing techniques  
to achieve the lowest possible on-resistance, extremely efficient and  
cost-effectiveness device.  
G
The SOT-26 package is universally used for all commercial–industrial  
applications.  
Pb-free; RoHS-compliant  
ABSOLUTE MAXIMUM RATINGS  
Symbol  
Parameter  
Drain-Source Voltage  
Rating  
Units  
V
VDS  
VGS  
-20  
±12  
Gate-Source Voltage  
V
ID@TA=25  
ID@TA=70℃  
IDM  
Continuous Drain Current3  
Continuous Drain Current3  
Pulsed Drain Current1,2  
-5  
A
-4  
A
-20  
A
PD@TA=25℃  
Total Power Dissipation  
2
W
Linear Derating Factor  
0.016  
-55 to 150  
-55 to 150  
W/℃  
TSTG  
TJ  
Storage Temperature Range  
Operating Junction Temperature Range  
THERMAL DATA  
Symbol  
Parameter  
Thermal Resistance Junction-ambient3  
Value  
62.5  
Unit  
Rthj-a  
Max.  
/W  
11/29/2007 Rev.1.00  
www.SiliconStandard.com  
1
SSM2603GY  
ELECTRICAL CHARACTERISTICS  
(TJ=25oC unless otherwise specified)  
Symbol  
BVDSS  
Parameter  
Test Conditions  
VGS=0V, ID=-250uA  
Min. Typ. Max. Units  
Drain-Source Breakdown Voltage  
-20  
-
-0.1  
-
-
V
ΔBVDSS/ΔTj  
Breakdown Voltage Temperature Coefficient Reference to 25, ID=-1mA  
-
-
-
V/℃  
mΩ  
mΩ  
RDS(ON)  
Static Drain-Source On-Resistance2 VGS=-10V, ID=-4.5A  
53  
65  
VGS=-4.5V, ID=-4.2A  
VGS=-2.5V, ID=-2.0A  
-
-
-
-
120 mΩ  
VGS(th)  
gfs  
Gate Threshold Voltage  
VDS=VGS, ID=-250uA  
VDS=-5V, ID=-2.8A  
VDS=-20V, VGS=0V  
VDS=-16V, VGS=0V  
-0.5  
-
-1.2  
V
Forward Transconductance  
Drain-Source Leakage Current (T=25oC)  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
9
-
S
IDSS  
uA  
uA  
nA  
nC  
nC  
nC  
ns  
ns  
ns  
ns  
pF  
pF  
pF  
-
-1  
j
Drain-Source Leakage Current (T=55oC)  
-
-10  
j
IGSS  
Qg  
±12V  
±100  
Gate-Source Leakage  
Total Gate Charge2  
Gate-Source Charge  
Gate-Drain ("Miller") Charge  
Turn-on Delay Time2  
Rise Time  
VGS  
=
-
ID=-4.2A  
10.6  
2.32  
3.68  
5.9  
3.6  
32.4  
2.6  
16  
-
Qgs  
Qgd  
td(on)  
tr  
VDS=-16V  
VGS=-4.5V  
VDS=-15V  
ID=-4.2A  
-
-
-
td(off)  
tf  
Turn-off Delay Time  
Fall Time  
RG=6Ω,VGS=-10V  
RD=3.6Ω  
VGS=0V  
-
-
Ciss  
Coss  
Crss  
Input Capacitance  
Output Capacitance  
Reverse Transfer Capacitance  
740 1200  
VDS=-15V  
f=1.0MHz  
167  
126  
-
-
SOURCE-DRAIN DIODE  
Symbol  
Parameter  
Test Conditions  
Min. Typ. Max. Units  
VSD  
trr  
Forward On Voltage2  
Reverse Recovery Time2  
Reverse Recovery Charge  
IS=-1.2A, VGS=0V  
IS=-4.2A, VGS=0V,  
dI/dt=100A/µs  
-
-
-
-
-1.2  
V
ns  
nC  
27.7  
22  
-
-
Qrr  
Notes:  
1.Pulse width limited by Max. junction temperature.  
2.Pulse width <300us , duty cycle <2%.  
3.Surface mounted on 1 in2 copper pad of FR4 board ; 156/W when mounted on min. copper pad.  
11/29/2007 Rev.1.00  
www.SiliconStandard.com  
2
SSM2603GY  
40  
30  
20  
10  
0
36  
32  
28  
24  
20  
16  
12  
8
-5.0V  
-4.0V  
T A =25 o  
C
T A = 1 5 0 o  
C
-5.0V  
-4.0V  
-3.0V  
-3.0V  
V G = -2.0V  
4
V
G = -2.0V  
0
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
-V DS , Drain-to-Source Voltage (V)  
-V DS , Drain-to-Source Voltage (V)  
Fig 1. Typical Output Characteristics  
Fig 2. Typical Output Characteristics  
220  
180  
140  
100  
60  
1.8  
1.6  
1.4  
1.2  
1
I D = -4.2A  
I D =-4.2A  
T A =25 o  
C
V GS = -4.5V  
Ω
0.8  
0.6  
20  
0
2
4
6
8
10  
12  
-50  
0
50  
100  
150  
T j , Junction Temperature ( o C)  
-V GS , Gate-to-Source Voltage (V)  
Fig 3. On-Resistance v.s. Gate Voltage  
Fig 4. Normalized On-Resistance  
v.s. Junction Temperature  
1.5  
10  
1
1
T j =150 o C  
T j =25 o C  
0.5  
0.1  
0
0.01  
-50  
0
50  
100  
150  
0
0.4  
0.8  
1.2  
1.6  
T j , Junction Temperature ( o C)  
-V SD , Source-to-Drain Voltage (V)  
Fig 5. Forward Characteristic of  
Reverse Diode  
Fig 6. Gate Threshold Voltage v.s.  
Junction Temperature  
11/29/2007 Rev.1.00  
www.SiliconStandard.com  
3
SSM2603GY  
f=1.0MHz  
C iss  
12  
10  
8
1000  
100  
10  
I D = -4.2A  
V DS = -16V  
C oss  
C rss  
6
4
2
0
0
5
10  
15  
20  
25  
1
5
9
13  
17  
21  
25  
29  
Q G , Total Gate Charge (nC)  
-V DS , Drain-to-Source Voltage (V)  
Fig 7. Gate Charge Characteristics  
Fig 8. Typical Capacitance Characteristics  
100  
1
Duty factor=0.5  
0.2  
0.1  
10  
0.1  
1ms  
0.05  
PDM  
1
0.01  
t
10ms  
T
Single Pulse  
0.01  
Duty factor = t/T  
100ms  
Peak Tj = PDM x Rthja + Ta  
Rthja = 156/W  
0.1  
T A =25 o C  
1s  
DC  
Single Pulse  
0.001  
0.01  
0.0001  
0.001  
0.01  
0.1  
1
10  
100  
1000  
0.1  
1
10  
100  
-V DS , Drain-to-Source Voltage (V)  
t , Pulse Width (s)  
Fig 9. Maximum Safe Operating Area  
Fig 10. Effective Transient Thermal Impedance  
VDS  
VG  
90%  
QG  
-4.5V  
QGS  
QGD  
10%  
VGS  
tr  
td(on)  
td(off)tf  
Charge  
Q
Fig 11. Switching Time Waveform  
Fig 12. Gate Charge Waveform  
11/29/2007 Rev.1.00  
www.SiliconStandard.com  
4
SSM2603GY  
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no  
guarantee or warranty, expressed or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no  
responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its  
use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including  
without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to  
the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of  
Silicon Standard Corporation or any third parties.  
11/29/2007 Rev.1.00  
www.SiliconStandard.com  
5

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