SSM4800M [SSC]
N-CHANNEL ENHANCEMENT MODE POWER MOSFET; N沟道增强型功率MOSFET
| 型号： | SSM4800M |
| 厂家： | 
SILICON STANDARD CORP. |
| 描述： | N-CHANNEL ENHANCEMENT MODE POWER MOSFET |
| 文件： | 总6页 (文件大小：445K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SSM4800M
N-CHANNEL ENHANCEMENT MODE
POWER MOSFET
Low On-Resistance
Fast Switching
BVDSS
R DS(ON)
I D
25V
18mΩ
9A
D
D
D
D
Simple Drive Requirement
G
S
S
SO-8
S
Description
D
S
Power MOSFETs from Silicon Standard provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and cost-effectiveness.
G
The SSM4800M is in the SO-8 package, which is widely preferred for
commercial and industrial surface mount applications, and is well suited
for low-voltage applications such as DC/DC converters.
Absolute Maximum Ratings
Symbol
Parameter
Rating
25
Units
V
VDS
VGS
Drain-Source Voltage
Gate-Source Voltage
V
± 20
Continuous Drain Current, VGS @ 10V
ID@TA=25℃
ID@TA=70℃
IDM
9
A
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current1
7
40
A
A
PD@TA=25℃
Total Power Dissipation
2.5
W
Linear Derating Factor
0.02
W/℃
℃
℃
TSTG
TJ
Storage Temperature Range
Operating Junction Temperature Range
-55 to 150
-55 to 150
Thermal Data
Symbol
Parameter
Value
50
Unit
Rthj-amb
Thermal Resistance Junction-ambient
Max.
℃/W
Rev.2.01 6/26/2003
www.SiliconStandard.com
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SSM4800M
Electrical Characteristics @ Tj=25oC (unless otherwise specified)
Symbol
BVDSS
Parameter
Test Conditions
VGS=0V, ID=250uA
Min. Typ. Max. Units
Drain-Source Breakdown Voltage
25
-
-
0.037
-
-
-
V
ΔBVDSS/ΔTj
Breakdown Voltage Temperature Coefficient Reference to 25℃, ID=1mA
Static Drain-Source On-Resistance VGS=10V, ID=9A
VGS=4.5V, ID=7A
V/℃
mΩ
RDS(ON)
-
18
-
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
33
3
mΩ
V
VGS(th)
gfs
Gate Threshold Voltage
VDS=VGS, ID=250uA
VDS=15V, ID=10A
VDS=25V, VGS=0V
VDS=20V, VGS=0V
Forward Transconductance
Drain-Source Leakage Current (T=25oC)
20
-
-
S
IDSS
uA
uA
nA
nC
nC
nC
ns
ns
ns
ns
pF
pF
pF
j
1
Drain-Source Leakage Current (T=55oC)
-
25
j
IGSS
Qg
Gate-Source Leakage
Total Gate Charge2
Gate-Source Charge
Gate-Drain ("Miller") Charge
Turn-on Delay Time2
Rise Time
V =
GS
-
± 20V
±100
ID=9A
10.9
1.9
7.4
7
-
-
-
-
-
-
Qgs
Qgd
td(on)
tr
VDS=15V
VGS=5V
VDS=15V
ID=1A
10.5
20
17.5
390
245
100
td(off)
tf
Turn-off Delay Time
Fall Time
RG=6.2Ω,VGS=10V
RD=15Ω
VGS=0V
-
-
-
-
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
VDS=25V
f=1.0MHz
Source-Drain Diode
Symbol
Parameter
Test Conditions
Min. Typ. Max. Units
A
A
V
IS
Continuous Source Current ( Body Diode )
Pulsed Source Current ( Body Diode )1
Forward On Voltage2
VD=VG=0V , VS=1.3V
-
-
-
-
-
-
2.3
40
ISM
VSD
Tj=25℃, IS=2.3A, VGS=0V
1.3
Notes:
1.Pulse width limited by safe operating area.
2.Pulse width <300us , duty cycle <2%.
Rev.2.01 6/26/2003
www.SiliconStandard.com
2 of 6
SSM4800M
40
30
20
10
0
40
30
20
10
0
T C =150 o C
T C =25 o C
V G =10V
V G =8.0V
V G =10V
V
V
G =8.0V
G =6.0V
V
G =6.0V
V
G =4.0V
V G =4.0V
0
1
2
3
4
5
6
0
1
2
3
4
5
6
V DS , Drain-to-Source Voltage (V)
V DS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1.80
34
30
26
22
18
14
10
I D =9A
I D =9A
1.60
V G =10V
T c =25 ℃
1.40
1.20
1.00
0.80
0.60
Ω
Ω
Ω
Ω
-50
0
50
100
150
2
3
4
5
6
7
8
9
10
11
T j , Junction Temperature ( o C)
V GS (V)
Fig 3. On-Resistance v.s. Gate Voltage
Fig 4. Normalized On-Resistance
v.s. Junction Temperature
Rev.2.01 6/26/2003
www.SiliconStandard.com
3 of 6
SSM4800M
10
9
8
7
6
5
4
3
2
1
0
3
2.5
2
1.5
1
0.5
0
25
50
75
100
125
150
0
50
100
150
T c , Case Temperature ( o C)
T c , Case Temperature ( o C)
Fig 5. Maximum Drain Current v.s.
Case Temperature
Fig 6. Typical Power Dissipation
1
100
10
1
DUTY=0.5
0.2
0.1
0.1
0.05
10us
0.02
0.01
PDM
100us
1ms
t
0.01
T
SINGLE PULSE
Duty factor = t/T
10ms
Peak Tj = PDM x Rthjc + TC
T c =25 o C
100ms
Single Pulse
0
0.001
0.1
1
10
100
0.0001
0.001
0.01
0.1
1
10
100
1000
V DS (V)
t , Pulse Width (s)
Fig 7. Maximum Safe Operating Area
Fig 8. Effective Transient Thermal Impedance
Rev.2.01 6/26/2003
www.SiliconStandard.com
4 of 6
SSM4800M
f=1.0MHz
16
14
12
10
8
10000
1000
100
I D =9A
DS =15V
V
Ciss
Coss
Crss
6
4
2
0
10
0
5
10
15
20
25
30
1
6
11
16
21
26
V DS (V)
Q G , Total Gate Charge (nC)
Fig 9. Gate Charge Characteristics
Fig 10. Typical Capacitance Characteristics
100
3
10
2
1
0
T j =150 o C
T j =25 o C
1
0.1
0.1
0.3
0.5
0.7
0.9
1.1
1.3
1.5
-50
0
50
100
150
V SD (V)
T j , Junction Temperature( o C)
Fig 11. Forward Characteristic of
Reverse Diode
Fig 12. Gate Threshold Voltage v.s.
Junction Temperature
Rev.2.01 6/26/2003
www.SiliconStandard.com
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SSM4800M
VDS
RD
90%
VDS
TO THE
OSCILLOSCOPE
D
S
0.6 x RATED VDS
RG
G
10%
VGS
+
-
10V
VGS
td(off)
td(on) tr
tf
Fig 13. Switching Time Circuit
Fig 14. Switching Time Waveform
VG
5V
VDS
QG
TO THE
OSCILLOSCOPE
D
S
0.6 x RATED VDS
QGD
QGS
G
VGS
+
1~ 3 mA
IG
-
ID
Q
Charge
Fig 15. Gate Charge Circuit
Fig 16. Gate Charge Waveform
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no
guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no
responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its
use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including
without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to
the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of
Silicon Standard Corporation or any third parties.
Rev.2.01 6/26/2003
www.SiliconStandard.com
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