SST32HF401-90-4E-L3K [SST]
Multi-Purpose Flash (MPF) + SRAM ComboMemory; 多用途闪存（ MPF） + SRAM ComboMemory
| 型号： | SST32HF401-90-4E-L3K |
| 厂家： | 
SILICON STORAGE TECHNOLOGY, INC |
| 描述： | Multi-Purpose Flash (MPF) + SRAM ComboMemory |
| 文件： | 总26页 (文件大小：324K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402
SST32HF201 / 202 / 401 / 4022Mb Flash + 1Mb SRAM, 2Mb Flash + 2Mb SRAM,
Preliminary Specifications
4Mb Flash + 1Mb SRAM, 4Mb Flash + 2Mb SRAM (x16) MCP ComboMemories
FEATURES:
•
MPF + SRAM ComboMemory
•
•
Latched Address and Data for Flash
Flash Fast Erase and Word-Program:
– SST32HF201: 128K x16 Flash + 64K x16 SRAM
– SST32HF202: 128K x16 Flash + 128K x16 SRAM
– SST32HF401: 256K x16 Flash + 64K x16 SRAM
– SST32HF402: 256K x16 Flash + 128K x16 SRAM
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Word-Program Time: 14 µs (typical)
– Chip Rewrite Time:
•
•
Single 2.7-3.3V Read and Write Operations
Concurrent Operation
SST32HF201/202: 2 seconds (typical)
SST32HF401/402: 4 seconds (typical)
– Read from or write to SRAM while
Erase/Program Flash
•
•
Flash Automatic Erase and Program Timing
– Internal VPP Generation
•
•
Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
Flash End-of-Write Detection
– Toggle Bit
– Data# Polling
Low Power Consumption:
– Active Current: 15 mA (typical) for
Flash or SRAM Read
– Standby Current: 20 µA (typical)
•
•
•
•
CMOS I/O Compatibility
JEDEC Standard Command Set
Conforms to Flash pinout
Package Available
•
•
Flexible Erase Capability
– Uniform 2 KWord sectors
– Uniform 32 KWord size blocks
– 48-ball LFBGA (6mm x 8mm)
Fast Read Access Times:
– Flash: 70 and 90 ns
– SRAM: 70 and 90 ns
PRODUCT DESCRIPTION
The SST32HF20x/40x ComboMemory devices integrate a
128K x16 or 256K x16 CMOS flash memory bank with a
64K x16 or 128K x16 CMOS SRAM memory bank in a
Multi-Chip Package (MCP), manufactured with SST’s pro-
prietary, high performance SuperFlash technology.
SRAM bank. The flash memory bank enable signal, BEF#
selects the flash memory bank. The WE# signal has to be
used with Software Data Protection (SDP) command
sequence when controlling the Erase and Program opera-
tions in the flash memory bank. The SDP command
sequence protects the data stored in the flash memory
bank from accidental alteration.
Featuring high performance Word-Program, the flash
memory bank provides a maximum Word-Program time of
14 µsec. The entire flash memory bank can be erased and
programmed word-by-word in typically 2 seconds for the
SST32HF201/202 and 4 seconds for the SST32HF401/
402, when using interface features such as Toggle Bit or
Data# Polling to indicate the completion of Program opera-
tion. To protect against inadvertent flash write, the
SST32HF20x/40x devices contain on-chip hardware and
software data protection schemes.The SST32HF20x/40x
devices offer a guaranteed endurance of 10,000 cycles.
Data retention is rated at greater than 100 years.
The SST32HF20x/40x provide the added functionality of
being able to simultaneously read from or write to the
SRAM bank while erasing or programming in the flash
memory bank. The SRAM memory bank can be read or
written while the flash memory bank performs Sector-
Erase, Bank-Erase, or Word-Program concurrently. All
flash memory Erase and Program operations will automati-
cally latch the input address and data signals and complete
the operation in background without further input stimulus
requirement. Once the internally controlled Erase or Pro-
gram cycle in the flash bank has commenced, the SRAM
bank can be accessed for Read or Write.
The SST32HF20x/40x devices consist of two independent
memory banks with respective bank enable signals. The
Flash and SRAM memory banks are superimposed in the
same memory address space. Both memory banks share
common address lines, data lines, WE# and OE#. The
memory bank selection is done by memory bank enable
signals. The SRAM bank enable signal, BES# selects the
The SST32HF20x/40x devices are suited for applications
that use both flash memory and SRAM memory to store
code or data. For systems requiring low power and small
form factor, the SST32HF20x/40x devices significantly
improve performance and reliability, while lowering power
©2001 Silicon Storage Technology, Inc.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF and ComboMemory are trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
S71209-00-000 9/01
1
557
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402
Preliminary Specifications
consumption, when compared with multiple chip solutions.
control and is used to gate data from the output pins. The
data bus is in high impedance state when OE# is high. See
Figure 2 for the Read cycle timing diagram.
The SST32HF20x/40x inherently use less energy during
erase and program than alternative flash technologies. The
total energy consumed is a function of the applied voltage,
current, and time of application. Since for any given voltage
range, the SuperFlash technology uses less current to pro-
gram and has a shorter erase time, the total energy con-
sumed during any Erase or Program operation is less than
alternative flash technologies.
SRAM Write
The SRAM Write operation of the SST32HF20x/40x is
controlled by WE# and BES#, both have to be low for the
system to write to the SRAM. During the Word-Write oper-
ation, the addresses and data are referenced to the rising
edge of either BES# or WE#, whichever occurs first. The
write time is measured from the last falling edge to the first
rising edge of BES# or WE#. See Figures 3 and 4 for the
Write cycle timing diagrams.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose
Erase and Program times increase with accumulated
Erase/Program cycles.
Flash Operation
With BEF# active, the SST32HF201/202 operate as 128K
x16 flash memory and the SST32HF401/402 operates as
256K x16 flash memory. The flash memory bank is read
using the common address lines, data lines, WE# and
OE#. Erase and Program operations are initiated with the
JEDEC standard SDP command sequences. Address and
data are latched during the SDP commands and during the
internally timed Erase and Program operations.
Device Operation
The ComboMemory uses BES# and BEF# to control oper-
ation of either the SRAM or the flash memory bank. When
BES# is low, the SRAM Bank is activated for Read and
Write operation. When BEF# is low the flash bank is acti-
vated for Read, Program or Erase operation. BES# and
BEF# cannot be at low level at the same time. If BES# and
BEF# are both asserted to low level bus contention will
result and the device may suffer permanent damage. All
address, data, and control lines are shared by SRAM Bank
and flash bank which minimizes power consumption and
loading. The device goes into standby when both bank
enables are high.
Flash Read
The Read operation of the SST32HF20x/40x devices is
controlled by BEF# and OE#. Both have to be low, with
WE# high, for the system to obtain data from the outputs.
BEF# is used for flash memory bank selection. When
BEF# and BES# are high, both banks are deselected and
only standby power is consumed. OE# is the output con-
trol and is used to gate data from the output pins. The data
bus is in high impedance state when OE# is high. Refer to
Figure 5 for further details.
SRAM Operation
With BES# low and BEF# high, the SST32HF201/401
operate as 64K x16 CMOS SRAM, and the SST32HF202/
402 operates as 128K x16 CMOS SRAM, with fully static
operation requiring no external clocks or timing strobes.
The SST32HF201/401 SRAM is mapped into the first 64
KWord address space of the device, and the
SST32HF202/402 SRAM is mapped into the first 128
KWord address space. When BES# and BEF# are high,
both memory banks are deselected and the device enters
standby mode. Read and Write cycle times are equal. The
control signals UBS# and LBS# provide access to the
upper data byte and lower data byte. See Table 3 for SRAM
read and write data byte control modes of operation.
Flash Erase/Program Operation
SDP commands are used to initiate the flash memory bank
Program and Erase operations of the SST32HF20x/40x.
SDP commands are loaded to the flash memory bank
using standard microprocessor write sequences. A com-
mand is loaded by asserting WE# low while keeping BEF#
low and OE# high. The address is latched on the falling
edge of WE# or BEF#, whichever occurs last. The data is
latched on the rising edge of WE# or BEF#, whichever
occurs first.
SRAM Read
Flash Word-Program Operation
The SRAM Read operation of the SST32HF20x/40x is
controlled by OE# and BES#, both have to be low with
WE# high for the system to obtain data from the outputs.
BES# is used for SRAM bank selection. OE# is the output
The flash memory bank of the SST32HF20x/40x devices is
programmed on a word-by-word basis. Before Program
operations, the memory must be erased first. The Program
©2001 Silicon Storage Technology, Inc.
S71209-00-000 9/01 557
2
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402
Preliminary Specifications
operation consists of three steps. The first step is the three-
byte load sequence for Software Data Protection. The sec-
ond step is to load word address and word data. During the
Word-Program operation, the addresses are latched on the
falling edge of either BEF# or WE#, whichever occurs last.
The data is latched on the rising edge of either BEF# or
WE#, whichever occurs first. The third step is the internal
Program operation which is initiated after the rising edge of
the fourth WE# or BEF#, whichever occurs first. The Pro-
gram operation, once initiated, will be completed, within 20
µs. See Figures 6 and 7 for WE# and BEF# controlled Pro-
gram operation timing diagrams and Figure 17 for flow-
charts. During the Program operation, the only valid flash
Read operations are Data# Polling and Toggle Bit. During
the internal Program operation, the host is free to perform
additional tasks. Any SDP commands loaded during the
internal Program operation will be ignored.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command (10H)
at address 5555H in the last byte sequence. The Erase
operation begins with the rising edge of the sixth WE# or
CE#, whichever occurs first. During the Erase operation,
the only valid read is Toggle Bit or Data# Polling. See Table
4 for the command sequence, Figure 9 for timing diagram,
and Figure 20 for the flowchart. Any commands issued dur-
ing the Chip-Erase operation are ignored.
Write Operation Status Detection
The SST32HF20x/40x provide two software means to
detect the completion of a Write (Program or Erase) cycle,
in order to optimize the system Write cycle time. The soft-
ware detection includes two status bits: Data# Polling
(DQ7) and Toggle Bit (DQ6). The End-of-Write detection
mode is enabled after the rising edge of WE#, which ini-
tiates the internal Program or Erase operation.
Flash Sector/Block-Erase Operation
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con-
flict with either DQ7 or DQ6. In order to prevent spurious
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the Write cycle, otherwise the rejec-
tion is valid.
The Flash Sector/Block-Erase operation allows the system
to erase the device on a sector-by-sector (or block-by-
block) basis. The SST32HF20x/40x offer both Sector-
Erase and Block-Erase mode. The sector architecture is
based on uniform sector size of 2 KWord. The Block-Erase
mode is based on uniform block size of 32 KWord. The
Sector-Erase operation is initiated by executing a six-byte
command sequence with Sector-Erase command (30H)
and sector address (SA) in the last bus cycle. The address
lines A16-A11, for SST32HF201/202, and A17-A11, for
SST32HF401/402, are used to determine the sector
address. The Block-Erase operation is initiated by execut-
ing a six-byte command sequence with Block-Erase com-
mand (50H) and block address (BA) in the last bus cycle.
The address lines A16-A15, for SST32HF201/202, and A17-
A15, for SST32HF401/402, are used to determine the block
address. The sector or block address is latched on the fall-
ing edge of the sixth WE# pulse, while the command (30H
or 50H) is latched on the rising edge of the sixth WE#
pulse. The internal Erase operation begins after the sixth
WE# pulse. The End-of-Erase operation can be deter-
mined using either Data# Polling or Toggle Bit methods.
See Figures 11 and 12 for timing waveforms. Any com-
mands issued during the Sector- or Block-Erase operation
are ignored.
Flash Data# Polling (DQ7)
When the SST32HF20x/40x flash memory banks are in
the internal Program operation, any attempt to read DQ7
will produce the complement of the true data. Once the
Program operation is completed, DQ7 will produce true
data. Note that even though DQ7 may have valid data
immediately following the completion of an internal Write
operation, the remaining data outputs may still be invalid:
valid data on the entire data bus will appear in subsequent
successive Read cycles, after an interval of 1 µs. During
internal Erase operation, any attempt to read DQ7 will pro-
duce a ‘0’. Once the internal Erase operation is completed,
DQ7 will produce a ‘1’. The Data# Polling is valid after the
rising edge of the fourth WE# (or BEF#) pulse for Program
operation. For Sector- or Block-Erase, the Data# Polling is
valid after the rising edge of the sixth WE# (or BEF#) pulse.
See Figure 8 for Data# Polling timing diagram and Figure
18 for a flowchart.
Flash Chip-Erase Operation
The SST32HF20x/40x provide a Chip-Erase operation,
which allows the user to erase the entire memory array to
the “1” state. This is useful when the entire device must be
quickly erased.
©2001 Silicon Storage Technology, Inc.
S71209-00-000 9/01 557
3
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402
Preliminary Specifications
Flash Toggle Bit (DQ6)
CONCURRENT READ/WRITE STATE TABLE
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating ‘1’s
and ‘0’s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the toggling will
stop. The flash memory bank is then ready for the next
operation. The Toggle Bit is valid after the rising edge of the
fourth WE# (or BEF#) pulse for Program operation. For
Sector- or Bank-Erase, the Toggle Bit is valid after the rising
edge of the sixth WE# (or BEF#) pulse. See Figure 9 for
Toggle Bit timing diagram and Figure 18 for a flowchart.
Flash
Program/Erase
Program/Erase
SRAM
Read
Write
The device will ignore all SDP commands when an Erase
or Program operation is in progress. Note that Product
Identification commands use SDP; therefore, these com-
mands will also be ignored while an Erase or Program
operation is in progress.
Product Identification
Flash Memory Data Protection
The Product Identification mode identifies the devices as
the SST32HF20x/40x and manufacturer as SST. This
mode may be accessed by software operations only.
The hardware device ID Read operation, which is typi-
cally used by programmers, cannot be used on this
device because of the shared lines between flash and
SRAM in the multi-chip package. Therefore, applica-
tion of high voltage to pin A9 may damage this device.
Users may use the software Product Identification opera-
tion to identify the part (i.e., using the device ID) when using
multiple manufacturers in the same socket. For details, see
Tables 3 and 4 for software operation, Figure 13 for the
software ID entry and Read timing diagram, and Figure 19
for the ID entry command sequence flowchart.
The SST32HF20x/40x flash memory bank provides both
hardware and software features to protect nonvolatile data
from inadvertent writes.
Flash Hardware Data Protection
Noise/Glitch Protection: A WE# or BEF# pulse of less than
5 ns will not initiate a Write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#
high will inhibit the Flash Write operation. This prevents
inadvertent writes during power-up or power-down.
TABLE 1: PRODUCT IDENTIFICATION
Flash Software Data Protection (SDP)
Address
Data
The SST32HF20x/40x provide the JEDEC approved soft-
ware data protection scheme for all flash memory bank
data alteration operations, i.e., Program and Erase. Any
Program operation requires the inclusion of a series of
three-byte sequence. The three-byte load sequence is
used to initiate the Program operation, providing optimal
protection from inadvertent Write operations, e.g., during
the system power-up or power-down. Any Erase operation
requires the inclusion of six-byte load sequence. The
SST32HF20x/40x devices are shipped with the software
data protection permanently enabled. See Table 4 for the
specific software command codes. During SDP command
sequence, invalid SDP commands will abort the device to
the read mode, within Read Cycle Time (TRC).
Manufacturer’s ID
Device ID
0000H
00BFH
SST32HF201/202
SST32HF401/402
0001H
0001H
2789H
2780H
T1.0 557
Product Identification Mode Exit/Reset
In order to return to the standard read mode, the Software
Product Identification mode must be exited. Exiting is
accomplished by issuing the Exit ID command sequence,
which returns the device to the Read operation. Please
note that the software-reset command is ignored during an
internal Program or Erase operation. See Table 4 for soft-
ware command codes, Figure 14 for timing waveform and
Figure 19 for a flowchart.
Concurrent Read and Write Operations
The SST32HF20x/40x provide the unique benefit of being
able to read from or write to SRAM, while simultaneously
erasing or programming the Flash. This allows data alter-
ation code to be executed from SRAM, while altering the
data in Flash. The following table lists all valid states.
Design Considerations
SST recommends a high frequency 0.1 µF ceramic capac-
itor to be placed as close as possible between VDD and
VSS, e.g., less than 1 cm away from the VDD pin of the
©2001 Silicon Storage Technology, Inc.
S71209-00-000 9/01 557
4
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402
Preliminary Specifications
device. Additionally, a low frequency 4.7 µF electrolytic
capacitor from VDD to VSS should be placed within 1 cm of
the VDD pin.
FUNCTIONAL BLOCK DIAGRAM
Address Buffers
Control Logic
SRAM
UBS#
LBS#
BES#
BEF#
OE#
DQ - DQ
15
A
-A
8
MS
0
I/O Buffers
DQ - DQ
7
0
WE#
Address Buffers
& Latches
SuperFlash
Memory
557 ILL B1.0
TOP VIEW (balls facing down)
SST32HF201/202
TOP VIEW (balls facing down)
SST32HF401/402
6
5
4
3
2
1
6
V
A13 A12 A14 A15 A16 USB# DQ15
V
SS
SS
A13 A12 A14 A15 A16 USB# DQ15
5
4
3
2
1
DQ6
DQ4
DQ3
DQ1
A9
A8
A10 A11 DQ7 DQ14 DQ13
DQ6
DQ4
DQ3
DQ1
A9
A8
A10 A11 DQ7 DQ14 DQ13
WE# NC LBS# NC DQ5 DQ12
V
WE# NC LBS# NC DQ5 DQ12
V
DD
DD
BES# NC
NC
A6
A2
NC DQ2 DQ10 DQ11
A5 DQ0 DQ8 DQ9
BES# NC
NC
A6
A2
NC DQ2 DQ10 DQ11
A7
A3
NC
A4
A7
A3
A17
A4
A5
A1
DQ0 DQ8 DQ9
A0 BEF# OE#
V
A1
A0 BEF# OE#
V
SS
SS
A
B
C
D
E
F
G
H
A
B
C
D
E
F
G
H
FIGURE 1: PIN ASSIGNMENTS FOR 48-BALL LFBGA
©2001 Silicon Storage Technology, Inc.
S71209-00-000 9/01 557
5
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402
Preliminary Specifications
TABLE 2: PIN DESCRIPTION
Symbol
Pin Name
Functions
AMS1-A0
Address Inputs
To provide flash addresses, A16-A0 for 2M and A17-A0 for 4M.
To provide SRAM addresses, A15-A0 for 1M and A16-A0 for 2M.
DQ15-DQ0
Data Input/output
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a flash Erase/Program cycle.
The outputs are in tri-state when OE# or BES# and BEF# are high.
BES#
BEF#
OE#
WE#
VDD
SRAM Memory Bank Enable
Flash Memory Bank Enable
Output Enable
To activate the SRAM memory bank when BES# is low.
To activate the Flash memory bank when BEF# is low.
To gate the data output buffers.
Write Enable
To control the Write operations.
Power Supply
2.7-3.3V power supply
VSS
Ground
UBS#
LBS#
NC
Upper Byte Control (SRAM)
Lower Byte Control (SRAM)
No Connection
To enable DQ15-DQ8
To enable DQ7-DQ0
Unconnected Pins
T2.0 557
1. AMS = Most significant address
TABLE 3: OPERATION MODES SELECTION
Mode
BES#1 BEF#1 OE# WE# UBS# LBS# DQ15 to DQ8 DQ7 to DQ0
Address
Not Allowed
Flash
VIL
VIL
X2
X
X
X
X
X
X
Read
VIH
VIH
X
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIL
VIL
X
X
X
X
X
X
DOUT
DIN
X
DOUT
DIN
X
AIN
AIN
Program
Erase
Sector or Block address,
XXH for Chip-Erase
SRAM
Read
VIL
VIL
VIL
VIL
VIL
VIL
VIHC
X
VIH
VIH
VIH
VIH
VIH
VIH
VIHC
X
VIL
VIL
VIL
X
VIH
VIH
VIH
VIL
VIL
VIL
X
VIL
VIL
VIH
VIL
VIL
VIH
X
VIL
VIH
VIL
VIL
VIH
VIL
X
DOUT
DOUT
High Z
DIN
DOUT
High Z
DOUT
DIN
AIN
AIN
AIN
AIN
AIN
AIN
X
Write
X
DIN
High Z
DIN
X
High Z
High Z
Standby
X
High Z
Flash Write Inhibit
VIL
X
X
X
X
High Z / DOUT High Z / DOUT
High Z / DOUT High Z / DOUT
High Z / DOUT High Z / DOUT
X
X
X
VIH
X
X
X
X
X
VIH
VIL
VIH
VIH
X
X
X
X
Output Disable
VIH
VIL
VIL
VIH
X
VIH
X
X
X
High Z
High Z
High Z
High Z
High Z
High Z
X
VIH
X
VIH
X
X
VIH
VIH
X
Product Identification
Software Mode
VIH
VIL
VIL
VIH
X
X
Manufacturer’s ID (00BFH)
Device ID3
AMSF4-A1=VIL, A0=VIH
(See Table 4)
T3.2 557
1. Do not apply BES#=VIL and BEF#=VIL at the same time
2. X can be VIL or VIH, but no other value.
3. Device ID for: SST32HF201/202 = 2789H and SST32HF401/402 = 2780H
4. AMS = Most significant flash address
©2001 Silicon Storage Technology, Inc.
S71209-00-000 9/01 557
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Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402
Preliminary Specifications
TABLE 4: SOFTWARE COMMAND SEQUENCE
Command
Sequence
1st Bus
Write Cycle
2nd Bus
Write Cycle
3rd Bus
Write Cycle
4th Bus
Write Cycle
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr1 Data
Addr1
Data Addr1 Data Addr1 Data
Addr1
Data Addr1 Data
Word-Program
Sector-Erase
Block-Erase
Chip-Erase
5555H AAH 2AAAH 55H 5555H A0H Data
WA2
3
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H
SAX
BAX
30H
50H
3
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
Software ID Entry4,5 5555H AAH 2AAAH 55H 5555H 90H
Software ID Exit
Software ID Exit
XXH
F0H
5555H AAH 2AAAH 55H 5555H F0H
T4.1 557
1. Address format A14-A0 (Hex),Address A15 can be VIL or VIH, but no other value, for the Command sequence.
2. WA = Program Word address
3. SAX for Sector-Erase; uses AMS-A11 address lines
BAX for Block-Erase; uses AMS-A15 address lines
AMS = Most significant address
AMS = A16 for SST32HF201/202 and A17 for SST32HF401/402
4. The device does not remain in Software Product ID mode if powered down.
5. With AMS-A1 = 0; SST Manufacturer’s ID = 00BFH, is read with A0 = 0,
SST32HF201/202 Device ID = 2789H, is read with A0 = 1,
SST32HF401/402 Device ID = 2780H, is read with A0 = 1.
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +125°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.3V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.0V to VDD+2.0V
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circuit Current1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 15 and 16
Range
Ambient Temp
0°C to +70°C
VDD
Commercial
Extended
2.7-3.3V
2.7-3.3V
-20°C to +85°C
©2001 Silicon Storage Technology, Inc.
S71209-00-000 9/01 557
7
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402
Preliminary Specifications
TABLE 5: DC OPERATING CHARACTERISTICS (VDD = VDDF AND VDDS = 2.7-3.3V)
Limits
Symbol Parameter
Min
Max Units Test Conditions
Address input=VIL/VIH, at f=1/TRC Min,
IDD
Power Supply Current
VDD=VDD Max, all DQs open
Read
Flash
OE#=VIL, WE#=VIH
BEF#=VIL, BES#=VIH
20
20
45
mA
mA
mA
SRAM
BEF#=VIH, BES#=VIL
BEF#=VIH, BES#=VIL
Concurrent Operation
Write
Flash
WE#=VIL
BEF#=VIL, BES#=VIH, OE#=VIH
25
20
30
1
mA
mA
µA
µA
µA
V
SRAM
BEF#=VIH, BES#=VIL
ISB
Standby VDD Current
Input Leakage Current
Output Leakage Current
Input Low Voltage
VDD=VDD Max, BEF#=BES#=VIHC
VIN=GND to VDD, VDD=VDD Max
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
ILI
ILO
1
VIL
0.8
VIH
Input High Voltage
0.7 VDD
VDD-0.3
V
VDD=VDD Max
VIHC
VOLF
VOHF
VOLS
VOHS
Input High Voltage (CMOS)
Flash Output Low Voltage
Flash Output High Voltage
Output Low Voltage
Output High Voltage
V
VDD=VDD Max
0.2
0.4
V
IOL=100 µA, VDD=VDD Min
IOH=-100 µA, VDD=VDD Min
IOL=1 mA, VDD=VDD Min
IOH=-500 µA, VDD=VDD Min
VDD-0.2
2.2
V
V
V
T5.1 557
TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
100
Units
µs
1
TPU-READ
Power-up to Read Operation
Power-up to Program/Erase Operation
1
TPU-WRITE
100
µs
T6.0 557
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 7: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
VI/O = 0V
Maximum
1
CI/O
I/O Pin Capacitance
Input Capacitance
24 pF
12 pF
1
CIN
VIN = 0V
T7.0 557
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 8: FLASH RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
Units
Test Method
1
NEND
10,000
100
Cycles JEDEC Standard A117
1
TDR
Years
mA
JEDEC Standard A103
JEDEC Standard 78
1
ILTH
100 + IDD
T8.0 557
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2001 Silicon Storage Technology, Inc.
S71209-00-000 9/01 557
8
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402
Preliminary Specifications
AC CHARACTERISTICS
TABLE 9: SRAM READ CYCLE TIMING PARAMETERS
SST32HF201/202/401/402-70
SST32HF201/202/401/402-90
Symbol
TRCS
Parameter
Min
Max
Min
Max
Units
ns
Read Cycle Time
70
90
TAAS
Address Access Time
70
70
35
70
90
90
45
90
ns
TBES
Bank Enable Access Time
Output Enable Access Time
UBS#, LBS# Access Time
BES# to Active Output
ns
TOES
ns
TBYES
ns
1
TBLZS
0
0
0
0
0
0
ns
1
TOLZS
Output Enable to Active Output
UBS#, LBS# to Active Output
BES# to High-Z Output
ns
1
TBYLZS
ns
1
TBHZS
25
25
35
35
35
45
ns
1
TOHZS
Output Disable to High-Z Output
UBS#, LBS# to High-Z Output
Output Hold from Address Change
0
0
ns
1
TBYHZS
ns
TOHS
10
10
ns
T9.0 557
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 10: SRAM WRITE CYCLE TIMING PARAMETERS
SST32HF201/202/401/402-70 SST32HF201/202/401/402-90
Symbol Parameter
Min
70
60
60
0
Max
Min
90
80
80
0
Max
Units
ns
TWCS
TBWS
TAWS
Write Cycle Time
Bank Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
ns
ns
TASTS
TWPS
TWRS
TBYWS
TODWS
TOEWS
TDSS
ns
Write Pulse Width
60
0
80
0
ns
Write Recovery Time
ns
UBS#, LBS# to End-of-Write
Output Disable from WE# Low
Output Enable from WE# High
Data Set-up Time
60
80
ns
30
40
ns
0
30
0
0
40
0
ns
ns
TDHS
Data Hold from Write Time
ns
T10.0 557
©2001 Silicon Storage Technology, Inc.
S71209-00-000 9/01 557
9
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402
Preliminary Specifications
TABLE 11: FLASH READ CYCLE TIMING PARAMETERS
SST32HF201/202/401/402-70
SST32HF201/202/401/402-90
Symbol Parameter
Min
Max
Min
Max
Units
ns
TRC
TBE
TAA
Read Cycle Time
70
90
Bank Enable Access Time
Address Access Time
70
70
35
90
90
45
ns
ns
TOE
TBLZ
Output Enable Access Time
BEF# Low to Active Output
OE# Low to Active Output
BEF# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
ns
1
1
0
0
0
0
ns
TOLZ
TBHZ
ns
1
1
20
20
30
30
ns
TOHZ
ns
1
TOH
0
0
ns
T11.0 557
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 12: FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol
TBP
Parameter
Min
Max
Units
µs
Word-Program Time
Address Setup Time
Address Hold Time
WE# and BEF# Setup Time
WE# and BEF# Hold Time
OE# High Setup Time
OE# High Hold Time
BEF# Pulse Width
WE# Pulse Width
20
TAS
0
30
0
ns
TAH
ns
TBS
ns
TBH
0
ns
TOES
TOEH
TBPW
TWP
TWPH
TBPH
TDS
0
ns
10
40
40
30
30
30
0
ns
ns
ns
WE# Pulse Width High
BEF# Pulse Width High
Data Setup Time
ns
ns
ns
TDH
Data Hold Time
ns
TIDA
TSE
Software ID Access and Exit Time
Sector-Erase
150
25
ns
ms
ms
TBE
Block-Erase
25
TSCE
Chip-Erase
100
ms
T12.0 557
©2001 Silicon Storage Technology, Inc.
S71209-00-000 9/01 557
10
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402
Preliminary Specifications
T
RCS
ADDRESSES A
MSS-0
BES#
T
T
OHS
AAS
T
BES
T
T
BLZS
BHZS
T
OE#
OES
T
T
OLZS
OHZS
T
BYES
UBS#, LBS#
T
T
BYLZS
BYHZS
DQ
DATA VALID
15-0
557 ILL F02.0
Note: WE# remains High (V ) for the Read cycle
IH
A
= Most Significant SRAM Address
MSS
FIGURE 2: SRAM READ CYCLE TIMING DIAGRAM
T
WCS
ADDRESSES A
MSS-0
WE#
T
ASTS
T
T
WPS
WRS
T
AWS
T
T
BWS
BES#
BYWS
UBS#, LBS#
T
OEWS
T
DHS
T
ODWS
T
DSS
NOTE 2
VALID DATA IN
NOTE 2
DQ
DQ
7-0
15-8,
557 ILL F03.1
Notes: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.
2. If BES# goes Low coincident with or after WE# goes Low, the output will remain at high impedance.
If BES# goes High coincident with or before WE# goes High, the output will remain at high impedance.
Because D signals may be in the output state at this time, input signals of reverse polarity must not be applied.
IN
FIGURE 3: SRAM WRITE CYCLE TIMING DIAGRAM (WE# CONTROLLED)1
©2001 Silicon Storage Technology, Inc.
S71209-00-000 9/01 557
11
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402
Preliminary Specifications
T
WCS
ADDRESSES A
MSS-0
WE#
T
T
WRS
WPS
T
BWS
BES#
T
AWS
T
T
BYWS
ASTS
UBS#, LBS#
T
T
DHS
DSS
DQ
DQ
7-0
15-8,
NOTE 2
NOTE 2
VALID DATA IN
557 ILL F04.0
Notes: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.
2. Because D signals may be in the output state at this time, input signals of reverse polarity must not be applied.
IN
FIGURE 4: SRAM WRITE CYCLE TIMING DIAGRAM (UBS#, LBS# CONTROLLED)1
T
T
AA
RC
ADDRESSES A
MSF-0
BEF#
OE#
T
BE
T
OE
T
T
OHZ
V
OLZ
IH
WE#
T
BHZ
T
OH
T
HIGH-Z
BLZ
HIGH-Z
DQ
15-0
DATA VALID
DATA VALID
557 ILL F05.0
A
= Most Significant Flash Address
MSF
FIGURE 5: FLASH READ CYCLE TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
S71209-00-000 9/01 557
12
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402
Preliminary Specifications
INTERNAL PROGRAM OPERATION STARTS
T
BP
5555
2AAA
5555
ADDR
ADDRESSES A
MSF-0
T
AH
T
DH
T
WP
WE#
T
T
AS
DS
T
WPH
OE#
T
CH
BEF#
T
CS
DQ
15-0
XXAA
SW0
XX55
SW1
XXA0
SW2
DATA
WORD
(ADDR/DATA)
557 ILL F06.0
A
MSF
= Most Significant Flash Address
Note: X can be V or V , but no other value
IL IH
FIGURE 6: FLASH WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS
T
BP
5555
2AAA
5555
ADDR
ADDRESSES A
MSF-0
T
AH
T
DH
T
CP
BEF#
T
T
AS
DS
T
CPH
OE#
WE#
T
CH
T
CS
DQ
15-0
XXAA
SW0
XX55
SW1
XXA0
SW2
DATA
WORD
(ADDR/DATA)
557 ILL F07.0
A
= Most Significant Flash Address
MSF
Note: X can be V or V , but no other value
IL IH
FIGURE 7: BEF# CONTROLLED FLASH PROGRAM CYCLE TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
S71209-00-000 9/01 557
13
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402
Preliminary Specifications
ADDRESSES A
MSF-0
T
CE
BEF#
OE#
T
OES
T
OEH
T
OE
WE#
DQ
7
Data
Data#
Data#
Data
557 ILL F08.0
A
= Most Significant Flash Address
MSF
FIGURE 8: FLASH DATA# POLLING TIMING DIAGRAM
ADDRESSES A
MSF-0
T
BE
BEF#
OE#
T
OES
T
T
OE
OEH
WE#
DQ
6
TWO READ CYCLES
WITH SAME OUTPUTS
A
= Most Significant Flash Address
MSF
557 ILL F09.0
FIGURE 9: FLASH TOGGLE BIT TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
S71209-00-000 9/01 557
14
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402
Preliminary Specifications
T
SCE
SIX-BYTE CODE FOR CHIP-ERASE
5555
2AAA
5555
5555
2AAA
5555
ADDRESS A
MSF-0
CE#
OE#
WE#
T
WP
DQ
15-0
XXAA
SW0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX10
SW5
557 ILL F10.0
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 12)
X can be V or V , but no other value
IL
IH
A
= Most Significant Flash Address
MSF
FIGURE 10: WE# CONTROLLED FLASH CHIP-ERASE TIMING DIAGRAM
T
SE
SIX-WORD CODE FOR SECTOR-ERASE
5555
2AAA
5555
5555
2AAA
SA
X
ADDRESSES A
MSF-0
BEF#
OE#
WE#
T
WP
DQ
15-0
XXAA
SW0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX30
SW5
557 ILL F11.0
Note: The device also supports BEF# controlled Sector-Erase operation. The WE# and BEF# signals are
interchangeable as long as minimum timings are met. (See Table 12)
X can be V or V , but no other value
IL
IH
SA = Sector Address
X
A
= Most Significant Flash Address
MSF
FIGURE 11: WE# CONTROLLED FLASH SECTOR-ERASE TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
S71209-00-000 9/01 557
15
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402
Preliminary Specifications
T
SBE
SIX-WORD CODE FOR BLOCK-ERASE
5555 5555 2AAA
5555
2AAA
BA
X
ADDRESSES A
MSF-0
BEF#
OE#
T
WP
WE#
DQ
15-0
XXAA
SW0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX50
SW5
557 ILL F12.0
Note: The device also supports BEF# controlled Block-Erase operation. The WE# and BEF# signals are
interchangeable as long as minimum timings are met. (See Table 12)
X can be V or V , but no other value
IL
IH
BA = Block Address
X
A
= Most Significant Flash Address
MSF
FIGURE 12: WE# CONTROLLED FLASH BLOCK-ERASE TIMING DIAGRAM
THREE-WORD SEQUENCE FOR
SOFTWARE ID ENTRY
ADDRESS A
14-0
5555
2AAA
5555
0000
0001
BEF#
OE#
T
IDA
T
WP
WE#
T
WPH
T
AA
DQ
15-0
XXAA
SW0
XX55
SW1
XX90
SW2
00BF
DEVICE ID
MFG ID
557 ILL F13.0
Note: X can be V or V , but no other value
Device ID = 2789H for SST32VF201/202 and
2780H for SST32VF401/402
IL
IH
FIGURE 13: SOFTWARE ID ENTRY AND READ
©2001 Silicon Storage Technology, Inc.
S71209-00-000 9/01 557
16
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402
Preliminary Specifications
THREE-WORD SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
5555
2AAA
5555
ADDRESS A
DQ
14-0
XXAA
XX55
XXF0
15-0
T
IDA
BEF#
OE#
T
WP
WE#
T
WHP
SW0
SW1
SW2
557 ILL F14.0
Note: X can be V or V , but no other value
IL IH
FIGURE 14: SOFTWARE ID EXIT AND RESET
©2001 Silicon Storage Technology, Inc.
S71209-00-000 9/01 557
17
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402
Preliminary Specifications
V
IHT
V
V
INPUT
REFERENCE POINTS
OUTPUT
OT
IT
V
ILT
557 ILL F15.0
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.
Note: VIT - VINPUT Test
VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
V
ILT - VINPUT LOW Test
FIGURE 15: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO TESTER
TO DUT
C
L
557 ILL F16.0
FIGURE 16: A TEST LOAD EXAMPLE
©2001 Silicon Storage Technology, Inc.
S71209-00-000 9/01 557
18
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402
Preliminary Specifications
Start
Write data: XXAAH
Address: 5555H
Write data: XX55H
Address: 2AAAH
Write data: XXA0H
Address: 5555H
Write Word
Address/Word
Data
Wait for end of
Program (T
Data# Polling
,
BP
bit, or Toggle bit
operation)
Program
Completed
557 ILL F17.0
X can be VIL or VIH, but no other value.
FIGURE 17: WORD-PROGRAM ALGORITHM
©2001 Silicon Storage Technology, Inc.
S71209-00-000 9/01 557
19
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402
Preliminary Specifications
Toggle Bit
Data# Polling
Internal Timer
Program/Erase
Initiated
Program/Erase
Initiated
Program/Erase
Initiated
Read DQ
7
Read word
Wait T
BP
SCE, or BE
,
T
T
No
Read same
word
Is DQ =
7
true data?
Program/Erase
Completed
Yes
No
Does DQ
match?
6
Program/Erase
Completed
Yes
Program/Erase
Completed
557 ILL F18.0
FIGURE 18: WAIT OPTIONS
©2001 Silicon Storage Technology, Inc.
S71209-00-000 9/01 557
20
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402
Preliminary Specifications
Software Product ID Entry
Command Sequence
Software Product ID Exit &
Reset Command Sequence
Write data: XXAAH
Address: 5555H
Write data: XXAAH
Address: 5555H
Write data: XXF0H
Address: XXXXH
Write data: XX55H
Address: 2AAAH
Write data: XX55H
Address: 2AAAH
Wait T
IDA
Write data: XX90H
Address: 5555H
Write data: XXF0H
Address: 5555H
Return to normal
operation
Wait T
IDA
Wait T
IDA
Return to normal
operation
Read Software ID
557 ILL F19.0
X can be VIL or VIH, but no other value.
FIGURE 19: SOFTWARE PRODUCT COMMAND FLOWCHARTS
©2001 Silicon Storage Technology, Inc.
S71209-00-000 9/01 557
21
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402
Preliminary Specifications
Chip-Erase
Sector-Erase
Block-Erase
Command Sequence
Command Sequence
Command Sequence
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX80H
Address: 5555H
Load data: XX80H
Address: 5555H
Load data: XX80H
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX10H
Address: 5555H
Load data: XX30H
Load data: XX50H
Address: SA
Address: BA
X
X
Wait T
SCE
Wait T
SE
Wait T
BE
Chip erased
to FFFFH
Sector erased
to FFFFH
Block erased
to FFFFH
557 ILL F20.0
X can be V or V , but no other value.
IL
IH
FIGURE 20: ERASE COMMAND SEQUENCE
©2001 Silicon Storage Technology, Inc.
S71209-00-000 9/01 557
22
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402
Preliminary Specifications
Concurrent
Operation
Load SDP
Command
Sequence
Flash
Program/Erase
Initiated
Wait for End of
Write Indication
Read or Write
SRAM
End
Wait
Flash Operation
Completed
End Concurrent
Operation
557 ILL F21.0
FIGURE 21: CONCURRENT OPERATION FLOWCHART
©2001 Silicon Storage Technology, Inc.
S71209-00-000 9/01 557
23
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402
Preliminary Specifications
PRODUCT ORDERING INFORMATION
Device
Speed
Suffix1
Suffix2
SST32HFxxx
-
XXX
-
XX
-
XX
Package Modifier
K = 48 balls
Package Type
L3 = LFBGA (6mm x 8mm x 1.4mm)
Temperature Range
C = Commercial = 0°C to +70°C
E = Extended = -20°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
70 = 70 ns
90 = 90 ns
Density
201 = 2 Mbit Flash + 1 Mbit SRAM
202 = 2 Mbit Flash + 2 Mbit SRAM
401 = 4 Mbit Flash + 1 Mbit SRAM
402 = 4 Mbit Flash + 2 Mbit SRAM
Voltage
H = 2.7-3.3V
Device Family
32 = MPF + SRAM ComboMemory
©2001 Silicon Storage Technology, Inc.
S71209-00-000 9/01 557
24
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402
Preliminary Specifications
Valid combinations for SST32HF201
SST32HF201-70-4C-L3K
SST32HF201-70-4E-L3K
SST32HF201-90-4C-L3K
SST32HF201-90-4E-L3K
Valid combinations for SST32HF202
SST32HF202-70-4C-L3K
SST32HF202-70-4E-L3K
SST32HF202-90-4C-L3K
SST32HF202-90-4E-L3K
Valid combinations for SST32HF401
SST32HF401-70-4C-L3K
SST32HF401-70-4E-L3K
SST32HF401-90-4C-L3K
SST32HF401-90-4E-L3K
Valid combinations for SST32HF402
SST32HF402-70-4C-L3K
SST32HF402-70-4E-L3K
SST32HF402-90-4C-L3K
SST32HF402-90-4E-L3K
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST
sales representative to confirm availability of valid combinations and to determine availability of new combinations.
©2001 Silicon Storage Technology, Inc.
S71209-00-000 9/01 557
25
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402
Preliminary Specifications
PACKAGING DIAGRAMS
BOTTOM VIEW
8.00 ± 0.20
5.60
0.80
TOP VIEW
6
5
6
5
4
3
2
1
4.00
6.00 ± 0.20
4
3
2
1
0.80
0.45 ± 0.05
(48X)
H G F E D C B A
A B C D E F G H
A1 CORNER
A1 CORNER
1.30 ± 0.10
SIDE VIEW
0.15
48ba-lfbga-L3K-6x8-450mic-ILL.1
SEATING PLANE
0.35 ± 0.05
1mm
Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210,
this specific package is not registered.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.1 (±.05) mm.
4. The actual shape of the corners may be slightly different than as portrayed in the drawing.
48-BALL LOW-PROFILE, FINE-PITCH BALL GRID ARRAY (LFBGA) 6MM X 8MM
SST PACKAGE CODE: L3K
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.ssti.com
©2001 Silicon Storage Technology, Inc.
S71209-00-000 9/01 557
26
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