SST39LF010-45-4C-WH_技术文档

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

SST39LF/VF512 / 010 / 020 / 0403.0 & 2.7V 512Kb / 1Mb / 2Mb / 4Mb (x8) MPF memories

Data Sheet

FEATURES:

•

Organized as 64K x8 / 128K x8 / 256K x8 / 512K x8

Single Voltage Read and Write Operations

•

Fast Erase and Byte-Program:

– Sector-Erase Time: 18 ms (typical)

– Chip-Erase Time: 70 ms (typical)

– Byte-Program Time: 14 µs (typical)

– Chip Rewrite Time:

– 3.0-3.6V for SST39LF512/010/020/040

– 2.7-3.6V for SST39VF512/010/020/040

•

Superior Reliability

1 second (typical) for SST39LF/VF512

2 seconds (typical) for SST39LF/VF010

4 seconds (typical) for SST39LF/VF020

8 seconds (typical) for SST39LF/VF040

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

Low Power Consumption:

•

Automatic Write Timing

– Internal V_PPGeneration

End-of-Write Detection

– Active Current: 10 mA (typical)

– Standby Current: 1 µA (typical)

•

Sector-Erase Capability

– Uniform 4 KByte sectors

Fast Read Access Time:

– Toggle Bit

– Data# Polling

•

CMOS I/O Compatibility

JEDEC Standard

– 45 ns for SST39LF512/010/020/040

– 55 ns for SST39LF020/040

– 70 and 90 ns for SST39VF512/010/020/040

– Flash EEPROM Pinouts and command sets

Packages Available

•

Latched Address and Data

•

– 32-lead PLCC

– 32-lead TSOP (8mm x 14mm)

– 48-ball TFBGA (6mm x 8mm) for 1 Mbit

PRODUCT DESCRIPTION

The SST39LF512/010/020/040 and SST39VF512/010/

020/040 are 64K x8, 128K x8, 256K x8 and 5124K x8

CMOS Multi-Purpose Flash (MPF) manufactured with

SST’s proprietary, high performance CMOS SuperFlash

technology. The split-gate cell design and thick oxide tun-

neling injector attain better reliability and manufacturability

compared with alternate approaches. The SST39LF512/

010/020/040 devices write (Program or Erase) with a 3.0-

3.6V power supply. The SST39VF512/010/020/040

devices write with a 2.7-3.6V power supply. The devices

conform to JEDEC standard pinouts for x8 memories.

significantly improves performance and reliability, while low-

ering power consumption. They inherently use less energy

during Erase and Program than alternative flash technolo-

gies. The total energy consumed is a function of the

applied voltage, current, and time of application. Since for

any given voltage range, the SuperFlash technology uses

less current to program and has a shorter erase time, the

total energy consumed during any Erase or Program oper-

ation is less than alternative flash technologies. These

devices also improve flexibility while lowering the cost for

program, data, and configuration storage applications.

Featuring high performance Byte-Program, the

SST39LF512/010/020/040 and SST39VF512/010/020/

040 devices provide a maximum Byte-Program time of 20

µsec. These devices use Toggle Bit or Data# Polling to indi-

cate the completion of Program operation. To protect

against inadvertent write, they have on-chip hardware and

Software Data Protection schemes. Designed, manufac-

tured, and tested for a wide spectrum of applications, they

are offered with a guaranteed endurance of 10,000 cycles.

Data retention is rated at greater than 100 years.

The SuperFlash technology provides fixed Erase and Pro-

gram times, independent of the number of Erase/Program

cycles that have occurred. Therefore the system software

or hardware does not have to be modified or de-rated as is

necessary with alternative flash technologies, whose Erase

and Program times increase with accumulated Erase/Pro-

gram cycles.

To meet surface mount requirements, the SST39LF512/

010/020/040 and SST39VF512/010/020/040 devices are

offered in 32-lead PLCC and 32-lead TSOP packages. The

39LF/VF010 is also offered in a 48-ball TFBGA package.

See Figures 1 and 2 for pinouts.

The SST39LF512/010/020/040 and SST39VF512/010/

020/040 devices are suited for applications that require

convenient and economical updating of program, configu-

ration, or data memory. For all system applications, they

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

MPF is a trademark of Silicon Storage Technology, Inc.

S71150-03-000 6/01

1

395

These specifications are subject to change without notice.

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

pulse, while the command (30H) is latched on the rising

edge of the sixth WE# pulse. The internal Erase operation

begins after the sixth WE# pulse. The End-of-Erase can be

determined using either Data# Polling or Toggle Bit meth-

ods. See Figure 9 for timing waveforms. Any commands

written during the Sector-Erase operation will be ignored.

Device Operation

Commands are used to initiate the memory operation func-

tions of the device. Commands are written to the device

using standard microprocessor write sequences. A com-

mand is written by asserting WE# low while keeping CE#

low. The address bus is latched on the falling edge of WE#

or CE#, whichever occurs last. The data bus is latched on

the rising edge of WE# or CE#, whichever occurs first.

Chip-Erase Operation

The SST39LF512/010/020/040 and SST39VF512/010/

020/040 devices provide a Chip-Erase operation, which

allows the user to erase the entire memory array to the “1s”

state. This is useful when the entire device must be quickly

erased.

Read

The Read operation of the SST39LF512/010/020/040 and

SST39VF512/010/020/040 device is controlled by CE#

and OE#, both have to be low for the system to obtain data

from the outputs. CE# is used for device selection. When

CE# is high, the chip is deselected and only standby power

is consumed. OE# is the output control and is used to gate

data from the output pins. The data bus is in high imped-

ance state when either CE# or OE# is high. Refer to the

Read cycle timing diagram for further details (Figure 4).

The Chip-Erase operation is initiated by executing a six-

byte Software Data Protection command sequence with

Chip-Erase command (10H) with address 5555H in the last

byte sequence. The internal Erase operation begins with

the rising edge of the sixth WE# or CE#, whichever occurs

first. During the internal Erase operation, the only valid read

is Toggle Bit or Data# Polling. See Table 4 for the command

sequence, Figure 10 for timing diagram, and Figure 18 for

the flowchart. Any commands written during the Chip-

Erase operation will be ignored.

Byte-Program Operation

The SST39LF512/010/020/040 and SST39VF512/010/

020/040 are programmed on a byte-by-byte basis. Before

programming, one must ensure that the sector, in which

the byte which is being programmed exists, is fully erased.

The Program operation consists of three steps. The first

step is the three-byte-load sequence for Software Data

Protection. The second step is to load byte address and

byte data. During the Byte-Program operation, the

addresses are latched on the falling edge of either CE# or

WE#, whichever occurs last. The data is latched on the ris-

ing edge of either CE# or WE#, whichever occurs first. The

third step is the internal Program operation which is initi-

ated after the rising edge of the fourth WE# or CE#, which-

ever occurs first. The Program operation, once initiated, will

be completed, within 20 µs. See Figures 5 and 6 for WE#

and CE# controlled Program operation timing diagrams

and Figure 15 for flowcharts. During the Program opera-

tion, the only valid reads are Data# Polling and Toggle Bit.

During the internal Program operation, the host is free to

perform additional tasks. Any commands written during the

internal Program operation will be ignored.

Write Operation Status Detection

The SST39LF512/010/020/040 and SST39VF512/010/

020/040 devices provide two software means to detect the

completion of a Write (Program or Erase) cycle, in order to

optimize the system write cycle time. The software detec-

tion includes two status bits: Data# Polling (DQ₇) and Tog-

gle Bit (DQ₆). The End-of-Write detection mode is enabled

after the rising edge of WE# which initiates the internal Pro-

gram or Erase operation.

The actual completion of the nonvolatile write is asynchro-

nous with the system; therefore, either a Data# Polling or

Toggle Bit read may be simultaneous with the completion

of the Write cycle. If this occurs, the system may possibly

get an erroneous result, i.e., valid data may appear to con-

flict with either DQ₇or DQ₆. In order to prevent spurious

rejection, if an erroneous result occurs, the software routine

should include a loop to read the accessed location an

additional two (2) times. If both reads are valid, then the

device has completed the Write cycle, otherwise the rejec-

tion is valid.

Sector-Erase Operation

The Sector-Erase operation allows the system to erase the

device on a sector-by-sector basis. The sector architecture

is based on uniform sector size of 4 KByte. The Sector-

Erase operation is initiated by executing a six-byte-com-

mand sequence with Sector-Erase command (30H) and

sector address (SA) in the last bus cycle. The sector

address is latched on the falling edge of the sixth WE#

S71150-03-000 6/01 395

2

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Data# Polling (DQ₇)

Software Data Protection (SDP)

When the SST39LF512/010/020/040 and SST39VF512/

010/020/040 are in the internal Program operation, any

attempt to read DQ₇will produce the complement of the

true data. Once the Program operation is completed, DQ₇

will produce true data. The device is then ready for the next

operation. During internal Erase operation, any attempt to

read DQ₇will produce a ‘0’. Once the internal Erase opera-

tion is completed, DQ₇will produce a ‘1’. The Data# Polling

is valid after the rising edge of fourth WE# (or CE#) pulse

for Program operation. For Sector- or Chip-Erase, the

Data# Polling is valid after the rising edge of sixth WE# (or

CE#) pulse. See Figure 7 for Data# Polling timing diagram

and Figure 16 for a flowchart.

The SST39LF512/010/020/040 and SST39VF512/010/

020/040 provide the JEDEC approved Software Data Pro-

tection scheme for all data alteration operation, i.e., Pro-

gram and Erase. Any Program operation requires the

inclusion of a series of three byte sequence. The three

byte-load sequence is used to initiate the Program opera-

tion, providing optimal protection from inadvertent Write

operations, e.g., during the system power-up or power-

down. Any Erase operation requires the inclusion of six

byte load sequence. These devices are shipped with the

Software Data Protection permanently enabled. See Table

4 for the specific software command codes. During SDP

command sequence, invalid commands will abort the

device to read mode, within T_RC

.

Toggle Bit (DQ₆)

Product Identification

During the internal Program or Erase operation, any con-

secutive attempts to read DQ₆will produce alternating 0s

and 1s, i.e., toggling between 0 and 1. When the internal

Program or Erase operation is completed, the toggling will

stop. The device is then ready for the next operation. The

Toggle Bit is valid after the rising edge of fourth WE# (or

CE#) pulse for Program operation. For Sector- or Chip-

Erase, the Toggle Bit is valid after the rising edge of sixth

WE# (or CE#) pulse. See Figure 8 for Toggle Bit timing dia-

gram and Figure 16 for a flowchart.

The Product Identification mode identifies the devices as

the SST39LF/VF512, SST39LF/VF010, SST39LF/VF020

and SST39LF/VF040 and manufacturer as SST. This

mode may be accessed by software operations. Users

may use the Software Product Identification operation to

identify the part (i.e., using the device ID) when using multi-

ple manufacturers in the same socket. For details, see

Table 4 for software operation, Figure 11 for the Software

ID Entry and Read timing diagram, and Figure 17 for the

Software ID entry command sequence flowchart.

Data Protection

TABLE 1: PRODUCT IDENTIFICATION

The SST39LF512/010/020/040 and SST39VF512/010/

020/040 provide both hardware and software features to

protect nonvolatile data from inadvertent writes.

Address

Data

Manufacturer’s ID

Device ID

0000H

BFH

Hardware Data Protection

SST39LF/VF512

SST39LF/VF010

SST39LF/VF020

SST39LF/VF040

0001H

D4H

D5H

D6H

D7H

Noise/Glitch Protection: A WE# or CE# pulse of less than 5

ns will not initiate a Write cycle.

V_DDPower Up/Down Detection: The Write operation is

inhibited when V_DDis less than 1.5V.

T1.1 395

Write Inhibit Mode: Forcing OE# low, CE# high, or WE#

high will inhibit the Write operation. This prevents inadvert-

ent writes during power-up or power-down.

Product Identification Mode Exit/Reset

In order to return to the standard Read mode, the Software

Product Identification mode must be exited. Exit is accom-

plished by issuing the Software ID Exit command

sequence, which returns the device to the Read operation.

Please note that the Software ID Exit command is ignored

during an internal Program or Erase operation. See Table 4

for software command codes, Figure 12 for timing wave-

form, and Figure 17 for a flowchart.

S71150-03-000 6/01 395

3

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

FUNCTIONAL BLOCK DIAGRAM

SuperFlash

X-Decoder

Memory

Memory Address

Address Buffers & Latches

Y-Decoder

CE#

I/O Buffers and Data Latches

Control Logic

OE#

WE#

DQ - DQ

7

0

395 ILL B1.1

SST39LF/VF040 SST39LF/VF020 SST39LF/VF010 SST39LF/VF512

SST39LF/VF512 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040

4

3

2

1

32 31 30

29

5

A7

A6

A7

A6

A7

A6

A7

A6

A14

A13

A8

A14

A13

A8

A14

A13

A8

A14

A13

A8

6

28

27

26

25

24

23

22

21

7

A5

8

A4

A9

32-lead PLCC

Top View

9

A3

A11

OE#

A10

CE#

DQ7

A11

OE#

A10

CE#

DQ7

A11

OE#

A10

CE#

DQ7

A11

OE#

A10

CE#

DQ7

10

11

12

13

A2

A1

A0

DQ0

14 15 16 17 18 19 20

395 ILL F02b.3

FIGURE 1: PIN ASSIGNMENTS FOR 32-LEAD PLCC

S71150-03-000 6/01 395

4

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

SST39LF/VF040 SST39LF/VF020 SST39LF/VF010 SST39LF/VF512

SST39LF/VF512 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040

A11

A9

A11

A9

A11

A9

A11

A9

1

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

OE#

A10

OE#

A10

OE#

A10

OE#

A10

2

A8

3

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

A13

A14

A17

WE#

A13

A14

A17

WE#

A13

A14

NC

A13

A14

NC

4

5

Standard Pinout

Top View

6

WE#

7

V

8

DD

A18

A16

A15

A12

A7

NC

A16

A15

A12

A7

NC

A16

A15

A12

A7

NC

A15

A12

A7

9

V

SS

Die Up

10

11

12

13

14

15

16

DQ2

DQ1

DQ0

A0

DQ2

DQ1

DQ0

A0

DQ2

DQ1

DQ0

A0

DQ2

DQ1

DQ0

A0

A6

A1

A5

A2

A4

A3

395 ILL F01.0

FIGURE 2: PIN ASSIGNMENTS FOR 32-LEAD TSOP (8MM X 14MM)

TOP VIEW (balls facing down)

SST39LF/VF010

6

A14 A13 A15 A16 NC NC NC V

SS

5

A9 A8 A11 A12 NC A10 DQ6 DQ7

4

3

2

1

WE# NC NC NC DQ5 NC V

NC NC NC NC DQ2 DQ3 V

DQ4

NC

DD

A7 NC A6 A5 DQ0 NC NC DQ1

A3 A4 A2 A1 A0 CE# OE# V

SS

A

B

C

D

E

F

G

H

FIGURE 3: PIN ASSIGNMENT FOR 48-BALL TFBGA (6MM X 8MM) FOR 1 MBIT

S71150-03-000 6/01 395

5

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

TABLE 2: PIN DESCRIPTION

Symbol

Pin Name

Functions

A_MS¹-A₀

Address Inputs

To provide memory addresses. During Sector-Erase A_MS-A₁₂address lines will select the

sector. During Block-Erase A_MS-A₁₆address lines will select the block.

DQ₇-DQ₀

Data Input/output

To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a Write cycle.

The outputs are in tri-state when OE# or CE# is high.

CE#

OE#

WE#

V_DD

Chip Enable

Output Enable

Write Enable

Power Supply

To activate the device when CE# is low.

To gate the data output buffers.

To control the Write operations.

To provide power supply voltage:

3.0-3.6V for SST39LF512/010/020/040

2.7-3.6V for SST39VF512/010/020/040

V_SS

NC

Ground

No Connection

Unconnected pins.

T2.1 395

1. A_MS= Most significant address

_MS= A₁₅for SST39LF/VF512, A₁₆for SST39LF/VF010, A₁₇for SST39LF/VF020, and A₁₈for SST39LF/VF040

A

TABLE 3: OPERATION MODES SELECTION

Mode

Read

CE#

V_IL

OE#

V_IL

WE#

V_IH

V_IL

DQ

D_OUT

D_IN

X¹

Address

A_IN

Program

Erase

V_IL

V_IH

A_IN

V_IL

Sector address,

XXH for Chip-Erase

Standby

V_IH

X

V_IL

X

High Z

X

Write Inhibit

High Z/ D_OUT

X

V_IH

Product Identification

Software Mode

V_IL

V_IH

See Table 4

T3.4 395

1. X can be V_ILor V_IH, but no other value.

S71150-03-000 6/01 395

6

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

TABLE 4: SOFTWARE COMMAND SEQUENCE

Command

Sequence

1st Bus

Write Cycle

2nd Bus

Write Cycle

3rd Bus

Write Cycle

4th Bus

Write Cycle

5th Bus

Write Cycle

6th Bus

Write Cycle

Addr¹Data Addr¹Data Addr¹Data Addr¹Data Addr¹Data Addr¹Data

5555H AAH 2AAAH 55H 5555H A0H Data

BA²

5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H

Byte-Program

3

Sector-Erase

SA_X

30H

Chip-Erase

5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H

5555H AAH 2AAAH 55H 5555H 90H

Software ID Entry^4,5

Software ID Exit⁶

XXH

F0H

5555H AAH 2AAAH 55H 5555H F0H

T4.2 395

1. Address format A₁₄-A₀(Hex),

Address A₁₅can be V_ILor V_IH, but no other value, for the Command sequence for SST39LF/VF512.

Addresses A₁₅-A₁₆can be V_ILor V_IH, but no other value, for the Command sequence for SST39LF/VF010.

Addresses A₁₅-A₁₇can be V_ILor V_IH, but no other value, for the Command sequence for SST39LF/VF020.

Addresses A₁₅-A₁₈can be V_ILor V_IH, but no other value, for the Command sequence for SST39LF/VF040.

2. BA = Program Byte address

3. SA_Xfor Sector-Erase; uses A_MS-A₁₂address lines

A_MS= Most significant address

A_MS= A₁₅for SST39LF/VF512, A₁₆for SST39LF/VF010, A₁₇for SST39LF/VF020, and A₁₈for SST39LF/VF040

4. The device does not remain in Software Product ID Mode if powered down.

5. With A_MS-A₁=0; SST Manufacturer’s ID= BFH, is read with A₀= 0,

SST39LF/VF512 Device ID = D4H, is read with A₀= 1

SST39LF/VF010 Device ID = D5H, is read with A₀= 1

SST39LF/VF020 Device ID = D6H, is read with A₀= 1

SST39LF/VF040 Device ID = D7H, is read with A₀= 1

6. Both Software ID Exit operations are equivalent

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum

Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation

of the device at these conditions or conditions greater than those defined in the operational sections of this data

sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to V_DD+ 0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to V_DD+ 1.0V

Voltage on A₉Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V

Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Output Short Circuit Current¹. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

1. Outputs shorted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE FOR SST39LF512/010/020/040

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns

Range

Ambient Temp

V_DD

Output Load

Commercial

0°C to +70°C

3.0-3.6V

C_L= 30 pF for SST39LF512/010/020/040

OPERATING RANGE FOR SST39VF512/010/020/040

C_L= 100 pF for SST39VF512/010/020/040

See Figures 13 and 14

Range

Ambient Temp

0°C to +70°C

V_DD

Commercial

Industrial

2.7-3.6V

-40°C to +85°C

S71150-03-000 6/01 395

7

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

TABLE 5: DC OPERATING CHARACTERISTICS

V_DD= 3.0-3.6V FOR SST39LF512/010/020/040 AND 2.7-3.6V FOR SST39VF512/010/020/040

Limits

Symbol Parameter

Min

Max Units Test Conditions

Address input=V_IL/V_IH, at f=1/T_RCMin

I_DD

Power Supply Current

V_DD=V_DDMax

Read

20

15

1

mA

µA

V

CE#=OE#=V_IL, WE#=V_IH, all I/Os open

CE#=WE#=V_IL, OE#=V_IH

CE#=V_IHC, V_DD=V_DDMax

V_IN=GND to V_DD, V_DD=V_DDMax

V_OUT=GND to V_DD, V_DD=V_DDMax

V_DD=V_DDMin

Write

I_SB

Standby V_DDCurrent

Input Leakage Current

Output Leakage Current

Input Low Voltage

Input High Voltage

Input High Voltage (CMOS)

Output Low Voltage

Output High Voltage

I_LI

I_LO

10

0.8

V_IL

V_IH

V_IHC

V_OL

V_OH

0.7V_DD

V

V_DD=V_DDMax

V_DD-0.3

V

V_DD=V_DDMax

0.2

V

I_OL=100 µA, V_DD=V_DDMin

I_OH=-100 µA, V_DD=V_DDMin

V_DD-0.2

V

T5.2 395

TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol

Parameter

Minimum

100

Units

1

T_PU-READ

Power-up to Read Operation

Power-up to Program/Erase Operation

µs

1

T_PU-WRITE

100

T6.1 395

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 7: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)

Parameter

Description

Test Condition

V_I/O= 0V

Maximum

1

C_I/O

I/O Pin Capacitance

Input Capacitance

12 pF

6 pF

1

C_IN

V_IN= 0V

T7.0 395

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 8: RELIABILITY CHARACTERISTICS

Symbol

Parameter

Endurance

Data Retention

Latch Up

Minimum Specification

Units

Test Method

1

N_END

10,000

100

Cycles JEDEC Standard A117

1

T_DR

Years

mA

JEDEC Standard A103

JEDEC Standard 78

1

I_LTH

100 + I_DD

T8.2 395

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

S71150-03-000 6/01 395

8

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

AC CHARACTERISTICS

TABLE 9: READ CYCLE TIMING PARAMETERS

V_DD= 3.0-3.6V FOR SST39LF512/010/020/040 AND 2.7-3.6V FOR SST39VF512/010/020/040

SST39LF512-45

SST39LF010-45

SST39VF512-70 SST39VF512-90

SST39VF010-70 SST39VF010-90

SST39LF020-45 SST39LF020-55 SST39VF020-70 SST39VF020-90

SST39LF040-45 SST39LF040-55 SST39VF040-70 SST39VF040-90

Symbol Parameter

Min

Max

Min

Max

Min

Max

Min

Max

Units

ns

T_RC

T_CE

T_AA

Read Cycle Time

45

55

70

90

Chip Enable Access Time

Address Access Time

45

30

55

30

70

35

90

45

ns

T_OE

T_CLZ

T_OLZ

Output Enable Access Time

CE# Low to Active Output

OE# Low to Active Output

CE# High to High-Z Output

OE# High to High-Z Output

Output Hold from Address Change

ns

1

0

ns

1

T_CHZ

T_OHZ

15

25

30

ns

1

ns

1

T_OH

0

ns

T9.2 395

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 10: PROGRAM/ERASE CYCLE TIMING PARAMETERS

Symbol Parameter

Min

Max

Units

T_BP

Byte-Program Time

20

µs

ns

ms

T_AS

Address Setup Time

Address Hold Time

WE# and CE# Setup Time

WE# and CE# Hold Time

OE# High Setup Time

OE# High Hold Time

CE# Pulse Width

0

30

0

T_AH

T_CS

T_CH

T_OES

T_OEH

T_CP

0

10

40

30

40

0

T_WP

WE# Pulse Width

1

T_WPH

WE# Pulse Width High

CE# Pulse Width High

Data Setup Time

1

T_CPH

T_DS

1

T_DH

Data Hold Time

1

T_IDA

Software ID Access and Exit Time

Sector-Erase

150

25

T_SE

T_SCE

Chip-Erase

100

T10.1 395

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

S71150-03-000 6/01 395

9

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

T

AA

RC

ADDRESS A

MS-0

CE#

OE#

WE#

T

CE

T

OE

T

OHZ

V

OLZ

IH

T

CHZ

T

OH

T

HIGH-Z

CLZ

HIGH-Z

DQ

7-0

DATA VALID

395 ILL F03.0

Note:

A

= Most significant address

MS

= A for SST39LF/VF512, A for SST39LF/VF010,

15

17

16

for SST39LF/VF020 and A for SST39LF/VF040

A

18

FIGURE 4: READ CYCLE TIMING DIAGRAM

INTERNAL PROGRAM OPERATION STARTS

T

BP

5555

2AAA

5555

ADDR

ADDRESS A

MS-0

T

AH

T

DH

T

WP

WE#

T

AS

DS

T

WPH

OE#

CE#

T

CH

T

CS

DQ

7-0

AA

SW0

55

A0

DATA

SW1

SW2

BYTE

395 ILL F04.0

(ADDR/DATA)

Note:

A

= Most significant address

MS

= A for SST39LF/VF512, A for SST39LF/VF010,

15

17

16

for SST39LF/VF020 and A for SST39LF/VF040

A

18

FIGURE 5: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

S71150-03-000 6/01 395

10

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

INTERNAL PROGRAM OPERATION STARTS

T

BP

5555

2AAA

5555

ADDR

ADDRESS A

MS-0

T

AH

T

DH

T

CP

CE#

T

AS

DS

T

CPH

OE#

WE#

T

CH

T

CS

DQ

7-0

AA

SW0

55

A0

DATA

SW1

SW2

BYTE

(ADDR/DATA)

395 ILL F05.0

Note:

A

= Most significant address

MS

= A for SST39LF/VF512, A for SST39LF/VF010,

15

17

16

for SST39LF/VF020 and A for SST39LF/VF040

A

18

FIGURE 6: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

ADDRESS A

MS-0

T

CE

CE#

OE#

WE#

T

OES

T

OEH

T

OE

DQ

7

D

D#

D

395 ILL F06.0

Note:

A

= Most significant address

MS

= A for SST39LF/VF512, A for SST39LF/VF010,

15

17

16

for SST39LF/VF020 and A for SST39LF/VF040

A

18

FIGURE 7: DATA# POLLING TIMING DIAGRAM

S71150-03-000 6/01 395

11

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

ADDRESS A

MS-0

T

CE

CE#

OE#

WE#

T

OES

T

OE

OEH

DQ

6

TWO READ CYCLES

WITH SAME OUTPUTS

Note:

A

= Most significant address

MS

395 ILL F07.0

= A for SST39LF/VF512, A for SST39LF/VF010,

15

17

16

for SST39LF/VF020 and A for SST39LF/VF040

A

18

FIGURE 8: TOGGLE BIT TIMING DIAGRAM

T

SE

SIX-BYTE CODE FOR SECTOR-ERASE

5555 5555 2AAA

5555

2AAA

SA

X

ADDRESS A

MS-0

CE#

OE#

WE#

T

WP

DQ

7-0

AA

55

SW1

80

SW2

AA

SW3

55

SW4

30

SW0

SW5

334 ILL F08.0

Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are

interchageable as long as minmum timings are met. (See Table 10)

SA = Sector Address

X

A

= Most significant address

MS

= A for SST39LF/VF512, A for SST39LF/VF010, A for SST39LF/VF020 and A for SST39LF/VF040

15 16 17 18

FIGURE 9: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM

S71150-03-000 6/01 395

12

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

T

SCE

SIX-BYTE CODE FOR CHIP-ERASE

5555

2AAA

5555

2AAA

5555

ADDRESS A

MS-0

CE#

OE#

WE#

T

WP

DQ

7-0

AA

55

SW1

80

SW2

AA

SW3

55

SW4

10

SW0

SW5

334 ILL F17.0

Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are

interchageable as long as minmum timings are met. (See Table 10)

A

= Most significant address

MS

= A for SST39LF/VF512, A for SST39LF/VF010, A for SST39LF/VF020 and A for SST39LF/VF040

15 16 17 18

FIGURE 10: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM

Three-byte sequence for

Software ID Entry

ADDRESS A

5555

2AAA

5555

0000

0001

14-0

CE#

OE#

WE#

T

IDA

T

WP

T

WPH

T

AA

DQ

7-0

AA

55

90

BF

Device ID

SW0

SW1

SW2

395 ILL F09.2

Note: Device ID = D4H for SST39LF/VF512, D5H for SST39LF/VF010, D6H for SST39LF/VF020, and D7H for SST39LF/VF040.

FIGURE 11: SOFTWARE ID ENTRY AND READ

S71150-03-000 6/01 395

13

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

THREE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

5555

2AAA

5555

ADDRESS A

14-0

DQ

AA

55

F0

7-0

T

IDA

CE#

OE#

T

WP

WE#

T

WHP

SW0

SW1

SW2

395 ILL F10.0

FIGURE 12: SOFTWARE ID EXIT AND RESET

S71150-03-000 6/01 395

14

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

V

IHT

V

INPUT

REFERENCE POINTS

OUTPUT

OT

IT

V

ILT

395 ILL F12.1

AC test inputs are driven at V_IHT(0.9 V_DD) for a logic “1” and V_ILT(0.1 V_DD) for a logic “0”. Measurement reference points

for inputs and outputs are V_IT(0.5 V_DD) and V_OT(0.5 V_DD). Input rise and fall times (10% ↔ 90%) are <5 ns.

Note: V_IT- V_INPUTTest

V_OT- V_OUTPUTTest

V_IHT- V_INPUTHIGH Test

V

_ILT- V_INPUTLOW Test

FIGURE 13: AC INPUT/OUTPUT REFERENCE WAVEFORMS

TO TESTER

TO DUT

C

L

395 ILL F11.1

FIGURE 14: A TEST LOAD EXAMPLE

S71150-03-000 6/01 395

15

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Start

Load data: AAH

Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: A0H

Address: 5555H

Load Byte

Address/Byte

Data

Wait for end of

Program (T

Data# Polling

,

BP

bit, or Toggle bit

operation)

Program

Completed

395 ILL F13.1

FIGURE 15: BYTE-PROGRAM ALGORITHM

S71150-03-000 6/01 395

16

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Toggle Bit

Data# Polling

Internal Timer

Byte-Program/

Erase

Byte-Program/

Erase

Byte-Program/

Erase

Initiated

Read DQ

7

Read byte

Wait T

BP

SCE, or SE

,

T

Read same

byte

Is DQ =

7

No

true data?

Program/Erase

Completed

Yes

No

Does DQ

match?

6

Program/Erase

Completed

Yes

Program/Erase

Completed

395 ILL F14.0

FIGURE 16: WAIT OPTIONS

S71150-03-000 6/01 395

17

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Software ID Entry

Software ID Exit &

Command Sequence

Reset Command Sequence

Load data: AAH

Address: 5555H

Load data: AAH

Address: 5555H

Load data: F0H

Address: XXH

Load data: 55H

Address: 2AAAH

Load data: 55H

Address: 2AAAH

Wait T

IDA

Load data: 90H

Address: 5555H

Load data: F0H

Address: 5555H

Return to normal

operation

Wait T

IDA

Wait T

IDA

Return to normal

operation

Read Software ID

395 ILL F15.2

FIGURE 17: SOFTWARE ID COMMAND FLOWCHARTS

S71150-03-000 6/01 395

18

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Chip-Erase

Sector-Erase

Command Sequence

Load data: AAH

Address: 5555H

Load data: AAH

Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: 55H

Address: 2AAAH

Load data: 80H

Address: 5555H

Load data: 80H

Address: 5555H

Load data: AAH

Address: 5555H

Load data: AAH

Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: 55H

Address: 2AAAH

Load data: 10H

Address: 5555H

Load data: 30H

Address: SA

X

Wait T

SCE

Wait T

SE

Chip erased

to FFH

Sector erased

to FFH

395 ILL F16.1

FIGURE 18: ERASE COMMAND SEQUENCE

S71150-03-000 6/01 395

19

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

PRODUCT ORDERING INFORMATION

Device

Speed

Suffix1

Suffix2

SST39xFxxx

-

XX

-

XX

-

XX

Package Modifier

H = 32 leads

K = 48 balls

Numeric = Die modifier

Package Type

N = PLCC

W = TSOP (die up) (8mm x 14mm)

B3 = TFBGA (6mm x 8mm)

Temperature Range

C = Commercial = 0°C to +70°C

I = Industrial = -40°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

45 = 45 ns

55 = 55 ns

70 = 70 ns

90 = 90 ns

Device Density

512 = 512 Kilobit

010 = 1 Megabit

020 = 2 Megabit

040 = 4 Megabit

Voltage

L = 3.0-3.6V

V = 2.7-3.6V

S71150-03-000 6/01 395

20

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Valid combinations for SST39LF512

SST39LF512-45-4C-NH

SST39LF512-45-4C-WH

Valid combinations for SST39VF512

SST39VF512-70-4C-NH

SST39VF512-70-4C-WH

SST39VF512-90-4C-NH

SST39VF512-90-4C-U4

SST39VF512-90-4C-WH

SST39VF512-70-4I-NH

SST39VF512-90-4I-NH

SST39VF512-70-4I-WH

SST39VF512-90-4I-WH

Valid combinations for SST39LF010

SST39LF010-45-4C-NH

SST39LF010-45-4C-WH

SST39LF010-45-4C-B3K

Valid combinations for SST39VF010

SST39VF010-70-4C-NH

SST39VF010-70-4C-WH

SST39VF010-70-4C-B3K

SST39VF010-90-4C-B3K

SST39VF010-90-4C-NH

SST39VF010-90-4C-U4

SST39VF010-90-4C-WH

SST39VF010-70-4I-NH

SST39VF010-90-4I-NH

SST39VF010-70-4I-WH

SST39VF010-90-4I-WH

SST39VF010-70-4I-B3K

SST39VF010-90-4I-B3K

Valid combinations for SST39LF020

SST39LF020-45-4C-NH

SST39LF020-55-4C-NH

SST39LF020-45-4C-WH

SST39LF020-55-4C-WH

Valid combinations for SST39VF020

SST39VF020-70-4C-NH

SST39VF020-70-4C-WH

SST39VF020-90-4C-NH

SST39VF020-90-4C-U4

SST39VF020-90-4C-WH

SST39VF020-70-4I-NH

SST39VF020-90-4I-NH

SST39VF020-70-4I-WH

SST39VF020-90-4I-WH

Valid combinations for SST39LF040

SST39LF040-45-4C-NH

SST39LF040-55-4C-NH

SST39LF040-45-4C-WH

SST39LF040-55-4C-WH

Valid combinations for SST39VF040

SST39VF040-70-4C-NH

SST39VF040-70-4C-WH

SST39VF040-90-4C-NH

SST39VF040-90-4C-U1

SST39VF040-90-4C-WH

SST39VF040-70-4I-NH

SST39VF040-90-4I-NH

SST39VF040-70-4I-WH

SST39VF040-90-4I-WH

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

S71150-03-000 6/01 395

21

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

PACKAGING DIAGRAMS

TOP VIEW

SIDE VIEW

BOTTOM VIEW

.485

.495

.447

.453

.106

.112

Optional

Pin #1 Identifier

.042

.048

.023

.029

.030

.040

.020 R.

MAX.

x 30˚

R.

2

1

32

.042

.048

.013

.021

.400 .490

BSC .530

.585

.595

.547

.553

.026

.032

.050

BSC.

.015 Min.

.075

.095

.050

BSC.

.026

.032

.125

.140

Note:

1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in inches (min/max).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.

4. Coplanarity: 4 mils.

32.PLCC.NH-ILL.2

32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC)

SST PACKAGE CODE: NH

1.05

0.95

Pin # 1 Identifier

.50

BSC

.270

.170

8.10

7.90

0.15

0.05

12.50

12.30

0.70

0.50

14.20

13.80

32.TSOP-WH-ILL.4

Note:

1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (min/max).

3. Coplanarity: 0.1 (±.05) mm.

4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads.

32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM

SST PACKAGE CODE: WH

S71150-03-000 6/01 395

22

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

BOTTOM VIEW

8.00 ± 0.20

5.60

0.80

TOP VIEW

6

5

4

3

2

1

6

5

4

3

2

1

4.00

6.00 ± 0.20

0.80

0.45 ± 0.05

(48X)

H

G F E D C B A

A

B C D E F G H

A1 CORNER

1.10 ± 0.10

SIDE VIEW

0.15

48ba-TFBGA-B3K-6x8-450mic-ILL.0

1mm

SEATING PLANE

0.35 ± 0.05

Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210,

this specific package is not registered.

2. All linear dimensions are in millimeters (min/max).

3. Coplanarity: 0.1 (±.05) mm.

4. The actual shape of the corners may be slightly different than as portrayed in the drawing.

48-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 6MM X 8MM

SST PACKAGE CODE: B3K

S71150-03-000 6/01 395

23

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036

www.SuperFlash.com or www.ssti.com

S71150-03-000 6/01 395

24


型号：	SST39LF010-45-4C-WH
厂家：	SILICON STORAGE TECHNOLOGY, INC
描述：	512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash 512千位/ 1兆位/ 2兆位/ 4兆位（ X8 ）多用途闪存闪存内存集成电路光电二极管
文件：	总24页 (文件大小：283K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SST39LF010-45-4C-WH [SST]

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