TSSOP-EP [STATSCHIP]

Small Outline Packages; 小外形封装
TSSOP-EP
型号: TSSOP-EP
厂家: STATS CHIPPAC, LTD.    STATS CHIPPAC, LTD.
描述:

Small Outline Packages
小外形封装

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中文:  中文翻译
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TSSOPand MSOP  
Small Outline Packages  
• Wide range of body sizes  
• 8 to 56 lead counts  
• Thermally enhanced versions  
available (TSSOP-ep and  
MSOP-ep)  
FEATURES  
DESCRIPTION  
STATS ChipPAC offers a complete line of Small Outline  
TSSOP  
Package (SOP) families including TSSOP, TSSOP-ep, and MSOP.  
STATS ChipPAC’s TSSOP (Thin Shrink Small Outline Package) is  
suitable for applications requiring a thin profile. TSSOP is a  
leadframe based, plastic encapsulated package with gull wing  
shaped leads on two sides with lead count ranging from 8 to  
56 leads. The ultra thin TSSOP is made possible by optimal wire  
looping control during the wire bonding process as well as  
optimal package warpage control during the molding process.  
TSSOP is designed to fill the niche of low pin count devices  
where low profile and small footprint are key design consider-  
ations. The TSSOP features 0.5 and 0.65mm lead pitch, and is  
ideal for low pin count analog and mixed signal devices in  
handheld applications such as PDAs and mobile / cellular  
phones.  
Taking the reliability of Small Outline Packages (SOP) one  
step further, STATS ChipPAC offers a Micro Small Outline  
Package (MSOP) for applications requiring thin, small, and  
high reliability. This smaller package offers a smaller footprint,  
shorter wires for improved electrical connections, and better  
moisture reliability (MRT/MSL).  
Body Size: 3.0 x 4.4mm to 14.0 x 6.1mm  
Lead Count: 8L to 56L  
Lead Pitch: 0.50mm & 0.65mm  
Package Height: 1.20mm max.  
JEDEC standard compliant (MO-153)  
Lead-free (Pb-free) and Green  
Thermal Enhancements: ep (exposed pad)  
MSOP  
Body Size: 3 x 3mm  
Lead Count: 8L & 10L  
Lead Pitch: 0.65mm (8L) and 0.50mm (10L)  
JEDEC standard compliant  
Lead-free (Pb-free) and Green  
Thermal enhancements: ep (exposed pad)  
APPLICATIONS  
• Analog and Operation Amplifiers  
• Controllers and Drivers  
In addition to standard TSSOP and MSOP, STATS ChipPAC  
offers thermally enhanced “ep” versions featuring an exposed  
die paddle for efficient heat dissipation. The exposed die  
attach pad design of the TSSOP package can provide excellent  
thermal dissipation by soldering the copper die attach pad  
directly onto the PCB, and is ideal for low pin count analog and  
mixed signal devices.  
• Logic, Memory, and RF/Wireless  
• Disk drives, video/audio and consumer electronics/  
appliances  
STATS ChipPAC uses the latest leadframe technology and  
state of the art design and simulation tools to achieve  
optimum electrical and thermal performance. STATS ChipPAC’s  
state of the art assembly facility and proven materials assure  
high yield manufacturing and long term reliability.  
www.statschippac.com  
TSSOP and MSOP  
Small Outline Packages  
RELIABILITY (all)  
SPECIFICATIONS (TSSOP)  
Temperature Cycling  
Temp/Humidity Test  
Pressure Cooker Test  
Condition C, -65°C/150°C, 1000 cycles  
85°C/85% RH, 1000 hrs  
Die Thickness  
9-11mil range preferred (TSSOP)  
6-16mil range preferred (TSSOP-ep)  
Gold Wire  
20µm (0.8mils) diameter, 99.99% Au  
121°C, 100% RH, 2 atm, 250 hrs  
Lead Finish  
Marking  
Sn/Pb (85/15%) or Matte Tin  
Laser  
Tube  
Packing Options  
SPECIFICATIONS (MSOP)  
Die Thickness  
6-9mil range preferred  
Gold Wire  
20µm (0.8mils) diameter, 99.99% Au  
Lead Finish  
Marking  
Sn/Pb (85/15%) or Matte Tin  
Laser  
Tube  
Packing Options  
THERMAL PERFORMANCE, θja (°C/W)  
Package  
Body Size (mm)  
4.4 x 7.8 x 0.9  
4.4 x 7.8 x 0.9  
Pad Size  
3.0 x 3.0  
3.0 x 3.0  
Die Size  
PCB Vias  
Thermal Performance θja (°C/W)  
30L TSSOP  
30L TSSOP-ep  
2.54 x 2.54  
2.54 x 2.54  
0
9
74.0  
49.5  
Note: Simulation data for package mounted on 4 layer PCB (per JEDEC JESD51-5) under natural convection as defined in JESD51.2.  
ELECTRICAL PERFORMANCE: 4.4 x 9.7 x 0.9 (38L)  
Conductor  
Pad Size  
(mm)  
Lead/Wire  
(mm)  
Resistance  
(mOhm)  
Inductance  
Capacitance  
Component  
Self (nH)  
Mutual (nH)  
Self (pF)  
Mutual (pF)  
Lead  
185 x 113  
0.6-3.09  
1.65  
5-25  
99  
0.30-1.70  
1.36  
0.14-0.77  
0.37-0.65  
0.51-1.42  
0.09-0.46  
0.08  
0.04-0.21  
0.01-0.02  
0.05-0.23  
Wire  
TOTALS  
104-124  
1.66-3.06  
0.17-0.54  
Note: Results are simulated values at 100MHz.  
CROSS-SECTION  
PACKAGE CONFIGURATIONS  
Package  
TSSOP  
Body Size (mm)  
3.0 x 4.4  
Lead Count  
8
TSSOP-ep  
TSSOP  
5.0 x 4.4  
6.5 x 4.4  
7.8 x 4.4  
9.7 x 4.4  
7.8 x 4.4  
12.5 x 6.1  
14.0 x 6.1  
3.0 x 3.0  
14, 16  
20  
24  
38  
30  
48  
MSOP  
56  
MSOP  
8, 10  
Corporate Office 10 Ang Mo Kio St. 65, #05-17/20 Techpoint, Singapore 569059 Tel: 65-6824-7777 Fax: 65-6720-7823  
Global Offices USA 510-979-8000 JAPAN 81-43-351-3320 CHINA 86-21-5976-5858 MALAYSIA 603-4257-6222  
KOREA 82-31-639-8911 TAIWAN 886-3-593-6565 UK 44-1483-413-700 NETHERLANDS 31-38-333-2023  
The STATS ChipPAC logo is a registered trademark of STATS ChipPAC Ltd. All other product names and other company names herein are for identification purposes only and may be the trademarks or registered trademarks  
of their respective owners. STATS ChipPAC disclaims any and all rights in those marks. STATS ChipPAC makes no guarantee or warranty of its accuracy in the information given, or that the use of such information  
will not infringe on intellectual rights of third parties. Under no circumstances shall STATS ChipPAC be liable for any damages whatsoever arising out of the use of, or inability to use the materials in this document.  
STATS ChipPAC reserves the right to change the information at any time and without notice.  
©Copyright 2005. STATS ChipPAC Ltd. All rights reserved.  
January 2005  

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