74ACT299M [STMICROELECTRONICS]

8 BIT PIPO SHIFT REGISTER WITH ASYNCHRONOUS CLEAR; 与异步清零8位PIPO移位寄存器
74ACT299M
型号: 74ACT299M
厂家: ST    ST
描述:

8 BIT PIPO SHIFT REGISTER WITH ASYNCHRONOUS CLEAR
与异步清零8位PIPO移位寄存器

移位寄存器 触发器 逻辑集成电路 光电二极管
文件: 总13页 (文件大小:104K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
74ACT299  
8 BIT PIPO SHIFT REGISTER  
WITH ASYNCHRONOUS CLEAR  
PRELIMINARY DATA  
HIGH SPEED:  
fMAX =170MHz(TYP.) at VCC =5V  
LOW POWER DISSIPATION:  
ICC =8 µA (MAX.) at TA =25 oC  
COMPATIBLEWITH TTL OUTPUTS  
VIH =2V (MIN), VIL = 0.8V(MAX)  
50TRANSMISSIONLINEDRIVING  
CAPABILITY  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL = 24 mA (MIN)  
BALANCEDPROPAGATIONDELAYS:  
tPLH tPHL  
B
M
(Plastic Package)  
(Micro Package)  
ORDER CODES :  
74ACT299B  
74ACT299M  
These devices have four modes (HOLD, SHIFT  
LEFT, SHIFT RIGHT and LOAD DATA). Each  
mode is chosen by two function select inputs (S0,  
S1) as shownin the Truth Table.  
When one or both enable inputs, (G1, G2) are  
high, the eight input/output terminals are in  
the high-impedance state ; however sequential  
operation or clearing of the register is not  
affected. Clear function is synchronousto clock.  
The device is designed to interface directly High  
Speed CMOS systems with TTL, NMOS and  
CMOS output voltage levels.  
OPERATING VOLTAGERANGE:  
VCC (OPR)= 4.5V to 5.5V  
PIN AND FUNCTION COMPATIBLEWITH  
74 SERIES299  
IMPROVED LATCH-UP IMMUNITY  
DESCRIPTION  
The ACT299 is an high-speed CMOS 8-BIT PIPO  
SHIFT REGISTERS (3-STATE) fabricated with  
sub-micron silicon gate and double-layer metal  
wiring C2MOS technology. It is ideal for low  
power applications mantaining high speed  
operation similar to equivalent Bipolar Schottky  
TTL.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/13  
April 1999  
74ACT299  
INPUT AND OUTPUT EQUIVALENT CIRCUIT  
PIN DESCRIPTION  
PIN No  
SYMBOL  
S0, S1  
NAME AND FUNCTION  
Mode Select Inputs  
1, 19  
2, 3  
G1, G2  
A/QA to H/QH  
QA’ to QH’  
CLEAR  
SR  
3 State Output Enable Inputs (Active LOW)  
Parallel Data Inputs or 3 State Parallel Outputs (Bus Driver)  
Serial Outputs (Standard Output)  
Asynchronous Master Reset Input (Active LOW)  
Serial Data Shift Right Input  
7, 13, 6, 14, 5, 15, 4, 16  
8, 17  
9
11  
12  
18  
10  
20  
CLOCK  
SL  
Clock Input (LOW to HIGH, Edge-triggered)  
Serial Data Shift Left Input  
GND  
Ground (0V)  
VCC  
Positive Supply Voltage  
TRUTH TABLE  
MODE  
INPUTS  
INPUTS/OUTPUTS  
SERIAL A/QA H/QH  
OUTPUTS  
FUNCTION  
SELECTED  
OUTPUT  
CONTROL  
CLOCK  
QA’  
QH’  
CLEAR  
S1  
H
L
S0  
H
X
L
G1*  
X
L
G2*  
X
L
SL  
X
X
X
X
X
X
H
L
SR  
X
Z
L
L
X
X
X
X
Z
L
Z
L
L
L
L
L
CLEAR  
X
L
X
L
L
L
X
L
L
L
L
HOLD  
H
H
H
H
H
H
L
L
L
X
QA0  
H
QH0  
QGn  
QGn  
H
QA0  
H
QH0  
QGn  
QGn  
H
SHIFT  
RIGHT  
L
H
H
L
L
L
H
L
L
L
L
L
L
SHIFT  
LEFT  
H
H
H
L
L
X
QBn  
QBn  
a
QBn  
QBn  
a
L
L
L
X
L
L
LOAD  
H
X
X
X
X
h
h
* When one or both output controls are high, the eight, input/output terminals arethe high impedanc e state: howewer sequential operation or clearing of  
theregister isnotaffected.  
Z
:HIGHIMPEDANCE  
Qn0 : THELEVELOF AnBEFORETHEINDICATEDSTEADYSTATEINPUTCONDITIONS WEREESTABLISED.  
Qnn :THELEVELOF Qn BEFORETHEMOSTRECENTACTIVETRANSITIONINDICATEDBYOR  
a,h :THELEVELOF THESTEADYSTATEINPUTSA, H,RESPECTIVELY.  
X
: DON’T CARE  
2/13  
74ACT299  
LOGIC DIAGRAM  
3/13  
74ACT299  
TIMING CHART  
4/13  
74ACT299  
ABSOLUTE MAXIMUM RATINGS  
Symbol  
VCC  
VI  
Parameter  
Value  
-0.5 to +7  
-0.5 to VCC + 0.5  
-0.5 to VCC + 0.5  
± 20  
Unit  
V
Supply Voltage  
DC Input Voltage  
V
VO  
DC Output Voltage  
DC Input Diode Current  
DC Output Diode Current  
DC Output Current  
V
IIK  
mA  
mA  
mA  
mA  
oC  
IOK  
± 20  
IO  
50  
±
ICC or IGND DC VCC or Ground Current  
400  
±
Tstg  
TL  
Storage Temperature  
-65 to +150  
300  
Lead Temperature (10 sec)  
oC  
AbsoluteMaximum Ratingsarethose values beyond whichdamage tothe device may occur. Functional operation under these condition isnot implied.  
RECOMMENDED OPERATING CONDITIONS  
Symbol  
VCC  
VI  
Parameter  
Value  
4.5 to 5.5  
0 to VCC  
0 to VCC  
-40 to +85  
8
Unit  
V
Supply Voltage  
Input Voltage  
V
VO  
Output Voltage  
V
oC  
Top  
Operating Temperature:  
dt/dv  
Input Rise and Fall Time VCC = 4.5 to 5.5V (note 1)  
ns/V  
1)VIN from0.8V to2.0V  
5/13  
74ACT299  
DC SPECIFICATIONS  
Symbol  
Parameter  
Test Conditions  
Value  
TA = 25 oC  
Min. Typ. Max. Min. Max.  
Unit  
VCC  
(V)  
-40 to 85 oC  
VIH  
VIL  
High Level Input Voltage  
Low Level Input Voltage  
4.5  
5.5  
4.5  
5.5  
4.5  
5.5  
4.5  
5.5  
4.5  
5.5  
4.5  
5.5  
5.5  
5.5  
VO = 0.1V or  
VCC - 0.1 V  
2.0  
2.0  
1.5  
1.5  
2.0  
2.0  
V
V
V
VO = 0.1V or  
VCC - 0.1 V  
1.5  
0.8  
0.8  
0.8  
0.8  
1.5  
VOH  
High Level Output  
Voltage  
I =-50  
A
4.4  
5.4  
4.49  
5.49  
4.4  
5.4  
µ
O
VI(*)  
VIH or  
VIL  
=
IO=-50 µA  
IO=-24 mA 3.86  
IO=-24 mA 4.86  
IO=50 µA  
3.76  
4.76  
VOL  
Low Level Output  
Voltage  
0.001 0.1  
0.001 0.1  
0.36  
0.1  
0.1  
0.44  
0.44  
±1  
VI(*)  
VIH or  
VIL  
=
V
IO=50 mA  
IO=24 mA  
IO=24 mA  
0.36  
II  
Input Leakage Current  
VI = VCC or GND  
±0.1  
µA  
µA  
IOZ  
3 State Output Leakage  
Current  
VI = VIH or VIL  
VO = VCC or GND  
±0.5  
±5  
ICCT  
ICC  
Max ICC /Input  
5.5  
5.5  
VI = VCC -2.1 V  
0.6  
1.5  
80  
mA  
Quiescent Supply  
Current  
VI = VCC or GND  
8
µA  
IOLD  
IOHD  
Dynamic Output Current  
(note 1, 2)  
5.5  
VOLD = 1.65 V max  
VOHD = 3.85 V min  
75  
mA  
mA  
-75  
1) Maximum test duration 2ms, one output loaded attime  
2)Incident wave switchingis guaranteed ontransmission lines withimpedances aslowas50 .  
(*) All outputs loaded.  
6/13  
74ACT299  
AC ELECTRICAL CHARACTERISTICS  
(CL = 50 pF, RL = 500 , Input tr = t =3 ns)  
f
Symbol  
Parameter  
Test Condition  
Value  
TA = 25 oC  
Min. Typ. Max. Min. Max.  
Unit  
VCC  
(V)  
5.0(*)  
-40 to 85 oC  
tPLH  
tPHL  
tPLH  
tPHL  
tPHL  
Propagation Delay Time  
CLOCK to Q’A, Q’H  
7.2  
7.4  
6.0  
6.3  
7.4  
7.2  
10.5  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
12.0  
ns  
ns  
ns  
ns  
ns  
ns  
Propagation Delay Time  
CLOCK to QA - QH  
5.0(*)  
5.0(*)  
5.0(*)  
5.0(*)  
5.0(*)  
5.0(*)  
11.4  
10.0  
10.5  
11.4  
9.6  
13.0  
11.5  
12.0  
13.0  
11.0  
5.0  
Propagation Delay Time  
CLEAR to Q’A, Q’H  
tPHL  
Propagation Delay Time  
CLEAR to QA - QH  
tPZL  
tPZH  
tPLZ  
tPHZ  
Output Enable Time  
Output Disable Time  
tw  
CLEAR pulse Width,  
LOW  
5.0  
ns  
ns  
ns  
tw  
ts  
CLOCK pulse Width  
5.0(*)  
5.0(*)  
5.0  
6.0  
5.0  
6.5  
Setup Time HIGH or  
LOW (S0 or S1 to CK)  
th  
ts  
th  
Hold Time HIGH or LOW  
(S0 or S1 to CK)  
5.0(*)  
5.0(*)  
5.0(*)  
0.0  
3.5  
2.0  
2.0  
0.0  
3.5  
2.0  
2.0  
ns  
ns  
Setup Time HIGH or  
LOW (SR or SL to CK)  
Hold Time HIGH or LOW  
(SR or SL to CK)  
ns  
ns  
tREM  
fMAX  
Recovery Time CLR to Q  
5.0(*)  
5.0(*)  
Maximum Clock  
Frequency  
80  
120  
80  
MHz  
*) Voltagerange is5V ± 0.5V  
CAPACITIVE CHARACTERISTICS  
Symbol  
Parameter  
Test Conditions  
Value  
TA = 25 oC  
Unit  
VCC  
-40 to 85 oC  
(V)  
Min. Typ. Max. Min. Max.  
CIN  
CI/O  
CPD  
Input Capacitance  
5
10  
10  
5.0  
5.0  
5.0  
pF  
pF  
Bus Input Capacitance  
13  
Power Dissipation  
fIN = 10 MHz  
160  
Capacitance (note 1)  
1)CPD isdefined as thevalue ofthe IC’sinternal equivalent capacitance whichiscalculated fromthe operating current consumption without load. (Referto  
7/13  
74ACT299  
TEST CIRCUIT  
TEST  
SWITCH  
Open  
tPLH, tPHL  
tPZL, tPLZ  
tPZH, tPHZ  
2VCC  
Open  
CL = 50 pF or equivalent (includes jigand probe capacitance)  
RL =R1 =500orequivalent  
RT = ZOUT ofpulse generator (typically50)  
WAVEFORM 1: PROPAGATION DELAYS  
(f=1MHz; 50% duty cycle)  
8/13  
74ACT299  
WAVEFORM 2: PROPAGATION DELAYS  
(f=1MHz; 50% duty cycle)  
WAVEFORM 3: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)  
9/13  
74ACT299  
WAVEFORM 4: PROPAGATION DELAYS  
(f=1MHz; 50% duty cycle)  
10/13  
74ACT299  
Plastic DIP-20 (0.25) MECHANICAL DATA  
mm  
inch  
TYP.  
DIM.  
MIN.  
0.254  
1.39  
TYP.  
MAX.  
MIN.  
0.010  
0.055  
MAX.  
a1  
B
b
1.65  
0.065  
0.45  
0.25  
0.018  
0.010  
b1  
D
E
e
25.4  
1.000  
8.5  
0.335  
0.100  
0.900  
2.54  
22.86  
e3  
F
7.1  
0.280  
0.155  
I
3.93  
L
3.3  
0.130  
Z
1.34  
0.053  
P001J  
11/13  
74ACT299  
SO-20 MECHANICAL DATA  
mm  
inch  
TYP.  
DIM.  
MIN.  
TYP.  
MAX.  
2.65  
0.20  
2.45  
0.49  
0.32  
MIN.  
MAX.  
0.104  
0.007  
0.096  
0.019  
0.012  
A
a1  
a2  
b
0.10  
0.004  
0.35  
0.23  
0.013  
0.009  
b1  
C
0.50  
0.020  
c1  
D
45 (typ.)  
12.60  
10.00  
13.00  
10.65  
0.496  
0.393  
0.512  
0.419  
E
e
1.27  
0.050  
0.450  
e3  
F
11.43  
7.40  
0.50  
7.60  
1.27  
0.75  
0.291  
0.19  
0.299  
0.050  
0.029  
L
M
S
8 (max.)  
P013L  
12/13  
74ACT299  
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences  
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is  
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are  
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products  
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.  
The ST logo is a trademark of STMicroelectronics  
1999 STMicroelectronics – Printed in Italy – All Rights Reserved  
STMicroelectronics GROUP OF COMPANIES  
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http://www.st.com  
.
13/13  

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