74ACT373SCTR [STMICROELECTRONICS]

Bus Driver, ACT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, 0.300 INCH, LEAD FREE, MS-013, SOIC-20;


型号：	74ACT373SCTR
厂家：	ST
描述：	Bus Driver, ACT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, 0.300 INCH, LEAD FREE, MS-013, SOIC-20 锁存器
文件：	总11页 (文件大小：241K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74ACT373

OCTAL D-TYPE LATCH

WITH 3 STATE OUTPUTS (NON INVERTED)

■

HIGH SPEED: t_PD= 6ns (TYP.) at V_CC= 5V

LOW POWER DISSIPATION:

I_CC= 4µA(MAX.) at T_A=25°C

COMPATIBLE WITH TTL OUTPUTS

■

_IH= 2V (MIN.), V_IL= 0.8V (MAX.)

50Ω TRANSMISSION LINE DRIVING

CAPABILITY

SYMMETRICAL OUTPUT IMPEDANCE:

|I_OH| = I_OL= 24mA (MIN)

BALANCED PROPAGATION DELAYS:

t_PLHt_PHL

OPERATING VOLTAGE RANGE:

V_CC(OPR) = 4.5V to 5.5V

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 373

DIP

SOP

TSSOP

T & R

ORDER CODES

PACKAGE

TUBE

DIP

SOP

74ACT373B

74ACT373M

74ACT373MTR

74ACT373TTR

TSSOP

IMPROVED LATCH-UP IMMUNITY

up at the D inputs. When the (OE) input is low, the

8 outputs will be in a normal logic state (high or

low logic level); when the (OE) input is high, the

outputs will be in a high impedance state.

This device is designed to interface directly High

Speed CMOS systems with TTL and NMOS

components.

DESCRIPTION

The 74ACT373 is a high-speed CMOS OCTAL

D-TYPE LATCH with 3 STATE OUTPUT NON

INVERTING fabricated with sub-micron silicon

gate and double-layer metal wiring C²MOS

technology.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

These 8 bit D-Type latch are controlled by a latch

enable input (LE) and an output enable input (OE).

When the (LE) input is high , the Q outputs follow

the data (D) inputs . When the (LE) is taken low,

the Q outputs will be latched at the logic levels set

PIN CONNECTION AND IEC LOGIC SYMBOLS

April 2001

1/11

74ACT373

INPUT AND OUTPUT EQUIVALENT CIRCUIT

PIN DESCRIPTION

PIN No

SYMBOL

NAME AND FUNCTION

3 state Output Enable

Input (Active LOW)

2, 5, 6, 9, 12,

15, 16,19

Q0 to Q7 3-State Outputs

D0 to D7 Data Inputs

3, 4, 7, 8, 13,

14, 17, 18

Latch Enable Input

Ground (0V)

GND

V_CC

Positive Supply Voltage

TRUTH TABLE

INPUTS

OUTPUT

NO CHANGE

X : Don’t care

Z : High Impedance

NOTE: Outputs are latched at the time when the input is taken LOW logic level

LOGIC DIAGRAM

This logic diagram has not be used to estimate propagation delays

2/11

74ACT373

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Value

Unit

V_CC

V_I

Supply Voltage

-0.5 to +7

DC Input Voltage

-0.5 to V_CC+ 0.5

V_O

I_IK

DC Output Voltage

DC Input Diode Current

DC Output Diode Current

DC Output Current

± 20

°C

I_OK

I_O

± 50

_CCor I_GNDDC V_CCor Ground Current

± 400

T_stg

Storage Temperature

-65 to +150

300

T_L

Lead Temperature (10 sec)

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is

not implied.

RECOMMENDED OPERATING CONDITIONS

Symbol

V_CC

V_I

Parameter

Value

Unit

Supply Voltage

4.5 to 5.5

0 to V_CC

Input Voltage

V_O

Output Voltage

T_op

Operating Temperature

-55 to 125

°C

ns/V

Input Rise and Fall Time V_CC= 4.5 to 5.5V (note 1)

dt/dv

1) V_INfrom 0.8V to 2.0V

3/11

74ACT373

DC SPECIFICATIONS

Test Condition

Value

_A= 25°C

Symbol

Parameter

-40 to 85°C -55 to 125°C Unit

V_CC

(V)

Min. Typ. Max. Min. Max. Min. Max.

V_IH

V_IL

High Level Input

Voltage

4.5

5.5

4.5

5.5

4.5

5.5

4.5

5.5

4.5

5.5

V_O= 0.1 V or

2.0

1.5

2.0

_CC-0.1V

V_O= 0.1 V or

_CC-0.1V

Low Level Input

Voltage

1.5

0.8

1.5

V_OH

High Level Output

Voltage

I_O=-50 µA

I_O=-24 mA

I_O=50 µA

I_O=24 mA

4.4

5.4

4.49

5.49

4.4

5.4

4.4

5.4

3.7

4.7

3.86

4.86

3.76

4.76

V_OL

Low Level Output

Voltage

0.001 0.1

0.36

0.1

0.5

4.5

5.5

0.44

0.36

I_I

Input Leakage Cur-

rent

V_I= V_CCor GND

5.5

± 0.1

± 1

µA

I_OZ

High Impedance

Output Leakege

Current

V_I= V_IHor V_IL

5.5

± 0.5

± 5

_O= V_CCor GND

V_I= V_CC- 2.1V

V_I= V_CCor GND

I_CCT

I_CC

Max I_CC/Input

5.5

0.6

1.5

1.6

Quiescent Supply

Current

µA

I_OLD

I_OHD

_OLD= 1.65 V max

Dynamic Output

Current (note 1, 2)

5.5

V_OHD= 3.85 V min

-75

-50

1) Maximum test duration 2ms, one output loaded at time

2) Incident wave switching is guaranteed on trasmission lines with impedances as low as 50Ω

AC ELECTRICAL CHARACTERISTICS (C_L= 50 pF, R_L= 500 Ω, Input t_r= t_f= 3ns)

Test Condition Value

-40 to 85°C -55 to 125°C Unit

Min. Typ. Max. Min. Max. Min. Max.

T_A= 25°C

Symbol

Parameter

V_CC

(V)

_PLHt_PHLPropagation Delay

5.0^(*)

5.5

6.0

7.0

1.3

-0.5

0.5

10.0

9.5

11.5

10.5

12.5

8.0

11.5

10.5

12.5

8.0

Time LE to Q

_PLHt_PHLPropagation Delay

Time D to Q

_PZLt_PZHOutput Enable

Time

_PLZt_PHZOutput Disable

Time

11.0

7.0

t_W

LE Minimum Pulse

Width, HIGH

t_s

Setup Time D to

7.0

8.0

LE, HIGH or LOW

t_h

Hold Time D to LE,

HIGH or LOW

0.0

1.0

(*) Voltage range is 5.0V ± 0.5V

4/11

74ACT373

CAPACITIVE CHARACTERISTICS

Test Condition

Value

-40 to 85°C -55 to 125°C Unit

T_A= 25°C

Symbol

Parameter

V_CC

(V)

Min. Typ. Max. Min. Max. Min. Max.

C_IN

C_OUT

C_PD

Input Capacitance

5.0

Output

Capacitance

Power Dissipation

Capacitance (note

f_IN= 10MHz

5.0

1) C_PDis defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without

load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I_CC(opr)= C_PDx V_CCx f_IN+ I_CC/n (per circuit)

TEST CIRCUIT

TEST

SWITCH

_PLH, t_PHL

t_PZL, t_PLZ

t_PZH, t_PHZ

C_L= 50pF or equivalent (includes jig and probe capacitance)

Open

2V_CC

Open

_L= R₁= 500Ω or equivalent

R_T= Z_OUTof pulse generator (typically 50Ω)

5/11

74ACT373

WAVEFORM 1: PROPAGATION DELAYS, LE MINIMUN PULSE WIDTH, Dn TO LE SETUP AND

HOLD TIMES (f=1MHz; 50% duty cycle)

WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle)

6/11

74ACT373

WAVEFORM 3: PROPAGATION DELAYS TIME (f=1MHz; 50% duty cycle)

7/11

74ACT373

Plastic DIP-20 (0.25) MECHANICAL DATA

inch

TYP.

DIM.

MIN.

0.254

1.39

TYP.

MAX.

MIN.

0.010

0.055

MAX.

1.65

0.065

0.45

0.25

0.018

0.010

25.4

1.000

8.5

2.54

0.335

0.100

0.900

22.86

7.1

0.280

0.155

3.93

3.3

0.130

1.34

0.053

P001J

8/11

74ACT373

SO-20 MECHANICAL DATA

inch

TYP.

DIM.

MIN.

TYP.

MAX.

2.65

0.20

2.45

0.49

0.32

MIN.

MAX.

0.104

0.007

0.096

0.019

0.012

0.10

0.004

0.35

0.23

0.013

0.009

0.50

0.020

45 (typ.)

12.60

10.00

13.00

10.65

0.496

0.393

0.512

0.419

1.27

0.050

0.450

11.43

7.40

0.50

7.60

1.27

0.75

0.291

0.19

0.299

0.050

0.029

8 (max.)

P013L

9/11

74ACT373

TSSOP20 MECHANICAL DATA

inch

TYP.

DIM.

MIN.

TYP.

MAX.

1.1

MIN.

MAX.

0.433

0.006

0.374

0.0118

0.0079

0.260

0.256

0.176

0.05

0.85

0.19

0.09

6.4

0.10

0.9

0.15

0.95

0.30

0.2

0.002

0.335

0.0075

0.0035

0.252

0.246

0.169

0.004

0.354

6.5

6.4

6.6

0.256

0.252

6.25

4.3

6.5

4.4

4.48

0.173

0.65 BSC

4^o

0.0256 BSC

4^o

0^o

8^o

0^o

8^o

0.50

0.60

0.70

0.020

0.024

0.028

PIN 1 IDENTIFICATION

10/11

74ACT373

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the

consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from

its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications

mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information

previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or

systems without express written approval of STMicroelectronics.

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11/11

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