74VHCT373AMTR [STMICROELECTRONICS]

OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING; 八D型具有三态输出的非反相LATCH
74VHCT373AMTR
型号: 74VHCT373AMTR
厂家: ST    ST
描述:

OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING
八D型具有三态输出的非反相LATCH

总线驱动器 总线收发器 逻辑集成电路 光电二极管 输出元件
文件: 总13页 (文件大小:283K)
中文:  中文翻译
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74VHCT373A  
OCTAL D-TYPE LATCH  
WITH 3 STATE OUTPUTS NON INVERTING  
HIGH SPEED: t = 6.4 ns (TYP.) at V = 5V  
PD CC  
LOW POWER DISSIPATION:  
I
= 4 µA (MAX.) at T =25°C  
CC  
A
COMPATIBLE WITH TTL OUTPUTS:  
= 2V (MIN.), V = 0.8V (MAX)  
POWER DOWN PROTECTION ON INPUTS  
& OUTPUTS  
V
IH  
IL  
SOP  
TSSOP  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 8 mA (MIN)  
OH  
OL  
Table 1: Order Codes  
PACKAGE  
BALANCED PROPAGATION DELAYS:  
t
t
PLH  
PHL  
OPERATING VOLTAGE RANGE:  
(OPR) = 4.5V to 5.5V  
V
SOP  
74VHCT373AMTR  
74VHCT373ATTR  
CC  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 373  
TSSOP  
IMPROVED LATCH-UP IMMUNITY  
precisely at the logic level of D input data. While  
the (OE) input is low, the 8 outputs will be in a  
normal logic state (high or low logic level) and  
while high level the outputs will be in a high  
impedance state.  
Power down protection is provided on all inputs  
and outputs and 0 to 7V can be accepted on  
inputs with no regard to the supply voltage. This  
device can be used to interface 5V to 3V since all  
inputs are equipped with TTL threshold.  
LOW NOISE: V  
= 0.9V (MAX.)  
OLP  
DESCRIPTION  
The 74VHCT373A is an advanced high-speed  
CMOS OCTAL D-TYPE LATCH with 3 STATE  
OUTPUTS NON INVERTING fabricated with  
sub-micron silicon gate and double-layer metal  
2
wiring C MOS technology.  
These 8 bit D-Type latch are controlled by a latch  
enable input (LE) and an output enable input (OE).  
While the LE inputs is held at a high level, the Q  
outputs will follow the data input precisely. When  
the LE is taken low, the Q outputs will be latched  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
Figure 1: Pin Connection And IEC Logic Symbols  
Rev. 4  
1/13  
December 2004  
74VHCT373A  
Figure 2: Input Equivalent Circuit  
Table 2: Pin Description  
PIN N°  
SYMBOL  
NAME AND FUNCTION  
1
OE  
3 State Output Enable  
Input (Active LOW)  
2, 5, 6, 9, 12,  
15, 16, 19  
Q0 to Q7 3-State Outputs  
3, 4, 7, 8, 13,  
14, 17, 18  
D0 to D7  
Data Inputs  
11  
10  
20  
LE  
Latch Enable Input  
Ground (0V)  
GND  
V
Positive Supply Voltage  
CC  
Table 3: Truth Table  
OE  
INPUTS  
LE  
OUTPUT  
Q
D
H
L
L
L
X
L
X
X
L
Z
NO CHANGE*  
H
H
L
H
H
X : Don’t Care  
Z : High Impedance  
* : Q Outputs are latched at the time when the LE input is taken low logic level.  
Figure 3: Logic Diagram  
This logic diagram has not be used to estimate propagation delays  
2/13  
74VHCT373A  
Table 4: Absolute Maximum Ratings  
Symbol  
Parameter  
Value  
Unit  
V
Supply Voltage  
-0.5 to +7.0  
-0.5 to +7.0  
-0.5 to +7.0  
V
V
V
CC  
V
DC Input Voltage  
I
V
DC Output Voltage (see note 1)  
DC Output Voltage (see note 2)  
DC Input Diode Current  
DC Output Diode Current  
DC Output Current  
O
V
-0.5 to V + 0.5  
V
O
CC  
I
- 20  
± 20  
mA  
mA  
mA  
mA  
°C  
IK  
I
OK  
I
± 25  
O
I
or I  
DC V or Ground Current  
± 50  
CC  
GND  
CC  
T
Storage Temperature  
-65 to +150  
300  
stg  
T
Lead Temperature (10 sec)  
°C  
L
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is  
not implied  
1) Output in OFF State  
2) High or Low State  
Table 5: Recommended Operating Conditions  
Symbol  
Parameter  
Value  
Unit  
V
Supply Voltage  
4.5 to 5.5  
0 to 5.5  
0 to 5.5  
V
V
CC  
V
Input Voltage  
I
V
Output Voltage (see note 1)  
Output Voltage (see note 2)  
Operating Temperature  
V
O
V
0 to V  
V
O
CC  
T
-55 to 125  
0 to 20  
°C  
ns/V  
op  
Input Rise and Fall Time (see note 3) (V = 5.0 ± 0.5V)  
dt/dv  
CC  
1) Output in OFF State  
2) High or Low State  
3) V from 0.8V to 2V  
IN  
3/13  
74VHCT373A  
Table 6: DC Specifications  
Test Condition  
Value  
T = 25°C  
Symbol  
Parameter  
-40 to 85°C -55 to 125°C Unit  
A
V
CC  
(V)  
Min. Typ. Max. Min. Max. Min. Max.  
V
High Level Input  
Voltage  
4.5 to  
5.5  
IH  
2
2
2
V
V
V
Low Level Input  
Voltage  
4.5 to  
5.5  
IL  
0.8  
0.8  
0.8  
V
High Level Output  
Voltage  
I =-50 µA  
4.5  
4.5  
4.5  
4.5  
4.4  
4.5  
0.0  
4.4  
3.8  
4.4  
3.7  
OH  
O
V
V
I =-8 mA  
3.94  
O
V
Low Level Output  
Voltage  
I =50 µA  
0.1  
0.1  
0.1  
OL  
OZ  
O
I =8 mA  
0.36  
0.44  
0.55  
O
I
High Impedance  
Output Leakage  
Current  
V = V or V  
4.5 to  
5.5  
I
IH  
IL  
±0.25  
± 2.5  
± 2.5  
µA  
V
= 0V to 5.5  
O
I
Input Leakage  
Current  
0 to  
5.5  
I
V = 5.5V or GND  
± 0.1  
± 1.0  
± 1.0  
µA  
µA  
I
I
Quiescent Supply  
Current  
CC  
V = V or GND  
5.5  
5.5  
0
4
40  
40  
I
CC  
+I  
Additional Worst  
Case Supply  
Current  
One Input at 3.4V,  
CC  
other input at V  
1.35  
0.5  
1.5  
5.0  
1.5  
5.0  
mA  
CC  
or GND  
I
Output Leakage  
Current  
OPD  
V
= 5.5V  
µA  
OUT  
Table 7: AC Electrical Characteristics (Input t = t = 3ns)  
r
f
Test Condition  
Value  
T = 25°C  
Symbol  
Parameter  
-40 to 85°C -55 to 125°C Unit  
A
V
C
L
CC  
(V) (pF)  
Min. Typ. Max. Min. Max. Min. Max.  
(*)  
t
Propagation Delay  
Time  
LE to Q  
15  
50  
15  
50  
5.4  
6.0  
6.4  
7.1  
12.3  
13.3  
8.5  
1.0  
1.0  
1.0  
1.0  
13.5  
14.5  
9.5  
1.0  
1.0  
1.0  
1.0  
13.5  
14.5  
9.5  
PLH  
5.0  
5.0  
5.0  
5.0  
ns  
ns  
t
PHL  
(*)  
(*)  
(*)  
t
t
Propagation Delay  
Time  
D to Q  
PLH  
PHL  
9.5  
10.5  
10.5  
(*)  
t
t
Output Enable  
Time  
15  
50  
6.2  
6.9  
10.9  
11.9  
1.0  
1.0  
12.5  
13.5  
1.0  
1.0  
12.5  
13.5  
PZL  
5.0  
5.0  
RL = 1KΩ  
RL = 1KΩ  
ns  
ns  
(*)  
PZH  
t
Output Disable  
Time  
PLZ  
PHZ  
(*)  
50  
6.7  
11.2  
1.0  
12.0  
1.0  
12.0  
5.0  
t
t
Pulse Width (LE)  
HIGH  
w
(*)  
(*)  
(*)  
6.5  
1.5  
3.5  
8.5  
1.5  
3.5  
8.5  
1.5  
3.5  
ns  
ns  
ns  
5.0  
5.0  
5.0  
t
Setup Time D to LE  
HIGH or LOW  
s
t
Hold Time D to LE  
HIGH or LOW  
h
t
t
Output to Output  
Skew time (note 1)  
OSLH  
(*)  
50  
1.0  
1.0  
1.0  
ns  
5.0  
OSHL  
(*) Voltage range is 5.0V ± 0.5V  
Note 1: Parameter guaranteed by design. t  
= |t  
- t  
|, t  
= |t  
- t  
|
soLH  
pLHm pLHn soHL  
pHLm pHLn  
4/13  
74VHCT373A  
Table 8: Capacitive Characteristics  
Test Condition  
Value  
-40 to 85°C -55 to 125°C Unit  
Min. Typ. Max. Min. Max. Min. Max.  
T = 25°C  
Symbol  
Parameter  
A
C
Input Capacitance  
4
9
10  
10  
10  
pF  
pF  
IN  
Output  
Capacitance  
C
OUT  
C
Power Dissipation  
Capacitance  
(note 1)  
PD  
14  
pF  
1) C is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without  
PD  
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I  
= C x V x f + I /8 (per Latch)  
CC(opr)  
PD CC IN CC  
Table 9: Dynamic Switching Characteristics  
Test Condition  
Value  
T = 25°C  
Symbol  
Parameter  
-40 to 85°C -55 to 125°C Unit  
Min. Typ. Max. Min. Max. Min. Max.  
A
V
(V)  
CC  
V
Dynamic Low  
Voltage Quiet  
Output (note 1, 2)  
0.6  
0.9  
OLP  
5.0  
V
-0.9  
2.0  
-0.6  
OLV  
Dynamic High  
Voltage Input  
(note 1, 3)  
V
C = 50 pF  
L
5.0  
5.0  
V
IHD  
Dynamic Low  
Voltage Input  
(note 1, 3)  
V
0.8  
ILD  
1) Worst case package.  
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.0V, (n-1) outputs switching and one output at GND.  
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.0V. Inputs under test switching: 3.0V to threshold (V ), 0V to threshold  
ILD  
(V ), f=1MHz.  
IHD  
5/13  
74VHCT373A  
Figure 4: Test Circuit  
TEST  
SWITCH  
t
t
t
, t  
Open  
PLH PHL  
, t  
V
CC  
PZL PLZ  
, t  
GND  
PZH PHZ  
C
R
R
=15/50pF or equivalent (includes jig and probe capacitance)  
L
L
T
= R1 = 1Kor equivalent  
= Z  
of pulse generator (typically 50)  
OUT  
Figure 5: Waveform - LE To Qn Propagation Delays, LE Minimun Pulse Width, Dn To LE Setup  
And Hold Times (f=1MHz; 50% duty cycle)  
6/13  
74VHCT373A  
Figure 6: Waveform - Output Enable And Disable Times (f=1MHz; 50% duty cycle)  
Figure 7: Waveform - Propagation Delay Time (f=1MHz; 50% duty cycle)  
7/13  
74VHCT373A  
SO-20 MECHANICAL DATA  
mm.  
inch  
TYP.  
DIM.  
MIN.  
TYP  
MAX.  
MIN.  
MAX.  
A
A1  
B
2.35  
2.65  
0.093  
0.104  
0.1  
0.33  
0.23  
12.60  
7.4  
0.30  
0.51  
0.32  
13.00  
7.6  
0.004  
0.013  
0.009  
0.496  
0.291  
0.012  
0.020  
0.013  
0.512  
0.299  
C
D
E
e
1.27  
0.050  
H
10.00  
0.25  
0.4  
10.65  
0.75  
1.27  
8°  
0.394  
0.010  
0.016  
0°  
0.419  
0.030  
0.050  
8°  
h
L
k
0°  
ddd  
0.100  
0.004  
0016022D  
8/13  
74VHCT373A  
TSSOP20 MECHANICAL DATA  
mm.  
inch  
TYP.  
DIM.  
MIN.  
TYP  
MAX.  
1.2  
MIN.  
MAX.  
0.047  
0.006  
0.041  
0.012  
0.0079  
0.260  
0.260  
0.176  
A
A1  
A2  
b
0.05  
0.8  
0.15  
1.05  
0.30  
0.20  
6.6  
0.002  
0.031  
0.007  
0.004  
0.252  
0.244  
0.169  
0.004  
0.039  
1
0.19  
0.09  
6.4  
c
D
6.5  
6.4  
0.256  
0.252  
E
6.2  
6.6  
E1  
e
4.3  
4.4  
4.48  
0.173  
0.65 BSC  
0.0256 BSC  
K
0˚  
8˚  
0˚  
8˚  
L
0.45  
0.60  
0.75  
0.018  
0.024  
0.030  
A2  
A
K
L
b
e
A1  
E
c
D
E1  
PIN 1 IDENTIFICATION  
1
0087225C  
9/13  
74VHCT373A  
Tape & Reel SO-20 MECHANICAL DATA  
mm.  
TYP  
inch  
TYP.  
DIM.  
MIN.  
MAX.  
330  
MIN.  
MAX.  
12.992  
0.519  
A
C
12.8  
20.2  
60  
13.2  
0.504  
0.795  
2.362  
D
N
T
30.4  
11  
1.197  
0.433  
0.528  
0.130  
0.161  
0.476  
Ao  
Bo  
Ko  
Po  
P
10.8  
13.2  
3.1  
0.425  
0.520  
0.122  
0.153  
0.468  
13.4  
3.3  
3.9  
4.1  
11.9  
12.1  
10/13  
74VHCT373A  
Tape & Reel TSSOP20 MECHANICAL DATA  
mm.  
TYP  
inch  
TYP.  
DIM.  
MIN.  
MAX.  
330  
MIN.  
MAX.  
12.992  
0.519  
A
C
12.8  
20.2  
60  
13.2  
0.504  
0.795  
2.362  
D
N
T
22.4  
7
0.882  
0.276  
0.280  
0.075  
0.161  
0.476  
Ao  
Bo  
Ko  
Po  
P
6.8  
6.9  
0.268  
0.272  
0.067  
0.153  
0.468  
7.1  
1.9  
4.1  
12.1  
1.7  
3.9  
11.9  
11/13  
74VHCT373A  
Table 10: Revision History  
Date  
Revision  
Description of Changes  
Order Codes Revision - pag. 1.  
16-Dec-2004  
4
12/13  
74VHCT373A  
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences  
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted  
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject  
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not  
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.  
The ST logo is a registered trademark of STMicroelectronics  
All other names are the property of their respective owners  
© 2004 STMicroelectronics - All Rights Reserved  
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www.st.com  
13/13  

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