A5973ADTR [STMICROELECTRONICS]
Up to 1.5 A step down switching regulator for automotive applications; 高达1.5 A降压开关稳压器用于汽车应用
| 型号： | A5973ADTR |
| 厂家： | 
ST |
| 描述： | Up to 1.5 A step down switching regulator for automotive applications |
| 文件： | 总19页 (文件大小：1108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A5973AD
Up to 1.5 A step down switching regulator
for automotive applications
Features
■ Qualified following the AEC-Q100
requirements (temperature grade 3),
see PPAP for more details
■ Temperature range -40 °C to 85 °C
■ 1.5 A DC output current
HSOP8 exposed pad
■ Operating input voltage from 4 V to 36 V
■ 3.3 V / ( 2 %) reference voltage
■ Output voltage adjustable from 1.235 V to 35 V
■ Low dropout operation: 100 % duty cycle
■ 500 kHz Internally fixed frequency
■ Voltage feedforward
Description
The A5973AD is a step down monolithic power
switching regulator with a minimum switch current
limit of 1.8 A so it is able to deliver more than
1.5 A DC current to the load depending on the
application conditions. The output voltage can be
set from 1.235 V to 35 V. The high current level is
also achieved thanks to an HSOP8 package with
exposed frame, that allows to reduce the R
down to approximately 40 °C/W. The device uses
an internal P-channel D-MOS transistor (with a
■ Zero load current operation
th(JA)
■ Internal current limiting
■ Inhibit for zero current consumption
■ Synchronization
typical R
of 250 mΩ) as switching element
DS(on)
to minimize the size of the external components.
An internal oscillator fixes the switching frequency
at 500 kHz. Having a minimum input voltage of
4 V only, it is particularly suitable for 5 V bus.
Pulse by pulse current limit with the internal
frequency modulation offers an effective constant
current short circuit protection. Pulse by pulse
current limit with the internal frequency
■ Protection against feedback disconnection
■ Thermal shutdown
Applications
■ Dedicated to automotive applications
modulation offers an effective constant current
short circuit protection.
Figure 1.
Typical application
L1 15uH
Vout=3.3V
VIN=4V to 35V
OUT
1
VCC
8
4
SYNCH
COMP
2
5
R1
D1
C4
A5973AD
5k6
STPS340U
C1
10uF
22nF
C2
330uF
6.3V
FB
6
7
3
35V
C3
VREF
3.3V
R3
CERAMIC
R2
INH
GND
220pF
4k7
3k3
May 2008
Rev 4
1/17
www.st.com
19
A5973AD
Contents
Contents
1
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
1.2
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
2.2
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
4
Electical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
Power supply and voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Voltages monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Oscillator and synchronizator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PWM comparator and power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Inhibit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5
Additional features and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1
5.2
5.3
Feedback disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Zero load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6
7
8
9
Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/19
A5973AD
Pin settings
1
Pin settings
1.1
Pin connection
Figure 2.
Pin connection (top view)
1.2
Pin description
Table 1.
N
Pin description
Pin
Description
1
OUT
Regulator output.
Master/slave synchronization. When it is open, a signal synchronous
with the turn-off of the internal power is present at the pin. When
connected to an external signal at a frequency higher than the internal
one, then the device is synchronized by the external signal. Connecting
together the SYNC pin of two devices, the one with the higher frequency
works as master and the other one, works as slave.
2
SYNCH
A logical signal (active high) disables the device. With IHN higher than
2.2 V the device is OFF and with INH lower than 0.8 V, the device is ON.
If INH is not used the pin must be grounded. When it is open, an internal
pullup disables the device.
3
4
5
INH
COMP
FB
E/A output for frequency compensation.
Feedback input. Connecting directly to this pin results in an output
voltage of 1.235 V. An extenal resistive divider is required for higher
output voltages (the typical value for the resistor connected between this
pin and ground is 4.7 k).
6
7
8
VREF
GND
VCC
3.3 V VREF. No cap is requested for stability.
Ground.
Unregulated DC input voltage.
3/19
A5973AD
Electrical data
2
Electrical data
2.1
Maximum ratings
Table 2.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
V8
V1
Input voltage
40
V
OUT pin DC voltage
-1 to 40
-5 to 40
V
V
OUT pin peak voltage at ∆t = 0.1 µs
I1
V4 , V5
V3
Maximum output current
Analog pins
int. limit.
4
V
INH
-0.3 to VCC
-0.3 to 4
2.25
V
V
V2
SYNCH
PTOT
Tj
Power dissipation at TA ≤ 70 °C
Operating junction temperature range
Storage temperature range
W
°C
°C
-40 to 150
-55 to 150
TSTG
2.2
Thermal data
Table 3.
Symbol
Rth(JA)
Thermal data
Parameter
SO8
Unit
Maximum thermal resistance junction-ambient
40 (1)
°C/W
1. Package mounted on board
4/19
A5973AD
Electical characteristics
3
Electical characteristics
Table 4. Electrical characteristics
(T = -40 °C to 125 °C, VCC = 12 V, unless otherwise specified)
J
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
Operating input voltage
range
VCC
RDS(on)
IL
V0=1.235 V; I0 = 2 A
4
36
V
Ω
A
Mosfet on resistance
0.250
2.3
0.5
Maximum limiting
current
VCC= 5 V
1.8
fSW
Switching frequency
Duty cycle
430
0
500
570
100
kHz
%
Dynamic characteristics (see test circuit).
4.4 V < VCC < 36 V,
20 mA < I0 < 2 A
V5
Voltage feedback
Efficiency
1.198
1.235
90
1.272
V
η
V0 = 5 V, VCC = 12 V
%
DC characteristics
Total operating
Iqop
Iq
5
7
mA
mA
µA
quiescent current
Quiescent current
Duty cycle=0;VFB=1.5 V
Vinh > 2.2 V
2.7
100
Total stand-by quiescent
current
Iqst-by
50
Inhibit
Device ON
0.8
0.4
V
V
INH threshold voltage
Device OFF
2.2
3.5
Error amplifier
VOH
VOL
High level output voltage VFB = 1 V
Low level output voltage VFB = 1.5 V
VCOMP = 1.9 V;
FB = 1 V
V
V
Io source
190
1
300
1.5
µA
Source output current
Sink output current
V
VCOMP = 1.9 V;
FB = 1 V
Io sink
Ib
mA
V
Source bias current
DC open loop gain
2.5
57
4
µA
RL = ∞
50
dB
5/19
A5973AD
Electical characteristics
Table 4. Electrical characteristics
(T = -40 °C to 125 °C, VCC = 12 V, unless otherwise specified)
J
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
ICOMP = -0.1 mA to
gm
Transconductance
2.3
mS
0.1 mA; VCOMP = 1.9 V
Synch function
High input voltage
2.5
VREF
0.74
V
V
VCC= 4.4 to 36 V;
VCC= 4.4 to 36 V;
Low input voltage
Vsynch= 0.74 V (1)
Vsynch= 2.33 V
0.11
0.21
0.25
0.45
Slave synch current
mA
Master output amplitude
Output pulse width
2.75
0.20
3
V
Isource= 3 mA
no load,
0.35
µs
Vsynch= 1.65 V
Reference section
I
REF = 0 to 5 mA
CC = 4.4 V to 36 V
Reference voltage
Line regulation
3.2
10
3.3
5
3.399
10
V
V
I
REF = 0 mA
CC = 4.4 V to 36 V
mV
V
Load regulation
8
15
30
mV
mA
I
REF = 0 mA
Short circuit current
18
1. Guaranteed by design.
6/19
A5973AD
Functional description
4
Functional description
The main internal blocks are shown in Figure 3, where is reported the device block diagram.
They are:
●
A voltage regulator that supplies the internal circuitry. From this regulator, a 3.3 V
reference voltage is externally available.
●
●
●
A voltage monitor circuit that checks the input and internal voltages.
A fully integrated sawtooth oscillator whose frequency is 500 kHz
Two embedded current limitations circuitries which control the current that flows
through the power switch. The pulse by pulse current limit forces the power switch OFF
cycle by cycle if the current reaches an internal threshold, while the frequency shifter
reduces the switching frequency in order to strongly reduce the duty cycle.
●
●
A transconductance error amplifier.
A pulse width modulator (PWM) comparator and the relative logic circuitry necessary
to drive the internal power.
●
●
●
An high side driver for the internal P-MOS switch.
An inhibit block for stand-by operation
A circuit to realize the thermal protection function.
Figure 3.
Block diagram
7/19
A5973AD
Functional description
4.1
Power supply and voltage reference
The internal regulator circuit (shown in Figure 4) consists of a start-up circuit, an internal
voltage preregulator, the bandgap voltage reference and the bias block that provides current
to all the blocks.
The starter gives the start-up currents to the whole device when the input voltage goes high
and the device is enabled (inhibit pin connected to ground).
The preregulator block supplies the bandgap cell with a preregulated voltage V
a very low supply voltage noise sensitivity.
that has
REG
4.2
Voltages monitor
An internal block senses continuously the VCC, VREF and VBG. If the voltages go higher than
their thresholds, the regulator starts to work. There is also an hysteresis on the VCC (UVLO).
Figure 4.
Internal regulator circuit
8/19
A5973AD
Functional description
4.3
Oscillator and synchronizator
Figure 5 shows the block diagram of the oscillator circuit.
The clock generator provides the switching frequency of the device that is internally fixed at
500 kHz. The frequency shifter block acts reducing the switching frequency in case of strong
overcurrent or short circuit. The clock signal is then used in the internal logic circuitry and is
the input of the Ramp generator and synchronizator blocks.
The ramp generator circuit provides the sawtooth signal, used to realize the PWM control
and the internal voltage feed forward, while the Synchronizator circuit generates the
synchronization signal. Infact the device has a synchronization pin that can works both as
master and slave.
As master to synchronize external devices to the internal switching frequency.
As slave to synchronize itself by external signal.
In particular, connecting together two devices, the one with the lower switching frequency
works as slave and the other one works as master.
To synchronize the device, the SYNC pin has to pass from a low level to a level higher than
the synchronization threshold with a duty cycle that can vary approximately from 10 % to
90 %, depending also on the signal frequency and amplitude.
The frequency of the synchronization signal must be at least higher than the internal
switching frequency of the device (500 kHz).
Figure 5.
Oscillator circuit
9/19
A5973AD
Functional description
4.4
Current protection
The L5973AD has two current limit protections, pulse by pulse and frequency fold back.
The schematic of the current limitation circuitry for the pulse by pulse protection is shown in
Figure 3.
The output power PDMOS transistor is split in two parallel PDMOS. The smallest one has a
resistor in series, RSENSE. The current is sensed through Rsense and if reaches the
threshold, the mirror is unbalanced and the PDMOS is switched off until the next falling edge
of the internal clock pulse.
Due to this reduction of the ON time, the output voltage decreases.
Since the minimum switch ON time (necessary to avoid false overcurrent signal) is not
enough to obtain a sufficiently low duty cycle at 500 kHz, the output current, in strong
overcurrent or short circuit conditions, could increase again. For this reason the switching
frequency is also reduced, so keeping the inductor current under its maximum threshold.
The Frequency Shifter (see Figure 5 on page 9) depends on the feedback voltage. As the
feedback voltage decreases (due to the reduced duty cycle), the switching frequency
decreases too.
Figure 6.
Current limitation circuitry
10/19
A5973AD
Functional description
4.5
Error amplifier
The voltage error amplifier is the core of the loop regulation. It is a transconductance
operational amplifier whose non inverting input is connected to the internal voltage
reference (1.235 V), while the inverting input (FB) is connected to the external divider or
directly to the output voltage. The output (COMP) is connected to the external compensation
network.
The uncompensated error amplifier has the following characteristics:
Table 5.
Uncompensated error amplifier
Tranconductance
2300 µS
65 dB
Low frequency gain
Minimum sink/source voltage
Output voltage swing
Input bias current
1500 µA/300 µA
0.4 V/3.65 V
2.5 µA
The error amplifier output is compared with the oscillator sawtooth to perform PWM control.
4.6
PWM comparator and power stage
This block compares the oscillator sawtooth and the error amplifier output signals
generating the PWM signal for the driving stage. The power stage is a very critical block
cause it has to guarantee a correct turn on and turn OFF of the PDMOS. The turn ON of the
power element, or better, the rise time of the current at turn on, is a very critical parameter to
compromise.
At a first approach, it looks like the faster it is the rise time, the lower are the turn on losses.
But there is a limit introduced by the recovery time of the recirculation diode. In fact when the
current of the power element equals the inductor current, the diode turns off and the drain of
the power is free to go high. But during its recovery time, the diode can be considered as an
high value capacitor and this produces a very high peak current, responsible of many
problems:
●
Spikes on the device supply voltage that cause oscillations (and thus noise) due to the
board parasitics.
●
●
●
Turn ON overcurrent causing a decrease of the efficiency and system reliability.
Big EMI problems.
Shorter freewheeling diode life.
The fall time of the current during the turn off is also critical. In fact it produces voltage
spikes (due to the parasitics elements of the board) that increase the voltage drop across
the PDMOS.
In order to minimize all these problems, a new topology of driving circuit has been used and
its block diagram is shown in Figure 7 on page 12.
The basic idea is to change the current levels used to turn on and off the power switch,
according with the PDMOS status and with the gate clamp status.
This circuitry allow to turn off and on quickly the power switch and to manage the above
question related to the freewheeling diode recovery time problem.
11/19
A5973AD
Functional description
The gate clamp is necessary to avoid that Vgs of the internal switch goes higher than
Vgsmax. The ON/OFF control block avoids any cross conduction between the supply line
and ground.
Figure 7.
Driving circuitry
4.7
4.8
Inhibit function
The inhibit feature allows to put in stand-by mode the device. With INH pin higher than 2.2 V
the device is disabled and the power consumption is reduced to less than 100 µA. With INH
pin lower than 0.8 V, the device is enabled. If the INH pin is left floating, an internal pull up
ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled.
The pin is also Vcc compatible.
Thermal shutdown
The shutdown block generates a signal that turns off the power stage if the temperature of
the chip goes higher than a fixed internal threshold (150 °C). The sensing element of the
chip is very close to the PDMOS area, so ensuring an accurate and fast temperature
detection. An hysteresis of approximately 20 °C avoids that the devices turns on and off
continuously
12/19
A5973AD
Additional features and protections
5
Additional features and protections
5.1
Feedback disconnection
In case of feedback disconnection, the duty cycle increases versus the maximum allowed
value, bringing the output voltage close to the input supply. This condition could destroy the
load.
To avoid this dangerous condition, the device is turned off if the feedback pin remains
floating.
5.2
Output overvoltage protection
The overvoltage protection, OVP, is realized by using an internal comparator, which input is
connected to the feedback, that turns off the power stage when the OVP threshold is
reached. This threshold is typically 30 % higher than the feedback voltage.
When a voltage divider is requested for adjusting the output voltage (see test application
circuit), the OVP intervention will be set at:
Equation 1
R1 + R2
--------------------
VOVP = 1.3 ×
× VFB
R2
Where R1 is the resistor connected between the output voltage and the feedback pin, while
R2 is between the feedback pin and ground.
5.3
Zero load
Due to the fact that the internal power is a PDMOS, no boostrap capacitor is required and
so, the device works properly also with no load at the output. In this condition it works in
burst mode, with random repetition rate of the burst.
13/19
A5973AD
Typical characteristics
6
Typical characteristics
Figure 8.
Junction temperature vs
output current
Figure 9.
Junction temperature vs
output current
Figure 10. Efficiency vs output current Figure 11. Efficiency vs output current
14/19
A5973AD
Package mechanical data
7
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
15/19
A5973AD
Package mechanical data
inch
Table 6.
Dim
HSOP8 mechanical data
mm
Min
Typ
Max
Min
Typ
Max
A
A1
A2
b
1.70
0.10
0.0669
0.0039
0.00
1.25
0.31
0.17
4.80
3
0.00
0.0492
0.0122
0.0067
0.1890
0.118
0.51
0.25
5.00
3.2
0.0201
0.0098
0.1969
0.126
c
D
4.90
3.1
0.1929
0.122
D1
E
5.80
3.80
2.31
6.00
3.90
2.41
1.27
6.20
4.00
2.51
0.2283
0.1496
0.091
0.2441
0.1575
0.099
E1
E2
e
0.095
h
0.25
0.40
0.50
1.27
0.0098
0.0157
0.0197
0.0500
L
k
0° (min), 8° (max)
ccc
0.10
0.0039
Figure 12. Package dimensions
16/19
A5973AD
Order codes
8
Order codes
Table 7.
Order code
Order code
Package
Packing
A5973AD
Tube
HSOP8
A5973ADTR
Tape and reel
17/19
A5973AD
Revision history
9
Revision history
Table 8.
Date
Document revision history
Revision
Changes
07-Aug-2007
31-Oct-2007
14-Jan-2008
2-May-2008
1
2
3
4
Initial release
Updated Table 4 on page 5, Table 8 on page 18
Updated Table 6 on page 16
Updated Table 4 on page 5
18/19
A5973AD
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