A7985A_技术文档

A7985A

2 A step-down switching regulator for automotive applications

Datasheet - production data

Applications

 Dedicated to automotive applications

 Automotive LED driving

Description

HSOP8 exposed pad

The A7985A is a step-down switching regulator

with a 2.5 A (minimum) current limited embedded

Power MOSFET, so it is able to deliver up to 2 A

current to the load depending on the application

conditions.

Features

 2 A DC output current

 Qualified following AEC-Q100 requirements

The input voltage can range from 4.5 V to 38 V,

while the output voltage can be set starting from

(see PPAP for more details)

0.6 V to V .

 4.5 V to 38 V input voltage

IN

 Output voltage adjustable from 0.6 V

Requiring a minimum set of external components,

the device includes an internal 250 kHz switching

frequency oscillator that can be externally

adjusted up to 1 MHz.

 250 kHz switching frequency, programmable

up to 1 MHz

 Internal soft-start and enable

 Low dropout operation: 100% duty cycle

 Voltage feed-forward

The HSOP8 package with exposed pad allows

the reduction of R

down to 40 °C/W.

th(JA)

 Zero load current operation

 Overcurrent and thermal protection

 HSOP8 package

Figure 1. Application circuit

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March 2014

DocID023128 Rev 5

1/44

This is information on a product in full production.

www.st.com

Contents

A7985A

Contents

1

Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1

1.2

Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2

3

4

5

Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.1

5.2

5.3

5.4

5.5

5.6

Oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Error amplifier and compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Enable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.1

6.2

6.3

6.4

Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.4.1

6.4.2

Type III compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Type II compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.5

6.6

6.7

Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7

Application ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.1

7.2

Positive buck-boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Inverting buck-boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

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A7985A

Contents

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8

9

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List of tables

A7985A

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Uncompensated error amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Input MLCC capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Inductors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Component list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

HSOP8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

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List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Oscillator circuit block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Sawtooth: voltage and frequency feed-forward; external synchronization . . . . . . . . . . . . . 12

Oscillator frequency vs. the FSW pin resistor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Soft-start scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

The error amplifier, the PWM modulator and the LC output filter . . . . . . . . . . . . . . . . . . . . 21

Figure 10. Type III compensation network. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 11. Open loop gain: module Bode diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 12. Open loop gain Bode diagram with ceramic output capacitor . . . . . . . . . . . . . . . . . . . . . . 24

Figure 13. Type II compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 14. Open loop gain: module Bode diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 15. Open loop gain Bode diagram with electrolytic/tantalum output capacitor . . . . . . . . . . . . . 28

Figure 16. Switching losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 17. Layout example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 18. Demonstration board application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 19. PCB layout: A7985A (component side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 20. PCB layout: A7985A (bottom side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 21. PCB layout: A7985A (front side). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 22. Junction temperature vs. output current at V = 24 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

IN

Figure 23. Junction temperature vs. output current at V = 12 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

IN

Figure 24. Junction temperature vs. output current at V = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

IN

Figure 25. Efficiency vs. output current at V = 1.8 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

O

Figure 26. Efficiency vs. output current at V = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

O

Figure 27. Efficiency vs. output current at V = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

O

Figure 28. Load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 29. Line regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 30. Load transient: from 0.4 A to 2 A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 31. Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 32. Short-circuit behavior at V = 12 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

IN

Figure 33. Short-circuit behavior at V = 24 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

IN

Figure 34. Positive buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 35. Maximum output current according to max. DC switch current (2.0 A): V = 12 V. . . . . . . 38

O

Figure 36. Inverting buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 37. Maximum output current according to switch max. peak current (2.0 A): V = -5 V. . . . . . 39

O

Figure 38. HSOP8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

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Pin settings

A7985A

1

Pin settings

1.1

Pin connection

Figure 2. Pin connection (top view)

1.2

Pin description

Table 1. Pin description

Description

N.

Type

1

OUT

Regulator output.

Master/slave synchronization. When it is left floating, a signal with

a phase shift of half a period in respect to the power turn-on is present at

the pin. When connected to an external signal at a frequency higher than

the internal one, the device is synchronized by the external signal, with

zero phase shift.

2

SYNCH

Connecting together the SYNCH pins of two devices, the one with the

higher frequency works as master and the other as slave; so the two

power turn-ons have a phase shift of half a period.

A logical signal (active high) enables the device. With EN higher than

1.2 V the device is ON and with EN lower than 0.63 V the device is OFF.

3

4

EN

COMP

Error amplifier output to be used for loop frequency compensation.

Feedback input. Connecting the output voltage directly to this pin the

output voltage is regulated at 0.6 V. To have higher regulated voltages an

external resistor divider is required from V_OUTto the FB pin.

5

6

FB

The switching frequency can be increased connecting an external

resistor from the FSW pin and ground. If this pin is left floating the device

works at its free-running frequency of 250 KHz.

FSW

7

8

GND

V_CC

Ground.

Unregulated DC input voltage.

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A7985A

Maximum ratings

2

Maximum ratings

Table 2. Absolute maximum ratings

Parameter

Symbol

Value

Unit

V_cc

Input voltage

45

OUT

Output DC voltage

-0.3 to V_CC

-0.3 to 4

-0.3 to V_CC

-0.3 to 1.5

2

F_SW, COMP, SYNCH Analog pin

V

EN

FB

Enable pin

Feedback voltage

P_TOT

T_J

Power dissipation at T_A< 60 °C

Junction temperature range

Storage temperature range

HSOP8

W

°C

-40 to 150

-55 to 150

T_stg

3

Thermal data

Table 3. Thermal data

Parameter

Maximum thermal resistance junction ambient⁽¹⁾HSOP8

Symbol

Value

Unit

R_th(JA)

40

°C/W

1. Package mounted on demonstration board.

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Electrical characteristics

A7985A

4

Electrical characteristics

T = -40 °C to 125 °C, V = 12 V, unless otherwise specified.

J

CC

Table 4. Electrical characteristics

Values

Symbol

Parameter

Test conditions

Unit

Min.

Typ. Max.

V_CC

V_CCON

V_CCHYS

R_DS(on)

I_LIM

Operating input voltage range

Turn-on V_CCthreshold

V_CCUVLO hysteresis

4.5

38

4.5

0.4

V

0.1

2.5

MOSFET on-resistance

Maximum limiting current

200

400

3.5

m

A

Oscillator

F_SW

V_FSW

D

Switching frequency

FSW pin voltage

210

0

250

275

100

kHz

V

1.254

Duty cycle

%

F_ADJ

Adjustable switching frequency

R_FSW= 33 k

1000

0.6

kHz

Dynamic characteristics

V_FB

Feedback voltage

4.5 V < V_CC< 38 V

0.588

0.612

V

DC characteristics

I_Q

Quiescent current

Duty cycle = 0, V_FB= 0.8 V

2.4

30

mA

I_QST-BY

Total standby quiescent current

20

A

Enable

Device OFF level

Device ON level

EN = V_CC

0.3

10

V_EN

EN threshold voltage

EN current

V

1.2

7.3

3

I_EN

7.5

µA

Soft-start

FSW pin floating

8.2

2

9.8

T_SS

Soft-start duration

ms

F_SW= 1 MHz, R_FSW= 33 k

Error amplifier

V_CH

V_CL

High level output voltage

Low level output voltage

Source COMP pin

V_FB< 0.6 V

V

V_FB> 0.6 V

0.1

I_{O SOURCE}

I_{O SINK}

G_V

V_FB= 0.5 V, V_COMP= 1 V

19

30

mA

dB

Sink COMP pin

V_FB= 0.7 V, V_COMP= 0.75 V

(1)

Open loop voltage gain

100

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A7985A

Electrical characteristics

Table 4. Electrical characteristics (continued)

Values

Unit

Symbol

Parameter

Test conditions

Min.

Typ. Max.

Synchronization function

V_{S_IN,HI}High input voltage

V_{S_IN,LO}Low input voltage

2

3.3

1

V

_{S_IN,HI}= 3 V, V_{S_IN,LO}= 0 V

100

300

t_{S_IN_PW}

Input pulse width

ns

V_{S_IN,HI}= 2 V, V_{S_IN,LO}= 1 V

V_SYNCH= 2.9 V

I_SYNCH,LO

V_{S_OUT,HI}

t_{S_OUT_PW}

Slave sink current

0.7

1

mA

V

Master output amplitude

Output pulse width

I_SOURCE= 4.5 mA

SYNCH floating

2

110

ns

Protection

Thermal shutdown

Hysteresis

150

30

T_SHDN

°C

1. Guaranteed by design.

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Functional description

A7985A

5

Functional description

The A7985A device is based on a “voltage mode”, constant frequency control. The output

voltage V is sensed by the feedback pin (FB) compared to an internal reference (0.6 V)

OUT

providing an error signal that, compared to a fixed frequency sawtooth, controls the ON and

OFF time of the power switch.

The main internal blocks are shown in the block diagram in Figure 3. They are:



A fully integrated oscillator that provides sawtooth to modulate the duty cycle and the

synchronization signal. Its switching frequency can be adjusted by an external resistor.

The voltage and frequency feed-forward are implemented



Soft-start circuitry to limit inrush current during the startup phase

Voltage mode error amplifier

Pulse width modulator and the relative logic circuitry necessary to drive the internal

power switch



High-side driver for embedded P-channel Power MOSFET switch

Peak current limit sensing block, to handle overload and short-circuit conditions

A voltage regulator and internal reference. It supplies internal circuitry and provides

a fixed internal reference



A voltage monitor circuitry (UVLO) that checks the input and internal voltages

A thermal shutdown block, to prevent thermal runaway.

Figure 3. Block diagram

VCC

REGULATOR

TRIMMING

UVLO

&

BANDGAP

EN

PEAK

CURRENT

LIMIT

1.254V

3.3V

0.6V

THERMAL

SOFT-

START

SHUTDOWN

COMP

DRIVER

S

R

Q

E/A

PWM

OUT

SYNCH

&

OSCILLATOR

PHASE SHIFT

FB

FSW

SYNCH

GND

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A7985A

Functional description

5.1

Oscillator and synchronization

Figure 4 shows the block diagram of the oscillator circuit. The internal oscillator provides

a constant frequency clock. Its frequency depends on the resistor externally connected to

the FSW pin. If the FSW pin is left floating, the frequency is 250 kHz; it can be increased as

shown in Figure 6 by an external resistor connected to ground.

To improve the line transient performance, keeping the PWM gain constant versus the input

voltage, the voltage feed-forward is implemented by changing the slope of the sawtooth

according to the input voltage change (see Figure 5.a).

The slope of the sawtooth also changes if the oscillator frequency is increased by the

external resistor. In this way, a frequency feed-forward is implemented (Figure 5.b) in order

to keep the PWM gain constant versus the switching frequency (see Section 6.4 on page 20

for PWM gain expression).

On the SYNCH pin the synchronization signal is generated. This signal has a phase shift of

180 ° with respect to the clock. This delay is useful when two devices are synchronized

connecting the SYNCH pin together. When SYNCH pins are connected, the device with the

higher oscillator frequency works as master, so the slave device switches at the frequency

of the master but with a delay of half a period. This minimizes the RMS current flowing

through the input capacitor (see the L5988D datasheet).

Figure 4. Oscillator circuit block diagram

Clock

FSW

Clock

SYNCH

Synchronization

Generator

Ramp

Sawtooth

Generator

The device can be synchronized to work at a higher frequency feeding an external clock

signal. The synchronization changes the sawtooth amplitude, changing the PWM gain

(Figure 5.c). This change must be taken into account when the loop stability is studied. To

minimize the change of the PWM gain, the free-running frequency should be set (with

a resistor on the FSW pin) only slightly lower than the external clock frequency. This pre-

adjusting of the frequency changes the sawtooth slope in order to render negligible the

truncation of sawtooth, due to the external synchronization.

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Functional description

A7985A

Figure 5. Sawtooth: voltage and frequency feed-forward; external synchronization

Figure 6. Oscillator frequency vs. the FSW pin resistor

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A7985A

Functional description

where:

Equation 1

28.5  10⁹

R_FSW= ----------------------------------------- – 3.23  10³

F

_SW– 250  10³

F

is desired switching frequency.

SW

5.2

Soft-start

Soft-start is essential to assure the correct and safe startup of the step-down converter. It

avoids inrush current surge and makes the output voltage increase monothonically.

The soft-start is performed by a staircase ramp on the non inverting input (V

amplifier. So the output voltage slew rate is:

) of the error

REF

Equation 2

R1





SR_OUT= SR_VREF 1 + -------





R2

where SR

is the slew rate of the non inverting input, while R1and R2 is the resistor

VREF

divider to regulate the output voltage (see Figure 7). The soft-start staircase consists of 64

steps of 9.5 mV each, from 0 V to 0.6 V. The time base of one step is of 32 clock cycles. So

the soft-start time and then the output voltage slew rate depend on the switching frequency.

Figure 7. Soft-start scheme

Soft-start time results:

Equation 3

32  64

SS_TIME= -----------------

Fsw

For example, with a switching frequency of 250 kHz, the SS

is 8 ms.

TIME

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Functional description

A7985A

5.3

Error amplifier and compensation

The error amplifier (E/A) provides the error signal to be compared with the sawtooth to

perform the pulse width modulation. Its non inverting input is internally connected to a 0.6 V

voltage reference, while its inverting input (FB) and output (COMP) are externally available

for feedback and frequency compensation. In this device the error amplifier is a voltage

mode operational amplifier, so with high DC gain and low output impedance.

The uncompensated error amplifier characteristics are shown in Table 5.

Table 5. Uncompensated error amplifier characteristics

Parameter

Value

Low frequency gain

GBWP

100 dB

4.5 MHz

Slew rate

7 V/s

Output voltage swing

Maximum source/sink current

0 to 3.3 V

17 mA/25 mA

In continuous conduction mode (CCM), the transfer function of the power section has two

poles due to the LC filter and one zero due to the ESR of the output capacitor. Different

kinds of compensation networks can be used depending on the ESR value of the output

capacitor. In case the zero introduced by the output capacitor helps to compensate the

double pole of the LC filter, a Type II compensation network can be used. Otherwise, a Type

III compensation network must be used (see Section 6.4 on page 20 for details of the

compensation network selection).

The methodology to compensate the loop is to introduce zeroes to obtain a safe phase

margin.

5.4

Overcurrent protection

The A7985A implements the overcurrent protection sensing current flowing through the

Power MOSFET. Due to the noise created by the switching activity of the Power MOSFET,

the current sensing is disabled during the initial phase of the conduction time. This avoids

an erroneous detection of a fault condition. This interval is generally known as “masking

time” or “blanking time”. The masking time is about 200 ns.

If the overcurrent limit is reached, the Power MOSFET is turned off, implementing the pulse-

by-pulse overcurrent protection. Under an overcurrent condition, the device can skip turn-on

pulses in order to keep the output current constant and equal to the current limit. If, at the

end of the “masking time”, the current is higher than the overcurrent threshold, the Power

MOSFET is turned off and one pulse is skipped. If, at the following switching-on, when the

“masking time” ends, the current is still higher than the overcurrent threshold, the device

skips two pulses. This mechanism is repeated and the device can skip up to seven pulses.

While, if at the end of the “masking time” the current is lower than the over current threshold,

the number of skipped cycles is decreased by one unit (see Figure 8).

So the overcurrent/short-circuit protection acts by switching off the Power MOSFET and

reducing the switching frequency down to one eighth of the default switching frequency, in

order to keep constant the output current around the current limit.

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A7985A

Functional description

This kind of overcurrent protection is effective if the output current is limited. To prevent the

current from diverging, the current ripple in the inductor during the ON-time must not be

higher than the current ripple during the OFF-time. That is:

Equation 4

V

_IN– V_OUT– R_DSON I_OUT– DCR  I_OUT

V

_OUT+ V_F+ R_DSON I_OUT+ DCR  I_OUT

------------------------------------------------------------------------------------------------------------  D = -----------------------------------------------------------------------------------------------------------  1 – D

L  F_SW

If the output voltage is shorted, V

0, I

= I , D/F

= T

, (1-D)/F

1/F

.

OUT

LIM

SW

ON_MIN

SW

So from the above equation the maximum switching frequency that guarantees to limit the

current results:

Equation 5

V_F+ DCR  I_LIM

1

*

F_SW= ------------------------------------------------------------------------------  ----------------------

V_IN– R_DSON+ DCR  I_LIM T_{ON_MIN}

With R

= 300 m, DRC = 0.08 , the worst condition is with V = 38 V, I

= 2.5 A;

LIM

DS(on)

IN

the maximum frequency to keep the output current limited during the short-circuit results

74 kHz.

Based on the pulse-by-pulse mechanism, that reduces the switching frequency down to one

eighth, the maximum F , adjusted by the FSW pin, that assures a full effective output

SW

current limitation is 74 kHz * 8 = 592 kHz.

If, with V = 38 V, the switching frequency is set higher than 592 kHz, during short-circuit

IN

condition the system finds a different equilibrium with higher current. For example, with

F

= 700 kHz and the output shorted to ground, the output current is limited around:

SW

Equation 6

*

V_IN F_SW– V_F T_{ON_MIN}

I_OUT= --------------------------------------------------------------------------------------------------------------- = 3.68A

*

DRC  T_{ON_MIN} + R_DSON+ DCR  F_SW

where F * is 700 kHz divided by eight.

SW

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Functional description

A7985A

Figure 8. Overcurrent protection

5.5

5.6

Enable function

The enable feature allows the device to be put into standby mode. With the EN pin lower

than 0.3 V, the device is disabled and the power consumption is reduced to less than 30A.

With the EN pin lower than 1.2 V, the device is enabled. If the EN pin is left floating, an

internal pull-down ensures that the voltage at the pin reaches the inhibit threshold and the

device is disabled. The pin is also V compatible.

CC

Hysteretic thermal shutdown

The thermal shutdown block generates a signal that turns off the power stage if the junction

temperature goes above 150 °C. Once the junction temperature goes back to about 120 °C,

the device restarts in normal operation. The sensing element is very close to the PDMOS

area, so ensuring an accurate and fast temperature detection.

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A7985A

Application information

6

Application information

6.1

Input capacitor selection

The capacitor connected to the input must be capable of supporting the maximum input

operating voltage and the maximum RMS input current required by the device. The input

capacitor is subject to a pulsed current, the RMS value of which is dissipated over its ESR,

affecting the overall system efficiency.

So the input capacitor must have an RMS current rating higher than the maximum RMS

input current and an ESR value compliant with the expected efficiency.

The maximum RMS input current flowing through the capacitor can be calculated as:

Equation 7

2  D²D²

I_RMS= I_O



D – -------------- + ------

²



where I is the maximum DC output current, D is the duty cycle, is the efficiency.

o

Considering = 1, this function has a maximum at D = 0.5 and it is equal to Io/2.

In a specific application the range of possible duty cycles must be considered in order to find

out the maximum RMS input current. The maximum and minimum duty cycles can be

calculated as:

Equation 8

V

_OUT+ V_F

D_MAX= ------------------------------------

_INMIN– V_SW

V

and

Equation 9

V

_OUT+ V_F

D_MIN= --------------------------------------

_INMAX– V_SW

V

where V is the forward voltage on the freewheeling diode and V

is voltage drop across

SW

F

the internal PDMOS.

The peak-to-peak voltage across the input capacitor can be calculated as:

Equation 10

I_O

V_PP= -------------------------  1 – ---  D + ---  1 – D + ESR  I_O

D











C_IN F_SW



where ESR is the equivalent series resistance of the capacitor.

Given the physical dimension, ceramic capacitors can well meet the requirements of the

input filter sustaining a higher input RMS current than electrolytic/tantalum types.

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Application information

Equation 11

A7985A

In this case, the equation of C as a function of the target V can be written as follows:

IN

PP

I_O

C_IN= --------------------------  1 – ---  D + ---  1 – D

D











V_PP F_SW



neglecting the small ESR of ceramic capacitors.

Considering = 1, this function has its maximum in D = 0.5, therefore, given the maximum

peak-to-peak input voltage (V

), the minimum input capacitor (C

) value is:

PP_MAX

IN_MIN

Equation 12

I_O

C_{IN_MIN}= -----------------------------------------------

2  V_{PP_MAX} F_SW

Typically, C is dimensioned to keep the maximum peak-to-peak voltage in the order of 1%

IN

of V

.

INMAX

In Table 6, some multi-layer ceramic capacitors suitable for this device are reported.

Table 6. Input MLCC capacitors

Manufacturer

Series

Cap value (F)

Rated voltage (V)

UMK325BJ106MM-T

GMK325BJ106MN-T

GRM32ER71H475K

10

50

35

50

Taiyo Yuden

muRata

4.7

A ceramic bypass capacitor, as close to the VCC and GND pins as possible, so that

additional parasitic ESR and ESL are minimized, is suggested in order to prevent instability

on the output voltage due to noise. The value of the bypass capacitor can go from 100 nF to

1 µF.

6.2

Inductor selection

The inductance value fixes the current ripple flowing through the output capacitor. So the

minimum inductance value in order to have the expected current ripple must be selected.

The rule to fix the current ripple value is to have a ripple at 20% -40% of the output current.

In continuous current mode (CCM), the inductance value can be calculated by the following

equation:

Equation 13

V

_IN– V_OUT

V_OUT+ V_F

I_L= -----------------------------  T_ON= ---------------------------  T_OFF

L

where T is the conduction time of the internal high-side switch and T

is the conduction

ON

OFF

time of the external diode (in CCM, F

= 1/(T + T

)). The maximum current ripple, at

SW

ON

OFF

fixed V

, is obtained at maximum T , that is at minimum duty cycle (see Section 6.1 to

OUT

OFF

calculate minimum duty). So by fixing I = 20% to 30% of the maximum output current, the

L

minimum inductance value can be calculated:

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A7985A

Application information

Equation 14

V

_OUT+ V_F1 – D

L_MIN= ---------------------------  --------------^M-----^I-^N--

I_MAXF_SW

where F

is the switching frequency, 1/(T + T

).

SW

ON

OFF

For example, for V

= 5 V, V = 24 V, I = 2 A and F

= 250 kHz, the minimum

SW

OUT

IN

O

inductance value to have I = 30% of I is about 28 H.

L

O

The peak current through the inductor is given by:

Equation 15

I_L

I_{L PK}= I_O+ -------

2

So if the inductor value decreases, then the peak current (that must be lower than the

minimum current limit of the device) increases. According to the maximum DC output

current for this product family (2 A), the higher the inductor value, the higher the average

output current that can be delivered, without triggering the overcurrent protection.

In Table 7 some inductor part numbers are listed.

Table 7. Inductors

Manufacturer

Series

Inductor value (H)

Saturation current (A)

MSS1038

MSS1048

3.8 to 10

12 to 22

8.2 to 15

2.2 to 4.7

1.5 to 3.3

6.6 to 12

3.9 to 6.5

3.84 to 5.34

3.75 to 6.25

4 to 6

Coilcraft

PD Type L

Wurth

PD Type M

CDRH6D226/HP

CDR10D48MN

3.6 to 5.2

4.1 to 5.7

SUMIDA

6.3

Output capacitor selection

The current in the capacitor has a triangular waveform which generates a voltage ripple

across it. This ripple is due to the capacitive component (charge or discharge of the output

capacitor) and the resistive component (due to the voltage drop across its ESR). So the

output capacitor must be selected in order to have a voltage ripple compliant with the

application requirements.

The amount of the voltage ripple can be calculated starting from the current ripple obtained

by the inductor selection.

Equation 16

I_MAX

V_OUT= ESR  I_MAX+ ------------------------------------

8  C_OUT f_SW

Usually the resistive component of the ripple is much higher than the capacitive one, if the

output capacitor adopted is not a multi-layer ceramic capacitor (MLCC) with very low ESR

value.

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44

Application information

A7985A

The output capacitor is important also for loop stability: it fixes the double LC filter pole and

the zero due to its ESR. In Section 6.4, how to consider its effect in the system stability is

illustrated.

For example, with V

= 5 V, V = 24 V, I = 0.9 A (resulting by the inductor value), in

OUT

IN

L

order to have a V

= 0.01 · V

, if the multi-layer ceramic capacitors are adopted,

OUT

10 µF are needed and the ESR effect on the output voltage ripple can be neglected. In case

of not-negligible ESR (electrolytic or tantalum capacitors), the capacitor is chosen taking into

account its ESR value. So, in the case of 330 µF with ESR = 70 mthe resistive

component of the drop dominates and the voltage ripple is 43 mV

The output capacitor is also important to sustain the output voltage when a load transient

with high slew rate is required by the load. When the load transient slew rate exceeds the

system bandwidth the output capacitor provides the current to the load. So if the high slew

rate load transient is required by the application, the output capacitor and system bandwidth

must be chosen in order to sustain the load transient.

In Table 8 below some capacitor series are listed.

Table 8. Output capacitors

Manufacturer

Series

Cap value (F)

Rated voltage (V)

ESR (m)

GRM32

GRM31

ECJ

22 to 100

10 to 47

6.3 to 25

6.3

< 5

muRata

10 to 22

< 5

PANASONIC

EEFCD

TPA/B/C

C3225

10 to 68

6.3

15 to 55

40 to 80

< 5

SANYO

TDK

100 to 470

22 to 100

4 to 16

6.3

6.4

Compensation network

The compensation network must assure stability and good dynamic performance. The loop

of the A7985A is based on the voltage mode control. The error amplifier is

a voltage operational amplifier with high bandwidth. So by selecting the compensation

network the E/A is considered as ideal, that is, its bandwidth is much larger than the system

one.

The transfer functions of the PWM modulator and the output LC filter are studied (see

Figure 10). The transfer function of the PWM modulator, from the error amplifier output

(COMP pin) to the OUT pin, results:

Equation 17

V_IN

G_PW0= --------

V_s

where V is the sawtooth amplitude. As seen in Section 5.1 on page 11, the voltage feed-

S

forward generates a sawtooth amplitude directly proportional to the input voltage, that is:

Equation 18

V_S= K  V_IN

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A7985A

Application information

In this way the PWM modulator gain results constant and equal to:

Equation 19

V_IN

G_PW0= -------- = --- = 18

V_s

1

K

The synchronization of the device with an external clock provided through the SYNCH pin

can modify the PWM modulator gain (see Section 5.1 on page 11 to understand how this

gain changes and how to keep it constant in spite of the external synchronization).

Figure 9. The error amplifier, the PWM modulator and the LC output filter

V_CC

V_S

V_REF

PWM

L

OUT

E/A

FB

COMP

ESR

G_PW0

G_LC

C_OUT

The transfer function on the LC filter is given by:

Equation 20

s

1 + -------------------------

2  f_zESR

G_LCs = ------------------------------------------------------------------------

²



s



1 + ---------------------------- + -------------------



2  Q  f_LC

2  f_LC

where:

Equation 21

1

f_LC= -----------------------------------------------------------------------

f_zESR= -------------------------------------------

2  ESR  C_OUT

ESR

2  L  C_OUT

 1 + --------------

R_OUT

Equation 22

R_OUT L  C_OUT R_OUT+ ESR

V_OUT

Q = ------------------------------------------------------------------------------------------ ,

L + C_OUT R_OUT E SR

R_OUT= --------------

I_OUT

As seen in Section 5.3 on page 14, two different kinds of network can compensate the loop.

In the two following paragraphs the guidelines to select the Type II and Type III

compensation network are illustrated.

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A7985A

6.4.1

Type III compensation network

The methodology to stabilize the loop consists in placing two zeroes to compensate the

effect of the LC double pole, thereby increasing phase margin; then to place one pole in the

origin to minimize the DC error on the regulated output voltage; finally to place other poles

far from the zero dB frequency.

If the equivalent series resistance (ESR) of the output capacitor introduces a zero with

a frequency higher than the desired bandwidth (that is: 2ESR C

< 1 / BW), the Type

OUT

III compensation network is needed. Multi-layer ceramic capacitors (MLCC) have very low

ESR (< 1 m), with very high frequency zero, so a Type III network is adopted to

compensate the loop.

In Figure 10, the Type III compensation network is shown. This network introduces two

zeroes (f , f ) and three poles (f , f , f ). They are expressed as:

Z1 Z2

P0 P1 P2

Equation 23

1

f_Z1= ------------------------------------------------ 

2  C₃ R₁+ R₃

f_Z2= -----------------------------

2  R₄ C₄

Equation 24

1

f_P2= -------------------------------------------

C₄ C₅

f_P0= 0

f_P1= -----------------------------

2  R₃ C₃

2  R₄ --------------------

C₄+ C₅

Figure 10. Type III compensation network

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A7985A

Application information

In Figure 11 the Bode diagram of the PWM and LC filter transfer function (G

· G (f))

LC

PW0

and the open loop gain (G

(f) = G

· G (f) · G

(f)) are drawn.

LOOP

PW0

LC

TYPEIII

Figure 11. Open loop gain: module Bode diagram

The guidelines for positioning the poles and the zeroes and for calculating the component

values can be summarized as follows:

1. Choose a value for R , usually between 1 k and 5 k.

1

2. Choose a gain (R /R ) in order to have the required bandwidth (BW), that means:

4

1

Equation 25

BW

R₄= ---------  K  R₁

f_LC

where K is the feed-forward constant and 1/K is equal to 18.

3. Calculate C by placing the zero at 50% of the output filter double pole frequency (f ):

4

LC

Equation 26

1

C₄= ---------------------------

  R₄ f_LC

4. Calculate C by placing the second pole at four times the system bandwidth (BW):

5

Equation 27

C₄

C₅= -------------------------------------------------------------

2  R₄ C₄ 4  BW – 1

5. Set also the first pole at four times the system bandwidth and also the second zero at

the output filter double pole:

Equation 28

R₁

1

R₃= --------------------------

4  BW

C₃= ----------------------------------------

2  R₃ 4  BW

----------------- – 1

f_LC

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Application information

A7985A

The suggested maximum system bandwidth is equal to the switching frequency divided by

3.5 (F /3.5), so lower than 100 kHz if the F is set higher than 500 kHz.

SW

For example, with V

= 5 V, V = 24 V, I = 2 A, L = 22 H, C

= 22 F, and

OUT

IN

O

OUT

ESR < 1 m, the Type III compensation network is:

Equation 29

R₁= 4.99k R₂= 680 R₃= 270 R₄= 1.1k C₃= 4.7nF C₄= 47nF C₅= 1pF

In Figure 12 the module and phase of the open loop gain is shown. The bandwidth is about

32 kHz and the phase margin is 51 °.

Figure 12. Open loop gain Bode diagram with ceramic output capacitor

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A7985A

Application information

6.4.2

Type II compensation network

If the equivalent series resistance (ESR) of the output capacitor introduces a zero with

a frequency lower than the desired bandwidth (that is: 2ESR C > 1 / BW), this zero

OUT

helps stabilize the loop. Electrolytic capacitors show not-negligible ESR (> 30 m), so with

this kind of output capacitor the Type II network combined with the zero of the ESR allows

the stabilizing of the loop.

In Figure 13 the Type II network is shown.

Figure 13. Type II compensation network

The singularities of the network are:

Equation 30

1

f_P1= -------------------------------------------

C₄ C₅

f_Z1= -----------------------------

2  R₄ C₄

f_P0= 0

2  R₄ --------------------

C₄+ C₅

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A7985A

In Figure 14 the Bode diagram of the PWM and LC filter transfer function (G

· G (f))

LC

PW0

and the open loop gain (G

(f) = G

· G (f) · G

(f)) are drawn.

LOOP

PW0

LC

TYPEII

Figure 14. Open loop gain: module Bode diagram

The guidelines for positioning the poles and the zeroes and for calculating the component

values can be summarized as follows:

1. Choose a value for R , usually between 1 k and 5 k, in order to have values of C4

1

and C5 not comparable with parasitic capacitance of the board.

2. Choose a gain (R /R ) in order to have the required bandwidth (BW), that means:

4

1

Equation 31

2

f_ESR

V_S

BW

f_ESRV_IN







R₄

=

-----------  -----------  --------  R₁



f_LC

where f

is the ESR zero:

ESR

Equation 32

1

f_ESR= -------------------------------------------

2  ESR  C_OUT

and V is the sawtooth amplitude. The voltage feed-forward keeps the ratio V /V constant.

S

IN

3. Calculate C by placing the zero one decade below the output filter double pole:

4

Equation 33

10

C₄= ------------------------------

2  R₄ f_LC

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A7985A

Application information

4. Then calculate C in order to place the second pole at four times the system bandwidth

3

(BW):

Equation 34

C₄

C₅= -------------------------------------------------------------

2  R₄ C₄ 4  BW – 1

For example, with V

= 5 V, V = 24 V, I = 2 A, L = 22 H, C

= 330 F, and

OUT

IN

O

OUT

ESR = 70 m the Type II compensation network is:

Equation 35

R₁= 1.1k R₂= 150 R₄= 4.99k C₄= 180nF C₅= 180pF

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A7985A

In Figure 15 the module and phase of the open loop gain is shown. The bandwidth is about

36 kHz and the phase margin is 53 °.

Figure 15. Open loop gain Bode diagram with electrolytic/tantalum output capacitor

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A7985A

Application information

6.5

Thermal considerations

The thermal design is important to prevent the thermal shutdown of the device if the junction

temperature goes above 150 °C. The three different sources of losses within the device are:

a) conduction losses due to the not-negligible R

equal to:

of the power switch; these are

DS(on)

Equation 36

P_ON= R_DSon I_OUT² D

where D is the duty cycle of the application and the maximum R

overtemperature is

DS(on)

220 m. Note that the duty cycle is theoretically given by the ratio between V

and V ,

OUT

IN

but actually it is quite higher to compensate the losses of the regulator. So the conduction

losses increase compared with the ideal case.

b) switching losses due to Power MOSFET turn-on and turn-off; these can be

calculated as:

Equation 37

T_RISE+ T_FALL



P_SW= V_IN I_OUT ------------------------------------------  Fsw = V_IN I_OUT T_SW F_SW

2

where T

and T

are the overlap times of the voltage across the power switch (V

)

DS

RISE

FALL

and the current flowing into it during turn-on and turn-off phases, as shown in Figure 16.

is the equivalent switching time. For this device the typical value for the equivalent

T

SW

switching time is 40 ns.

c) Quiescent current losses, calculated as:

Equation 38

P_Q= V_IN I_Q

where I is the quiescent current (I = 2.4 mA).

Q

The junction temperature T can be calculated as:

J

Equation 39

T_J= T_A+ Rth_JA P_TOT

where T is the ambient temperature and P is the sum of the power losses just seen.

A

TOT

R

is the equivalent thermal resistance junction to ambient of the device; it can be

th(JA)

calculated as the parallel of many paths of heat conduction from the junction to the ambient.

For this device the path through the exposed pad is the one conducting the largest amount

of heat. The R

measured on the demonstration board described in the following

th(JA)

paragraph is about 40 °C/W for the HSOP8 package.

DocID023128 Rev 5

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44

Application information

A7985A

Figure 16. Switching losses

6.6

Layout considerations

The PC board layout of the switching DC/DC regulator is very important to minimize the

noise injected in high impedance nodes and interference generated by the high switching

current loops.

In a step-down converter, the input loop (including the input capacitor, the Power MOSFET

and the freewheeling diode) is the most critical one. This is due to the fact that the high

value pulsed current is flowing through it. In order to minimize the EMI, this loop must be as

short as possible.

The feedback pin (FB) connection to the external resistor divider is a high impedance node,

so the interference can be minimized by placing the routing of the feedback node as far as

possible from the high current paths. To reduce the pick-up noise, the resistor divider must

be placed very close to the device.

To filter the high frequency noise, a small bypass capacitor (220 nF -1 µF) can be added as

close as possible to the input voltage pin of the device.

Thanks to the exposed pad of the device, the ground plane helps to reduce the thermal

resistance junction to ambient; so a large ground plane enhances the thermal performance

of the converter allowing high power conversion.

30/44

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A7985A

Application information

In Figure 17 a layout example is shown.

Figure 17. Layout example

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44

Application information

A7985A

6.7

Application circuit

In Figure 18 the demonstration board application circuit is shown.

Figure 18. Demonstration board application circuit

Table 9. Component list

Reference

Part number

Description

Manufacturer

C1

C2

C3

C4

C5

C6

R1

R2

R3

R4

R5

D1

UMK325BJ106MM-T

10 F, 50 V

22 F, 25 V

Taiyo Yuden

muRata

GRM32ER61E226KE15

3.3 nF, 50 V

33 nF, 50 V

100 pF, 50 V

470 nF, 50 V

4.99 k, 1%, 0.1 W 0603

1.1 k, 1%, 0.1 W 0603

330 , 1%, 0.1 W 0603

1.5 k, 1%, 0.1 W 0603

150 k1%, 0.1 W 0603

3 A DC, 40 V

STPS3L40

STMicroelectronics

Coilcraft

10 H, 30%, 3.9 A,

DCR_MAX= 35 m

L1

MSS1038-103NL

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DocID023128 Rev 5

A7985A

Application information

Figure 19. PCB layout: A7985A (component side)

Figure 20. PCB layout: A7985A (bottom side)

Figure 21. PCB layout: A7985A (front side)

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44

Application information

A7985A

Figure 22. Junction temperature vs. output

Figure 23. Junction temperature vs. output

current at V = 12 V

current at V = 24 V

IN

VQFN

HSOP

VQFN

HSOP

V_OUT=5V

V_OUT=3.3V

V_OUT=1.8V

V_OUT=5V

V_OUT=3.3V

V_OUT=1.8V

V_IN=24V

F_SW=250KHz

V_IN=12V

_SW=250KHz

T_AMB=25 C

F

T_AMB=25 C

Figure 24. Junction temperature vs. output

current at V = 5 V

Figure 25. Efficiency vs. output current

at V = 1.8 V

IN

O

85

80

75

70

65

60

55

50

45

40

Vo=1.8V

FSW=250kHz

VQFN

HSOP

V_OUT=3.3V

V_OUT=1.8V

V_OUT=1.2V

V_IN=5V

F

_SW=250KHz

T_AMB=25 C

Vin=5V

Vin=12V

Vin=24V

0.100

0.600

1.100

1.600

2.100

Io [A]

Figure 26. Efficiency vs. output current

Figure 27. Efficiency vs. output current

at V = 5 V

at V = 3.3 V

O

95

90

85

80

75

70

65

60

95

90

85

80

75

70

65

60

55

50

Vo=5.0V

FSW=250kHz

Vo=3.3V

FSW=250kHz

Vin=12V

Vin=18V

Vin=24V

Vin=5V

Vin=12V

Vin=24V

0.100

0.600

1.100

1.600

2.100

0.100

0.600

1.100

1.600

2.100

Io [A]

34/44

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A7985A

Application information

Figure 28. Load regulation

Figure 29. Line regulation

3.345

3.340

3.335

3.330

3.325

3.320

3.315

3.3500

3.3450

3.3400

3.3350

3.3300

3.3250

3.3200

Vin=5V

Io=1A

Io=2A

Vin=12V

Vin=24V

5.0

10.0

15.0

20.0

25.0

V_IN[V]

30.0

35.0

40.0

3.310

0.00

0.50

1.00

1.50

2.00

Io [A]

Figure 30. Load transient: from 0.4 A to 2 A

Figure 31. Soft-start

V_OUT

500mV/div

V_OUT

100mV/div

AC coupled

I_L

500mA/div

V_IN=24V

V

C

_OUT=3.3V

_OUT=47uF

L=10uH

_SW=520k

V_FB

200mV/div

I

_L500mA/div

F

Time base 1ms/div

Time base 100us/div

Figure 32. Short-circuit behavior at V = 12 V

Figure 33. Short-circuit behavior at V = 24 V

IN

SYNCH

5V/div

SYNCH

5V/div

OUT

5V/div

OUT

5V/div

V_OUT

1V/div

V_OUT

1V/div

I_L

1A/div

0.5A/div

Timebase 10us/div

DocID023128 Rev 5

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44

Application ideas

A7985A

7

Application ideas

7.1

Positive buck-boost

The A7985A can implement the step-up/down converter with a positive output voltage.

Figure 34 shows the schematic: one Power MOSFET and one Schottky diode are added to

the standard buck topology to provide a 12 V output voltage with input voltage from 4.5 V to

38 V.

Figure 34. Positive buck-boost regulator

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The relationship between input and output voltage is:

Equation 40

D

V_OUT= V_IN -------------

1 – D

so the duty cycle is:

Equation 41

V_OUT

D = -----------------------------

V

_OUT+ V_IN

The output voltage isn’t limited by the maximum operating voltage of the device (38 V),

because the output voltage is sensed only through the resistor divider. The external Power

MOSFET maximum drain to source voltage, must be higher than output voltage; the

maximum gate to source voltage must be higher than the input voltage (in Figure 34, if V is

IN

higher than 16 V, the gate must be protected through a Zener diode and resistor).

36/44

DocID023128 Rev 5

A7985A

Application ideas

The current flowing through the internal Power MOSFET is transferred to the load only

during the OFF time, so according to the maximum DC switch current (2.0 A), the maximum

output current for the buck boost topology can be calculated from Equation 42.

Equation 42

I_OUT

I_SW= -------------  2 A

1 – D

where I

is the average current in the embedded Power MOSFET in the ON time.

SW

To chose the right value of the inductor and to manage transient output current, which, for

a short time, can exceed the maximum output current calculated by Equation 42, also the

peak current in the Power MOSFET must be calculated. The peak current, shown in

Equation 43, must be lower than the minimum current limit (2.5 A).

Equation 43

I_OUT

r

2

I_SW,PK= -------------  1 + --  3.7A

1 – D

V_OUT

r = ------------------------------------  1 – D²

I_OUT L  F_SW

where r is defined as the ratio between the inductor current ripple and the inductor DC

current.

Therefore, in the buck boost topology the maximum output current depends on the

application conditions (firstly input and output voltage, secondly switching frequency and

inductor value).

In Figure 35 the maximum output current for the above configuration is depicted, varying the

input voltage from 4.5 V to 38 V.

The dashed line considers a more accurate estimation of the duty cycles given Equation 44,

where power losses across diodes, the external Power MOSFET, and the internal Power

MOSFET are taken into account.

DocID023128 Rev 5

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44

Application ideas

A7985A

Figure 35. Maximum output current according to max. DC switch current (2.0 A):

V = 12 V

O

Equation 44

V

_OUT+ 2  V_D

D = -------------------------------------------------------------------------------------------

_IN– V_SW– V_SWE+ V_OUT+ 2  V_D

V

where V is the voltage drop across the diodes, V

and V

across the internal and

SWE

D

SW

external Power MOSFET.

7.2

Inverting buck-boost

The A7985A device can implement the step-up/down converter with a negative output

voltage.

Figure 34 shows the schematic to regulate -5 V: no further external components are added

to the standard buck topology.

The relationship between input and output voltage is:

Equation 45

D

V_OUT= –V_IN -------------

1 – D

so the duty cycle is:

Equation 46

V_OUT

D = -----------------------------

V

_OUT– V_IN

As in the positive one, in the inverting buck-boost the current flowing through the Power

MOSFET is transferred to the load only during the OFF time. So according to the maximum

DC switch current (2.0 A), the maximum output current can be calculated from Equation 42,

where the duty cycle is given by Equation 46.

38/44

DocID023128 Rev 5

A7985A

Application ideas

Figure 36. Inverting buck-boost regulator

The GND pin of the device is connected to the output voltage so, given the output voltage,

the input voltage range is limited by the maximum voltage the device can withstand across

VCC and GND (38 V). Therefore, if the output is -5 V, the input voltage can range from 4.5 V

to 33 V.

As in the positive buck-boost, the maximum output current according to application

conditions is shown in Figure 37. The dashed line considers a more accurate estimation of

the duty cycles given by Equation 47, where power losses across diodes and the internal

Power MOSFET are taken into account.

Equation 47

V

_OUT– V_D

D = ----------------------------------------------------------------

–V_IN– V_SW+ V_OUT– V_D

Figure 37. Maximum output current according to switch max. peak current (2.0 A):

V = -5 V

O

DocID023128 Rev 5

39/44

44

Package information

A7985A

8

Package information

In order to meet environmental requirements, ST offers these devices in different grades of

®

ECOPACK packages, depending on their level of environmental compliance. ECOPACK

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK is an ST trademark.

Figure 38. HSOP8 package outline

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(ꢉ ꢉꢁꢉꢊꢃPPꢃ7\Sꢁ

$0ꢈꢈꢆꢂꢀYꢈ

40/44

DocID023128 Rev 5

A7985A

Package information

Table 10. HSOP8 package mechanical data

Dimensions (mm)

Symbol

Min.

Typ.

Max.

A

A1

A2

b

1.70

0.00

1.25

0.31

0.17

4.80

5.80

3.80

0.150

0.51

0.25

5.00

6.20

4.00

c

D

4.90

6.00

3.90

1.27

E

E1

e

h

0.25

0.40

0.00

0.50

1.27

8.00

0.10

L

k

ccc

DocID023128 Rev 5

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44

Ordering information

A7985A

9

Ordering information

Table 11. Ordering information

Package

Order code

Packaging

A7985A

HSOP8

Tube

A7985ATR

Tape and reel

42/44

DocID023128 Rev 5

A7985A

Revision history

10

Revision history

Table 12. Document revision history

Changes

Date

Revision

19-Apr-2012

1

Initial release.

Document status promoted from preliminary data to production data.

08-Oct-2012

04-Jul-2013

12-Aug-2013

2

3

4

In Section 5.6 changed temperature value from 130 to 120 °C.

Updated values for V_FBparameter in Table 4: Electrical

characteristics.

Changed V_FBparameter in Table 4: Electrical characteristics from

0.594 to 0.588.

Updated Figure 34: Positive buck-boost regulator on page 36

(replaced by a new figure).

Updated Section 8: Package information on page 40 (reversed order

of Figure 38 and Table 10, minor modifications).

17-Mar-2014

6

Updated cross-references throughout document.

Minor modifications throughout document.

DocID023128 Rev 5

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44

A7985A

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DocID023128 Rev 5


型号：	A7985A
厂家：	ST
描述：	2 A step-down switching regulator for automotive applications 开关光电二极管
文件：	总44页 (文件大小：1134K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

A7985A [STMICROELECTRONICS]

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