AIS1120SXTR [STMICROELECTRONICS]
Embedded self-test;
| 型号： | AIS1120SXTR |
| 厂家： | 
ST |
| 描述： | Embedded self-test |
| 文件： | 总58页 (文件大小：1653K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AIS1120SX
AIS2120SX
MEMS automotive acceleration sensor:
single/dual-axis with SPI interface
Datasheet - production data
Description
The AIS1120SX / AIS2120SX is a central
acceleration sensor with a single or dual axis
sensing element and an IC interface able to
provide acceleration information to a master
control unit via an SPI protocol.
The sensing element, capable of detecting the
acceleration, is manufactured using a dedicated
process developed by ST to produce inertial
sensors and actuators in silicon.
SOIC8
The IC interface is manufactured using a BCD
process that allows a high level of integration. The
device is factory trimmed to better tune the
characteristics of the sensing element with the
acceleration information to be supplied.
Features
AEC-Q100 qualified
3.3 V single supply operation
14-bit data output
The AIS1120SX / AIS2120SX has a full scale of
120 g. The acquisition chain consists of a C/V
converter, a full-differential charge amplifier, a 2
nd
order analog-to-digital converter and a digital
core, which includes filtering, compensation and
interpolation, control logic and SPI protocol
generation.
120 g full scale
Slow and fast offset cancellation
Embedded self-test
The differential capacitance of the sensor is
proportional to the proof mass displacement;
thus, by sensing the differential capacitance, the
position of the sensor is determined. Then, since
Selectable low-pass filter
SPI interface
®
ECOPACK compliant
the mass position is known, and the position is
related to the input acceleration, the input
acceleration can be easily deduced.
Extended temperature range -40 °C to +105 °C
Applications
The device is available in a plastic SOIC8
package and is guaranteed to operate over a
temperature range extending from -40 °C to
+105 °C.
Airbag systems
Vibrations, impact monitoring
Table 1. Device summary
Sensitivity Operating temperature
Order code
g-range
Package
Packing
axes
range [C]
120 g
120 g
x
-40 to +105
-40 to +105
SOIC8N
SOIC8N
Tape and reel
Tape and reel
AIS1120SXTR
AIS2120SXTR
xy
January 2017
DocID028312 Rev 3
1/58
This is information on a product in full production.
www.st.com
Contents
AIS1120SX / AIS2120SX
Contents
1
Block diagrams and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1
Block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1.1
1.1.2
1.1.3
1.1.4
1.1.5
1.1.6
1.1.7
1.1.8
1.1.9
Mechanical element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Sigma-Delta converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Filter architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Decimation filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Low-pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Signal compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Linear interpolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Signal delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Offset cancellation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.1.10 State machine and on-chip-oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.1.11 Power domain block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2
Customer accessible data arrays (registers) . . . . . . . . . . . . . . . . . . . . 17
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
REG_CTRL_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
REG_CTRL_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
REG_CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
REG_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
REG_CHID_REVID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
REG_ACC_CHX_LOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
REG_ACC_CHX_HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
REG_ACC_CHY_LOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
REG_ACC_CHY_HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.10 REG_OSC_COUNTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.11 REG_ID_SENSOR_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.12 REG_ID_VEH_MANUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.13 REG_ID_SENSOR_MANUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.14 REG_ID_LOT_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.15 REG_ID_LOT_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.16 REG_ID_LOT_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2/58
DocID028312 Rev 3
AIS1120SX / AIS2120SX
Contents
2.17 REG_ID_LOT_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.18 REG_ID_WAFER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.19 REG_ID_COOR_X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.20 REG_ID_COOR_Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.21 REG_RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.22 OFF_CHX_HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.23 OFF_CHX_LOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.24 OFF_CHY_HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.25 OFF_CHY_LOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.26 Other addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3
Power-on phase and initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.1
3.2
3.3
3.4
3.5
3.6
Initialization procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Phase1 (T1): Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Phase2 (T2): configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Phase 3 (T3): fast offset cancellation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Phase 4 (T4): test phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Phase 5 (T5): normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4
Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . 36
4.1
4.2
4.3
4.4
4.5
Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Digital blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5
Interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.1
32-bit communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.1.1
5.1.2
5.1.3
Acceleration commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Non-acceleration commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
SPI CRC polynomial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.2
5.3
5.4
32-bit SPI bit information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
DocID028312 Rev 3
3/58
58
Contents
AIS1120SX / AIS2120SX
Recommendations for operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6
7
7.1
SOIC8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4/58
DocID028312 Rev 3
AIS1120SX / AIS2120SX
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
REG_CTRL_0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
REG_CTRL_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
REG_CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
REG_STATUS_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
REG_STATUS_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
REG_STATUS_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
REG_CHID_REVID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
REG_ACC_CHX_LOW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
REG_ACC_CHX_HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
REG_ACC_CHY_LOW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
REG_ACC_CHY_HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
REG_OSC_COUNTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
REG_ID_SENSOR_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
REG_ID_VEH_MANUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
REG_ID_SENSOR_MANUF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
REG_ID_LOT_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
REG_ID_LOT_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
REG_ID_LOT_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
REG_ID_LOT_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
REG_ID_WAFER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
REG_ID_COOR_X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
REG_ID_COOR_Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
REG_RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
OFF_CHX_HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
OFF_CHX_LOW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
OFF_CHY_HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
OFF_CHY_LOW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Timing delay by block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Temperature sensor data example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Digital range and levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
400 Hz digital filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
800 Hz digital filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
1600 Hz digital filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Acceleration data example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Acceleration commands function of SDI bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Acceleration commands function of SDO bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Error codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
SDO bit examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Non-acceleration command function of SDI bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Non-acceleration commands function of SDO bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
32-bit SPI command: bits from 31 to 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
32-bit SPI command: bits from 15 to 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Bit decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
DocID028312 Rev 3
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58
List of tables
AIS1120SX / AIS2120SX
Table 49.
Table 50.
Table 51.
Table 52.
SPI timing table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Error flags and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
SOIC8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6/58
DocID028312 Rev 3
AIS1120SX / AIS2120SX
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
AIS1120SX block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
AIS2120SX block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Differential capacitive system (dual axis) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2nd order sigma-delta modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Filter architecture diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
FIR vs. 4th and 6th order Bessel filter for amplitude frequency response . . . . . . . . . . . . . 11
FIR vs. 3rd and 4th order Bessel filter for group delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
8-to-1 interpolation timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Signal delay of reading-chain blocks with 400 Hz filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 10. Signal delay of reading-chain blocks with 800 Hz filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11. Signal delay of reading-chain blocks with 1600 Hz filter. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12. Offset cancellation block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 13. Offset cancellation flag monitoring flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 14. Power domain block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 15. Detectable accelerations and pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 16. Accessible registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 17. Power-up flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 18. Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 19. Phase 2 state flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 20. Cap-loss detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 21. Phase 3 state flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 22. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 23. SPI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 24. Acceleration commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 25. Non-acceleration commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 26. SPI timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 27. Additional SPI timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 28. SOIC8 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 29. SOIC8 package marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 30. SOIC8 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
DocID028312 Rev 3
7/58
58
Block diagrams and pin description
AIS1120SX / AIS2120SX
1
Block diagrams and pin description
1.1
Block diagrams
Figure 1. AIS1120SX block diagram
Figure 2. AIS2120SX block diagram
8/58
DocID028312 Rev 3
AIS1120SX / AIS2120SX
Block diagrams and pin description
1.1.1
Mechanical element
A proprietary process is used to create a surface micromachined accelerometer. This
technology allows processing suspended silicon structures which are attached to the
substrate in few points called anchors and are free to move in the direction of the sensed
acceleration thanks to flexible springs. In order to be compatible with standard packaging
techniques, a cap is placed at wafer level on the top of the sensing element.
From an electrical point of view, the sensor can be represented as a differential capacitive
system (see below for a dual-axis element). When the acceleration is applied to the sensor,
the proof mass displaces from its nominal position, causing an unbalance in the capacitive
half-bridge. This unbalance is measured using charge integration in response to a voltage
pulse applied to the sense capacitor:
Figure 3. Differential capacitive system (dual axis)
The differential capacitive change towards acceleration can be expressed, in small
displacements approximation, as:
Where C is the at-rest capacitance, m is the inertial mass, a the acceleration, k stiffness of
0
the springs and g the distance between capacitor electrodes.
1.1.2
Sigma-Delta converter
nd
A 2 order sigma-delta modulator is used to convert the differential voltage that comes from
the charge-to-voltage converter to a pulse-density modulated (PDM) data stream. The data
stream will be further processed through on-chip digital filters.
nd
Figure 4. 2 order sigma-delta modulator
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DocID028312 Rev 3
9/58
58
Block diagrams and pin description
AIS1120SX / AIS2120SX
1.1.3
Filter architecture
Figure 5. Filter architecture diagram
The architecture of the digital filters allows selecting 3 different cut-off frequencies based on
2 bits in the register map: FIR_BW_SEL[1:0].
The cut-off frequencies are 400 Hz, 800 Hz, and 1600 Hz. For the 1600 Hz filter, the noise
level is higher and the ENOB is 10/11 bits, and not 12 bits.
The cut-off frequency has to be selected for each axis during the initialization phase. Once
the initialization phase is finished and the end of the initialization bit is set, the cut-off
frequency is locked and any attempt to change it during normal mode will generate an SPI
error.
The cut-off frequencies can be selected as described below:
FIR_BW_SEL[1:0]:
= "00" FIR with F3DB = 400 Hz is selected (default);
= "01" FIR with F3DB = 800 Hz is selected;
= "10" FIR with F3DB = 1600 Hz is selected (ENOB is 10/11bits in this mode);
= "11" FIR with F3DB = 400 Hz is selected.
1.1.4
Decimation filter
Differential delay: D=1
Number of sections: N=3
Decimation factor:
–
–
–
M = 32 if FIR_BW_SEL[1:0] = "00" (400 Hz)
M = 16 if FIR_BW_SEL[1:0] = "01" (800 Hz)
M = 8 if FIR_BW_SEL[1:0] = "10" (1600 Hz)
10/58
DocID028312 Rev 3
AIS1120SX / AIS2120SX
Block diagrams and pin description
1.1.5
Low-pass filter
H_LPF (Z) is a FIR digital filter with 26 coefficients (K = 25):
Figure 6 and Figure 7 shows the comparison between the FIR filter and an analog Bessel
filter when the cut-off frequency is 400 Hz.
th
th
Figure 6. FIR vs. 4 and 6 order Bessel filter for amplitude frequency response
rd
th
Figure 7. FIR vs. 3 and 4 order Bessel filter for group delay
DocID028312 Rev 3
11/58
58
Block diagrams and pin description
AIS1120SX / AIS2120SX
1.1.6
1.1.7
Signal compensation
On-chip EEPROM bits are used to compensate sensitivity error and offset error.
Linear interpolation
The device features an L-to-1 linear data interpolation computed from the present and the
previous samples. L depends on the cut-off frequency selected:
Interpolation factor:
–
–
–
L = 16 if FIR_BW_SEL[1:0] = "00" or “11”
L = 8 if FIR_BW_SEL[1:0] = "01"
L = 4 if FIR_BW_SEL[1:0] = "10"
The data interpolation helps reduce sample jitter. The digital result will have a latency of one
sample time before being sent to the SPI bus.
The maximum jitter will be 62.5 s/16 = 3.9 s.
Figure 8 shows an interpolation example.
Figure 8. 8-to-1 interpolation timing
12/58
DocID028312 Rev 3
AIS1120SX / AIS2120SX
Block diagrams and pin description
1.1.8
Signal delays
Figure 9. Signal delay of reading-chain blocks with 400 Hz filter
Figure 10. Signal delay of reading-chain blocks with 800 Hz filter
Figure 11. Signal delay of reading-chain blocks with 1600 Hz filter
1.1.9
Offset cancellation
The offset cancellation is performed in the last step of the digital signal processing and
includes two modes:
1. Slow offset cancellation
2. Fast offset cancellation
The digital low-pass filter with selectable bandwidth (fast, slow cancellation) is controlled by
a state machine. Fast offset cancellation is used after power-on. Slow offset cancellation, for
continuously running offset cancellation, operates in normal mode.
Offset cancellation uses a moving average filter with a fixed update limit. Fast offset
cancellation occurs after power up while EOI = 0. Slow offset cancellation occurs after EOI
is set to 1.
The Offset Cancellation Error Flag is set when the offset is outside the offset correction
range (±1020 LSB) during slow offset cancellation. A hardware error is indicated based on
this flag being set for the affected axis. The flow chart for the offset cancellation block is
shown in the following figure.
DocID028312 Rev 3
13/58
58
Block diagrams and pin description
AIS1120SX / AIS2120SX
Figure 12. Offset cancellation block diagram
Figure 13. Offset cancellation flag monitoring flow
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1.1.11
State machine and on-chip-oscillator
There is an on-chip oscillator implemented. The clock frequency is trimmed to 16.384 MHz
at room temp. This clock is used for the digital core. One 1024 KHz clock divided from this
main clock is used for the sigma-delta convertor and digital signal processing module
(DSP).
Power domain block diagram
Figure 14 shows the power domain of the device. A pre-regulator is implemented to improve
power supply sensitivity and PSRR of the device. The pre-regulator provides power to an
on-chip bandgap reference and the EEPROM.
14/58
DocID028312 Rev 3
AIS1120SX / AIS2120SX
Block diagrams and pin description
Figure 14. Power domain block diagram
Key blocks of the power section are:
1. Pre-regulator: based on a self-biased supply-thermal independent structure, which is
able to produce an internal stable voltage of 2.8 V ±15%, with a maximum output
current of 3 mA. The architecture is based on a bandgap cell, which produces a
thermal-independent reference, which is used in turn to produce the voltage pre-
regulator output; the pre-regulator is powered by VDD, and is designed to supply only
some internal low-power blocks.
2. Regulator: an on-chip 2.8 V regulator supplies internal power for the device; it should
not be used to power other devices via the VREG terminal. A bypass capacitor is
required on the VREG pin to keep the regulator stable.
3. Bandgap reference: the voltage bandgap is powered by the voltage pre-regulator and
is used as voltage reference for all other circuits including the front-end, supervision
circuits and A/D converter.
4. Charge-to-voltage converter: the C/V converter consists of a fully differential charge
integrator with a continuous time ICMFB (Input Common Mode Feedback) control loop,
discrete time ICMFB, and a Switched Capacitor OCMFB (Output Common Mode
Feedback) control loop. Furthermore the C/V converter has one 9-bit DAC in order to
trim the offset of the measurement chain and mechanical element.
5. Self-test charge pump: the self-test charge pump internally generates a voltage
higher than the 2.8 V regulated supply voltage. The charge pump is activated when the
self-test mode is enabled and provides an excitation voltage of 6.6 V. During the self-
test the voltage is applied and disconnected to the sensor according to a duty cycle
which allows simulating a well-known force on the sensor.
DocID028312 Rev 3
15/58
58
Block diagrams and pin description
AIS1120SX / AIS2120SX
1.2
Pin description
Figure 15. Detectable accelerations and pinout
C1 = 1 μF ± 10%, 10 V (ceramic, VREG capacitor)
C2 = 0.1 μF ± 10%, 10 V (ceramic, power supply decoupling capacitor)
Note:
An acceleration of the device in the "+X" or “+Y” directions results in a positive output
change, a deceleration in this direction (or acceleration to the opposite side) results in a
negative output signal.
Table 2. Pin description
Pin#
Name
Function
1
2
3
4
5
SCL
SDI
SPI clock
SPI data in
SPI data out
SPI chip select
SDO
CS
GND
Power supply return pin (ground level)
Voltage regulator output. A ceramic capacitor of 1.0 μF ± 10%
10 V must be connected to this pin, which should not be used to
power other devices.
6
VREG
This pin provides power to the device. A ceramic capacitor of
0.1 μF ± 10% 10 V must be connected to this pin.
7
8
VDD
MP
Connect to GND
16/58
DocID028312 Rev 3
2
Customer accessible data arrays (registers)
Figure 16. Accessible registers
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Customer accessible data arrays (registers)
AIS1120SX / AIS2120SX
2.1
REG_CTRL_0
Table 3. REG_CTRL_0
REG_CTRL_0 (address: 0x00)
Reset
state
Name
Bit#
R/W
Description
0
[7:1]
R
0
End of initialization: Initialization
is the time interval from reset to
Self-test end:
=”0” then device is in
Initialization Phase
= “1” then the device is in end of
initialization phase (device is in
normal mode)
Rules :
-When END_OF_BIT="1" then
writing operations of
REG_CTRL_1 and
END_OF_INIT
0
R/W
0
REG_CONFIG bits do not have
effect and generate error flags
CTRL_REG_1_WR_ERR="1"/C
ONFIG_REG_WR_ERR="1".
-Cannot write EOI='1' if there is
EE or HE error.
-Cannot write EOI='1' if device is
in +ve or -ve self-test (either
CHX or CHY).
Doing so, RE error (and
CONFIG_REG_0_WR_ERR='1')
will be produced
18/58
DocID028312 Rev 3
AIS1120SX / AIS2120SX
Customer accessible data arrays (registers)
2.2
REG_CTRL_1
Table 4. REG_CTRL_1
REG_CTRL_1 (address: 0x01)
Reset
state
Name
Bit#
R/W
Description
0
[7:3]
R
0
Self-test commands:
= "000" then device is in 0 g self-test if EOI='0';
= "001" then device starts self-test on channel X
with positive voltage;
= "010" then device starts self-test on channel X
with negative voltage;
= "011" then device is in 0 g self-test if EOI='0'
= "100" then device is in 0 g self-test if EOI='0'
= "101" then device starts self-test on channel Y
with positive voltage;
= "110" then device starts self-test on channel Y
with negative voltage;
= "111" then device is in 0 g self-test if EOI='0'
Rules :
-Cannot write if EOI='1'
-Cannot start a self-test on CHX/CHY if the
channel is not enabled
SELF_TEST_CMD
[2:0]
R/W
0
-Cannot switch from non-0g(-ve/+ve) self_test to
another non-0g self_test(-ve/+ve) without going to
0g self-test
Note:
When starting channel X self-test:
Channel X acceleration command will read
channel X self-test value
Channel Y acceleration command will read
temperature sensor value for self-test temperature
compensation algorithm.
When starting channel Y self-test:
Channel X acceleration command will read
temperature sensor value for self-test temperature
compensation algorithm.
Channel Y acceleration command will read
channel Y self-test value
DocID028312 Rev 3
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58
Customer accessible data arrays (registers)
AIS1120SX / AIS2120SX
2.3
REG_CONFIG
Table 5. REG_CONFIG
REG_CONFIG (address: 0x02)
Reset
state
Name
Bit#
R/W
Description
Channel Y FIR bandwidth selection bits:
if = "00" FIR with F3DB = 400 Hz is selected;
if = "01" FIR with F3DB = 800 Hz is selected;
if = "10" FIR with F3DB = 1600 Hz is selected
(resolution is 10/11bits in this mode);
if = "11" FIR with F3DB = 400 Hz is selected.
FIR_BW_SEL_CHY[1:0]
[7:6]
R/W
00
FIR_BW_SEL_CHY[1:0] is writable if
END_OF_INIT="0".
Writing FIR_BW_SEL_CHY[1:0] when
END_OF_INIT="1" or when Channel Y self-test is
activated, does not have effect and generates an
error:
CONFIG_REG_WR_ERR="1".
Channel X FIR bandwith selection bits:
if = "00" FIR with F3DB = 400 Hz is selected;
if = "01" FIR with F3DB = 800 Hz is selected;
if = "10" FIR with F3DB = 1600 Hz is selected
(resolution is 10/11bits in this mode);
if = "11" FIR with F3DB = 400 Hz is selected.
FIR_BW_SEL_CHX[1:0]
[5:4]
R/W
00
FIR_BW_SEL_CHX[1:0] is writable if
END_OF_INIT="0".
Writing FIR_BW_SEL_CHX[1:0] when
END_OF_INIT="1" or when Channel X self-test is
activated does not have effect and generates an
error:
CONFIG_REG_WR_ERR="1".
Offset monitor channel Y disable bit.
if = "0" then channel Y offset monitor is on;
if = "1" then channel Y offset monitor is off.
DIS_OFF_MON_CHY is writable if
END_OF_INIT="0".
DIS_OFF_MON_CHY
3
R/W
0
Writing DIS_OFF_MON_CHY when
END_OF_INIT="1" does not have effect and
generates an error:
CONFIG_REG_WR_ERR="1"
20/58
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AIS1120SX / AIS2120SX
Customer accessible data arrays (registers)
Table 5. REG_CONFIG (continued)
REG_CONFIG (address: 0x02)
Reset
state
Name
Bit#
R/W
Description
Offset monitor channel X disable bit.
= "0" then channel X offset monitor is on;
= "1" then channel X offset monitor is off.
DIS_OFF_MON_CHX is writable if
END_OF_INIT="0".
DIS_OFF_MON_CHX
2
R/W
0
Writing DIS_OFF_MON_CHX when
END_OF_INIT="1" does not have effect and
generates an error: CONFIG_REG_WR_ERR="1"
Offset cancellation channel Y disable bit.
= "0" then channel Y offset cancellation circuit is
on;
= "1" then channel Y offset cancellation circuit is
off.
DIS_OFF_CANC_CHY
1
R/W
0
DIS_OFF_CANC_CHY is writable if
END_OF_INIT="0".
Writing DIS_OFF_CANC_CHY when
END_OF_INIT="1" does not have effect and
generates an error: CONFIG_REG_WR_ERR="1"
Offset cancellation channel X disable bit.
= "0" then channel X offset cancellation circuit is
on;
= "1" then channel X offset cancellation circuit is
off.
DIS_OFF_CANC_CHX
0
R/W
0
DIS_OFF_CANC_CHX is writable if
END_OF_INIT="0".
Writing DIS_OFF_CANC_CHX when
END_OF_INIT="1" does not have effect and
generates an error: CONFIG_REG_WR_ERR="1"
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Customer accessible data arrays (registers)
AIS1120SX / AIS2120SX
2.4
REG_STATUS
Table 6. REG_STATUS_0
REG_STATUS_0 (address: 0x03)
Reset
state
Name
Bit#
[7:6]
5
R/W
Description
Status Error bits:
if = "00" device is in initialization phase (power-up,
configuration, fast offset cancellation);
if = "01" device is in normal mode (EOI = 1);
STATUS [1:0]
R
00
if = "10" device is test phase (0 g test or active self
test); EOI = 0;
if = "11" device is in initialization phase or normal
mode and some errors are detected: acceleration
data are disregarded due to errors in device.
“0”: normal mode;
“1”: test mode
TESTMODE_ENABLED
R
0
Will be set to '1' if write EOI = '1' attempt is made
with the device in +ve or -ve self-test (either CHX
or CHY).
REG_CTRL_0_WR_ERR(1)
Not used
4
3
R
R
0
0
“0” always
Loss of capacitor:
if = "0" then loss of capacitor is not detected
(correct behavior);
if = "1" then loss of capacitor is detected (wrong
behavior).
Note:
LOSS_CAP
2
R
0
1.LOSS_CAP check is done during the power-up
stage (~400 μs after POR) only.
2.Recommended VDD ramp rate >1 V/ms
3.It is recommended that LOSS_CAP flag (and all
other hardware flags) be reconfirmed with soft
POR after power up (END_OF_PWRUP='1').
="1": end of power-up sequence; ready for self-
test.
END_OF_PWRUP
RST_ACTIVE
1
0
R
R
0
0
Reset Active bit:
if = "0" then device is out of reset;
if = "1" then device has undergone a soft reset
sequence. Cleared by a read.
1. Bit not latched (cleared by any read command).
22/58
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AIS1120SX / AIS2120SX
Customer accessible data arrays (registers)
Table 7. REG_STATUS_1
REG_STATUS_1 (address: 0x04)
Reset
state
Name
Bit#
R/W
Description
SPI error:
if = "0" then SPI format data is compliant with
specifications (correct behavior);
SPI_ERR(1)
7
R
R
0
0
if = "1" then SPI format data is not complaint with
specifications (wrong behavior).
EEPROM Error: CRC error reading EEPROM.
if = "0" EEPROM reading is correct.
if = "1" EEPROM reading is wrong.
EEPROM_ERR
6
The bit can be cleared by a READ if NVM bit
ErrFlgCfg='1'. If ErrFlgCfg='0', then this bit can't
be cleared.
Not used
5:4
3
R
R
0
0
"0" always
The sensor sets this flag when the offset is outside
the offset monitoring threshold (±1020 LSB)
during slow offset cancellation for channel Y; this
also creates hardware failure. When the offset is
within the threshold, the flag will be '0' (not
latched)
OFF_CANC_CHY_ERR
The sensor sets this flag when the offset is outside
the offset monitoring threshold (±1020 LSB)
during slow offset cancellation for channel X; this
also creates hardware failure. When the offset is
within the threshold, the flag will be '0' (not
latched)
OFF_CANC_CHX_ERR
2
1
R
R
0
0
Configuration register writing operation error:
if = "0" then a writing operation is not addressed
by the SPI on REG_CONFIG register when
END_OF_INIT=1 (correct behavior);
REG_CONFIG_WR_ERR(1)
if = "1" then a writing operation is addressed by
the SPI on REG_CONFIG register when
END_OF_INIT=1 (wrong behavior).
Control register 1 writing operation error:
if = "0" then a writing operation is not addressed
by the SPI on REG_CNTR_1 register when
END_OF_INIT=1 (correct behavior);
REG_CTRL_1_WR_ERR(1)
0
R
0
if = "1" then a writing operation is addressed by
the SPI on REG_CNTR_1 register when
END_OF_INIT=1 (wrong behavior).
1. Bit not latched (cleared by any read command).
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Customer accessible data arrays (registers)
AIS1120SX / AIS2120SX
Table 8. REG_STATUS_2
REG_STATUS_2 (address: 0x05)
Reset
state
Name
Bit#
R/W
Description
if = "1" then CHY ADC saturation detected (wrong
behavior).
A2D_SAT_CHY
7
R
0
if = "1" then CHY ADC saturation detected (wrong
behavior).
A2D_SAT_CHX
Not used
6
5
R
R
0
0
Charge pump error:
if = "0" then charge pump error is not detected
(correct behavior);
CHARGE_PUMP_ERR
4
R
0
if = "1" charge pump error is detected (wrong
behavior).
VREG low-voltage detection:
if = "0" then regulated voltage VREG is over the
minimum supply voltage (correct behavior);
VREG_LOW_VOLT_DET
3
R
0
= "1" then regulated voltage VREG is under the
minimum supply voltage (wrong behavior).
This also creates hardware failure (not latched).
VREG high-voltage detection:
if = "0" then regulated voltage VREG is under the
maximum supply voltage (correct behavior);
VREG_HIGH_VOLT_DET
VDD_LOW_VOLT_DET
VDD_HIGH_VOLT_DET
2
1
0
R
R
R
0
0
0
if = "1" then regulated voltage VREG is over the
maximum supply voltage (wrong behavior).
This also creates hardware failure (not latched).
VDD low-voltage detection:
if = "0" then supply voltage VDD is over the
minimum supply voltage (correct behavior);
if = "1" then supply voltage VDD is under the
minimum supply voltage (wrong behavior).
This also creates hardware failure (not latched).
VDD high-voltage detection:
if = "0" then supply voltage VDD is under the
maximum supply voltage (correct behavior);
if = "1" then supply voltage VDD is over the
maximum supply voltage (wrong behavior).
This also creates hardware failure (not latched).
24/58
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AIS1120SX / AIS2120SX
Customer accessible data arrays (registers)
2.5
REG_CHID_REVID
Table 9. REG_CHID_REVID
REG_CHID_REVID (address: 0x06)
Reset
state
Name
Bit#
R/W
Description
Not used
Not used
7
6
R
R
0
0
= “1”: CHY reading chain enabled (copied NVM
bit)
CHY_ACTIVE
5
R
0
= “1”: CHX reading chain enabled (copied NVM
bit)
CHX_ACTIVE
Not used
4
3
R
R
0
0
Copied NVM bits 0x7C: bit 7 to bit 5
011 for A3
REVID
[2:0]
R
0
100 for A4
2.6
2.7
REG_ACC_CHX_LOW
Table 10. REG_ACC_CHX_LOW
REG_ACC_CHX_LOW (address: 0x07)
Reset
state
Name
Bit#
[7:0]
R/W
Description
REG_ACC_CHX
R
0x00
Channel X acceleration data LSBs register
REG_ACC_CHX_HIGH
Table 11. REG_ACC_CHX_HIGH
REG_ACC_CHX_HIGH (address: 0x08)
Reset
state
Name
Bit#
R/W
Description
Reading REG_ACC_CHX_LOW register sets the
bit to '1' and REG_ACC_CHX_HIGH is locked to
its corresponding LOW byte i.e
AccelDataXLatch
7
R
0
REG_ACC_CHX_LOW;
Cleared when it is read.
Not used
6
R
R
0
0
REG_ACC_CHX
[5:0]
Channel X acceleration data MSBs register
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Customer accessible data arrays (registers)
AIS1120SX / AIS2120SX
2.8
REG_ACC_CHY_LOW
Table 12. REG_ACC_CHY_LOW
REG_ACC_CHY_LOW (address: 0x09)
Reset
state
Name
Bit#
[7:0]
R/W
Description
Channel Y acceleration data LSBs register
REG_ACC_CHY
R
0x00
2.9
REG_ACC_CHY_HIGH
Table 13. REG_ACC_CHY_HIGH
REG_ACC_CHY_HIGH (address: 0x0A)
Reset
state
Name
Bit#
R/W
Description
Reading REG_ACC_CHY_LOW register sets the
bit to '1' and REG_ACC_CHY_HIGH is locked to
its corresponding LOW byte, i.e.
AccelDataYLatch
7
R
0
REG_ACC_CHY_LOW;
Cleared when it is read.
Not used
6
R
R
0
0
REG_ACC_CHY
[5:0]
Channel Y acceleration data MSBs register
2.10
REG_OSC_COUNTER
Table 14. REG_OSC_COUNTER
REG_OSC_COUNTER (address: 0x0B)
Reset
state
Name
Bit#
R/W
Description
Free run oscillator counter to verify oscillator is
running. The counter is updated every 8 kHz.
OSC_COUNTER
[7:0]
R
0x00
To verify oscillator frequency, the ECU can
compare the oscillator counter by reading the
ECU clock.
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AIS1120SX / AIS2120SX
Customer accessible data arrays (registers)
2.11
REG_ID_SENSOR_TYPE
Table 15. REG_ID_SENSOR_TYPE
REG_ID_SENSOR_TYPE (address: 0x0C)
Reset
state
Name
Bit#
R/W
Description
0x1A for single axis sensor;
0x2A for dual axis sensor.
ID_SENSOR_TYPE
[7:0]
R
0x00
2.12
REG_ID_VEH_MANUF
Table 16. REG_ID_VEH_MANUF
REG_ID_VEH_MANUF (address: 0x0D)
Reset
state
Name
Bit#
R/W
Description
Not used
[7:4]
[3:0]
R
R
0
ID_VEH_MANUF
0x00
Vehicle manufacturer ID number “0x00”
2.13
REG_ID_SENSOR_MANUF
Table 17. REG_ID_SENSOR_MANUF
REG_ID_SENSOR_MANUF (address: 0x0E)
Reset
state
Name
ID_SENSOR_MANUF
Bit#
R/W
Description
[7:0]
R
0x00
Sensor manufacturer ID number LSBs (“0x00”)
2.14
REG_ID_LOT_0
Table 18. REG_ID_LOT_0
REG_ID_LOT_0 (address: 0x0F)
Name
ID_LOT[7:0]
Bit#
R/W
Reset state
Description
[7:0]
R
0
ASIC lot ID number [7:0]
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Customer accessible data arrays (registers)
AIS1120SX / AIS2120SX
2.15
REG_ID_LOT_1
Table 19. REG_ID_LOT_1
REG_ID_LOT_1 (address: 0x10)
Name
ID_LOT[15:8]
Bit#
R/W
Reset state
Description
[7:0]
R
0
ASIC lot ID number [15:8]
2.16
REG_ID_LOT_2
Table 20. REG_ID_LOT_2
REG_ID_LOT_2 (address: 0x11)
Name
ID_LOT[23:16]
Bit#
R/W
Reset state
Description
[7:0]
R
0
ASIC lot ID number [23:16]
2.17
REG_ID_LOT_3
Table 21. REG_ID_LOT_3
REG_ID_LOT_3 (address: 0x12)
Name
Not used
ID_LOT[29:24]
Bit#
R/W
Reset state
Description
[7:6]
[5:0]
R
R
0
0
ASIC lot ID number [29:24]
2.18
REG_ID_WAFER
Table 22. REG_ID_WAFER
REG_ID_WAFER (address: 0x13)
Name
Bit#
R/W
Reset state
Description
Not used
[7:5]
R
0
0
ASIC wafer ID
number
ID_WAFER
[4:0]
R
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DocID028312 Rev 3
AIS1120SX / AIS2120SX
Customer accessible data arrays (registers)
2.19
REG_ID_COOR_X
Table 23. REG_ID_COOR_X
REG_ID_COOR_X (address: 0x14)
Name
ID_COOR_X
Bit#
R/W
Reset state
0x00
Description
[7:0]
R
Die coordinate X
2.20
REG_ID_COOR_Y
Table 24. REG_ID_COOR_Y
REG_ID_COOR_Y (address: 0x15)
Name
ID_COOR_Y
Bit#
R/W
Reset state
0x00
Description
[7:0]
R
Die coordinate Y
2.21
REG_RESET
Table 25. REG_RESET
REG_RESET (address: 0x16)
Name
Bit#
R/W
Reset state
Description
Not used
[7:3]
R
0
Software reset: device is caused to go under reset if
3 consecutive SPI write operations are executed in
the following sequence:
SOFT_RST
[1:0]
R/W
00
1. SOFT_RST[1:0]=10;
2. SOFT_RST[1:0]=01;
3. SOFT_RST[1:0]=10.
2.22
OFF_CHX_HIGH
Table 26. OFF_CHX_HIGH
OFF_CHX_HIGH (address: 0x17)
Name
OFF_CHX[10:3]
Bit#
R/W
Reset state
Description
Channel X offset correction
data MSB register
[7:0]
R
0x00
DocID028312 Rev 3
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58
Customer accessible data arrays (registers)
AIS1120SX / AIS2120SX
2.23
OFF_CHX_LOW
Table 27. OFF_CHX_LOW
OFF_CHX_LOW (address: 0x18)
Name
Bit#
R/W
Reset state
Description
Reading OFF_CHX_HIGH register sets the bit
to “1” and OFF_CHX_LOW is locked to its
corresponding HIGH byte i.e. OFF_CHX_HIGH;
OFFDataXLatch
7
R
0
Cleared when it is read.
Not used
[6:3]
[2:0]
R
R
0
0
OFF_CHX[2:0]
Channel X offset correction data LSB register
2.24
OFF_CHY_HIGH
Table 28. OFF_CHY_HIGH
OFF_CHY_HIGH (address: 0x19)
Name
OFF_CHY[10:3]
Bit#
R/W
Reset state
Description
[7:0]
R
0x00
Channel Y offset correction data MSB register
2.25
OFF_CHY_LOW
Table 29. OFF_CHY_LOW
OFF_CHY_LOW (address: 0x1A)
Name
Bit#
R/W
Reset state
Description
Reading OFF_CHY_HIGH register sets the bit
to “1” and OFF_CHY_LOW is locked to its
corresponding HIGH byte i.e.
OFFDataYLatch
7
R
0
OFF_CHY_HIGH;
Cleared when it is read.
Not used
[6:3]
[2:0]
R
R
0
0
OFF_CHY[2:0]
Channel Y offset correction data LSB register
2.26
Other addresses
0x1B: not used
0x1C: not used
0x1D: not used
0x1E: Reserved
0x1F: Reserved
30/58
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AIS1120SX / AIS2120SX
Power-on phase and initialization
3
Power-on phase and initialization
3.1
Initialization procedure
Figure 17. Power-up flowchart
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1. User initiated
DocID028312 Rev 3
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Power-on phase and initialization
AIS1120SX / AIS2120SX
3.2
Phase1 (T1): Power-up timing
The power domain block diagram is shown in section 1.1.11. Power-up timing and sequence
are shown in Figure 18. Once VDD has ramped up, VPRE follows that. After VPRE reaches
a threshold value, internal signal nPOR_VPRE is asserted. The signal resets the EEPROM
registers. Therefore, EEPROM settings are ready for bandgap and regulator output
(VREG). Then, another POR circuit will monitor the output VREG. If it reaches a target
threshold, nPOR will be asserted. nPOR is used to reset all the registers of the main digital
core.
The device waits for regulator and bandgap to be at appropriate levels (regulator >2.6 V,
bandgap >1.1 V) before it starts executing its state machine (starting with EEPROM
download). The device starts its state machine approximately 5 μs (deglitch time) after the
bandgap and regulator reach their threshold levels.
Figure 18. Power-up timing
Table 30 shows the typical timing delay for each block:
Table 30. Timing delay by block
Timing
Condition (VDD rising time of 100µs)
Delay [μs]
tpre
VPRE settles down to 90%
VREF settles down to 90%
90
tBG
250
190
250
450
195
tPOR
tREG
tEEPROM
tOSC
VREG settles down to 90%
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AIS1120SX / AIS2120SX
Power-on phase and initialization
3.3
Phase2 (T2): configuration
Once nPOR is asserted, the device will initialize the registers to the default settings and
start ASIC diagnostic procedure. If an error is detected, the corresponding error bit will be
set in DEVSTAT register. This phase is characterized by (ST1:ST0 = "00").
Figure 19. Phase 2 state flow
The diagnostic procedure in this stage includes cap-loss detection, charge pump check for
self-test, and VREG/VCC low-voltage monitoring. Cap-loss mode is initiated after EEPROM
download where the regulator is disabled 1 μs. Without a load cap the regulator voltage
would fall below the UV threshold and the device latches it as cap-loss flag.
Figure 20. Cap-loss detection
DocID028312 Rev 3
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Power-on phase and initialization
AIS1120SX / AIS2120SX
3.4
Phase 3 (T3): fast offset cancellation
After the configuration/initialization phase (t2), the device will start fast offset cancellation
which takes max. 345 ms. Also there is 6 ms window for self-test calibration. During phase 3
(t3), sensor data is still available through the SPI but the ND flag (see Section 5.1.1:
Acceleration commands) will be used and ST1:ST0 is still kept "00" if no error occurs until
phase T4.
Figure 21. Phase 3 state flow
3.5
Phase 4 (T4): test phase
After phase 3 the device is still in the programming phase. Offset is close to 0. This phase is
characterized by (ST1:ST0 = "10"). The device can be programmed to execute the active
self-test. The actuation of transducer will be controlled through SPI command.
The active self-test applies an electrostatic force to the mechanical sensor. When the self-
test mode is activated, the voltage between the rotor and stator is changed. This generates
an attractive electrostatic force and causes the rotor to move towards the stator. The
displacement of the rotor will be measured at the output of the ADC.
Note:
For the 2-axis version the self-test has to be executed sequentially.
When starting channel X self-test:
a) Channel X acceleration command will read channel X self-test value
b) Channel Y acceleration command will read temperature sensor value for self-test
temperature compensation algorithm.
When starting channel Y self-test:
a) Channel X acceleration command will read temperature sensor value for self-test
temperature compensation algorithm.
b) Channel Y acceleration command will read channel Y self-test value
The acceleration data is given in 14-bit format (bit 25-12 of SDO data frame). Its MSB (D13)
represents the sign bit and the negative value is in two's complementary format.
34/58
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AIS1120SX / AIS2120SX
Power-on phase and initialization
When configured/read as a temperature sensor value, the 14-bit output is unsigned data. Its
value could be estimated as:
ADC_out = -16 x (Temp - 25) + 7280
The following table shows a few examples of temperature sensor data.
Table 31. Temperature sensor data example
Temp. (°C)
D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
-40
25
1
0
0
0
1
1
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
0
1
1
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
105
Temperature compensation is only enabled during the active self-test phase.
3.6
Phase 5 (T5): normal operation
After the programming phase the ECU will set the End-of-Initialization (EOI) bit and the
device will start normal operation. ST1:ST0 is switched to "01".
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58
Mechanical and electrical specifications
AIS1120SX / AIS2120SX
4
Mechanical and electrical specifications
4.1
Mechanical characteristics
3.13 V V 3.47 V, -40°C T 105°C, acceleration = 0 g, over lifetime, unless
DD
OP
otherwise noted.
Table 32. Mechanical characteristics
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
FS
S0
Full-scale range(1)
Sensitivity
Offset cancellation ON
±114
±120
68
g
LSB/g
VDD = 3.3 V
T = 25°C
SE
Sensitivity Error
Frequency = 0 Hz
At time t = 0
-5
-1
+5
+1
%
Including ratiometric error
VDD = 3.6 V to PD
threshold
SRE
Sensitivity ratiometricity error
%
Sensitivity change vs
temperature
TCSo
-40°C TOP 105°C
±0.02
LSB/g/°C
SO_drift Sensitivity drift
Over lifetime
1
4
%
DNL
Differential non linearity
LSB
Including ratiometric
error, excluding noise
effects, offset cxl disabled
Off_Raw1 Zero-g level offset(2)
-680
-2
680
2
LSB
LSB
Including ratiometric
error, excluding noise
effects, offset cxl enabled
Off_Cxl1 Zero-g level offset
Off_Mon_
Offset monitor threshold
Th
Signed value
-1020
-400
1020
400
LSB
LSB
Off_Mon_
Offset monitor Headroom
HdD
NL
Non linearity of sensitivity(1)
Cross axis(1)
Best fit straight line
+2
% FS
%
CrAx
Package alignment error
-5
13.7
10.25
951
+5
Cut_Off MEMS cutoff frequency (-3 dB)
15.86
11.34
1108
18.94
12.45
1231
+105
kHz
kHz
g
F0
Gclip
Top
MEMS resonant frequency
g-cell clipping
Operating temperature range
-40
°C
1. Guaranteed by design, verified at characterization level
2. 14-bit data, equivalent to ±170 LSB on 12 bits
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AIS1120SX / AIS2120SX
Mechanical and electrical specifications
4.2
Electrical characteristics
3.13 V V 3.47 V, -40°C T 105°C, acceleration = 0 g, over lifetime, unless
DD
OP
otherwise noted.
Table 33. Electrical characteristics
Test conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
Vreg
ISS
Supply voltage
-5%
-5%
3
3.3
2.8
+5%
+5%
6
V
V
Supply current
Supply current
Single axis
mA
mA
ISD
Dual axis
4
8
Offset cancellation(1)
AVG
Averaging period
-5%
-1
1024
334
+5%
+1
ms
Offset correction value per
update
Off_CVU
LSb
Default startup phase enable
time
Time to guarantee the
internal offset is removed
Off_DSPE
317
351(2)
ms
Off_Fast Fast offset cancellation
Off_Slow Slow offset cancellation
-5%
0.8
8000
1
+5%
1.2
LSb/s
LSb/s
Self-test
VDD = 3.30 V, T = 25°C,
Frequency = 0 Hz
ST
Self-test output change
1632
LSb
%
ST_TOL Self-test tolerance
Across temp, over life time
-15
15
2
ST_TON_
Specification reached for a
400 Hz 3-pole filter
Self-test turn-on/off time
TOFF
ms
Noise
RMS
Nois_RMS Output noise
Nois_P2P Output noise
+4
LSb
LSb
peak-to-peak
+16
Angular acceleration sensitivity(3)
AAS
LOAD
Fosc
Angular acceleration sensitivity
5*10-6 g*s2/ rad
SDO pin load(4)
Oscillator frequency
Capacitive load drive
Oscillator frequency
60
pF
-5%
16.384
+5%
MHz
Power supply rejection ratio
1*Fsw, 2*Fsw, 3*Fsw,
4*Fsw, 5*Fsw, 6*Fsw
PSRR
Power supply RR
0.5
LSb/mV
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Mechanical and electrical specifications
AIS1120SX / AIS2120SX
Table 33. Electrical characteristics (continued)
Symbol
Parameter
Test conditions
Clipping
Min.
Typ.
Max.
Unit
Dig_Clip Digital output
-5%
370
120
400
+5%
430
g
Low-pass filter
Cut_off Cut-off frequency (400 Hz filter)
Hz
1. Offset cancellation can vary with oscillator frequency
2. Internal offset is removed in max. 345 ms; another 6 ms are needed for self-test calibration. During this phase, SPI will
report ND flag if acceleration command being sent.
3. Based on simulation and characterization
4. Guaranteed by design
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AIS1120SX / AIS2120SX
Mechanical and electrical specifications
4.3
Digital blocks
Table 34. Digital range and levels
Symbol
Bit
ACC_RNG Range for acceleration data
Parameter
Conditions
Min
Typ
Max Unit
14 bit
+8191 LSb
ADC resolution
-8192
Out_Hi
Out_Low
In_Hi
Logic output high (SDO pin)
Logic output low (SDO pin)
Logic input high (all inputs)
Logic input low (all inputs)
Max static current = 2 mA VDD-0.6
VDD
0.6
VDD
1
V
V
V
V
Max static current = 2 mA
0.0
2
In_Low
0.0
Input capacitance at high impedence
(SDO pin)
CIN1
2
pF
CIN2
Input capacitance at CS/SDI/SCK pin
10
50
pF
μA
μA
V
I_Pull_D
I_Pull_U
Internal pull-down current (SDI, SCK) Vin = Vcc to 0 V
10
10
27
27
Internal pull-up current (CS)
Vin = Vcc to 0 V
50
UVT_VDD Undervoltage threshold (VDD
)
2.7
2.1
2.9
2.3
3.1
2.5
UVT_VREG Undervoltage threshold (VREG)
UV_DET1 Under/overvoltage detection time
Hard_Res Hard reset threshold (VREG)
V
VDD below threshold
VREG below threshold
6
25
5
40
μs
μs
1.5
10.5
1.8
1.5
2.1
2.2
2
V
Res_t
Rec_t
Reset activation time
Reset recovery time
After SPI command
μs
Reset to first SPI
access
1
ms
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58
Mechanical and electrical specifications
AIS1120SX / AIS2120SX
Table 35. 400 Hz digital filter
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Signal delay(1)
Overall signal delay
Interpolation output
0.84
0.976
1.0
ms
Sampling rate(1)
256
kHz
1. Based on simulations
Table 36. 800 Hz digital filter
Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Signal delay(1)
Overall signal delay
Interpolation output
0.4
0.507
0.6
ms
Sampling rate(1)
256
kHz
1. Based on simulations
Table 37. 1600 Hz digital filter
Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Signal delay(1)
Overall signal delay
Interpolation output
0.19 0.273 0.32
256
ms
Sampling rate(1)
kHz
1. Based on simulations
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AIS1120SX / AIS2120SX
Mechanical and electrical specifications
4.4
Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 38. Absolute maximum ratings
Symbol
Ratings
Value
Unit
VDD
VREG
SCK,SDI
AUNP
Supply voltage
-0.3 to 7.0(1)
-03. to 3.0
-0.3 to VDD
2000
V
V
V
Mechanical shock with device unpowered
Drop shock survivability (concrete floor)
g
hDROP
1.2
m
kV
V
ESD protection HBM (low-voltage pins)
CDM
2
ESD
750
TSTG
Tj
Storage temperature range
Operating temperature range
-55 to +150
-40 to +105
°C
°C
1. Not for continued operation
This device is sensitive to mechanical shock, improper handling can cause
permanent damage to the part.
This device is sensitive to electrostatic discharge (ESD), improper handling can
cause permanent damage to the part.
4.5
Factory calibration
The IC interface is factory calibrated for sensitivity (S ) and Zero-g level (Off_Raw).
0
The trimming values are stored inside the device in a non-volatile structure. When the
device is turned on, the trimming parameters are downloaded into the registers to be
employed during normal operation which allows the device to be used without further cali-
bration.
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Interface description
AIS1120SX / AIS2120SX
5
Interface description
The AIS1120SX / AIS2120SX provides a bi-directional 3.3 V SPI interface for
communication with the MCU at a 32-bit data word size. Each transfer consists of two
frames of 32 clocks per frame.
The sensor always operates in slave mode whereas the MCU provides the master function.
The interface consists of 4 ports as shown below.
Figure 22. SPI
Serial clock (SCK): input for master clock signal. This clock determines the speed of data
transfer and all receiving and sending is done synchronous to this clock.
Chip Select (CS): CS activates the SPI interface. As long as CS is high, the IC does not
accept the clock signal or data and the output SDO is in high impedance. Whenever CS is in
a low logic state, data can be transferred from and to the microcontroller.
Serial Input (SDI): accelerometer data in is latched by the rising edge of SCL (see
Figure 23: SPI timings).
Serial Output (SDO): accelerometer data out is set by the falling edge of SCL (see
Figure 23: SPI timings).
5.1
32-bit communication protocol
The communication between slave and master is transmitted by 32-bit data word, MSB first.
An off-frame protocol is used meaning that each transfer is completed through a sequence
of 2 phases.
The answer of a given request is sent within the very next frame.
The acceleration data for the x-axis, y-axis channel will be frozen at the rising edge of CS of
the Request and submitted during the Response (see Figure 23).
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AIS1120SX / AIS2120SX
Interface description
Figure 23. SPI timings
CS is the Chip Select and it is controlled by the SPI master. It goes low at the start of the
transmission and goes back high at the end of a phase. SCL is the Serial port Clock and it is
controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI is
Serial Data Input and SDO is Serial Data Output. SDI is captured at the rising edge of SCL
and SDO is driven at the falling edge of SCL.
The SPI instructions used can be subdivided into two classes, acceleration and non-
acceleration commands.
5.1.1
Acceleration commands
These commands are used to request sensor data for channel X or Y. The acceleration data
is given in 14-bit format (bit 25-12 of SDO data frame). The MSB (D13) represents the sign
bit and the negative value is in two's complementary format.
The following table shows a few examples of full range and 0 g offset:
Table 39. Acceleration data example
Accel
[g]
D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
120.4
-120.5
0.015
-0.015
0
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
Each 32-bit frame can request one of two channels (X or Y), see definition of bits CH1:CH0.
00 x data
01 y data
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58
Interface description
AIS1120SX / AIS2120SX
The format of the acceleration commands is shown below.
Figure 24. Acceleration commands
The function of the individual bits of SDI and SDO is shown in Table 40 and Table 41.
Table 40. Acceleration commands function of SDI bits
Name
Bit position
Description
Definition
Sensor channel source for data:
00: X-data (CH1)
01: Y -data (CH2)
10: CH3
CH1:CH0
[31:30]
Channel select
11: CH4
Identifies sensor data request:
1: sensor data
SEN
29
SEN bit
0: non-sensor data
P
28
Parity bit
N/A
Odd parity bit, cover bit 31-8
Always 0
Not used
C7:C0
[27:8]
[7:0]
CRC
CRC bits for SDI
Table 41. Acceleration commands function of SDO bits
Name
Bit position
Description
Definition
Identifies sensor data request:
1: sensor data
SEN
31
SEN bit
0: non-sensor data
Sensor channel source for data:
00: X-data (CH1)
01: Y -data (CH2)
10: CH3
CH1-CH0
P
[30:29]
28
Channel select
Parity bit
11: CH4
Odd parity bit, cover bit 31-8
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AIS1120SX / AIS2120SX
Interface description
Table 41. Acceleration commands function of SDO bits (continued)
Name
Bit position
Description
Definition
Type of data:
00: Initialization
01: Normal mode
10: Self-test mode
11: Error data
ST1:ST0
[27:26]
[25:12]
Status
D13:D0
SF3-SF0
C7:C0
Data
Sensor data / self-test data (14 bit)
0000: No error
0001: EEPROM Error (EE)
0010: SPI Error (SE)
0011: Request Error (RE)
0100: Condition Not Correct (CNC)
0101: No Data available (ND)
0110: Hardware Error (HE)
1000: ADC saturation error (AS)
1111: In test mode (TE)
[11:8]
[7:0]
Status flag bits
CRC
CRC error bits for SDO
Error codes are to be interpreted as follows:
EEPROM Error (EE): any error related to internal EEPROM e.g. mismatch of internal CRC.
SPI Error (SE): any violation of SPI format e.g. incorrect number of clocks during the frame,
or parity mismatch of SDI, or CRC mismatch of SDI.
Request Error (RE): set when unexpected or invalid command is received by sensor,
locked registers are read or written during any undefined state of sensor.
Condition Not Correct (CNC): set when data for undefined channel (for single axis
sensor), CH3 or CH4 are requested.
No Data available (ND): set when data is requested during power-up sequence (cap-
loss/charge pump/fast offset cancel).
X channel Hardware Error (X_HE): Set when there is cap-loss error, charge pump error,
VDD_low, VREG_low or X offset cancel saturate (after EOI) occurs.
Y channel Hardware Error (Y_HE): Set when there is cap loss error, charge pump error,
VDD_low, VREG_low or Y offset cancel saturate (after EOI) occurs.
Test mode (TE): Set when the part is in test mode.
Priority of error codes: EE (Highest) -> SE -> RE -> CNC -> ND -> HE -> TE (lowest)
Table 42. Error codes
ST1:ST0
SF flags
11
11
11
EE = 0001 NVM CRC error
SE = 0010 frame CRC error
RE = 0011 request error (register 03, bit4 shows this error also)
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58
Interface description
AIS1120SX / AIS2120SX
Table 42. Error codes (continued)
CNC = 0100 condition not correct error
ND = 0101 no data error
11
11
11
HE = 0110 (cap loss error + charge pump error + VDD undervoltage +
VREG undervoltage + VDD overvoltage + VREG overvoltage + SLOW
offset max)
00
AS = 1000 (ADC internal > 160G)
Table 43 provides some examples of SDO bit sequence interpretation.
Table 43. SDO bit examples
31
30
29
28 27
26
[25:12]
[11:8]
[7:0]
Definition
SEN CH1 CH0
P
ST1 ST2 D11:D2/error
SF3:SF0
0101
CRC Device status
CRC INIT, self test off
CRC INIT, self test off
CRC Normal mode
CRC Normal mode
CRC Self-test mode
CRC Self-test mode
CRC Error response
CRC Error response
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
X, Init no ST
Y, Init no ST
X data
0101
0000
Y data
0000
X data
0000
Y data
0000
X data
Status flag
Status flag
Y data
Notes:
1.Once the device finishes fast offset cancellation (and self-test calibration), it automatically
enters into the programming phase (ST1:ST0 status "10") until the EOI command has been
sent. During this phase, if there is not any self-test initialization command from SPI, 0 g in
self-test phase on both channels could be read from the acceleration commands.
2.When starting channel X self-test:
a.Channel X acceleration command will read channel X self-test value
b.Channel Y acceleration command will read temperature sensor value for self-test
temperature compensation algorithm.
3.When starting channel Y self-test:
c.Channel X acceleration command will read temperature sensor value for self-test
temperature compensation algorithm.
d.Channel Y acceleration command will read channel Y self-test value
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Interface description
5.1.2
Non-acceleration commands
These commands are used to write/read control and status registers.
Figure 25. Non-acceleration commands
The function of the individual bits of SDI and SDO are shown in Table 44 and Table 45.
Table 44. Non-acceleration command function of SDI bits
Name
Bit position
Description
Definition
Operation type:
00: N/A
OP1:OP0
[31:30]
Opcode
01: Write
10: N/A
11: Read
Sensor data request type:
1: sensor data
SEN
29
SEN bit
0: non-sensor data
P
28
Parity bit
N/A
Odd parity bit, cover bit 31-8
Always 0
Not used
A4:A0
D7:D0
Not used
C7:C0
[27:26]
[25:21]
[20:13]
[12:8]
[7:0]
Address
Data
Register address for R/W operations
Data for write
N/A
Always 0
CRC
CRC bits for SDI
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58
Interface description
AIS1120SX / AIS2120SX
Table 45. Non-acceleration commands function of SDO bits
Name
Bit position
Description
Definition
Sensor data request type:
1: sensor data
SEN
31
SEN bit
0: non-sensor data
Copied from SDI request if accepted
00: N/A
01: Write
10: N/A
11: Read
OP1:OP0
[30:29]
Opcode
P
28
Parity bit
N/A
Odd parity bit, cover bit 31-8
Always 0
Not used
A4:A0
D7:D0
Not used
[27:26]
25:21
20:13
12
Address
Data
Register address for R/W operations
Read data / error code
Always 0
N/A
0000: No error
0001: EEPROM Error (EE)
0010: SPI Error (SE)
0011: Request Error (RE)
1111: In test mode (TE)
SF3:SF0
C7:C0
[11:8]
[7:0]
Status flag bits
CRC
CRC bits for SDO
Error codes are to be interpreted as follows:
EEPROM Error (EE): any error related to internal EEPROM e.g. mismatch of internal CRC.
SPI Error (SE): any violation of SPI format e.g. incorrect number of clocks during the frame,
parity mismatch of SDI, or CRC mismatch of SDI.
Request Error (RE): set when unexpected or invalid command is received by sensor,
locked registers are read or written during any undefined state of sensor.
Test mode (TE): set when the part is in test mode
Priority of error codes: EE (Highest) -> SE -> RE -> TE (lowest)
5.1.3
SPI CRC polynomial
To check the integrity of the sensor signals (SO) and commands (SI) to the sensor, an 8-bit
CRC (Cyclic Redundancy Check, Baicheva C2) is used.
8
5
3
2
The applied polynomial is: X +X +X +X +X+1 = 0x97
with:
HD = 4 for 32-bit data
Initial value = 0000 0000b
Target value = 0x00
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Interface description
5.2
32-bit SPI bit information
Table 46. 32-bit SPI command: bits from 31 to 16
Acceleration
BIT
31
30
29 28 27
26
0
25
0
24
0
23 22 21 20 19 18 17 16
SDI CH1 CH0 SEN
SDO SEN CH1 CH0
P
P
0
0
0
0
0
0
0
0
0
D1
1
ST1 ST0 D13 D12
D10 D9 D8 D7 D6 D5 D4
Non-acceleration
BIT
31
30
29 28 27
26
0
25
A4
A4
24
23 22 21 20 19 18 17 16
SDI OP1 OP0 SEN
SDO SEN OP1 OP0
P
P
0
0
A3 A2 A1 A0 D7 D6 D5 D4 D3
A3 A2 A1 A0 D7 D6 D5 D4 D3
0
Table 47. 32-bit SPI command: bits from 15 to 0
Acceleration
BIT
SDI
15 14 13
12
0
11
0
10
0
9
0
8
0
7
6
5
4
3
2
1
0
0
0
0
C7 C6 C5 C4 C3 C2 C1 C0
SDO D3 D2 D1
D0 SF3 SF2 SF1 SF0 C7 C6 C5 C4 C3 C2 C1 C0
Non-acceleration
BIT
15 14 13
12
0
11
0
10
0
9
0
8
0
7
6
5
4
3
2
1
0
SDI D2 D1 D0
SDO D2 D1 D0
C7 C6 C5 C4 C3 C2 C1 C0
0
SF3 SF2 SF1 SF0 C7 C6 C5 C4 C3 C2 C1 C0
Table 48. Bit decoding
CH[1:0]
000 X Data
OP[1:0]
N/A
SEN
ST[1:0]
SF[3:0]
Non-sensor
Sensor
Initialization
Normal mode
Selt-test mode
Error data
No error
001 Y Data
010 N/A
011 N/A
100
Write
N/A
EEPROM error
SPI error (SE)
Read
Request error (RE)
Condition not correct (CNC)
No data (ND)
101
110
Hardware error (HE)
ADC saturation (AS)
In test mode (TE)
1000
1111
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Interface description
AIS1120SX / AIS2120SX
5.3
Timing parameters
Figure 26. SPI timing parameters
Figure 27. Additional SPI timing parameters
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Interface description
Table 49. SPI timing table
No.
Parameter
SPI operating frequency
Symbol
fOP
tWSCKh
tWSCKl
tSCK
tf
Min.
-
Max.
Unit
MHz
ns
-
5
A
B
C
D
E
F
G
H
I
Clock (SCK) high time
49
95
200
5.5
5.5
10
10
-
-
Clock (SCK) low time
-
-
ns
SCK period
ns
Clock (SCK) and CS fall time
Clock (SCK) and CS rise time
Data input (MOSI) setup time
Data input (MOSI) hold time
Data output (MISO) access time
Data output (MISO) valid after SCK
Data output (MISO) disable time
Enable (SS) lead time
50
50
-
ns
tr
ns
tsu
ns
thi
-
ns
ta
60
60
100
-
ns
tv
-
ns
K
L
tdis
-
ns
tlead
tlag
10
25
1.9
10
10
ns
M
N
P
Q
Enable (SS) lag time
-
ns
Sequential transfer delay
Clock enable time
ttd
-
μs
ns
tCLE
tCLD
-
Clock disable time
-
ns
Timing reference: 0.2 Vs - 0.8 Vs (Vs = V
-D
)
VDDD GND
Explanation:
c) Q: SCK stable (low or high) before CS falling
d) P: SCK stable (low or high) after CS rising
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5.4
Error management
The device replies with an error response if one of the following errors has occurred:
Table 50. Error flags and description
Description
Flags
REG_CTRL_0_WR_ERR
LOSSCAP
‘1’: when there is a request error writing the REG_CTRL_0(Address=0x00) register
‘1’: when there a loss of cap on VREG PAD (set only during power-up)
‘1’: when power-up sequencer has finished initialization (completed charge pump test,
cap-loss test, fast offset cancel);
END_OF_PWRUP
RST_ACTIVE
‘1’: when soft reset is issued
SPI_ERR
‘1’: when SPI error occurs
EEPROM_ERR
‘1’: when EEPROM error (e.g mismatch in CRC) occurs during power-up
‘1’: when offset cancellation error for CHY occur
‘1’: when offset cancellation error for CHX occurs
‘1’:when there is a request error writing the REG_CONFIG (Address=0x012) register
‘1’: when there is a request error writing the REG_CTRL_1 (Address=0x01) register
‘1’: when A2D saturates for CHY
OFF_CANC_CHY_ERR
OFF_CANC_CHX_ERR
REG_CONFIG_WR_ERR
REG_CTRL_1_WR_ERR
A2D_SAT_CHY
A2D_SAT_CHX
‘1’: when A2D saturates for CHX
CHARGE_PUMP_ERR
VREG_LOW_ERR
VREG_HIGH_ERR
VDD_LOW_ERR
‘1’: when charge pump test fails at power-up
‘1’: when VREG falls below its LOW threshold
‘1’: when VREG goes above its HIGH threshold
‘1’: when VDD falls below its LOW threshold
VDD_HIGH_ERR
‘1’: when VDD goes above its HIGH threshold
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Recommendations for operation
6
Recommendations for operation
1. It's recommended to power up VDD first, then provide SPI logic signals. This is
recommended to avoid the potential of powering the device via the SPI pins when VDD
is not in the specified operating range.
2. Recommended VDD ramp rate > 1 V/ms
3. It is recommended that all flags be reconfirmed with soft POR after power-up.
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Package information
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7
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
7.1
SOIC8 package information
Figure 28. SOIC8 package outline
ꢆꢆꢀꢈꢆꢁꢋBꢏ
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Package information
Table 51. SOIC8 package mechanical data
Databook (mm)
Ref.
Min.
Typ.
Max.
A
A1
A2
b
1.75
0.25
0.10
1.25
0.31
0.10
4.80
5.80
3.80
0.51
0.25
5.00
6.20
4.00
c
D
4.90
6.00
3.90
1.27
E
E1
e
h
0.25
0.40
0.50
1.27
L
L1
L2
k
1.04
0.25
0
8°
ccc
0.10
Figure 29. SOIC8 package marking
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Figure 30. SOIC8 recommended footprint
ꢆꢆꢀꢈꢆꢁꢋBꢏ
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Revision history
8
Revision history
Table 52. Revision history
Date
Revision
Changes
18-Sep-2015
19-Aug-2016
1
2
Initial release
Updated Section 5.1.3: SPI CRC polynomial
Document status promoted to production data
20-Jan-2017
3
Updated SDO pin load in Table 33: Electrical characteristics
Updated tSCK and tv in Table 49: SPI timing table
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