D95NH02L [STMICROELECTRONICS]
N-channel 24V - 0.005239ohm - 80A - DPAK Ultra low gate charge STripFET TM Power MOSFET; N沟道24V - 0.005239ohm - 80A - DPAK超低栅极电荷的STripFET TM功率MOSFET
| 型号： | D95NH02L |
| 厂家： | 
ST |
| 描述： | N-channel 24V - 0.005239ohm - 80A - DPAK Ultra low gate charge STripFET TM Power MOSFET |
| 文件： | 总15页 (文件大小：464K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STD95NH02L
N-channel 24V - 0.005239Ω - 80A - DPAK
Ultra low gate charge STripFET™ Power MOSFET
General features
Type
VDSS
RDS(on)
ID
STD95NH02L
24V
<0.005Ω
80A(1)
1. Value limited by wire bonding
3
■ Conduction losses reduced
■ Switching losses reduced
■ Low threshold device
1
DPAK
Description
The device is based on the latest generation of
ST’s proprietary STripFET™ technology. An
innovative layout enables the device to also
exhibit extremely low gate charge for the most
demanding requirements in high-frequency DC-
DC converters. It’s therefore ideal for high-density
converters in Telecom and Computer
Internal schematic diagram
applications.
Applications
■ Switching application
Order codes
Part number
Marking
Package
Packaging
STD95NH02LT4
D95NH02L
DPAK
Tape & reel
August 2006
Rev 3
1/15
www.st.com
15
Contents
STD95NH02L
Contents
1
2
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
4
5
6
7
Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Packing mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2/15
STD95NH02L
Electrical ratings
1
Electrical ratings
Table 1.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
(1)
Vspike
Drain-source voltage rating
Drain-source voltage (VGS = 0)
Drain-gate voltage (RGS = 20kΩ)
Gate-source voltage
30
24
V
V
VDS
VDGR
VGS
24
V
20
V
(2)
ID
Drain current (continuous) at TC = 25°C
Drain current (continuous) at TC = 100°C
Drain current (pulsed)
80
A
(2)
ID
68
A
(3)
IDM
320
100
0.67
600
A
PTOT
Total dissipation at TC = 25°C
Derating factor
W
W/°C
mJ
(4)
EAS
Single pulse avalanche energy
Tj
Operating junction temperature
Storage temperature
-55 to 175
°C
Tstg
1. Guaranted when external Rg= 4.7Ω and Tf < Tfmax
2. Value limited by wire bonding
3. Pulse width limited by safe operating area
4. Starting Tj =25°C, Id = 40A, Vdd = 22V
Table 2.
Thermal data
Rthj-case Thermal resistance junction-case max
1.5
100
275
°C/W
°C/W
°C
Rthj-amb Thermal resistance junction-to ambient max
TJ
Maximum lead temperature for soldering purpose
3/15
Electrical characteristics
STD95NH02L
2
Electrical characteristics
(T
=25°C unless otherwise specified)
CASE
Table 3.
Symbol
On/off states
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Drain-source
V(BR)DSS
ID = 250µA, VGS =0
24
V
breakdown voltage
Zero gate voltage
V
DS = 20V
1
µA
µA
IDSS
drain current (VGS = 0)
VDS = 20V, TC = 125°C
10
Gate-body leakage
current (VDS = 0)
IGSS
VGS
=
20V
100
nA
V
VGS(th)
RDS(on)
Gate threshold voltage
VDS = VGS, ID = 250µA
1
VGS = 10V, ID = 40A
VGS = 5V, ID = 40A
0.0039 0.005
0.0055 0.009
Ω
Ω
Static drain-source on
resistance
Table 4.
Symbol
Dynamic
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Forward
transconductance
(1)
gfs
VDS = 10V, ID = 10A
30
S
Input capacitance
Output capacitance
Ciss
Coss
Crss
2070
990
90
pF
pF
pF
VDS = 15V, f = 1MHz,
VGS = 0
Reverse transfer
capacitance
td(on)
tr
td(off)
tf
Turn-on delay time
Rise time
20
110
47
ns
ns
ns
ns
VDD = 12V, ID = 40A
RG = 4.7Ω VGS = 10V
(see Figure 13)
Turn-off delay time
Fall time
20
Qg
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain charge
VDD = 12V, ID = 80A,
VGS = 5V, RG = 4.7Ω
(see Figure 14)
17
7.6
6.8
nC
nC
nC
(2)
Qoss
Output charge
VDS =19V, VGS =0V
VDS < 0V, VGS = 5V
f=1MHz Gate DC
22.6
15
nC
nC
Third-quadrant gate
chatge
(3)
Qgls
Bias =0 Test Signal
Level =20mV
RG
Gate Input Resistance
1.8
Ω
Open Drain
1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
2. Qoss.= Coss * ∆ Vin, Coss = Cgd + Cgd. See Chapter 4: Appendix A
3. Gate charge for synchronous operation
4/15
STD95NH02L
Electrical characteristics
Table 5.
Source drain diode
Parameter
Symbol
Test conditions
Min.
Typ.
Max. Unit
Source-drain current
ISD
80
A
A
Source-drain current
(pulsed)
(1)
ISDM
320
(2)
VSD
Forward on voltage
ISD = 40A, VGS = 0
1.3
V
trr
Reverse recovery time
ISD = 80A, di/dt = 100A/µs,
42
50.4
2.4
ns
nC
A
Qrr
Reverse recovery charge VDD = 20V, Tj = 150°C
IRRM
Reverse recovery current (see Figure 15)
1. Pulse width limited by safe operating area.
2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
5/15
Electrical characteristics
STD95NH02L
2.1
Electrical characteristics (curves)
Figure 1. Safe operating area
Figure 2. Thermal impedance
Figure 3. Output characterisics
Figure 4. Transfer characteristics
Figure 5. Transconductance
Figure 6. Static drain-source on resistance
6/15
STD95NH02L
Electrical characteristics
Figure 7. Gate charge vs gate-source voltage Figure 8. Capacitance variations
Figure 9. Normalized gate threshold voltage Figure 10. Normalized on resistance vs
vs temperature
temperature
Figure 11. Source-drain diode forward
characteristics
Figure 12. Normalized BV
vs temperature
DSS
7/15
Test circuit
STD95NH02L
3
Test circuit
Figure 13. Switching times test circuit for
resistive load
Figure 14. Gate charge test circuit
Figure 15. Test circuit for inductive load
switching and diode recovery times
Figure 16. Unclamped Inductive load test
circuit
Figure 17. Unclamped inductive waveform
Figure 18. Switching time waveform
8/15
STD95NH02L
Appendix A
4
Appendix A
Figure 19. Buck converter: power losses estimation
The power losses associated with the FETs in a synchronous buck converter can be
estimated using the equations shown in the table below. The formulas give a good
approximation, for the sake of performance comparison, of how different pairs of devices
affect the converter efficiency. However a very important parameter, the working
temperature, is not considered. The real device behavior is really dependent on how the
heat generated inside the devices is removed to allow for a safer working junction
temperature.
●
●
●
●
●
●
●
●
●
The low side (SW2) device requires:
Very low R to reduce conduction losses
DS(on)
Small Qgls to reduce the gate charge losses
Small Coss to reduce losses due to output capacitance
Small Qrr to reduce losses on SW1 during its turn-on
The Cgd/Cgs ratio lower than Vth/Vgg ratio especially with low drain to source
voltage to avoid the cross conduction phenomenon;
The high side (SW1) device requires:
Small Rg and Ls to allow higher gate current peak and to limit the voltage feedback on
the gate
●
●
Small Qg to have a faster commutation and to reduce gate charge losses
Low R
to reduce the conduction losses.
DS(on)
Table 6.
Power losses calculation
High side switching (SW1)
Low side switch (SW2)
Pconduction
RDS(on)SW2 *I2L *(1−δ )
RDS(on)SW1 *I2L *δ
IL
Ig
Pswitching
Zero Voltage Switching
V *(Qgsth(SW1) + Qgd(SW1) )*f *
in
9/15
Appendix A
STD95NH02L
Table 6.
Power losses calculation
High side switching (SW1)
Low side switch (SW2)
Recovery
Not applicable
Not applicable
(1)
V *Qrr(SW2) *f
in
Pdiode
Conductio
n
Vf(SW2) *IL *tdeadtime *f
Pgate(QG)
Qg(SW1) *Vgg *f
Qgls(SW2) *Vgg *f
V *Qoss(SW1) *f
V *Qoss(SW2) *f
PQoss
in
in
2
2
1. Dissipated by SW1 during turn-on
Table 7.
Paramiters meaning
Parameter
Meaning
d
Duty-cycle
Qgsth
Qgls
Post threshold gate charge
Third quadrant gate charge
On state losses
Pconduction
Pswitching
Pdiode
On-off transition losses
Conduction and reverse recovery diode losses
Gate drive losses
Pgate
PQoss
Output capacitance losses
10/15
STD95NH02L
Package mechanical data
5
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
11/15
Package mechanical data
STD95NH02L
DPAK MECHANICAL DATA
mm.
inch
TYP.
DIM.
MIN.
TYP
MAX.
MIN.
MAX.
A
A1
A2
B
2.2
0.9
2.4
1.1
0.23
0.9
5.4
0.6
0.6
6.2
0.086
0.035
0.001
0.025
0.204
0.017
0.019
0.236
0.094
0.043
0.009
0.035
0.212
0.023
0.023
0.244
0.03
0.64
5.2
b4
C
0.45
0.48
6
C2
D
D1
E
5.1
0.200
6.4
6.6
0.252
0.260
E1
e
4.7
0.185
0.090
2.28
e1
H
4.4
9.35
1
4.6
0.173
0.368
0.039
0.181
0.397
10.1
L
(L1)
L2
L4
R
2.8
0.8
0.110
0.031
0.6
0°
1
0.023
0°
0.039
8°
0.2
0.008
V2
8°
0068772-F
12/15
STD95NH02L
Packing mechanical data
6
Packing mechanical data
DPAK FOOTPRINT
All dimensions are in millimeters
TAPE AND REEL SHIPMENT
REEL MECHANICAL DATA
mm
MIN. MAX. MIN. MAX.
330 12.992
inch
DIM.
A
B
C
D
G
N
T
1.5
12.8
20.2
16.4
50
0.059
13.2 0.504 0.520
0.795
18.4 0.645 0.724
1.968
22.4
0.881
BASE QTY
BULK QTY
2500
TAPE MECHANICAL DATA
2500
mm
MIN. MAX. MIN. MAX.
6.8 0.267 0.275
10.4 10.6 0.409 0.417
12.1 0.476
inch
DIM.
A0
B0
B1
D
7
1.5
1.5
1.6 0.059 0.063
0.059
D1
E
1.65 1.85 0.065 0.073
7.4 7.6 0.291 0.299
2.55 2.75 0.100 0.108
F
K0
P0
P1
P2
R
3.9
7.9
1.9
40
4.1 0.153 0.161
8.1 0.311 0.319
2.1 0.075 0.082
1.574
W
15.7
16.3 0.618 0.641
13/15
Revision history
STD95NH02L
7
Revision history
Table 8.
Date
Revision history
Revision
Changes
13-Sep-2004
27-May-2005
09-Aug-2006
1
2
3
First release
Some values changed in Table 4: Dynamic.
New template, no content change
14/15
STD95NH02L
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