E-TDA7421N [STMICROELECTRONICS]
AM/FM, AUDIO SINGLE CHIP RECEIVER, PQFP64, TQFP-64;
| 型号： | E-TDA7421N |
| 厂家： | 
ST |
| 描述： | AM/FM, AUDIO SINGLE CHIP RECEIVER, PQFP64, TQFP-64 信息通信管理 商用集成电路 |
| 文件： | 总47页 (文件大小：332K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TDA7421N
AM/FM tuner for car radio and Hi-Fi applications
Not For New Design
Features
■ High performance front-end IC for AM/FM
receivers
■ Fully integrated high-speed PLL for optimized
RDS applications
■ FM MPX/AM audio output, 450 kHz AM IF
output for stereo AM applications
■ AM double conversion architecture
LQFP64
■ AM/FM station detector and digital IF-counter
■ Single frequency reference for both AM and
FM
■ Full electrical adjustment
2
■ i c bus programmable
The FM quality detection circuit, in conjunction
with the digital IF counter, enables the stop-
station function in “seek” mode and MPX mute
during reception. The combination of
programmable level detector and IF counter
allows reliable AM stop-station performance.
Description
The TDA7421N is a high-performance tuner
circuit which integrates AM and FM sections, PLL
frequency synthesizer and IF counter on a single
chip.
The Automatic Gain Control (AGC) operates on
different signal bandwidths in order to optimize
sensitivity and dynamic range.
Use of BiCMOS technology allows the
implementation of tuning functions with a
minimum of external components.Value spread of
external components can be fully compensated
by means of on-chip electrical adjustment
controlled by external microprocessor.
2
I C-bus controls functions such as AGC, amplifier
gains, PLL and counter settings.
Table 1.
Device summary
Order code
Package
Packing
TDA7421N
LQFP64
LQFP64
Tray
Tray
E-TDA7421N(1)
1. In ECOPACK® package see Section 8: Package information on page 45.
January 2009
Rev 2
1/47
This is information on a product still in production but not recommended for new designs.
www.st.com
1
Contents
TDA7421N
Contents
1
2
3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
3.2
3.3
3.4
3.5
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
FM section global performances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
AM section global performances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4
Function description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1
4.2
4.3
4.4
4.5
FM section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
AM section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PLL section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
FM and AM operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.5.1
4.5.2
4.5.3
4.5.4
Three state phase comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Charge pump current generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Low noise CMOS op-amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Inlock detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.6
4.7
4.8
IF counter system for AM/FM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Intermediate frequency main counter (IFMC) . . . . . . . . . . . . . . . . . . . . . 23
Up-down counter filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2
5
I C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.1
5.2
5.3
5.4
5.5
5.6
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Data transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2/47
TDA7421N
Contents
5.7
Frame examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6
Data byte specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.1
6.2
PLL data byte specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Tuner data byte specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7
8
9
Component description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3/47
List of tables
TDA7421N
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
FM section global performances. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
AM section global performances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
IF counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Address organization (PLL and IF counter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Control register function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Tuner subaddress. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PLL subaddress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Charge pump control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PLL counter 1 (LSB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PLL counter 2 (MSB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PLL reference counter 1 (LSB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PLL reference counter 2 (MSB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Lock detector and PLL mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
IF counter reference control 1 (LSB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
IF counter reference control 2 (MSB) and IF counter mode select. . . . . . . . . . . . . . . . . . . 34
IF counter control 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
IF counter control 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Address organization (Tuner AM/FM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Status (subaddress 00H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
FM stop station / FM IF AGC (subaddress 01H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
FM smeter slider\IF2 amplifier (subaddress 02H). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
AM stop station / AM AGC1 (subaddress 03H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
IFT1/IFT2 (subaddress 04H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Front-end adjustment (subaddress 05H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
FM demodulator adjustment (subaddress 06H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
FM soft mute / FM IF amplifier/fm audio mute gain (subaddress 07H). . . . . . . . . . . . . . . . 42
FM hole detector / FM detuning detector (subaddress 08H) . . . . . . . . . . . . . . . . . . . . . . . 42
Tuner testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Component description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
4/47
TDA7421N
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
AM test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
FM test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Charge pump logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
FM and AM operation (swallow mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Counter result diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Phase comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
IF counter block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2
Figure 10. I C bus timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 11. Example for addressing the PLL part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 12. Example for addressing the tuner part:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 13. LQFP64 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5/47
Block diagram
TDA7421N
1
Block diagram
Figure 1.
Block diagram
9DAU1402
A M B P F
I F R E F
A M
L I M I N +
L I M I N -
I N
A M P 2 O U T
F M I F
A M I F 2
A M P 2 I N +
F M I F
O U T -
A M M I X 2
A M P 2 I N -
F M I F
I N -
A M M I X 2
A M P 1 O U T
F M I F
M I X 2 I N +
A G C I T C
A M
A M P 1 I N +
F M I F
A M
A M P 1 I N -
F M I F
A G C I N
F M I F
V C O
M I X O U T +
M I X O U T -
6/47
TDA7421N
Pin description
2
Pin description
Figure 2.
Pin connection (top view)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
3
4
5
6
7
8
9
AM MIX1 IN -
AM MIX1 IN +
FM MIX IN -
FM MIX IN +
FM RF AGC IN
FM AGC OUT
RF GND
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
FM IF AMP2 OUT
IF1 VCC
FM LIM IN +
FM LIM IN -
IF1 GND
FM BW TC
FM MUTE DRIVE
FM SMETER AM SMETER
VCO B
FM DET ADJ
VCO E
FM SD AM SD
OSC GND
XTAL D
10
11
12
13
14
AUDIO OUT
FM QUAD+
XTAL G
FM QUAD-
IF2 VCC
AM IF2 IN
AM REF
OSC VCC
FM ANT ADJ
FM RF ADJ
PLL VCC
15
16
AM BPF
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
D98AU909
Table 2.
Pin #
Pin description
Pin name
Function
1
2
AM MIX1 IN -
AM MIX1 IN +
FM MIX1 IN -
FM MIX1 IN +
AM 1st mixer negative input (differential -)
AM 1st mixer positive input (differential +)
FM mixer negative input (differential -)
FM mixer positive input (differential +)
3
4
5
FM RF AGC IN RF AGC input
6
FM AGC OUT
RF GND
FM AGC output voltage
7
RF ground
8
VCO B
Local oscillator input to the transistor base
Local oscillator input to the transistor emitter
Oscillator ground
9
VCO E
10
11
12
13
14
OSC GND
XTAL D
Crystal oscillator MOS amplifier output
Crystal oscillator MOS amplifier input
Oscillator positive supply
XTAL G
OSC VCC
FM ANT ADJ
Tuning varicap voltage for antenna FM filter
7/47
Pin description
Table 2.
TDA7421N
Pin description (continued)
Pin name
Pin #
Function
15
16
17
18
19
20
21
22
23
24
25
26
27
FM RF ADJ
PLL VCC
LP OUT
LP IN1
Tuning varicap voltage for RF FM filter
PLL positive supply
Op Amp output to PLL loop filters
FM loop filter connection to op-amp inverting input
AM loop filter connection to op-amp inverting input
FM-HS loop filter connection to op-amp inverting input
Voltage reference to Op Amp noninverting input
PLL ground
LP IN2
LP IN3
PLL VREF
PLL GND
SLEEP
I2C bus disconnect signal
SDA
I2C bus data
SCL
I2C bus clock
DIG VDD
DIG GND
Digital positive supply
Digital ground
IFC SSTOP
AM STEREO
OUT
IF-Counter stop signal or
AM IF2 amplifier output
28 (*)
29
30
31
32
33
34
35
36
37
38
39
CLN GND
IF2 GND
“Clean” ground
IF2 ground
AM AGC2 TC
AM DET
AM 2nd AGC time constant
AM detector capacitor
AM BPF
AM IF filter
AM REF
Reference voltage of AM IF amplifier
AM IF2 amplifier input
AM IF2 in
IF2 VCC
IF2 positive supply
FM QUAD -
FM QUAD +
AUDIO OUT
FM quadrature detector tank (differential -)
FM quadrature detector tank (differential +)
FM MPX/AM Audio output
FM SD
AM SD
FM station detector output or
AM station detector output
40(1)
FM SMETER
AM SMETER
FM DET ADJ
FM S-meter output or
AM S-meter output or
FM detector adjustment output
41(1)
42
43
44
45
FM MUTE DRIVE FM mute time constant
FM BW TC
IF1 GND
FM detuning detector time constant
IF1 ground
FM LIM IN -
FM limiter negative input (differential -)
8/47
TDA7421N
Pin description
Table 2.
Pin #
Pin description (continued)
Pin name
Function
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
FM LIM IN +
IF1 VCC
FM limiter negative input (differential +)
IF1 positive supply
FM IF AMP2 OUT FM 2nd IF amplifier output
FM IF AMP2 IN - FM 2nd IF amplifier negative input (differential -)
FM IF AMP2 IN + FM 2nd IF amplifier positive input (differential +)
FM IF AMP1 OUT FM 1st IF amplifier output
FM IF AMP IN - FM 1st IF amplifier negative input (differential -)
FM IF AMP IN + FM 1st IF amplifier positive input (differential +)
AM S-METER TC AM S-meter time constant
AM MIX2 OUT AM 2nd mixer output
RF VCC
RF positive supply
AM MIX2 IN -
AM MIX2 IN +
FM IF AGC IN
MIX OUT -
AM 2nd mixer negative input (differential -)
AM 2nd mixer positive input (differential +)
FM IF AGC input
FM/AM 1st mixer negative output (differential -)
FM/AM 1st mixer positive output (differential +)
AM 1st AGC time constant
MIX OUT +
AM AGC1 TC
AM AGC1 RF
AMP
63
64
AM 1st AGC voltage output (to RF amplifier)
AM AGC1 PIN AM 1st AGC current output (to antenna attenuation diodes)
1. Pin function is user defined by software.
9/47
Electrical specifications
TDA7421N
3
Electrical specifications
3.1
Absolute maximum ratings
Table 3.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
Tamb
Tstg
Operating temperature range
-40 to 85
-55 to 150
10.2
°C
°C
V
Storage Temperature Range
VCC
VDD
Analog Supply Voltages (PLL, RF, IF1, IF2, OSC)
Digital Supply Voltage
5.5
V
3.2
Thermal data
Table 4.
Symbol
Thermal data
Parameter
Typ. Value
Unit
Rth j-amb, fa Thermal resistance junction to ambient, free air
Rth j-amb, sol Thermal Resistance Junction to ambient, soldered
68
55
°C/W
°C/W
3.3
FM section global performances
Table 5.
FM section global performances
Refer to evaluation circuit– Input 98.1 MHz, 40 kHz dev., 1 kHz mod., 60 dBmV antenna
level, mono.– MPX Output, de-enphasis 50 ms, BPF 200 Hz-15 kHz
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
Total supply current including
mixer
FM ICC
90
mA
S+N/N
THD
Signal to noise ratio
66
dB
%
Total harmonic distortion
0.3
mVRM
VO AF
US1
Audio output level
75 kHz Deviation
400
0
S
antenna level at which
S+N/N = 40 dB
Usable sensitivity (40dB)
dBμV
antenna level at which
S+N/N = 26 dB
US2
Usable sensitivity (26dB)
AGC starting point
-6
dBμV
dBμV
AGCSP
55
10/47
TDA7421N
Electrical specifications
3.4
AM section global performances
Table 6.
AM section global performances
Refer to evaluation circuit.
Input: fc = 999 kHz, f mod = 400 Hz, m = 30 %, 74 dB μV
specified.
antenna level unless otherwise
emf
Audio output + RC BPF (BPF 20 Hz - 20 kHz)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
Total supply current including
mixers
ΔMICC
80
mA
dBμV
(emf)
VIN MIN
VIN US
Maximum sensitivity
Usable sensitivity
ΔVAF = - 20 dB
13
27
dBμV
(emf)
S+N/N = 20 dB
ΔVis
AGC range
ΔVAF = -10 dB
50
54
dB
dB
S+N/N
Signal to noise ratio
VINRF = 74 dBu
fim = 22.399 MHz, antenna level
@ VΔF = -10 dB
αIMAG
αTw
Image rejection
dB
Tweet, Δ(S+N/N)
f1 = 900 kHz; f2 = 1350 kHz
1.2
0.3
1
dB
%
%
%
THD
Total harmonic distortion
m = 80 %
VINRF = 120 dBμVemf
0.3
mVRM
VAF
Audio output level
AM IF2 output level
107
105
S
VAMST
dBμV
3.5
Electrical characteristics
Table 7.
Symbol
Electrical characteristics
Parameter
Test condition
Min.
Typ.
Max.
Unit
DC parameters (Tamb = 25 °C; VCC = 8 V, Vdd = 5 V, no RF input unless otherwise specified)
PLL VCC PLL supply voltage
PLL ICC PLL supply current
DIG Vdd Digital supply voltage
7.5
4.75
7.5
10
V
AM mode
FM mode
1.6
3.0
mA
mA
V
5.25
10
AM mode
FM mode
4.6
4.0
mA
mA
V
DIG Idd
RF VCC
RF ICC
Digital supply current
RF supply voltage
RF supply current
AM mode
FM mode
27.0
13.0
mA
mA
11/47
Electrical specifications
TDA7421N
Table 7.
Symbol
Electrical characteristics (continued)
Parameter Test condition
IF1 supply voltage
Min.
Typ.
Max.
Unit
IF1 VCC
IF1 ICC
IF2 VCC
IF2 ICC
7.5
10
10
10
V
AM mode
4.0
mA
mA
V
IF1 supply current
IF2 supply voltage
IF2 supply current
FM mode
22.0
7.5
7.5
AM mode
FM mode
10.0
28.0
mA
mA
V
OSC VCC Oscillator supply voltage
OSC ICC Oscillator supply current
Voltage controlled oscillator (VCO)
AM mode
FM mode
17.0
81.0
mA
mA
Ref: FM test circuit, measure Vosc with high impedance FET probe
Vtun = 0
Europe/USA
Japan
80.9
55
98.2
65.4
fVCOmin
fVCOmax
Minimum VCO frequency
Maximum VCO frequency
MHz
MHz
Vtun = VCC
Europe/USA
Japan
123.2
79.2
128
90
f
OSC = 108.8MHz, Europe/USA
VOSC
C/N
Oscillator Amplitude
Carrier to Noise
110
85
dBμV
fOSC = 72.3MHz
Japan
1 kHz offset
dBc/Hz
Reference Oscillator
Ref: AM test circuit, measure VXTAL with high impedance FET probe
fXTAL
Reference frequency
Oscillator amplitude
10.25
108
MHz
VXTAL
dBμV
FM front-end electrical adjustments
Ref: FM test circuit, measure VANTADJ and VRFADJ referred to VPLLOUT
ANTADJ Maximum FM antenna filter
adjustment voltage offset
VPLLOUT = 2.5 V,
ANA3-0 set to 1111
21
2.8
21
25
3.6
25
27
4.4
27
%
%
%
%
MAX OFF
ANTADJ FM antenna filter adjustment
VPLLOUT = 2.5 V,
ANA3-0 set to 1001
voltage offset step
STEP OFF
RFADJ
Maximum FM RF filter
VPLLOUT = 2.5 V,
RFA3-0 set to 1111
adjustment voltage offset
MAX OFF
RFADJ
FM RF filter adjustment voltage VPLLOUT = 2.5 V,
offset step RFA3-0 set to 1001
2.8
3.6
4.4
STEP OFF
FM mixer
Ref: FM test circuit, measure input at VMIXFMIN, output at VMIXOUT
Single-ended input resistance
(pin 3, pin4)
RIN,MIX
12
Ω
dB
GMIX
Conversion gain
fIN = 98.1 MHz
21.8
108
3rd order intermodulation
distortion intercept point
fd = 98.1 MHz; fu1 = 98.2 MHz;
fu2 = 98.3 MHz;
IP3MIX
dBμV
12/47
TDA7421N
Electrical specifications
Table 7.
Symbol
Electrical characteristics (continued)
Parameter
Test condition
Min.
Typ.
Max.
Unit
CP1MIX
CAdj1
1dB compression point
fIN = 98.1 MHz
90
dBμV
Value of the minimum adjusting
capacitance step
T1A3-0 set to 1000
0.38
pF
FM AGC
Ref: FM test circuit, measure input at VFMRFAGCIN and VFMIFAGCIN, output at VFMAGCOUT
fRFAGCIN = 98.1 MHz
VRFAGCSTA Open loop RF AGC starting
Value of VFMRFAGCIN at which
80
20
dBμV
KΩ
point
RT
VFMAGCOUT = 4 V
RIN,RFAGC Input resistance
fIFAGCIN = 10.7 MHz
Value of VFMIFAGCIN at which
VFMAGCOUT = 4 V
VIFAGCTART Open loop IF AGC starting point
77
dBμV
FAGC2-0 set to 111
RIN,IFAGC Input resistance
20
10
KΩ
KΩ
R
Output resistance
OUT,FMAGC
FM IF amplifier 1
Ref: FM test circuit, measure input at VFMAMP1IN, output at VFMAMP1OUT
RIN,AMP1 Input resistance
330
330
18.5
Ω
Ω
ROUT,AMP1 Output resistance
GAMP1
Typical gain
fIN = 10.7 MHz
dB
fd = 10.7 MHz; fu1= 10.8 MHz;
fu2= 10.9 MHz;
FBH3-0 set to 0100
3rd order intermodulation
distortion intercept point
IP3AMP1
dBμV
dBμV
fIN = 10.7 MHz;
FBH3-0 set to 0100
CP1AMP1 1dB compression point
FM IF amplifier 2
Ref: FM test circuit, measure input at VFMAMP2IN, output at VFMAMP2OUT
RIN,AMP2 Input resistance
ROUT,AMP2 Output resistance
GMIN,AMP2 Minimum gain
GMAX,AMP2 Maximum gain
f = 10.7 MHz
330
330
6
Ω
Ω
f = 10.7 MHz
fIN = 10.7MHz, FBL1-0 set to 01
fIN = 10.7MHz, FBL1-0 set to 00
dB
dB
10
fd = 10.7 MHz; fu1= 10.8 MHz;
fu2= 10.9 MHz;
FBL3-0 set to 0100
3rd order intermodulation
distortion intercept point
IP3AMP2
dBμV
dBμV
fIN = 10.7 MHz;
FBL3-0 set to 0100
CP1AMP2 1dB compression point
13/47
Electrical specifications
TDA7421N
Table 7.
Symbol
Electrical characteristics (continued)
Parameter Test condition
Min.
Typ.
Max.
Unit
FM limiter, field strength meter and demodulator
Ref: FM test circuit, measure:
– Input at VFMLIMIN, fIN = 10.7 MHz
– FS meter output at VFMSMETER (FMADJ set to 0, FSL4-0 set to 00000)
– demodulator adjustment output at VFSMETER (FMADJ set to 1)
RIN,LIM
GLIM
LS
Limiter input resistance
Limiter gain
Limiting sensitivity
Smeter 1
330
90
Ω
dB
dBμv
V
23
SM1
SM2
SM3
SM4
VFMLIMIN = 40 dBμV
FMLIMIN = 60 dBμV
1.1
2.3
3.7
4.9
Smeter 2
V
V
Smeter 3
VFMLIMIN = 80 dBμV
VFMLIMIN = 100 dBμV
V
Smeter 4
V
VFMLIMIN = 70 dBμV;
FSL4-0 set to 00000
SMMin shift Smeter minimum shift voltage
SMMax shift Smeter maximum shift voltage
0.0
1.5
2
V
V
VFMLIMIN = 70 dBμV;
FSL4-0 set to 11111
mV
/
/
RMS
GDEM
Demodulator conversion gain
VFMLIMIN > LS
kHz
Demodulator adjustment
conversion gain
mV
kHz
RMS
GDEMADJ
CAdjDem
V
FMLIMIN > LS
14
50
Value of the minimum adjusting
capacitance step
DEM6-0 set to 0000001
fF
FM audio amplifier
Ref: FM test circuit, VFMLIMIN, = 95 dBμV, fIN = 10.7 MHz; measure:
– MPX output at VAUDIO, BPF 200 Hz to 15 kHz, 50 μs de-emphasis.
– muting voltage at VMUTE, DRIVE
VMUTE,DRIVE for which
VMUTE
Mute voltage
Play voltage
ΔVAF = -11.5dB;
AUM1-0 set to 11
2
V
VMUTE,DRIVE for which
VPLAY
0.3
V
ΔVAF = -1dB, AUM1-0 set to 11
Audio amplifier gain in play
conditions
GAMP,PLAY
VMUTE,DRIVE < VPLAY
9
-5
dB
dB
dB
MUTEATT
VMUTE,DRIVE > VMUTE
AUM1-0 set to 00
;
;
Minimum mute attenuation
Maximum mute attenuation
AF output level
MIN
MUTEATT
VMUTE,DRIVE > VMUTE
-12.5
400
0.3
AUM1-0 set to 11
MAX
fDEV = 75KHz, FMOD = 1 kHz,
VMUTE,DRIVE < VMUTE
VAF
mV
RMS
fDEV = 40 kHz, FMOD = 1 kHz,
VMUTE,DRIVE < VMUTE
THD
AF total harmonic distortion
%
14/47
TDA7421N
Electrical specifications
Table 7.
Symbol
Electrical characteristics (continued)
Parameter
Test condition
Min.
Typ.
Max.
Unit
fDEV = 40 kHz, FMOD = 1 kHz,
VMUTE,DRIVE < VMUTE
S+N/N
AF signal to noise ratio
80
dB
AM modulation depht 30 %,
fMOD = 1 kHz, with respect to
FM modulated signal with fDEV
= 40KHz, VMUTE,DRIVE < VMUTE
AMR
Amplitude modulation rejection
67
1
dB
AUDIOcurr Output current capability
5
mA
MUTE Rout Mute drive output resistance
KΩ
FM quality detectors
Field strength detector
Ref: FM test circuit, HDDIS and BWDIS set to 1, measure:
– Input at VFMLIMIN, fIN = 10.7 MHz, CW
– output at VMUTE,DRIVE
VFMLIMIN level at which
VMUTE,DRIVE = VMUTE, FSM3-0
set to 0000
Field strength detector
minimum threshold
FSDMIN
FSDMAX
dBμV
dBμV
VFMLIMIN level at which
VMUTE,DRIVE = VMUTE, FSM3-0
set to 1111
Field strength detector
maximum threshold
67.5
Detuning detector
Ref: FM test circuit; HDDIS and SMDIS set to 1, measure:
– Input at VFMLIMIN, CW
– output at VMUTE,DRIVE
frequency shift from 10.7 MHz
at which VMUTE,DRIVE = VPLAY
DDSTART Detuning detector starting point
23
30
kHz
kHz
frequency shift from 10.7MHz +
DDSTART at which
VMUTE,DRIVE = VMUTE,
Detuning detector minimum
DDSlope,min
muting slope
BWM2-0 set to 100, SEEK set to 0
frequency shift from 10.7 MHz +
DDSTART at which
VMUTE,DRIVE = VMUTE,
Detuning detector maximum
DDSlope,max
10
kHz
s/s
muting slope
BWM2-0 set to 001, SEEK set to 0
ratio of "reception" mode
integration time constant inside
the Detuning Detector with
respect to "seek" mode
Detuning Detector Time
DDTRC
34/6
Constant Ratio
Adjacent channel detector
Ref: FM test circuit; BWDIS and SMDIS set to 1, measure:
– Input at VFMLIMIN: desired 10.7 MHz, 95 dBμV CW; undesired 10.8 MHz CW
– output at VMUTE,DRIVE
Adjacent channel quality
ACDMAX detector maximum sensitivity
threshold
amplitude of undesired signal at
which VMUTE,DRIVE = VMUTE
,
91
dBu
HDM4-0 set to 11111
15/47
Electrical specifications
TDA7421N
Table 7.
Symbol
Electrical characteristics (continued)
Parameter
Test condition
Min.
Typ.
Max.
Unit
Adjacent channel quality
detector minimum sensitivity
threshold
amplitude of undesired signal at
ACDMIN
which VMUTE,DRIVE = VPLAY
,
94.8
dBu
HDM4-0 set to 00000
Field strength station detector
Ref: FM Test circuit; SEEK set to 1, HDDIS and BWDIS set to 1, measure:
– Input at VFMLIMIN: desired 10.7MHz, CW
– Output at VFMSD
VFMLIMIN level at which
VFMSD = 2.5V;
FSS4-0 set to 00000
Field strength station detector
minimum threshold
FSSDMIN
FSSDMAX
dBμV
dBμV
VFMLIMIN level at which
VFMSD = 2.5V;
FSS4-0 set to 11111
Field strength station detector
maximum threshold
Detuning station detector
Ref: FM test circuit; SEEK set to 1, HDDIS and SMDIS set to 1, measure:
– Input at VFMLIMIN, CW;
– Output at VFMSD
Symbol
DSD
Parameter
Test Condition
Min.
Typ.
28
Max.
Unit
KHz
Detuning Station Detector
Threshold
frequency shift from 10.7MHz at
which VFMSD = 2.5V
Adjacent channel station detector
Ref: FM test circuit; SEEK set to 1, HDDIS and SMDIS set to 1, measure:
- Input at VFMLIMIN: desired 10.7MHz, 95dBμV CW; undesired 10.8MHz CW
- output at VFMSD
amplitude of undesired signal at
Adjacent channel detector
maximum sensitivity threshold
ACSDMAX
which VFMSD = 2.5V, HDM4-0
set to 11111
92.5
94.9
dBμV
dBμV
amplitude of undesired signal at
which VFMSD = 2.5V, HDM4-0
set to 00000
Adjacent channel detector
minimum sensitivity threshold
ACSDMIN
AM mixer 1
Ref: AM test circuit, measure input at VMIX1AMIN, output at VMIXOUT
RIN,MIX1 Input resistance
1.2
7.6
KΩ
GMIX1
Conversion gain
fIN = 1 MHz
dB
3rd order intermodulation
distortion intercept point
fd = 1MHz; fu1 = 1.1MHz;
fu2 = 1.2MHz
IP3MIX1
131
110
0.38
dBμV
dBμV
pF
CP1MIX1 1dB compression point
Value of the minimum adjusting
fIN = 1MHz
CAdj1
T1A3-0 set to 1000
capacitance step
16/47
TDA7421N
Electrical specifications
Table 7.
Symbol
Electrical characteristics (continued)
Parameter Test condition
Min.
Typ.
Max.
Unit
AM wide and narrow AGC
Ref: AM test circuit; measure input at VMIX1AMIN and VMIX2AMIN, output at VAMAGC1AMP and VAMAGC1PIN
fWAGCIN = 999 kHz, AAGW1-0
Open loop wide AGC minimum
starting point
VWAGCMIN
VWAGCMAX
VNAGCMIN
VNAGCMAX
set to 11; VMIX1AMIN at which
VAMAGC1AMP = 2.5V
95
101
81
dBμV
dBμV
dBμV
dBμV
fWAGCIN = 999 kHz, AAGW1-0
set to 00; VMIX1AMIN at which
VAMAGC1AMP = 2.5V
Open loop wide AGC maximum
starting point
fNAGCIN = 10.7 MHz, AAGN1-0
set to 11; VMIX2AMIN at which
VAMAGC1AMP = 2.5V
Open loop narrow AGC
minimum starting point
fNAGCIN = 10.7 MHz, AAGN3-0
set to 00; VMIX2AMIN at which
VAMAGC1AMP = 2.5V
Open loop narrow AGC
maximum starting point
87
ROutAMAGC1 Output resistance
23.3
1.4
kΩ
Maximum antenna attenuation fWAGCIN = 999 kHz; VMIX1AMIN
IAMAGC1PIN
mA
diode current
= 120dBμV; AAGW1-0 set to 00
AM mixer 2
Ref: AM Test Circuit; measure input at VMIX2AMIN, output at VMIX2OUT (switches must be in position 2 for AGC
measurements).
RIN,MIX2 Input resistance
5
KΩ
GMIX2
Maximum conversion gain
fIN = 10.7 MHz
25
dB
3rd order intermodulation
distortion intercept point
fd = 10.7 MHz; fu1 = 10.8 MHz;
fu2 = 10.9 MHz
IP3MIX2
117
107
1.57
dBμV
dBμV
pF
CP1MIX2 1dB compression point
Value of the minimum adjusting
fIN = 10.7 MHz
CAdj2
T2A3-0 set to 0001
capacitance step
fIN = 10.7 MHz; Value of
VMIX2AMIN for which VMIX2OUT
is 1 dB compressed;
AGCMIXSP AGC2 starting point on mixer 2
48
dBμV
IF2A1-0 set to 10
fIN = 10.7 MHz:ΔVMIX2OUT for
ΔVMIX2AMIN = 1 dB;
IF2A1-0 set to 10
AGC2 intervention slope on
AGCMIXIS
mixer 2
0.1
dB/dB
fIN = 10.7 MHz; range of
VMIX2AMIN above AGCMIXSP for
which VMIX2OUT is not
AGCMIXR AGC2 range on mixer 2
50
dB
increasing linearly with a
1dB/dB slope; IF2A1-0 set to 10
AM IF2 amplifier
Ref: AM test circuit; f = 450 kHz, measure input at V
, output at V
(switches must be in position 1).
IN
IF2AMPIN
IF2AMPOUT
RIN,IF2AMP Input resistance
2
kΩ
17/47
Electrical specifications
TDA7421N
Table 7.
Symbol
Electrical characteristics (continued)
Parameter
Test condition
Min.
Typ.
Max.
Unit
VIF2AMPIN = 10 dBμV;
IF2A1-0 set to 00
GIF2AMPMIN Minimum gain
GIF2AMPMAX Maximum gain
50
dB
VIF2AMPIN = 10 dBμV;
IF2A1-0 set to 11
59
60
dB
Value of VIF2AMPIN for which
AGCAMPSP AGC2 starting point on IF2 amp VIF2AMPOUT is 1dB
compressed, IF2A1-0 set to 01
dBμV
fIN = 10.7MHzRange of
VIF2AMPIN above AGCAMPSP for
which VIF2AMPOUT is not
AGCAMPR AGC2 range on IF2 amp
33
dB
increasing linearly with a
1dB/dB slope; IF2A1-0 set to 01
fIN = 10.7MHz; ΔVIF2AMPOUT for
ΔVIF2AMPIN = 1dB;
IF2A1-0 set to 1
AGC2 intervention slope on IF2
AGCAMPIS
amp
0.1
dB/dB
s/s
Ratio of AGC2 "reception" Time
Constant and "seek" Time
Constant
AGCTCR AGC2 time constant ratio
150/5
VIF2AMPIN = 72dBmV;
AMSTEREO set to 1
IFAMST
AM IF2 output level at pin 28
106
150
dBμV
μA
IFAMSTcurr Current capability of pin 28
AMSTEREO set to 1
AM Field strength meter and field strength station detector
Ref: AM test circuit; fIN = 10.7 MHz, measure input at VMIX2AMIN, outputs at VAMSMETER and at VAMSD (switches in
position 2).
AMSM1
AMSM2
AMSM3
AM smeter 1 at VAMSMETER
AM smeter 2 at VAMSMETER
AM smeter 3 at VAMSMETER
VMIX2AMIN = 40dBμV
VMIX2AMIN = 60dBμV
VMIX2AMIN = 80dBμV
1.4
3.4
4.8
V
V
V
V
at which V
=
MIX2AMIN
AMSD
Station detector minimum
threshold
AMSDMIN
AMSDMAX
2.5V; ASS3-0 set to 0000, SEEK
set to 1
27
dBμV
dBμV
V
at which V
=
MIX2AMIN
AMSD
Station detector maximum
threshold
2.5V; ASS3-0 set to 1111, SEEK
set to 1
IF counter output
Ref: AM & FM test circuit, measure at pin 28
VFMLIMIN at which Vpin 28 =
2.5V, SEEK set to 1, EW2-0 set
to 101, IFS2-0 set to 010
IFCFM
IFCAM
FM IFC sensitivity
AM IFC sensitivity
34
dBμV
VIF2AMPIN at which Vpin 28 =
2.5V, SEEK set to 1, EW2-0 set
to 011, IF2-0 set to 100, AMFM
STBY1-0 set to 10
29
dBμV
μA
IFCcurrent IFC current capability
150
18/47
TDA7421N
Electrical specifications
Table 7.
Symbol
Electrical characteristics (continued)
Parameter Test condition
Min.
Typ.
Max.
Unit
SD output impedance
Measure output at VFMSD
SDIMP,ON SD output impedance
SDDIS set to 0
700
W
SDIMP,TS SD output impedance (Tri-state) SDDIS set to 1
7
MΩ
Loop filter input/output
(LP_IN1, LP_IN2, LP_IN3, LP_OUT)
-IIN
IIN
Input leakage current
Input leakage current
Output voltage low
Output voltage high
Output current sink
Output current source
VIN = GND; PDout = Tristate
VIN = VDD; PDout = Tristate
IIN = -0.2 mA; VCC = 8.5 V
IOUT = 0.2 mA; VCC = 8. 5V
VPLL = 8.5 V;
-2
-2
0
0
2
2
μA
μA
V
VOL
VOH
IOUT
IOUT
0.5
8
V
10
10
mA
mA
Vout = 0.5 to 8 V
I2C bus Interface
fSCL SCL clock frequency
tAA
100
300
500
kHz
ns
SCl low to SDA data valid
Time the bus must be free for
the new transmission
tbuf
4.7
μs
tHD-STA
tLOW
tHIGH
tSU-SDA
tHD-DAT
tSU-DAT
tR
Start condition hold time
Clock low period
4.0
4.7
4.0
4.7
0
μs
μs
μs
μs
μs
ns
μs
μs
μs
ns
V
Clock high period
Start condition setup time
Data input hold time
Date input setup time
SDA & SCL rise time
SDA & SCL Full Time
Stop condition setup time
DATA out time
250
tF
tSU-STO
tDH
4.7
300
VIL
Input low voltage
1
VIH
Input high voltage
3
V
19/47
Electrical specifications
TDA7421N
Figure 3.
AM test circuit
T3
VMiXOUT
VCC
2
1
330
2K
VMiX2AMIN
T2
VCC
64
63
61
60 58
57 56
55
54
AGC
W & N
AMSMETER
1
2
2
1
VMIX1AMIN
35
34
VIF2AMPIN
2K
15pF
VXTAL
11
-
+
1M
12
AGC2
DET
VIF2AMPOUT
15pF
33
40
VAMSD
41
31
32
VAMSMETER
D98AU910
Figure 4.
FM test circuit
VMIXOUT
330
VFMAMP1OUT
VFMAMP2OUT
VFMIFAGCIN
T2
VCC
10nF
330
10nF
10nF
330
VTun
10nF
10nF
10nF
10nF
T1
3
4
61
60
59
53
52
51
50
49
48
VMiXFMIN
330
330
330
50
330
-
-
+
+
10nF
VTun
330K
VCC
46
45
VFMLIMIN
5K
V1
10nF
330
8
9
22pF
15pF
68pF
L2
5
6
VFMRFAGCIN
FM AGC
AUDIO
38
10nF
DEMOD
VFMAGCOUT
L6
10nF
37
14
15
16
40
41
VSMSHIFT
39
VAUDIO
42
31
VAMTADJ VRFADJ VPLLOUT VFMSD
VMUTEDRIVE
10nF
VSMFLT
100K
D00AU1196
20/47
TDA7421N
Function description
4
Function description
4.1
FM section
Featuring a single conversion configuration, it comprises a multi-stage IF limiter whose gain
2
is I C controlled and a quadrature demodulator with detuning and adjacent channel
detectors. Signal meter and stop station functions are also supported
4.2
4.3
AM section
AM signal is converted by means of UP-DOWN configuration (IF1 = 10.7 MHz, IF2 =
450 kHz) and MW/LW bands are covered.
PLL section
Three operating modes are available:
Table 8.
Operating modes
PM0
PM1
Operating mode
0
1
0
1
0
0
1
1
Standby
AM
not used
FM
They are user programmable with the mode PM registers.
4.4
4.5
Standby mode
It stops all functions. This allows low current consumption without loss of information in all
registers. The pin LP-OUT is forced to 0V in power on. All data registers are set to FE
(11111110). The oscillator does not run in stand-by mode.
FM and AM operation
The FM or AM signal applies to a 32/33 prescaler, which is controlled by a 5 bit counter (A).
The 5 bit register (PC0 to PC4) controls this divider.
The output of the prescaler connects to a 11 bit divider (B). The 11 bit register (PC5 to
PC15) controls the divider 'B'.
4.5.1
Three state phase comparator
The phase comparator generates a phase error signal according to phase difference
between fSYN and fREF. This phase error signal drives the charge pump current generator.
21/47
Function description
TDA7421N
4.5.2
Charge pump current generator
This stage generates signed pulses of current. The phase error signal decides the duration
and polarity of those pulses.The current absolute values are programmable by A0, A1, A2
registers for high current and B0, B1 registers for low current.
4.5.3
Low noise CMOS op-amp
An internal voltage divider at pin VREF connects the positive input of the low noise Op-
Amp.The charge pump output connects the negative input. This internal amplifier in
cooperation with external components can provide an active filter. The negative input is
switchable to three input pins (LPIN 1, LPIN 2 and LPIN 3), to increase the flexibility in
application.This feature allows two separate active filters for different applications.A logical
"1" in the LPIN 1/2 register activates pin LPIN 1, otherwise pin LPIN 2 is active. While the
high current mode is activated LPIN 3 is switched on.
4.5.4
Inlock detector
The charge pump is switched in low current mode as the truth table and the related figure
shows.
Table 9.
Truth table
Lock (by inlock
detector)
Curr. high
Lock ENA
Charge pump current
0
1
1
1
1
X
1
1
0
0
X
1
0
1
0
low current
low current
high current
high current
high current
The charge pump is forced in low current mode when a phase difference of 10-40 µs is
reached.
A phase difference larger than the programmed values will switch the charge pump
immediately in the high current mode.
Few programmable delays are available for inlock detection.
4.6
IF counter system for AM/FM
The IF counter mode is controlled by IFCM register:
Table 10. IF counter mode
IFCM1
IFCM0
Function
0
0
1
1
0
1
0
1
Not used
FM mode
AM mode
Not used
22/47
TDA7421N
Function description
A sample timer to generate the gate signal for the main counter is built with a 14 bit
programmable counter to have the possibility to use any frequency. In FM mode a 6.25 KHz,
in AM mode a 1KHz signal is generated. This counter is followed by an asynchronous
divider to generate several sampling times.
Table 11. Address organization (PLL and IF counter)
MSB
LSB
Bit 0
Function
Subadd
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PLL CHARGE PUMP
LL COUNTER
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
LPIN1/2 CURRH
B1
PC5
PC13
RC5
RC13
D3
B0
PC4
PC12
RC4
RC12
D2
A3
PC3
PC11
RC3
RC11
D1
A2
PC2
A1
A0
PC7
PC15
RC7
PC6
PC14
RC6
RC14
-
PC1
PC9
RC1
RC9
PM1
IRC1
IRC9
EW1
CF1
PC0
PC8
RC0
RC8
PM0
IRC0
IRC8
EW0
CF0
PLL COUNTER
PC10
RC2
RC10
D0
LL REF COUNTER
LL REF COUNTER
LL LOCK DETECT
FC REF COUNTER
FC REF COUNTER
FC CONTROL
RC15
LDENA
IRC7
IRC6
IRC5
IRC4
IRC12
-
IRC3
IRC11
-
IRC2
IRC10
EW2
CF2
IFCM1 IFCM0 IRC13
IFENA
IFS2
-
-
C CONTROL
IFS1
IFS0
CF4
CF3
4.7
Intermediate frequency main counter (IFMC)
This counter is a 13-21 bit synchronous autoreload down-counter. Four bits are
programmable to have the possibility for an adjust to the frequency of the IF filter.The
counter length is automatically adjusted to the chosen sampling time and the counter mode.
At the start the counter will be loaded with a defined value which is an equivalent to the
divider value (tsample fIF).If a correct frequency is applied to the IF counter frequency
inputs IF-AM and IF-FM, at the end of the sampling time the main counter is changing its
state from 0 to 1FFFFFH.This is detected by a control logic. The frequency range inside
which a successful count results is detected is adjustable setting bits EW 0, 1, 2.
4.8
Up-down counter filter
The information coming from the IF main counter control logic is shifted into a 5 bit up down
counter circuit clocked by the sampling time signal. At the start (rising edge of the IFENA
signal) the counter is set to 10H and the SSTOP signal is forced to "1".Only when the
counter reaches the value 10H - step, SSTOP goes to "0".SSTOP will be "1" again, if the
counter reaches the value 10h + step.
23/47
Function description
Figure 5.
TDA7421N
Charge pump logic
CURR HIGH
CHARGE PUMP
CURRENT
LOCKENA
LOCK
D96AU548
Figure 6.
FM and AM operation (swallow mode)
I2C bus
REGISTER
R0 ...R15
REF OSC IN
fosc
fref
PD
DIVIDER
: R
fsyn
I2C bus
REGISTER
PC0 ...PC4
I2C bus
COUNTER
A
AM IN
FM IN
REGISTER
PC5 ... P15
(O/I)
PRESCALER
32/33
DIVIDER
: B
D96AU545
ttim = (IFRC + 1) / fosc
tcnt = (CF + 1697) / fIF FM mode
tcnt = (CF + 44) / fIF AM mode
Counter result succeeded:
ttim > tcnt - terr and
ttim > tcnt + terr
Counter result failed:
ttim< tcnt + terr or
ttim > tcnt - terr
where:
ttim = IF time cycle time
tcnt = IF counter cycle time
terr = discrimination window (controlled by the EW registers)
24/47
TDA7421N
Function description
Figure 7.
Counter result diagram
succeeded
t
-t
t
+t
t
tim
cnt ERR
cnt ERR
failed
failed
D96AU551
The precision of the measurements is adjustable by controlling the discrimination window.
This is adjustable by programming the control registers EW0...EW2.
The measurement time per cycle is adjustable by setting the register IFS0 - IFS2.
The center frequency of the discrimination window is adjustable by the control register
"CF0" to "CF4". The available values are reported in databyte specification
25/47
2
I C bus interface
TDA7421N
2
5
I C bus interface
5.1
General description
2
The TDA7421N supports the I C bus protocol. This protocol defines the devices sending
data into the bus as transmitter and the receiving device as the receiver.
The device that controls the transfer is a master and the device being controlled is the slave.
The master will always initiates data transfer and provide the clock to transmit or receive
operations.
5.2
5.3
Data transition
Data transition on the SDA line must only occur when the clock SCL is low. SDA transitions
while SCL is high will be interpreted as START or STOP condition.
Start condition
A start condition is defined by a HIGH to LOW transition of the SDA line while SCL is at a
stable HIGH level. This START condition must precede any command and initiate a data
transfer onto the bus.The TDA7421N continuously monitors the SDA and SCL lines for a
valid START and will not response to any command if this condition has not been met.
Stop condition
A STOP condition is defined by a LOW to HIGH transition of the SDA while the SCL line is at
a stable HIGH level. This condition terminate the communication between the devices and
force's the bus interface of the TDA7421N into the initial condition.
Figure 8.
Phase comparator
26/47
2
TDA7421N
I C bus interface
5.4
Acknowledge
Indicates a successful data transfer. The transmitter will release the bus after sending 8 bit
of data. During the 9th clock cycle the receiver will pull the SDA line to LOW level to indicate
it has received the eight bits of data correctly.
5.5
5.6
Data transfer
During data transfer the TDA7421N samples the SDA line on the leading edge of the SCL
clock, Therefore, for proper device operation the SDA line must be stable during the SCL
LOW to HIGH transition.
Device addressing
To start the communication between two devices, the bus master must initiate a start
instruction sequence, followed by an eight bit word corresponding to the address of the
device it is addressing. The most significant 6 bits of the slave address identify the device
type.
The TDA7421N device code is fixed as "110001".
The next significant bit is used either to address the tuner section (1) or the PLL section (0)
of the chip.
Following a START condition the master sends slave address word; the TDA7421N will
"acknowledge" after this first transmission and wait for a second word (the word address
field).This 8 bit address field provides an access to any of the 8 internal addresses. Upon
receipt of the word address the TDA7421N slave device will respond with an "acknowledge".
At this time, all the following words transmits to the TDA7421N will be considered as
data.The internal address will be automatically incremented. After each word receipt the
TDA7421N will answer with an "acknowledge".
The interface protocol comprises:
●
●
●
●
●
a subaddress byte
a sequence of data (N-bytes + acknowledge)
a stop condition (P)
a start condition (S)
a chip address byte
Table 12. Control register function
REGISTER NAME
FUNCTION
PC
RC
Programmable counter for VCO frequency
Reference counter PLL
Reference counter IF
IRC
IFCM
EW
IF Counter Mode
Frequency error window
Enable IF counter
IFENA
27/47
2
I C bus interface
TDA7421N
Table 12. Control register function (continued)
REGISTER NAME
FUNCTION
CF
IFS
Center frequency IF counter
Sampling time IF counter
PM
Standby, FM, AM, AM swallow mode (PLL mode)
Programmable delay for lock detector
Loop filter input select
D
LPIN1/2
A
Charge pump high current
Charge pump low current
B
LDENA
CURRH
Lock detector enable
Set current high
Figure 9.
IF counter block diagram
IFENA
EW-REGISTER
IF-AM
11-21 BIT COUNTER
ZD
CF-REGISTER
UP/DOWN COUNTER
IF-FM
OSC
14 BIT COUNTER
IFC-REGISTER
3 BIT COUNTER
IFS-REGISTER
D97AU809
2
Figure 10. I C bus timing diagram
t
t
t
t
R
HIGH
R
LOW
SCL
t
t
SU-STA
HD-DAT
t
SUBTOP
t
SD-DAT
t
HD-STA
SDA IN
t
t
t
txt
AA
DH
SDA OUT
D95AU378
28/47
2
TDA7421N
I C bus interface
5.7
Frame examples
Figure 11. Example for addressing the PLL part
CHIP ADDRESS
SUBADDRESS
DATA 1 to DATA n
MSB
1
LSB
0
MSB
ACK T2 T1 T0
LSB
MSB
LSB
S
1
0
0
0
1
0
I
A3 A2 A1 A0 ACK
ACK
P
D96AU549
Figure 12. Example for addressing the tuner part:
CHIP ADDRESS
SUBADDRESS
DATA 1 to DATA n
MSB
1
LSB
0
MSB
0
LSB
A3 A2 A1 A0 ACK
MSB
LSB
S
1
0
0
0
1
1
ACK
0
0
I
ACK
P
D96AU550
ACK:
S:
Acknowledge
Start
P:
Stop
I:
Page mode
T2, T1, T0:
Used in test mode (for PLL only, for TUNER addressing they must be 0)
A3, A2, A1, A0: Mode selection
Table 13. Tuner subaddress
MSB
LSB
A0
Function
X
X
X
I
A3
A2
A1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Status
FM stop station/FM IF AGC
FM smeter slider/ AM IF2 AMP
AM AGC1/AM stop station
IFT1/IFT2
Front-end adjustment
FM demod. adjustment
FM audio mute gain/FM IF buffers/FM soft
mute
0
1
1
1
1
1
0
0
0
0
0
1
FM hole detector/FM detuning
Tuner testing
0
1
Page mode disabled
Page mode enabled
must be "0”
0
0
0
29/47
2
I C bus interface
TDA7421N
Table 14. PLL subaddress
MSB
LSB
A0
Function
T3(1)
T2
T1
I
A3
A2
A1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
Charge pump control
PLL counter 1 (LSB)
PLL counter 2 (MSB)
PLL reference counter 1 (LSB)
PLL reference counter 2 (MSB)
PLL lock detector control and PLL mode select
IFC reference counter 1 (LSB)
IFC reference counter 2 (MSB) and IFC mode select
IF counter control 1
IF counter control 2
0
1
Page mode disabled
Page mode enabled
1. T1, T2, T3 are used for testing the PLL, in application mode they have to be "0".
30/47
TDA7421N
Data byte specification
6
Data byte specification
6.1
PLL data byte specification
Table 15. Charge pump control
MSB
LSB
D0
Function
D7
D6
D5
D4
D3
D2
D1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
High current = 0 mA
High current = 0.5 mA
High current = 1.0 mA
High current = 1.5 mA
High current = 2.0 mA
High current = 2.5 mA
High current = 3.0 mA
High current = 3.5 mA
High current = 4.5 mA
High current = 5.0 mA
High current = 5.5 mA
High current = 6.0 mA
High current = 6.5 mA
High current = 7.0 mA
High current = 7.5 mA
Low current = 0 μA
0
0
1
1
0
1
0
1
Low current = 15 μA
Low current = 100 μA
Low current = 115 μA
Select low Current
0
1
Select high Current
Select loop filter 1
0
1
Select loop filter 2
LPIN1/2 CURRH
B1
B0
A3
A2
A1
A0
Bit name
Subaddress = 00H
31/47
Data byte specification
TDA7421N
Table 16. PLL counter 1 (LSB)
MSB
LSB
D0
Function
D7
D6
D5
D4
D3
D2
D1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
LSB = 0
LSB = 1
LSB = 2
all combinations allowed
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
1
LSB = 252
LSB = 253
LSB = 254
LSB = 255
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0 Bit name
Subaddress = 01H
Table 17. PLL counter 2 (MSB)
MSB
LSB
D0
Function
D7
D6
D5
D4
D3
D2
D1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
MSB = 0
MSB = 256
MSB = 512
all combinations allowed
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
1
MSB = 64768
MSB = 65024
MSB = 65280
MSB = 65536
1
1
PC15 PC14 PC13 PC12 PC11 PC10
PC9
PC8 Bit name
Subaddress = 02H
Swallow mode: fvco/fsyn = LSB + MSB + 32
Table 18. PLL reference counter 1 (LSB)
MSB
LSB
D0
Function
D7
D6
D5
D4
D3
D2
D1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
LSB = 0
LSB = 1
LSB = 2
all combinations allowed
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
1
LSB = 252
LSB = 253
LSB = 254
LSB = 255
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0 Bit name
Subaddress =03H
32/47
TDA7421N
Data byte specification
Function
Table 19. PLL reference counter 2 (MSB)
MSB
LSB
D0
D7
D6
D5
D4
D3
D2
D1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
MSB = 0
MSB = 256
MSB = 512
all combinations allowed
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
1
MSB = 64768
MSB = 65024
MSB = 65280
MSB = 65536
1
1
RC15 RC14
RC13 RC12 RC11 RC10
RC9
RC8 Bit name
Subaddress = 04H
fOSC/fREF = LSB + MSB + 1
Table 20. Lock detector and PLL mode control
MSB
LSB
D0
Function
D7
D6
D5
D4
D3
D2
D1
0
0
1
1
0
1
0
1
PLL standby mode
PLL AM
not used
PLL FM mode
0
0
1
1
0
1
0
1
PD phase difference threshold 10ns
PD phase difference threshold 20ns
PD phase difference threshold 30ns
PD phase difference threshold 40ns
Not used in application mode
0
0
1
1
0
1
0
1
Activation delay = 4 · fref
Activation delay = 6 · fref
Activation delay = 8 · fref
0
1
No lock detector controlled charge pump
Lock detector controlled charge pump
LDENA
D3
D2
D1
D0
PM1
PM0 Bit name
: Subaddress = 05H
33/47
Data byte specification
TDA7421N
Table 21. IF counter reference control 1 (LSB)
MSB
LSB
D0
Function
D7
D6
D5
D4
D3
D2
D1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
LSB = 0
LSB = 1
LSB = 2
all combinations allowed
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
1
LSB = 252
LSB = 253
LSB = 254
LSB = 255
1
1
1
1
1
1
1
1
1
1
IRC7 IRC6
IRC5
IRC4
IRC3
IRC2
IRC1
IRC0 Bit name
Subaddress = 06H
Table 22. IF counter reference control 2 (MSB) and IF counter mode select
MSB
D7
LSB
D0
Function
D6
D5
D4
D3
D2
D1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
MSB = 0
MSB = 256
MSB = 512
all combinations allowed
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
MSB = 15616
MSB = 15872
MSB = 16128
0
0
1
1
0
1
0
1
NOT USED IN APPLICATION MODE
IF counter FM mode
IF counter AM mode
not used
IFCM1 IFCM0 IRC13 IRC12 IRC11 IRC10 IRC9
IRC8 Bit name
Subaddress = 07H
fosc/ftim = LSB + MSB + 1
34/47
TDA7421N
Data byte specification
Function
Table 23. IF counter control 1
MSB
LSB
D0
D7
D6
D5
D4
D3
D2
D1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
don't use
don't use
don't use
EW delta f = 6.25 kHz (FM); 1 kHz (AM)
EW delta f = 12.5 kHz (FM); 2 kHz (AM)
EW delta f = 25 kHz (FM); 4 kHz (AM)
EW delta f = 50 kHz (FM); 8 kHz (AM)
EW delta f = 100 kHz (FM); 16 kHz (AM)
IF counter disabled / standby
0
1
IF counter enabled
IFENA
EW2
EW1
EW0 Bit name
Subaddress = 08H
Table 24. IF counter control 2
MSB
LSB
D0
Function
D7
D6
D5
D4
D3
D2
D1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
fcenter = 10.60000 MHz (FM) 448 kHz (AM)
fcenter = 10.60625 MHz (FM) 449 kHz (AM)
fcenter = 10.61250 MHz (FM) 450 kHz (AM)
fcenter = 10.61875 MHz (FM) 451 kHz (AM)
fcenter = 10.62500 MHz (FM) 452 kHz (AM)
fcenter = 10.63125 MHz (FM) 453 kHz (AM)
fcenter = 10.63750 MHz (FM) 454 kHz (AM)
fcenter = 10.64375 MHz (FM) 455 kHz (AM)
fcenter = 10.65000 MHz (FM) 456 kHz (AM)
fcenter = 10.65625 MHz (FM) 457 kHz (AM)
fcenter = 10.66250 MHz (FM) 458 kHz (AM)
fcenter = 10.66875 MHz (FM) 459 kHz (AM)
fcenter = 10.67500 MHz (FM) 460 kHz (AM)
fcenter = 10.68125 MHz (FM) 461 kHz (AM)
fcenter = 10.68750 MHz (FM) 462 kHz (AM)
fcenter = 10.69375 MHz (FM) 463 kHz (AM)
fcenter = 10.70000 MHz (FM) 464 kHz (AM)
fcenter = 10.70625 MHz (FM) 465 kHz (AM)
fcenter = 10.71250 MHz (FM) 466 kHz (AM)
35/47
Data byte specification
TDA7421N
Table 24. IF counter control 2 (continued)
MSB
LSB
D0
Function
D7
D6
D5
D4
D3
D2
D1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
fcenter = 10.71875 MHz (FM) 467 kHz (AM)
fcenter = 10.72500 MHz (FM) 468 kHz (AM)
fcenter = 10.73125 MHz (FM) 469 kHz (AM)
fcenter = 10.73750 MHz (FM) 470 kHz (AM)
fcenter = 10.74375 MHz (FM) 471 kHz (AM)
fcenter = 10.75000 MHz (FM) 472 kHz (AM)
fcenter = 10.75625 MHz (FM) 473 kHz (AM)
fcenter = 10.76250 MHz (FM) 474 kHz (AM)
fcenter = 10.76875 MHz (FM) 475 kHz (AM)
fcenter = 10.77500 MHz (FM) 476 kHz (AM)
fcenter = 10.78125 MHz (FM) 477 kHz (AM)
fcenter = 10.78750 MHz (FM) 478 kHz (AM)
fcenter = 10.79375 MHz (FM) 479 kHz (AM)
tsample = 20.48 ms (FM mode); 128 ms (AM; MODE)
tsample = 10.24 ms (FM mode); 64 ms (AM; MODE)
tsample = 5.12 ms (FM mode); 32 ms (AM; MODE)
tsample = 2.56 ms (FM mode); 16 ms (AM; MODE)
tsample = 1.28 ms (FM mode); 8 ms (AM;MODE)
tsample = 640 ms (FM mode); 4 ms (AM;MODE)
tsample = 320 ms (FM mode); 2 ms (AM; MODE)
tsample = 160 ms (FM mode); 1 ms (AM; MODE)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
IFS2 IFS1 IFS0 CF4
CF3 CF2
CF1 CF0 bit name
Subaddress = 09H
36/47
TDA7421N
Data byte specification
6.2
Tuner data byte specification
)
Table 25. Address organization (Tuner AM/FM
MSB
LSB
Function
Subad
B7
B6
B5
B4
B3
B2
B1
B0
AM
STEREO
AM/FM/ AM/FM/ AM/FM/
STATUS
00H
01H
02H
N.U.
FMMUTE FMADJ
SEEK
STBY
FSS2
STBY
FSS1
STBY
FSS0
FM STOP STATION/
FM IF AGC
FAG2
FSL4
FAG1
FSL3
FAG0
FSL2
FSS4
FSL1
FSS3
FSL0
FM SMETER
SLIDER/ AM IF2 AMP
IF2A1
IF2A0
N.U.
AM AGC1/AM STOP
STATION
O3H
04H
05H
ASS3
T2A3
ANA3
ASS2
T2A2
ANA2
ASS1
T2A1
ANA1
ASS0
T2A0
ANA0
AAGN1 AAGN0 AAGW1 AAGW0
IFT1/IFT2
T1A3
RFA3
T1A2
RFA2
T1A1
RFA1
T1A0
RFA0
FRONT-END
ADJUSTMENT
FM DEMOD
ADJUSTMENT
06H
07H
N.U.
DEM6
FSM2
DEM5
FSM1
DEM4
FSM0
DEM3
FFBL1
DEM2
FBL0
DEM1
AUM1
DEM0
AUM0
FM AUDIO MUTE
GAIN/FM IF
BUFFERS/FM SOFT
MUTE
FSM3
FM HOLE
DETECTOR/FM
DETUNING
08H
09H
BWM2
BWM1
T2
BWM0
T1
HDM4
T0
HDM3
HDM2
HDM1
HDM0
TUNER TESTING
PLLTEST
SDDIS BWDIS HDDID SMDIS
Table 26. Status (subaddress 00H)
MSB
LSB
S6
S5
S4
S3
S2
S1
S0
Function
FM
FM
ADJ
AM
STEREO
AM/FM/ AM/FM/ AM/FM/
Standby Standby Standby
SEEK
MUTE
0
0
0
1
1
0
0
1
1
0
0
1
0
0
0
Standby
FM on
AM on (/6)
AM on (/10)
AM on (/8)
RECEPTION
SEEK
0
1
0
1
AM
AM
AM
AM
AM
AM
AM IFC Out
AM Stereo OUT
37/47
Data byte specification
TDA7421N
Table 26. Status (subaddress 00H) (continued)
MSB
LSB
S0
S6
S5
S4
S3
S2
S1
Function
FM
FM
ADJ
AM
STEREO
AM/FM/ AM/FM/ AM/FM/
Standby Standby Standby
SEEK
MUTE
FM on for demodulator
adjustment, demod. on
0
1
1
FM
FM
FM
FM
FM
FM
FM on for demodulator
adjustment, demod.
muted
1
)
Table 27. FM stop station / FM IF AGC (subaddress 01H
MSB
LSB
FAG2
FAG1
FAG0
FSS4
FSS3
FSS2
FSS1
FSS0
Function
FM
stop
FM
stop
station
MSB
FM
stop
FM
stop
FM
stop
FM
IF AGC
MSB
FM
IF AGC
LSB
FM
IF AGC
station
LSB
station station station
FM stop station threshold
0
X
1
0
X
1
0
X
1
0
X
1
0
X
1
Maximum sensitivity
Minimum sensitivity
all combinations allowed
FM IF AGC threshold
0
X
1
1
0
X
1
1
0
X
0
1
Maximum sensitivity
Minimum sensitivity
Keyed AGC disabled
all combinations allowed
Table 28. FM smeter slider\IF2 amplifier (subaddress 02H)
MSB
LSB
FSL4
FSL3
FSL2
FSL1
FSL0
IF2A1
IF2A0
Function
FM
FM
FM
FM
FM
AM if
2Amp
MSB
AM if
2Amp
LSB
smeter
slider
MSB
smeter
slider
LSB
smeter
slider
smeter
slider
smeter
slider
FM smeter sliding (mV)
0
0
0
0
0
0
38/47
TDA7421N
Data byte specification
Table 28. FM smeter slider\IF2 amplifier (subaddress 02H) (continued)
MSB
FSL4
FM
LSB
FSL3
FM
FSL2
FM
FSL1
FM
FSL0
FM
IF2A1
IF2A0
Function
AM if
2Amp
MSB
AM if
2Amp
LSB
smeter
slider
MSB
smeter
slider
LSB
smeter
slider
smeter
slider
smeter
slider
0
X
1
0
X
1
0
X
1
0
X
1
1
X
1
48
1500
all combinations allowed
IF2 amplifier gain
0
0
1
1
0
1
0
1
50dB
53dB
56dB
59dB
Table 29. AM stop station / AM AGC1 (subaddress 03H)
MSB
LSB
ASS3
ASS2
ASS1
ASS0 AAGN1 AAGN0 AAGW1 AAGW0
AM
Function
AM
stop
AM
AM
stop
AM
stop
AM
AM
NAGC
MSB
AM
stop
station
LSB
NAGC WAGC
WAGC
LSB
station
MSB
LSB
station station
MSB
AM WAGC threshold
0
X
1
0
X
1
Minimum sensitivity
Maximum sensitivity
all comb. allowed
AM NAGC threshold
0
X
1
0
X
1
Minimum sensitivity
Maximum sensitivity
all comb. allowed
AM stop station threshold
0
X
1
0
X
1
0
X
1
0
X
1
Maximum sensitivity
Minimum sensitivity
all combinations allowed
39/47
Data byte specification
TDA7421N
Table 30. IFT1/IFT2 (subaddress 04H)
MSB
LSB
T2A3
T2A2
T2A1
T2A0
T1A3
T1A2
IF T1
T1A1
IF T1
T1A0
Function
IF T2
adjust
MSB
IF T2
adjust adjust
LSB
IF T1
IF T1
adjust
LSB
IF T2
adjust adjust
IF T2
adjust adjust
MSB
Adjustment capacitor
0
0
1
1
1
1
0
1
0
1
1
1
0
1
1
0
1
1
0
1
0
1
0
1
15Cift1
8Cift1
4Cift1
2Cift1
Cift2 (= 380 pF)
0
all combinations allowed
0
0
0
0
1
1
0
0
0
1
0
1
0
0
1
0
0
1
0
1
0
0
0
1
0
Cift1 (= 1.57 pF)
2Cift2
4Cift2
8Cift2
15Cift2
all combinations allowed
Table 31. Front-end adjustment (subaddress 05H)
MSB
LSB
ANA3
ANA2
ANA1
ANA0
RFA3
RFA2
RFA1
RFA0
Function
ANT
adjustm adjustm
MSB
ANT
ANT
RF
RF
RF
adjustm
LSB
ANT
adjustm
RF
adjustm
adjustm adjustm adjustm
LSB
MSB
Voffset RF varicap / VPLL
X
0
0
0
0
1
1
1
0
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
0
1
0
0
1
1
0
0
0
-3.6 %
-7.2 %
-14.3 %
-25 %
3.6 %
7.2 %
14.3 %
40/47
TDA7421N
Data byte specification
Table 31. Front-end adjustment (subaddress 05H) (continued)
MSB
ANA3
ANT
adjustm adjustm
MSB
LSB
ANA2
ANT
ANA1
ANA0
ANT
RFA3
RF
RFA2
RF
RFA1
RFA0
Function
RF
adjustm
LSB
ANT
adjustm
RF
adjustm
adjustm adjustm adjustm
LSB
MSB
1
1
1
1
25 %
all combinations allowed
Voffset antenna varicap / VPLL
X
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
0
-3.6 %
-7.2 %
-14.3 %
-25 %
3.6 %
7.2 %
14.3 %
25 %
all combinations allowed
Table 32. FM demodulator adjustment (subaddress 06H)
MSB
LSB
DEM6
DEM5
DEM4
DEM3
DEM2
DEM1
DEM0
Function
demadj
MSB
demadj
LSB
demadj demadj demadj demadj demadj
Adjustment capacitor
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
0
1
Cdemod (= 50fF)
2Cdemod
4Cdemod
8Cdemod
16Cdemod
32Cdemod
64Cdemod
127Cdemod
all combinations allowed
41/47
Data byte specification
TDA7421N
Table 33. FM soft mute / FM IF amplifier/fm audio mute gain (subaddress 07H)
MSB
LSB
FSM3
FSM2
FM
FSM1
FM
FSM0
FBL1
FBL0
AUM1
AUM0
Function
FM
softmute
MSB
FM
softmute
LSB
Mute
Depth
MSB
Mute
Depth
LSB
buff 2
gain
buff 2
gain
softmute softmute
FM soft mute threshold
0
X
1
0
X
1
0
X
1
0
X
1
Maximum sensitivity
Minimum sensitivity
all combinations allowed
Audio max mute attenuation
0
0
1
1
0
1
0
1
-5
-7.5
-10
-12.5
all comb. allowed
Buffer 2 Gain (dB)
0
0
1
0
1
0
10
6
8
all else not allowed
Table 34. FM hole detector / FM detuning detector (subaddress 08H)
MSB
LSB
BWM2 BWM1 BWM0 HDM4
HDM3
HDM2
HDM1
HDM0
Function
BW
Slope
BW
Slope
BW
Slope
Hole
det
MSB
Hole
det
Hole
det
Hole
det
Hole
det LSB
30 kHz 15 kHz 10 kHz
Muting sensitivity (hole depth)
0
X
1
0
X
1
0
X
1
0
X
1
0
X
1
Minimum (deep hole)
Maximum (shallow hole)
all combinations allowed
RECEPTION
Detuning mute range (kHz)
0
0
0
1
1
0
10
15
42/47
TDA7421N
Data byte specification
Table 34. FM hole detector / FM detuning detector (subaddress 08H) (continued)
MSB
LSB
BWM2 BWM1 BWM0 HDM4
HDM3
HDM2
HDM1
HDM0
Function
BW
Slope
BW
Slope
BW
Slope
Hole
det
MSB
Hole
det
Hole
det
Hole
det
Hole
det LSB
30 kHz 15 kHz 10 kHz
1
0
0
30
all else not allowed
SEEK
Clamping window
0
0
1
X
1
X
Not allowed
Faster Clamping Window
( 1 kHz over Threshold)
0
X
1
0
X
1
Slower Clamping Window
( 4 kHz over Threshold)
all combinations allowed
Table 35. Tuner testing
MSB
LSB
PLL test
T2
T1
T0
SDDIS
BWDIS
HDDIS
SMDIS
Function
Test
mode
PLL
Test
mode
MSB
Test
mode
LSB
SD
output
disable
Hole
detector
disable disable
Soft
mute
Test
mode
Bandwidth
disable
0
0
0
0
0
0
0
0
no test
Test modes
1
1
0
1
1
0
1
1
0
1
1
1
Soft Mute Test
Hole Detector Test
Bandwidth Test
Audio Mute and SD Disabled
all else not allowed
0
0
0
1
1
0
1
1
0
1
1
0
1
0
0
AMSSDAC Test
FMSSDAC Test
FMSMDAC Test
FMHDDAC Test
FMIFAGCDAC Test
all else not allowed
1
PLL Test
43/47
Component description
TDA7421N
7
Component description
Table 36. Component description
Component
Description
CF1
CF3-CF4
CF2
Ceramic filter 10.7 MHz, 180 kHz BW
Ceramic filter 10.7 MHz, 150 kHz BW
Ceramic filter 450 kHz, 6 kHz BW
FM RF transformer
Unloaded Q= 69
3-1= 3 3/4T - 6-4= 3T 0.12f2UEW
CTUNING(3-1)= 26.6 pF @ 100 MHz
T1
T2
T3
L2
L6
AM/FM IF1 transformer
Unloaded Q= 70
1-3= 12T - 1-5= 6 - 5-3= 6 - 4-6= 2T 0.08f2UEW
CINT(1-3) = 51 pF; CEXT(1-3) = 5 pF
AM IF2 transformer
Unloaded Q= 40
1-3= 178T - 1-2= 89T - 2-3= 89T - 4-6= 33T 0.05f2UEW
CINT(1-3) = 180 pF; CEXT(1-3) = 20 pF
Oscillator coil
Unloaded Q= 8
06-4= 2 1/2T 0.12f2UEW
CTUNING(6-4)= 36.8 pF @ 100 MHz
Demodulator Coil
Unloaded Q= 35
6-4= 27T 0.1f2UEW
CINT(4-6)= 47 pF; CEXT(4-6) = 13.5 pF
18nF
2.7K
AM BPF RC
27nF
100K
D98AU915
44/47
TDA7421N
Package information
8
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
Figure 13. LQFP64 mechanical data and package dimensions
mm
inch
DIM.
OUTLINE AND
MECHANICAL DATA
MIN. TYP. MAX. MIN.
TYP. MAX.
0.063
A
A1
A2
B
1.60
0.05
1.35
0.17
0.09
0.15 0.002
0.006
1.40
0.22
1.45 0.053 0.055 0.057
0.27 0.0066 0.0086 0.0106
0.0035
C
D
11.80 12.00 12.20 0.464 0.472 0.480
9.80 10.00 10.20 0.386 0.394 0.401
D1
D3
e
7.50
0.50
0.295
0.0197
E
11.80 12.00 12.20 0.464 0.472 0.480
9.80 10.00 10.20 0.386 0.394 0.401
E1
E3
L
7.50
0.60
1.00
0.295
0.75 0.0177 0.0236 0.0295
0.0393
0.45
L1
K
LQFP64 (10 x 10 x 1.4mm)
0˚ (min.), 3.5˚ (min.), 7˚(max.)
0.080
ccc
0.0031
D
D1
D3
A
A2
A1
48
33
32
49
0.08mm ccc
Seating Plane
17
16
64
1
C
e
K
0051434 F
45/47
Revision history
TDA7421N
9
Revision history
Table 37. Document revision history
Date
Revision
Changes
24-Aug-2000
1
Initial release.
Document reformatted.
Document status changed from preliminary data to not for new
design.
23-Jan-2009
2
Updated Table 1: Device summary on page 1.
Updated Section 8: Package information on page 45.
46/47
TDA7421N
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47/47
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