ESDA25LY [STMICROELECTRONICS]
Automotive dual Transil array for ESD protection; 汽车双阵列的Transil ESD保护
| 型号： | ESDA25LY |
| 厂家： | 
ST |
| 描述： | Automotive dual Transil array for ESD protection |
| 文件： | 总10页 (文件大小：92K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESDA25LY
Automotive dual Transil™ array for ESD protection
Features
3
■ 2 Unidirectional Transil functions
■ Low leakage current: 1 µA @ 24 V
■ 300 W peak pulse power (8/20 µs)
2
1
Benefits
SOT23-3L
■ High ESD protection level: up to 25 kV
■ High integration
Figure 1.
Functional diagram
■ Suitable for high density boards
Complies with the following standards
1
■ IEC 61000-4-2 level 4
– 15 kV (air discharge)
– 8 kV (contact discharge)
3
■ MIL STD 883G - Method 3015-7 Class 3B
– (human body model)
2
Applications
Where transient overvoltage protection in ESD
sensitive equipment is required, such as :
Description
■ Computers
The ESDA25LY is a dual monolithic voltage
suppressor designed to protect components
which are connected to data and transmission
lines against ESD.
■ Printers
■ Communication systems and cellular phones
It clamps the voltage just above the logic level
supply for positive transients, and to a diode drop
below ground for negative transients.
It can also work as bidirectionnal suppressor by
connecting only pin1 and 2.
It is particulary recommended for the RS232 I/O
port protection where the line interface withstands
only with 2 kV ESD surges.
TM: Transil is a trademark of STMicroelectronics.
A.S.D.™= Application Specific Discretes
February 2010
Doc ID 16914 Rev 1
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www.st.com
10
Characteristics
ESDA25LY
1
Characteristics
Table 1.
Symbol
Absolute maximum ratings (T
= 25°C)
amb
Parameter
Value
Unit
MIL STD 883E-Method 3015-7
IEC 61000-4-2 air discharge
IEC 61000-4-2 contact discharge
25
16
9
VPP
ESD discharge
kV
PPP
Tj
Peak pulse power (8/20 µs)
Junction temperature
300
150
W
°C
Tstg
TL
Storage temperature range
-55 to +150
260
°C
°C
°C
Maximum lead temperature for soldering during 10 s at 5 mm for case
Operating temperature range
Top
-40 to +125
Figure 2.
Electrical characteristics (definitions)
I
Symbol
VBR
Parameter
Breakdown voltage
Clamping voltage
Leakage current @ VRM
Stand-off voltage
IF
=
=
=
=
=
=
=
=
=
=
VCL
IRM
VRM
IF
IPP
IR
VF
Rd
αT
VF
V
CL VBR VRM
V
Forward current
IRM
IR
Peak pulse current
Breakdown current
Forward voltage drop
Dynamic impedance
Voltage temperature
Slope = 1/Rd
IPP
Table 2.
Electrical characteristics (values, T
= 25 °C)
amb
VBR @ IR
IRM @ VRM
max.
VF@ IF
max.
Rd
αT
C
min.
max.
typ.
note(1)
max.
note(2) 0V bias
typ.
Order code
V
V
mA
1
µA
1
V
V
mA
10
mΩ
10-4/C
pF
50
ESDA25LY
25
30
24
1.2
1000
10
1. Square pulse, Ipp = 15 A, tp = 2.5 µs.
2. Δ VBR = αT* (Tamb - 25 °C) * VBR (25 °C)
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ESDA25LY
Figure 3.
Characteristics
Peak power dissipation versus
initial junction temperature
Figure 4.
Peak pulse power versus
exponential pulse duration
(Tj initial = 25 °C)
PPP[Tj initial] / PPP[Tj initial = 25 °C]
P
(W)
PP
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
3000
1000
Tj initial = 25°C
100
10
Tj initial (°C)
tp(µs)
100
0
25
50
75
100
125
150
1
10
Figure 5.
Clamping voltage versus peak
pulse current (Tj initial = 25 °C,
rectangular waveform, tp = 2.5µs)
Figure 6.
Capacitance versus reverse applied
voltage (typical values)
C(pF)
200
IPP(A)
50.0
F = 1 MHz
VOSC = 30 mVRMS
Tj = 25 °C
100
50
10.0
1.0
tp = 2.5 µs
20
VCL(V)
VR(V)
50
0.1
0
10
1
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
2
5
10
20
Figure 7.
Relative variation of leakage
current versus junction
Figure 8.
Peak forward voltage drop versus
forward current (typical values)
temperature (typical values)
IR[Tj] / IR[Tj = 25 °C]
IFM(A)
5.00
200
100
Tj = 25 °C
1.00
0.10
0.01
10
VFM(V)
3.5 4.0
Tj(°C)
125
1
25
50
75
100
0.0
0.5
1.0
1.5
2.0
2.5
3.0
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Calculation of the clamping voltage
ESDA25LY
2
Calculation of the clamping voltage
2.1
Use of the dynamic resistance
The ESDA family has been designed to clamp fast spikes like ESD. Generally the PCB
designers need to calculate easily the clamping voltage VCL. This is why we give the
dynamic resistance in addition to the classical parameters. The voltage across the
protection cell can be calculated with the following formula:
VCL = VBR + Rd IPP
Where Ipp is the peak current through the ESDA cell.
3
Dynamic resistance measurement
The short duration of the ESD has led us to prefer a more adapted test wave, as below
defined, to the classical 8/20 µs and 10/1000 µs surges.
As the value of the dynamic resistance remains stable for a surge duration lower than 20 µs,
the 2.5 µs rectangular surge is well adapted. In addition both rise and fall times are
optimized to avoid any parasitic phenomenon during the measurement of Rd.
Figure 9.
2.5 µs duration measurement wave
I
I
PP
t
2µs
t
= 2.5µs
p
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ESDA25LY
ESD Protection by ESDA25LY
4
ESD Protection by ESDA25LY
Electrostatic discharge (ESD) is a major cause of failure in electronic systems.
Transient Voltage Suppressors (TVS) are an ideal choice for ESD protection. They are
capable of clamping the incoming transient to a low enough level such that damage to the
protected semiconductor is prevented.
Surface mount TVS arrays offer the best choice for minimal lead inductance.
They serve as parallel protection elements, connected between the signal line to ground. As
the transient rises above the operating voltage of the device, the TVS array becomes a low
impedance path diverting the transient current to ground.
The ESDA25LY array is the ideal board level protection of ESD sensitive semiconductor
components.
The tiny SOT23 package allows design flexibility in the design of high density boards where
the space saving is at a premium. This enables to shorten the routing and contributes to
hardening againt ESD.
Figure 10. ESD protection diagram
I/O
I/O
I/O
I/O
ESD
sensitive
device
GND
2 * ESDA25LY
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Circuit board layout
ESDA25LY
5
Circuit board layout
Circuit board layout is a critical design step in the suppression of ESD induced transients.
The following guidelines are recommended :
●
The ESDA25LY should be placed as close as possible to the input terminals or
connectors.
●
The path length between the ESD suppressor and the protected line should be
minimized
●
●
●
All conductive loops, including power and ground loops should be minimized
The ESD transient return path to ground should be kept as short as possible.
Ground planes should be used whenever possible.
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ESDA25LY
Ordering information scheme
6
Ordering information scheme
Figure 11. Ordering information scheme
ESDA 25 LY
ESD Array
Breakdown Voltage
25 V = 25 Volts min.
Packages
L = SOT23-3L
Y = Automotive grade
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Package information
ESDA25LY
7
Package information
●
●
Epoxy meets UL94, V0
Lead-free packages
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
Table 3.
SOT23-3L dimensions
Dimensions
Millimeters
Ref.
Inches
Min. Max.
A
Min.
Max.
E
A
A1
B
0.89
0
1.4
0.1
0.035
0
0.055
0.004
0.02
e
0.3
0.51
0.18
3.04
1.05
2.1
0.012
0.003
0.108
0.033
0.067
0.047
0.083
B
D
e1
c
0.085
2.75
0.85
1.7
0.007
0.12
D
e
S
0.041
0.083
0.063
0.108
A1
e1
E
1.2
1.6
c
L
H
L
2.1
2.75
H
0.6 typ.
0.024 typ.
S
0.35
0.65
0.014
0.026
Figure 12. Footprint (dimensions in mm)
0.95
0.61
1.26
0.73
3.25
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ESDA25LY
Ordering information
8
Ordering information
Table 4.
Order code
ESDA25LY
Ordering information
Marking
Package
Weight
Base qty
3000
Delivery mode
EL2Y
SO23-3L
0.01 g
Tape and reel
9
Revision history
Table 5.
Date
01-Feb-2010
Document revision history
Revision
Changes
1
First issue.
Doc ID 16914 Rev 1
9/10
ESDA25LY
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