GM5221 [STMICROELECTRONICS]
1280 X 1024 PIXELS DOT MAT LCD DSPL CTLR, PQFP208, PLASTIC, QFP-208;
| 型号： | GM5221 |
| 厂家： | 
ST |
| 描述： | 1280 X 1024 PIXELS DOT MAT LCD DSPL CTLR, PQFP208, PLASTIC, QFP-208 CD |
| 文件： | 总47页 (文件大小：1285K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Genesis Microchip Publication
PRELIMINARY DATA SHEET
gm5221-LF-BC
Integrated Multimedia LCD Controller
GENESIS MICROCHIP CONFIDENTIAL
Publication Number: C5221-DAT-04A
Publication Date: March 2004
Genesis Microchip Inc.
www.genesis-microchip.com
/ info@genesis-microchip.com.com
The following are trademarks or registered trademarks of Genesis Microchip, Inc.:
GenesisTM, Genesis Display PerfectionTM, ESMTM, RealColorTM, Ultra-Reliable DVITM, Real RecoveryTM, SageTM, JagASMTM
SureSyncTM, Adaptive Backlight Control™, FaroudjaTM, DCDiTM, TrueLifeTM, IntelliCombTM
,
Other brand or product names are trademarks of their respective holders.
© Copyright 2002, 2003, 2004 Genesis Microchip Inc. All Rights Reserved.
Genesis Microchip Inc. reserves the right to change or modify the information contained herein without notice. It is
the customer’s responsibility to obtain the most recent revision of the document. Genesis Microchip Inc. makes no
warranty for the use of its products and bears no responsibility for any errors or omissions that may appear in this
document.
gm5221-LF-BC Multimedia LCD Controller Preliminary Data Sheet
Table Of Contents
1
Overview........................................................................................................................................ 7
1.1 gm5221 System Design Example ................................................................................................ 7
1.2 gm5221 Features.......................................................................................................................... 8
gm5221 Pinout............................................................................................................................... 9
gm5221 Pin List........................................................................................................................... 10
Functional Description................................................................................................................. 15
4.1 Clock Generation ....................................................................................................................... 15
4.1.1 Using the Internal Oscillator with External Crystal............................................................ 15
4.1.2 Clock Synthesis................................................................................................................... 18
4.2 Chip Initialization ...................................................................................................................... 19
4.2.1 Hardware Reset................................................................................................................... 19
4.2.2 Power Sequencing............................................................................................................... 21
4.3 Analog to Digital Converter (ADC)........................................................................................... 21
4.3.1 ADC Pin Connection .......................................................................................................... 21
4.3.2 ADC Characteristics ........................................................................................................... 23
4.3.3 Clock Recovery Circuit ...................................................................................................... 23
4.3.4 Sampling Phase Adjustment ............................................................................................... 24
4.3.5 SOG and CSYNC support .................................................................................................. 24
4.4 Ultra-Reliable Digital Visual Interface Receiver (DVI Rx)....................................................... 25
4.4.1 DVI Receiver Characteristics ............................................................................................. 25
4.4.2 High-Bandwidth Digital Content Protection (HDCP) ........................................................ 26
4.5 ITU656 Video Input Port........................................................................................................... 26
4.6 Test Pattern Generator (TPG) .................................................................................................... 26
4.7 Input Format Measurement........................................................................................................ 27
4.7.1 HSYNC / VSYNC Delay.................................................................................................... 27
4.7.2 Horizontal and Vertical Measurement................................................................................ 28
4.7.3 Format Change Detection ................................................................................................... 28
4.7.4 Watchdog............................................................................................................................ 28
4.7.5 Internal Odd/Even Field Detection (For Interlaced Inputs to ADC Only).......................... 28
4.7.6 Input Pixel Measurement.................................................................................................... 29
4.7.7 Image Phase Measurement ................................................................................................. 29
4.7.8 Image Boundary Detection ................................................................................................. 29
4.7.9 Image Auto Balance............................................................................................................ 29
4.8 Intelligent Image Processing™ Zoom/Shrink/Sharpening Filter............................................... 29
4.8.1 Variable Zoom Scaling ....................................................................................................... 29
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gm5221-LF-BC Multimedia LCD Controller Preliminary Data Sheet
4.8.2 Horizontal and Vertical Shrink........................................................................................... 30
4.8.3 Programmable Sharpening Filter........................................................................................ 30
4.9 Advanced Digital Color Controls .............................................................................................. 30
4.9.1 Adaptive Contrast and Color (ACC)................................................................................... 30
4.9.2 Active Color Management–II (ACM-II) ............................................................................ 31
4.9.3 Gamma Look-Up-Table (LUT) .......................................................................................... 31
4.9.4 Color Standardization and sRGB Support.......................................................................... 31
4.9.5 Video Windowing............................................................................................................... 31
4.10 Display Output Interface.......................................................................................................... 31
4.10.1 Display Synchronization................................................................................................... 32
4.10.2 Display Timing Programming .......................................................................................... 32
4.10.3 Output Dithering............................................................................................................... 33
4.10.4 Dual Four-Channel LVDS Transmitter ............................................................................ 33
4.10.5 Single Pixel TTL Output................................................................................................... 34
4.10.6 Panel Power Sequencing (PPWR, PBIAS)....................................................................... 34
4.11 Energy Spectrum Management (ESM).................................................................................... 35
4.12 On-Screen Display (OSD) ....................................................................................................... 35
4.12.1 On-Chip OSD SRAM ....................................................................................................... 35
4.12.2 Color Look-up Table (LUT)............................................................................................. 36
4.13 On-Chip Microcontroller (OCM)............................................................................................. 36
4.13.1 Compiling firmware.......................................................................................................... 37
4.13.2 Embedded Bootstrap Function.......................................................................................... 37
4.13.3 In-System-Programming (ISP) of External FLASH ROM............................................... 38
4.13.4 UART Interface ................................................................................................................ 38
4.13.5 DDC2Bi Interface............................................................................................................. 38
4.13.6 JTAG Interface ................................................................................................................. 39
4.13.7 General Purpose Inputs and Outputs (GPIO).................................................................... 39
4.13.8 Low-Bandwidth ADC (LBADC)...................................................................................... 40
4.13.9 Low Power State............................................................................................................... 40
4.13.10 Pulse Width Modulation (PWM).................................................................................... 40
4.14 Bootstrap Configuration Pins................................................................................................... 41
4.15 Electrostatic Discharge (ESD) ................................................................................................. 41
Electrical Specifications .............................................................................................................. 42
5.1 Preliminary DC Characteristics ................................................................................................. 42
5.2 Preliminary AC Characteristics ................................................................................................. 44
Ordering Information................................................................................................................... 46
Mechanical Specifications ........................................................................................................... 47
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gm5221-LF-BC Multimedia LCD Controller Preliminary Data Sheet
List Of Tables
Table 1. Analog Input Port................................................................................................................ 10
Table 2. DVI Input Port .................................................................................................................... 10
Table 3. RCLK PLL Pins.................................................................................................................. 11
Table 4. Input Video Port.................................................................................................................. 11
Table 5. System Interface.................................................................................................................. 12
Table 6. LVDS Display Interface ..................................................................................................... 13
Table 7. TTL Display Interface......................................................................................................... 13
Table 8. RESET Time....................................................................................................................... 20
Table 9. Requirement for RESETn due to Glitch in AVDD_3.3V................................................... 20
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Pin Connection for RGB Input with HSYNC/VSYNC .................................................. 22
ADC Characteristics ....................................................................................................... 23
DVI Receiver Characteristics ......................................................................................... 25
Supported LVDS 24-bit Panel Data Mappings............................................................... 34
Supported LVDS 18-bit Panel Data Mapping ................................................................ 34
GPIO and Alternate Functions........................................................................................ 40
Bootstrap Signals............................................................................................................ 41
Absolute Maximum Ratings........................................................................................... 42
DC Characteristics.......................................................................................................... 43
Maximum Speed of Operation........................................................................................ 44
Input Timing for ITU656 Video Port ............................................................................. 44
OCM ROM Interface Timing ......................................................................................... 45
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gm5221-LF-BC Multimedia LCD Controller Preliminary Data Sheet
List Of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
gm5221 System Design Example..................................................................................... 7
gm5221 Pin Out Diagram................................................................................................. 9
gm5221 Functional Block Diagram................................................................................ 15
Using the Internal Oscillator with External Crystal........................................................ 16
Internal Oscillator Output............................................................................................... 17
Sources of Parasitic Capacitance .................................................................................... 17
Internally Synthesized Clocks ........................................................................................ 18
On-chip Clock Domains ................................................................................................. 19
Reset Pulse vs. +3.3V_AVDD power line...................................................................... 20
Figure 10. Glitch in 3.3V AVDD..................................................................................................... 20
Figure 11. Correct Power Sequencing.............................................................................................. 21
Figure 12. Example ADC Signal Terminations ............................................................................... 22
Figure 13. gm5221 Clock Recovery ................................................................................................ 24
Figure 14. Supported SOG and CSYNC signals.............................................................................. 25
Figure 15. ITU-R BT656 Input Format............................................................................................ 26
Figure 16. Some of gm5221 Built-in Test Patterns.......................................................................... 27
Figure 17. Active Data Crosses HSYNC Boundary ........................................................................ 28
Figure 18. ODD/EVEN Field Detection .......................................................................................... 29
Figure 19. Digital Color Controls .................................................................................................... 30
Figure 20. Display Windows and Timing ........................................................................................ 32
Figure 21. Single Pixel Width Display Data.................................................................................... 34
Figure 22. Panel Power Sequencing................................................................................................. 35
Figure 23. OSD Cell Map ................................................................................................................ 36
Figure 24. Programming the OCM .................................................................................................. 37
Figure 25. Factory Calibration and Test Environment..................................................................... 39
Figure 26. Timing Diagram for ITU656 Video Port........................................................................ 44
Figure 27. OCM ROM Interface Timing Diagram .......................................................................... 45
Figure 28. gm5221 208-pin PQFP Mechanical Drawing................................................................. 47
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gm5221-LF-BC Multimedia LCD Controller Preliminary Data Sheet
1 Overview
The gm5200 family devices are an all-in-one LCD monitor controllers supporting resolutions up to
SXGA (1280x1024). The gm5221 leverages Genesis patented advanced image-processing technology as
well as a proven integrated ADC/PLL and an Ultra-Reliable DVI™ compliant digital receiver to provide
excellent image quality. gm5221 also integrates a microcontroller, an OSD controller, and dual LVDS
transmitters.
1.1 gm5221 System Design Example
Figure 1 below shows a typical dual interface LCD monitor system based on the gm5221. Designs based
on the gm5221 have reduced system cost, simplified hardware and firmware design and increased
reliability because only a minimal number of components are required in the system.
Analog
LCD
RGB
LVDS
Panel
Module
gm5221
DVI
Backlight
Inverter
Video
NTSC/
Decoder
PAL
(optional)
PROM
EEPROM
Keypad
Figure 1.
gm5221 System Design Example
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gm5221-LF-BC Multimedia LCD Controller Preliminary Data Sheet
1.2 gm5221 Features
•
•
Intelligent Image Processing™
•
Embedded X86 On-chip Microcontroller
•
•
•
Fully programmable zoom ratios
•
•
•
•
•
•
•
•
•
•
•
High-performance X86 MCU with on-chip RAM and ROM
External parallel ROM or serial SPI ROM interface
Unified memory architecture simplifies chip programming
23 general-purpose inputs/outputs (GPIOs) available
2-wire serial bus master to control NVRAM, video decoder
Two DDC2Bi ports with DMA buffer to internal RAM
Four PWM outputs for analog backlight control, audio, etc.
General-purpose ADC’s for keypad and temperature sensing
Integrated reset circuit
High-quality shrink capability from UXGA resolution
Programmable coefficients for variable sharpness control
•
RealRecovery™ provides full color recovery image for
refresh rates higher than those supported by the LCD panel
Analog RGB Input Port
•
•
Supports up to 162 MHz (SXGA 75Hz / UXGA 60Hz)
On-chip high-performance PLLs (single reference crystal
required)
Slow clock mode for 50mW sleep mode power consumption
JTAG debug / ICE support for firmware debugging
•
•
•
Composite-sync and Sync-on-Green (SOG) support
Input format detection
Phase and image positioning
•
•
Built-in Test Pattern Generator
•
Simplifies manufacturing / test
•
Ultra-Reliable DVI-Compliant Input Port
Energy Spectrum Management (ESM™)
•
•
•
Operating up to 165 MHz (up to UXGA 60Hz)
•
•
Digital clock spectrum management
Eliminates EMI suppression components and shielding
Direct connect to all DVI 1.0-compliant transmitters
High-bandwidth Digital Content Protection (HDCP)
Note: HDCP function is available H version only.
•
Built-in LVDS Transmitters
•
•
CCIR-656 8-bit Video Input Port
•
•
•
•
Four channel 6/8-bit LVDS transmitter
•
•
•
Supporting NTSC / PAL interlaced and progressive
Direct connect to commercially available video decoders
Spatial de-interlacing
Support for 8 or 6-bit panels with high-quality dithering
Single / double wide up to SXGA 75Hz output
Pin swap, odd / even swap and red / blue group swap of RGB
outputs for flexibility in board layout
Advanced Color Management
•
Highly integrated System-on-a-Chip
•
•
•
Programmable gamma correction (CLUT)
•
•
•
•
•
•
All system clocks synthesized from a single external crystal
50mW power saving mode
TV color controls including hue and saturation controls
Full color matrix allows end-users to experience the same
colors as viewed on CRTs and other displays (e.g. sRGB
compliance)
5-Volt tolerant inputs
Two Layer PCB support
On-chip reset feature to eliminate external reset component
Integrated Schmitt trigger for HSYNC and VSYNC
•
•
Advanced Active Color Management ™ (ACM-II) provide
flesh-tone compensation and image enhancement
Adaptive Contrast and Color™ (ACC) ensures full dynamic
range is used in video content
PACKAGE
•
On-chip Versatile OSD Controller
•
•
208-pin PQFP
3.3V IO and 1.8V core power supplies
•
•
•
•
•
•
On-chip RAM for high-quality programmable menus
1, 2 and 4-bit per pixel character cells
Horizontal and vertical stretch of OSD menus
Blinking, transparency and blending
Supports two independent OSD menu rectangles
Proportional fonts
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gm5221-LF-BC Multimedia LCD Controller Preliminary Data Sheet
2 gm5221 Pinout
The gm5221 devices are packaged in a 208-pin Plastic Quad Flat Pack (PQFP).
AGND_ADC
RESERVED
AVDD_ADC_3.3
AGND_RED
RED-
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
ROM_DATA3
ROM_DATA2
ROM_DATA1
ROM_DATA0
ROM_OEn
1
2
3
4
5
RED+
ROM_WEn
6
AVDD_RED_3.3
AGND_GREEN
GREEN-
ROM_CSn
7
CRVSS
8
CVDD_1.8
9
GREEN+
RESERVED
AVDD_LV_E_3.3
AVSS_LV_E
CH3P_LV_E/ER0
CH3N_LV_E/ER1
CLKP_LV_E/ER2
CLKN_LV_E/ER3
CH2P_LV_E/ER4
CH2N_LV_E/ER5
CH1P_LV_E/ER6
CH1N_LV_E/ER7
CH0P_LV_E/EG0
CH0N_LV_E/EG1
AVSS_LV_E
AVDD_LV_E_3..3
AVSS_LV
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
SOG_MCSS
AVDD_GREEN_3.3
AGND_BLUE
BLUE-
BLUE+
AVDD_BLUE_3.3
CRVSS
CVDD_1.8
RESERVED
VDD_RXPLL_1.8
GND_RXPLL
RESERVED
AVDD_RXC_3.3
RXC-
RXC+
AGND_RXC
AVDD_RX0_3.3
RX0-
AVDD_LV_3.3
AVDD_LV_O_3.3
AVSS_LV_O
CH3P_LV_O/EG2
CH3N_LV_O/EG3
CLKP_LV_O/EG4
CLKN_LV_O/EG5
CH2P_LV_O/EG6
CH2N_LV_O/EG7
CH1P_LV_O/EB0
CH1N_LV_O/EB1
CH0P_LV_O/EB2
CH0N_LV_O/EB3
AVSS_LV_O
AVDD_LV_O_3..3
CVDD_1..8
RX0+
AGND_RX0
VDD_RX0_1.8
AVDD_RX1_3.3
RX1-
RX1+
AGND_RX1
VDD_RX1_1.8
AVDD_RX2_3.3
RX2-
RX2+
AGND_RX2
VDD_RX2_1.8
AGND_IMB
REXT
CVSS
EB4
AVDD_IMB_3.3
VCLK
EB5
EB6
GPIO23/VDATA0
GPIO22/VDATA1
GPIO21/VDATA2
GPIO20/VDATA3
GPIO19/VDATA4
GPIO18/VDATA5
N/C
EB7
DEN
DHS
DVS
RVDD_3.3
CRVSS
N/C
Figure 2.
gm5221 Pin Out Diagram
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gm5221-LF-BC Multimedia LCD Controller Preliminary Data Sheet
3 gm5221 Pin List
I/O Legend: A = Analog, I = Input, O = Output, P = Power, G = Ground, N/C = No connect inside chip.
Table 1.
Analog Input Port
Pin Name
AVDD_BLUE_3.3
No I/O Description
141
AP
Analog power (3.3V) for the blue channel. Must be bypassed with capacitor to AGND_BLUE
pin on system board.
BLUE+
BLUE-
AGND_BLUE
142
143
144
AI
AI
AG
Positive analog input for Blue channel.
Negative analog input for Blue channel.
Analog ground for the blue channel. Must be directly connected to the analog system ground
plane.
AVDD_GREEN_3.3
SOG_MCSS
145
146
AP
I
Analog power (3.3V) for the green channel. Must be bypassed with capacitor to
AGND_GREEN pin on system board.
Dedicated Sync-on-Green pin.
NOTE: This pin requires the same AC-couple capacitor (if applicable) like the regular RGB
input pins. See 4.3.5
GREEN+
GREEN-
147
148
AI
AI
Positive analog input for Green channel.
Negative analog input for Green channel.
NOTE: For SOG support this pin should be pulled down to GND through a 1MΩ resistor. See
4.3.5
AGND_GREEN
AVDD_RED_3.3
149
150
AG
AP
Analog ground for the green channel. Must be directly connected to the analog system
ground plane.
Analog power (3.3V) for the red channel. Must be bypassed with capacitor to AGND_RED
pin on system board.
RED+
RED-
AGND_RED
151
152
153
AI
AI
AG
Positive analog input for Red channel.
Negative analog input for Red channel.
Analog ground for the red channel. Must be directly connected to the analog system ground
plane.
AVDD_ADC_3.3
154
AG
Analog power (3.3V) for ADC analog blocks that are shared by all three channels. Includes
bandgap reference, master biasing and full scale adjust. Must be bypassed with capacitor to
AGND_ADC pin on system board.
AGND_ADC
156
AG
Analog ground for ADC analog blocks that are shared by all three channels. Includes
bandgap reference, master biasing and full scale adjust. Must be directly connected to
analog system ground plane.
GND1_ADC
VDD1_ADC_1.8
HSYNC/CSYNC
VSYNC
163
164
181
182
AG
Digital GND for ADC clocking circuit. Must be directly connected to the digital system ground
plane
AP
Digital power (1.8V) for ADC encoding logic. Must be bypassed with capacitor to
GND1_ADC pin on system board.
I
I
ADC input horizontal sync or composite sync input.
[Input, Schmitt trigger with 1V hysteresis and 1.65V threshold, 5V-tolerant]
ADC input vertical sync.
[Input, Schmitt trigger with 1V hysteresis and 1.65V threshold, 5V-tolerant]
Table 2.
No I/O Description
DVI Input Port
Pin Name
AVDD_IMB_3.3
113
AP
Analog VDD (3.3V) for internal biasing circuits. Must be bypassed with capacitors
REXT
114
AI
External termination resistor.
A 1% 250Ω resistor should be connected from this pin to AVDD_IMB.
Analog GND for internal biasing circuits. Must be connected directly to the ground plane.
VDD (1.8V) for TMDS input pair 2.
AGND_IMB
VDD_RX2_1.8
115
116
AG
AP
Must be bypassed with external capacitor to GND_RX2.
Analog GND for TMDS input pair 2. Must be connected directly to the analog ground plane.
TMDS input pair 2
AGND_RX2
RX2+
RX2-
AVDD_RX2_3.3
VDD_RX1_1.8
AGND_RX1
RX1+
117
118
119
120
121
122
123
AG
AI
AI
AP
AP
AG
AI
TMDS input pair 2
Analog VDD (3.3V) for TMDS input pair 2. Must be bypassed with capacitor to AGND_RX2.
VDD (1.8V) for TMDS input pair 2. Must be bypassed with external capacitor to GND_RX1.
Analog GND for TMDS input pair 1. Must be connected directly to the analog ground plane.
TMDS input pair 1
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gm5221-LF-BC Multimedia LCD Controller Preliminary Data Sheet
Pin Name
RX1-
AVDD_RX1_3.3
VDD_RX0_1.8
AGND_RX0
RX0+
RX0-
AVDD_RX0_3.3
AGND_RXC
No I/O Description
124
125
126
127
128
129
130
131
AI
AP
AP
AG
AI
AI
AP
AG
TMDS input pair 1
Analog VDD (3.3V) for TMDS input pair 2. Must be bypassed with to AGND_RX1.
VDD (1.8V) for TMDS input pair 2. Must be bypassed with external capacitor to GND_RX0.
Analog GND for TMDS input pair 0. Must be connected directly to the analog ground plane.
TMDS input pair 0
TMDS input pair 0
Analog VDD (3.3V) for TMDS input pair 2. Must be bypassed with capacitor to AGND_RX0.
Analog GND for TMDS input clock pair. Must be connected directly to the analog ground
plane.
RXC+
RXC-
AVDD_RXC_3.3
132
133
134
AI
AI
AP
TMDS input clock pair
TMDS input clock pair
Analog VDD (3.3V) for TMDS input clock pair.
Must be bypassed with 100pF capacitor to AGND_RXC.
Analog GND for the TMDS receiver internal PLL.
Must be connected directly to the analog ground plane.
Analog VDD (1.8V) for the TMDS receiver internal PLL.
Must be bypassed with a capacitor to AGND_RXPLL.
Reserved. Leave unconnected.
GND_RXPLL
VDD_RXPLL_1.8
CLK_OUT
136
137
138
AG
AP
AO
Table 3.
No I/O Description
RCLK PLL Pins
Pin Name
GND_RPLL
165
AG
Digital GND for ADC clocking circuit. Must be directly connected to the digital system ground
plane.
VDD_RPLL_1.8
AGND_RPLL
166
168
AP
AG
Digital power (1.8V) for ADC digital logic. Must be bypassed with capacitor to GND1_ADC.
Analog ground for the Reference DDS PLL. Must be directly connected to the analog system
ground plane.
XTAL
TCLK
AVDD_RPLL_3.3
169
170
171
AO
AI
AP
Crystal oscillator output.
Reference clock (TCLK) from the 14.3MHz crystal oscillator.
Analog VDD (3.3V)
Table 4.
No I/O Description
Input Video Port
Pin Name
VCLK
112
I
Video port data clock input. Up to 75Mhz
[Input, 5V-tolerant]
GPIO23/VDATA0
GPIO22/VDATA1
GPIO21/VDATA2
GPIO20/VDATA3
GPIO19/VDATA4
GPIO18/VDATA5
GPIO17/VDATA6
GPIO16/VDATA7
111
110
109
108
107
106
103
102
IO
Input YUV data in 8-bit BT656 or GPIO23:16 if VPORT is disabled.
[Bi-Directional, 5V-tolerant]
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Table 5.
No I/O Description
System Interface
Pin Name
GPIO0
81
82
83
84
85
88
89
90
91
92
93
98
99
100
101
69
77
78
IO
General-purpose input/output signals
GPIO1
[Bi-directional, Schmitt trigger, 5V-tolerant]
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7/IRQin
GPIO8/IRQout
GPIO9/SCL
GPIO10/SDA
GPIO11/PWM0
GPIO12/PWM1
GPIO13/PWM2
GPIO14/PWM3
GPIO15
DDC_SCL_VGA
DDC_SDA_VGA
DDC_SCL_DVI
DDC_SDA_DVI
RESETn
General-purpose input/output signal [Bi-directional, Schmitt trigger, 5V-tolerant] or OCM
interrupt and chip status.
IO
IO
General-purpose input/output signals [Bi-directional, Schmitt trigger, 5V-tolerant] or master
device on serial interface bus.
General-purpose input/output signal or PWM signals.
[Bi-directional, Schmitt trigger, 5V-tolerant]
IO
IO
General-purpose input/output signal [Bi-directional, Schmitt trigger, 5V-tolerant]
DDC2Bi clock for VGA Port
DDC2Bi data for VGA Port [internal 10KΩ pull-up resistor]
DDC2Bi and HDCP clock for DVI Port
DDC2Bi and HDCP data for DVI Port [internal 10KΩ pull-up resistor]
79
80
178
IO
IO
Hardware Reset (active low) [Schmitt trigger, 5v-tolerant]
Connect to ground with 0.01uF (or larger) capacitor. See section, Chip Initialization, for
detail
LBADC_VDD_3.3
LBADC_IN1
LBADC_IN2
LBADC_IN3
LBADC_RETURN
LBADC_GND
172
173
174
175
176
177
71
AP
AI
AI
Analog 3.3V power supply for general-purpose ADC
LBADC channel 1
LBADC channel 2
LBADC channel 3
Analog Ground (signal return path) for LBADC channels 1, 2 and 3
Ground
Host input clock or 186 UART Data In or JTAG clock signal.
[Input, Schmitt trigger, 5V-tolerant]
Host input data or 186 UART Data Out or JTAG mode signal.
[Bi-directional, Schmitt trigger, slew rate limited, 5V-tolerant]
JTAG data input signal.
JTAG data output signal.
JTAG reset signal.
AI
AG
AG
IO
HOST_SCL/UART_DI
HOST_SDA/UART_DO
72
IO
JTAG_TDI
JTAG_TDO
JTAG_RESET
66
64
56
IO
IO
IO
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Table 6.
LVDS Display Interface
Pin Name
No I/O Description
AVDD_LV_E_3.3
AVSS_LV_E
CH3P_LV_E
CH3N_LV_E
CLKP_LV_E
CLKN_LV_E
CH2P_LV_E
CH2N_LV_E
CH1P_LV_E
CH1N_LV_E
CH0P_LV_E
CH0N_LV_E
AVSS_LV_E
AVDD_LV_E_3.3
AVSS_LV
AVDD_LV_3.3
AVDD_LV_O_3.3
AVSS_LV_O
CH3P_LV_O
CH3N_LV_O
CLKP_LV_O
CLKN_LV_O
CH2P_LV_O
CH2N_LV_O
CH1P_LV_O
CH1N_LV_O
CH0P_LV_O
CH0N_LV_O
AVSS_LV_O
AVDD_LV_O_3.3
PPWR
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
67
68
43
44
45
46
47
48
49
AP
AG
O
O
O
O
O
O
O
O
O
O
AG
AP
AG
AP
AP
AG
O
O
O
O
O
O
O
O
O
Digital Power for LVDS outputs. Connect to digital 3.3V supply.
Ground for LVDS outputs.
Ground for LVDS outputs.
Digital Power for LVDS outputs. Connect to digital 3.3V supply.
Ground for LVDS outputs.
Analog Power for LVDS outputs. Connect to analog 3.3V supply.
Digital Power for LVDS outputs. Connect to digital 3.3V supply.
Ground for LVDS outputs.
O
AG
AP
O
O
O
O
O
O
O
Ground for LVDS outputs.
Digital Power for LVDS outputs. Connect to digital 3.3V supply.
Panel Power Control [Tri-state output, 5V- tolerant]
Panel Bias Control (backlight enable) [Tri-state output, 5V- tolerant]
Reserved. Leave unconnected.
Reserved. Leave unconnected.
Reserved. Leave unconnected.
PBIAS
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Reserved. Leave unconnected.
Reserved. Leave unconnected. (Display Enable for TTL interface)
Reserved. Leave unconnected. (Display Horizontal Sync for TTL interface)
Reserved. Leave unconnected. (Display Vertical Sync for TTL interface)
O
O
Table 7.
No I/O Description
For 8-bit panels
TTL Display Interface
Pin Name
For 6-bit panels
AVDD_LV_E_3.3
AVSS_LV_E
ER0
ER1
ER2
ER3
ER4
ER5
ER6
ER7
EG0
EG1
AVSS_LV_E
AVDD_LV_E_3.3
AVSS_LV
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
AP
AG
O
O
O
O
O
O
O
O
O
O
AG
AP
AG
Analog Power for TTL outputs. Connect to analog 3.3V supply.
Ground
Red channel bit 0
Red channel bit 1
Red channel bit 2
Red channel bit 3
Red channel bit 4
Red channel bit 5
Red channel bit 6
Red channel bit 7
Green channel bit 0
Green channel bit 1
Ground for TTL outputs.
Not used.
Not used.
Red channel bit 0
Red channel bit 1
Red channel bit 2
Red channel bit 3
Red channel bit 4
Red channel bit 5
Not used.
Not used.
Digital Power for TTL outputs. Connect to digital 3.3V supply.
Ground for TTL outputs.
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Pin Name
No I/O Description
For 8-bit panels
For 6-bit panels
AVDD_LV_3.3
AVDD_LV_O_3.3
AVSS_LV_O
EG2
EG3
EG4
EG5
EG6
EG7
EB0
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
43
44
45
46
47
48
49
55
67
68
AP
AP
AG
O
O
O
O
O
O
O
O
O
O
AG
AP
O
O
O
Digital Power for TTL outputs. Connect to digital 3.3V supply.
Digital Power for TTL outputs. Connect to digital 3.3V supply.
Ground for TTL outputs.
Green channel bit 2
Green channel bit 3
Green channel bit 4
Green channel bit 5
Green channel bit 6
Green channel bit 7
Blue channel bit 0
Blue channel bit 1
Blue channel bit 2
Blue channel bit 3
Ground
Green channel bit 0
Green channel bit 1
Green channel bit 2
Green channel bit 3
Green channel bit 4
Green channel bit 5
Not used.
Not used.
Blue channel bit 0
Blue channel bit 1
EB1
EB2
EB3
AVSS_LV_O
AVDD_LV_O_3.3
EB4
EB5
EB6
EB7
DEN
DHS
DVS
Digital Power for TTL outputs. Connect to digital 3.3V supply.
Blue channel bit 4
Blue channel bit 5
Blue channel bit 6
Blue channel bit 7
Display Enable.
Blue channel bit 2
Blue channel bit 3
Blue channel bit 4
Blue channel bit 5
O
O
O
O
O
O
O
Display Horizontal Sync.
Display Vertical Sync.
Display Pixel Clock
Panel Power Control [Tri-state output, 5V- tolerant]
Panel Bias Control (backlight enable) [Tri-state output, 5V- tolerant]
DCLK
PPWR
PBIAS
Note: TTL bus is single pixel per clock only.
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4 Functional Description
A functional block diagram is illustrated below. Each of the functional units shown is described in the
following sections.
EEPROM
Serial I/F
Keypad Sensing
Temp Sensor
Parallel
ROM IF
GPIO
XTAL
Digital PLL
Clock
3X General-
4 X
X86-style
External
ROM I/F
Back-light
Purpose ADC
PWM
Micro-controller
Generation
Reset
Host
On-chip
OSD
Circuit
Interface
RAM / ROM
Controller
Triple
ADC &
PLL
Analog
RGB
Histogram
ACC™
Luma
Ultra-
Reliable
DVI Rx
Y
Shaping
DVI
LVDS
Tx
Display
Control
LVDS
Panel I/F
HDCP
ACM-II™
Chroma
Adjust
ITU656
uv
Test
Pattern
High Light Window
Generator
Figure 3.
gm5221 Functional Block Diagram
4.1 Clock Generation
The gm5221 features three clock inputs. All additional clocks are internal clocks derived from one or
more of these:
1. Crystal Input Clock (TCLK and XTAL). This is the input pair to an internal crystal oscillator and
corresponding logic. A 14.3 MHz TV crystal is recommended. Other crystal frequencies may be used,
but require custom programming. This is illustrated in Figure 4 below.
2. DVI Differential Input Clock (RC+ and RC-)
3. Video Clock (VCLK)
4.1.1 Using the Internal Oscillator with External Crystal
An external crystal is used with an internal clock oscillator to provide a clock reference for the device. 14,
20, and 24 MHz crystals are supported.
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The oscillator circuit is designed to provide a very low jitter and very low harmonic clock to the internal
circuitry of the chip. An Automatic Gain Control (AGC) is used to insure startup and operation over a
wide range of conditions. The oscillator circuit also minimizes the overdrive of the crystal, which reduces
the aging of the crystal.
The state of the ROM_ADDR13 pin is sampled at reset (see section 4.14). If the pin is left unconnected
(internal pull-down) then internal oscillator is enabled. In this mode a crystal resonator is connected
between TCLK and the XTAL with the appropriately sized loading capacitors CL1 and CL2. The size of
C
L1 and CL2 are determined from the crystal manufacturer’s specification and by compensating for the
parasitic capacitance of the device and the printed circuit board traces. The loading capacitors are
terminated to the analog VDD power supply. This connection increases the power supply rejection ratio
when compared to terminating the loading capacitors to ground.
gm5221
Vdda
CL1
152
Vdd
TCLK
151
Vdda
OSC_OUT
XTAL
100 K
TCLK Distribution
CL2
180 uA
10
N/C
Reset State Logic
ROM_ADDR13
Internal Oscillator Enable
Internal Pull Down
Resistor
~ 60K
Figure 4.
Using the Internal Oscillator with External Crystal
The TCLK oscillator uses a Pierce Oscillator circuit. The output of the oscillator circuit, measured at the
TCLK pin, is an approximate sine wave with a bias of about 2 volts above ground (see Figure 5). The
peak-to-peak voltage of the output can range from 250 mV to 1000 mV depending on the specific
characteristics of the crystal and variation in the oscillator characteristics. The output of the oscillator is
connected to a comparator that converts the sine wave to a square wave. The comparator requires a
minimum signal level of about 50-mV peak to peak to function correctly. The output of the comparator is
buffered and then distributed to the internal circuits.
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3.3 Volts
~ 2 Volts
250 mV peak to peak
to
1000 mV peak to peak
time
Figure 5.
Internal Oscillator Output
One of the design parameters that must be given some consideration is the value of the loading capacitors
used with the crystal as shown in Figure 6. The loading capacitance (Cload) on the crystal is the
combination of CL1 and CL2 and is calculated by Cload = ((CL1 * CL2) / (CL1 + CL2)) + Cshunt. The shunt
capacitance Cshunt is the effective capacitance between the XTAL and TCLK pins. For the gm5221 this is
approximately 9 pF. CL1 and CL2 are a parallel combination of the external loading capacitors (Cex), the
PCB board capacitance (Cpcb), the pin capacitance (Cpin), the pad capacitance (Cpad), and the ESD
protection capacitance (Cesd). The capacitances are symmetrical so that CL1 = CL2 = Cex + CPCB + Cpin
+
Cpad + CESD. The correct value of Cex must be calculated based on the values of the load capacitances.
Approximate values are provided in Figure 6.
CL1 = Cex1 + Cpcb + Cpin + Cpad + Cesd
Vdda
Cex1
Cpcb
Cpin
Cpad
Cesd
Cesd
141
Internal Oscillator
TCLK
gm5221
Cshunt
142
Vdda
XTAL
Cex2
Cpcb
Cpin
Cpad
Approximate values:
CPCB ~ 2 pF to 10 pF (layout dependent)
Cpin ~ 1.1 pF
Cpad ~ 1 pF
CL2 = Cex1 + Cpcb + Cpin + Cpad + Cesd
Cesd ~ 5.3 pF
Cshunt ~ 9 pF
Figure 6.
Sources of Parasitic Capacitance
Some attention must be given to the details of the oscillator circuit when used with a crystal resonator.
The PCB traces should be as short as possible. The value of Cload that is specified by the manufacturer
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should not be exceeded because of potential start up problems with the oscillator. Additionally, the crystal
should be a parallel resonate-cut and the value of the equivalent series resistance must be less then 90 Ω.
4.1.2 Clock Synthesis
The gm5221 synthesizes additional clocks using PLLs as follows:
1) T_CLK - Main Timing Clock is the output of the chip internal crystal oscillator. T_CLK is derived
from the TCLK/XTAL pad input.
2) R_CLK - Reference Clock synthesized by RCLK PLL using T_CLK or EXTCLK as the reference.
RCLK PLL output port is not to exceed 4 standard loads.
3) DVI_CLK - DVI Output Clock synthesized by DVI receiver PLL using RC+/RC-as the reference.
4) S_CLK - Input Source Clock synthesized by SDDS PLL using input HS as the reference. The SDDS
also uses the R_CLK to drive internal digital logic.
5) D_CLK - Display Clock synthesized by DDDS PLL using IP_CLK as the reference. The DDDS also
uses the R_CLK to drive internal digital logic.
6) F_CLK - Fixed Frequency Clock synthesized by FDDS. Used as OCM_CLK domain driver.
7) ADC_DEL_ACLK - ADC Output Clock is a delayed A_CLK. The analog ADC performs the delay
adjustment.
S_CLK
D_CLK
INT_HS
XTAL
SDDS
IP_CLK
DDDS
T_CLK
TCLK
REF1
REF2
RCLK
PLL
FDDS
F_CLK
R_CLK
EXTCLK
RC+
RC-
DVI_CLK
DVI RX
Figure 7.
Internally Synthesized Clocks
The on-chip clock domains are selected from the synthesized clocks as shown in Figure 8 below. These
include:
1) IP_CLK - Input Clock Domain
2) OCM_CLK - Host Interface and On-chip Micro-controller Clock
3) DP_CLK – Scaling Filter and Display Pixel Clock
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4) IFM_CLK - Source Timing Measurement Domain
5) A_CLK - ADC Clock Domain
The clock selection for each domain as shown in the figure below is controlled using the
CLOCK_CONFIG register.
DVI_CLK
F_CLK
A_CLK
IP_CLK
OCM_CLK
A_CLK
T_CLK
ADC_DEL_ACLK
VCLK
DDDS_CLK
IP_CLK
TCLK
IFM_CLK
SDDS_CLK
DP_CLK
Figure 8.
On-chip Clock Domains
4.2 Chip Initialization
4.2.1 Hardware Reset
The gm5221 device integrated a Reset Pulse generator, so that a Reset IC is not required externally.
Hardware Reset is performed by an internal Reset Pulse generator, or by holding the RESETn pin low for
a minimum of 150ms. The Reset Pulse is around 150ms in duration, a low-true output on pin RESETn. A
TCLK input (see Clock Options above) must be applied during and after the reset. When the reset period
is complete and RESETn is de-asserted, the power-up sequence is as follows:
1. Reset all registers of all types to their default state (this is 00h unless otherwise specified in the
gm5221 Register Listing).
2. Force each clock domain into reset. This continues for 64 local clock domain cycles following the
de-assertion of RESETn.
3. Operate the OCM_CLK domain at the TCLK frequency.
4. Preset the RCLK PLL to output ~200MHz clock (assumes 14.3MHz TCLK crystal frequency).
Figure 9 below shows the relationship between RESETn and 3.3V AVDD power rail (AVDD_3.3): Tr is
the reset active period, and Tp is the hold time of push button that grounds RESETn pin.
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AVDD_3.3
3.3V
2.5V
t
Push reset
button
Reset button
released
RESETn
3.3V
t
Tp
Tr
Tr
Push Button hold time
Figure 9.
Reset Pulse vs. +3.3V_AVDD power line
Where
Table 8.
RESET Time
RESETn active period (Tr) specification
Min
Max
160
Tr
100
The reset threshold for the 3.3V AVDD power rail is 2.5V, and a glitch filter in the reset circuitry will
ignore the AVDD_3.3 glitch if the glitch duration is less than 100 ns. However, if AVDD_3.3 voltage
drops below 2.5V and the glitch duration is more than 100ns, the RESETn will be asserted to reset the
chip. Figure 10 below illustrates the AVDD_3.3V glitch that will cause RESETn to be asserted.
Td
AVDD_3.3
AVDD
2.5
Vg
t
0
Td = Duration of AVDD_3.3 glitch
Vg = Voltage level of AVDD_3.3 glitch
Figure 10.
Glitch in 3.3V AVDD
Table 9.
Requirement for RESETn due to Glitch in AVDD_3.3V
Requirement for RESETn due to AVDD_3.3V glitch
Min
Max
Td
Vg
100ns
2.5V
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Note: The RESETn pin should be connected to ground with a 0.01uF capacitor to avoid spontaneous reset
conditions.
4.2.2 Power Sequencing
At any time during the power-up sequence the actual voltage of the 3.3V RVDD power supply should
always be equal to or higher than the actual voltage of the 1.8V CVDD power supply. In mathematical
terms, VRVDD >= VCVDD at all times. This is illustrated in 0.
In addition, the system designer must ensure that the 1.8V core VDD supply must be active for at least
1ms before the rising edge of the chip RESETn signal during the chip power-up sequence. The rising
edge of RESETn signal is used to latch the bootstrap configurations, so its correct timing relationship to
the core VDD is critical for correct chip operation.
Parameter
VRVDD-CVDD(for all t>0)
TCVDD->RESETn
Min
0V
150ms
Typ
Max
Voltage
RVDD (3.3V)
CVDD (1.8V)
VRVDD-CVDD(t)
TCVDD->RESETn
Time
t
Voltage
RESETn
0V
Time
Figure 11.
Correct Power Sequencing
4.3 Analog to Digital Converter (ADC)
4.3.1 ADC Pin Connection
The analog RGB signals are connected to the gm5221 as described below:
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Table 10. Pin Connection for RGB Input with HSYNC/VSYNC
Pin Name
ADC Signal Name
Red+
Red-
Red
Terminate as illustrated in Figure 12.
SOG_MCS
Green+
Green-
Blue+
Blue-
HSYNC
Dedicated Sync-on-Green pin
Green
Terminate as illustrated in Figure 12.
Blue
Terminate as illustrated in Figure 12.
Horizontal Sync. Terminate as illustrated in Figure 12.
Vertical Sync. Terminate as with HSYNC illustrated in Figure 12.
VSYNC
20Ω
RED +
0.01uF
75Ω
57.6Ω
RED -
RED
Pin #1
0.01uF
gm5221
20Ω
470Ω
GREEN
Pin #2
SOG_MCSS
0.01uF
GREEN +
DB15
75Ω
BLUE
Pin #3
0.01uF
57.6Ω
HSYNC
Pin #13
GREEN -
0.01uF
VSYNC
Pin #14
20Ω
BLUE +
GND
Pin
#5,6,7,8
0.01uF
75Ω
57.6Ω
BLUE -
0.01uF
HSYNC
HS
VS
VSYNC
Figure 12.
Example ADC Signal Terminations
Note that if Sync-On-Green (SoG) or Sync-On-Y (SoY) is not required then SOG_MCSS pin should be
left unconnected.
Note that it is important to follow the recommended layout guidelines (see the system layout guidelines).
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Also note that the ADC can be used to sample analog signals in the YPbPr color space. In this case the
digital color controls are used to convert these signals to the RGB color domain for display on the LCD
panel.
4.3.2 ADC Characteristics
The table below summarizes the characteristics of the ADC:
Table 11. ADC Characteristics
MIN
TYP
MAX NOTE
290 MHz Guaranteed by design. Note that the Track &
Hold Amp Bandwidth is programmable. 290
MHz is the maximum setting.
Track & Hold Amp Bandwidth
Full Scale Adjust Range at RGB Inputs
Full Scale Adjust Sensitivity
0.55 V
0.90 V
+/- 1 LSB
+/- 1 LSB
+/-0.5 LSB
Measured at ADC Output.
Independent of full scale RGB input.
Measured at ADC Output.
162.5 MHz
+/-0.9 LSB Fs = 135 MHz
Guaranteed by test.
Fs =135 MHz
Zero Scale Adjust Sensitivity
Sampling Frequency (Fs)
Differential Non-Linearity (DNL)
No Missing Codes
Integral Non-Linearity (INL)
Channel to Channel Matching
10 MHz
+/- 1.5 LSB
+/- 0.5 LSB
Note that input formats with resolutions or refresh rates higher than that supported by the LCD panel are
supported as recovery modes only. This is called RealRecovery™. For example, it may be necessary to
shrink the image. This may introduce image artifacts. However, the image is clear enough to allow the
user to change the display properties.
The ADC has a built in clamp circuit for AC-coupled inputs. By inserting series capacitors (about 10 nF),
the DC offset of an external video source can be removed. The clamp pulse position and width are
programmable.
4.3.3 Clock Recovery Circuit
The SDDS (Source Direct Digital Synthesis) clock recovery circuit generates the clock used to sample
analog RGB data (ACLK or source clock). This circuit is locked to HSYNC of the incoming video signal.
Patented digital clock synthesis technology makes the clock circuits resistant to temperature/voltage drift.
Using DDS (Direct Digital Synthesis) technology, the clock recovery circuit can generate any ACLK
clock frequency within the range of 10MHz to 165MHz.
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BLUE
GREEN
B
G
RED
R
ACLK
SCLK
HS
input HS
SDDS
SCLK
ACLK
Input Analog
Video
Phase Delay
Input HSync
SCLK
ACLK
Phase
Delay
Figure 13.
gm5221 Clock Recovery
4.3.4 Sampling Phase Adjustment
The programmable ADC sampling phase is adjusted by delaying the (input HSYNC aligned) SCLK to
produce the ADC clock (ACLK) inside the SDDS. The phase delay is programmable in 64 steps as a
fraction of the ACLK period. The accuracy of the sampling phase is checked and the result read from a
register. This feature enables accurate auto-adjustment of the ADC sampling phase.
4.3.5 SOG and CSYNC support
The gm5221 has the capability to support the following types of SOG and CSYNC inputs without having
to use external components. The signals below show the Negative types of SOG and CSYNC signals. The
gm5221 can also support the Positive types.
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XOR - CSYNC
NOR – CSYNC: OFF SERRATION: OFF
SERRATED (0.5 H)
Figure 14.
Supported SOG and CSYNC signals
4.4 Ultra-Reliable Digital Visual Interface Receiver (DVI Rx)
The Ultra-Reliable DVITM receiver block of the gm5221 is compliant with DVI 1.0 single link
specifications. Digital Visual Interface (DVI) is a standard. This block supports an input clock frequency
ranging from 20 MHz to 165 MHz.
4.4.1 DVI Receiver Characteristics
Please note that it is very important to follow the recommended layout guidelines for these signals.
Table 12. DVI Receiver Characteristics
MIN
TYP
MAX
NOTE
DC Characteristics
Differential Input Voltage
150mV
AVDD
–300m V
AVDD
-10mV
1200mV
Input Common Mode Voltage
AVDD
-37mV
AVDD
+10mV
Behavior when Transmitter Disable
AC Characteristics
Input clock frequency
20 MHz
150mV
165 MHz
Input differential sensitivity (Peak-to-peak)
Max differential input (peak-to-peak)
Allowable Intra-Pair skew at Receiver
Allowable Inter-Pair skew at Receiver
1560 mV
250 ps
4.0 ns
Input clock = 160 MHz
Through register programming, the receiver unit may be placed in one of three states:
•
•
Active: The receiver block is fully on and running.
Standby: RC (clock) channel and the data channel carrying syncs remain active. Data and other control signals
are not decoded.
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•
Off: The receiver block is powered down.
4.4.2 High-Bandwidth Digital Content Protection (HDCP)
NOTE: This section applies to the HDCP enabled version gm5221H only. HDCP is disabled in the non-
HDCP enabled version gm5221.
The HDCP system allows authentication of a video receiver by a video transmitter, decryption of
transmitter-encoded video data by the receiver, and periodic renew-ability of authentication during
transmission. The gm5221 implements circuitry to allow full support of the HDCP 1.0 protocol for DVI
inputs.
For enhanced security, Genesis provides a means of storing and accessing the secret key given to
individual monitor units in an encrypted format.
Further details of the protocol and theory of the system can be found in the High-bandwidth Digital
Content Protection System specification (see www.digital-cp.com).
4.5 ITU656 Video Input Port
The ITU656 video input port connects to commercially available NTSC or PAL video decoders. ITU-BT-
656 video format consists of pixel clock and 8 bits of data. No separate HSYNC, VSYNC signals are
required. The internal 656 decoder extracts these from the embedded timing data.
VCLK
YUV(7:0)
Blanking
FF
00
00 SAV Cb
Y
1
Cr
2
Y
3
Cb
4
Y
5
Cr
Y
Cb
FF
00
00 EAV Blanking
(Input)
1710 1711 1712 1713 1714 1715
Preamble
0
1437 1438 1439 1440 1441 1442 1443 1444
Preamble
Active Video
Timing Reference word
Timing Reference word
SAV (Start of Active Video)
EAV (End of Active Video)
Figure 15.
ITU-R BT656 Input Format
YCbCr input to the gm5221 is always automatically clamped to restrict the input data to ITU-R BT601
levels:
•
•
•
•
Y Bottom clamping:
Y Top clamping:
CbCr Bottom clamping:
CbCr Top clamping:
Y data < 16 is clamped to 16.
Y data > 235 is clamped to 235.
CbCr data < 16 is clamped to 16.
CbCr data > 240 is clamped to 240.
4.6 Test Pattern Generator (TPG)
gm5221 contains a number of preset test patterns, some of which are shown in Figure 16. There are also
parameter based test patterns for generating ramps and grids. Once programmed, the gm5221 test pattern
generator can replace a video source (e.g. a PC) during factory calibration and test. This simplifies the test
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procedure and eliminates the possibility of image noise being injected into the system from the source.
The foreground and background colors are programmable. In addition, the gm5221 OSD controller can be
used to produce other patterns.
Figure 16.
Some of gm5221 Built-in Test Patterns
4.7 Input Format Measurement
The gm5221 has an Input Format Measurement block (the IFM) providing the capability of measuring the
horizontal and vertical timing parameters of the input video source. This information may be used to
determine the video format and to detect a change in the input format. It is also capable of detecting the
field type of interlaced formats.
The IFM features a programmable reset, separate from the regular gm5221 soft reset. This reset disables
the IFM, reducing power consumption. The IFM is capable of operating while gm5221 is running in
power down mode.
Horizontal measurements are measured in terms of the selected IFM_CLK (either TCLK or RCLK/4),
while vertical measurements are measured in terms of HSYNC pulses.
4.7.1 HSYNC / VSYNC Delay
The active input region captured by the gm5221 is specified with respect to internal HSYNC and
VSYNC. By default, internal syncs are equivalent to the HSYNC and VSYNC at the input pins and thus
force the captured region to be bounded by external HSYNC and VSYNC timing. However, the gm5221
provides an internal HSYNC and VSYNC delay feature that removes this limitation.
This HSYNC and VSYNC delay is used for image positioning of ADC input data. HSYNC is delayed by
a programmed number of selected input clocks.
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active data crosses HS boundary
delayed HS placed safely within blanking
Data
HS (system)
Internal Delayed HS
Figure 17.
Active Data Crosses HSYNC Boundary
4.7.2 Horizontal and Vertical Measurement
The IFM is able to measure the horizontal period and active high pulse width of the HSYNC signal, in
terms of the selected clock period (either TCLK or RCLK/4.). Horizontal measurements are performed on
only a single line per frame (or field). The line used is programmable. It is able to measure the vertical
period and VSYNC pulse width in terms of rising edges of HSYNC.
Once enabled, measurement begins on the rising VSYNC and is completed on the following rising
VSYNC. Measurements are made on every field / frame until disabled.
4.7.3 Format Change Detection
The IFM is able to detect changes in the input format relative to the last measurement and then alert both
the system and the on-chip microcontroller. The microcontroller sets a measurement difference threshold
separately for horizontal and vertical timing. If the current field / frame timing is different from the
previously captured measurement by an amount exceeding this threshold, a status bit is set. An interrupt
can also be programmed to occur.
4.7.4 Watchdog
The watchdog monitors input VSYNC / HSYNC. When any HSYNC period exceeds the programmed
timing threshold (in terms of the selected IFM_CLK), a register bit is set. When any VSYNC period
exceeds the programmed timing threshold (in terms of HSYNC pulses), a second register bit is set. An
interrupt can also be programmed to occur.
4.7.5 Internal Odd/Even Field Detection (For Interlaced Inputs to ADC Only)
The IFM has the ability to perform field decoding of interlaced inputs to the ADC. The user specifies start
and end values to outline a “window” relative to HSYNC. If the VSYNC leading edge occurs within this
window, the IFM signals the start of an ODD field. If the VSYNC leading edge occurs outside this
window, an EVEN field is indicated (the interpretation of odd and even can be reversed). The window
start and end points are selected from a predefined set of values.
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HS
window
Window
Start
Window End
VS - even
VS - odd
Figure 18.
ODD/EVEN Field Detection
4.7.6 Input Pixel Measurement
The gm5221 provides a number of pixel measurement functions intended to assist in configuring system
parameters such as pixel clock, SDDS sample clocks per line and phase setting, centering the image, or
adjusting the contrast and brightness.
4.7.7 Image Phase Measurement
This function measures the sampling phase quality over a selected active window region. This feature
may be used when programming the source DDS to select the proper phase setting.
4.7.8 Image Boundary Detection
The gm5221 performs measurements to determine the image boundary. This information is used when
programming the Active Window and centering the image.
4.7.9 Image Auto Balance
The gm5221performs MIN and MAX pixel value measurements on the input data that is used to adjust
brightness and contrast.
4.8 Intelligent Image Processing™ Zoom/Shrink/Sharpening Filter
4.8.1 Variable Zoom Scaling
The scaling engine uses an advanced third generation multi-tap, non-linear scaling engine, which uses
FIR filter technique and can accept nearly any input resolution and can scale it to any output resolution, in
a range from one-half reduction to a 256-fold expansion. Scaling is highly configurable, with options to
scale in both horizontal and vertical directions with different methods. The scalar must scale nearly any
signal input to accommodate nearly any panel input. Moreover, it provides high quality scaling of real
time video and graphics images. An input field/frame is scalable in both the vertical and horizontal
dimensions.
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Interlaced fields may be spatially de-interlaced by vertically scaling and repositioning the input fields to
align with the output display’s pixel map.
4.8.2 Horizontal and Vertical Shrink
A shrink function may be performed on the input data. This is an arbitrary horizontal/vertical reduction to
between (50% + 1 pixel/line) to 100% of the input. For example, this allows UXGA 1600x1200 pixels to
be displayed as SXGA 1280x1024. For example, this is useful to allow the user to use Windows Display
Properties to reduce the screen resolution if it is higher than that of the display.
4.8.3 Programmable Sharpening Filter
The coefficients used in the scaling engine are programmable and can be used to perform sharpening. For
example, font edges can be enhanced in text or spreadsheet applications, or motion video images can be
sharpened. This is available at any scale factor, or when scaling is not required (i.e. 1:1 mode).
4.9 Advanced Digital Color Controls
The digital color controls consist of the components shown in Figure 19.
A C C
8
8
8
8
Adaptive
C ontrast
R /Y
G /U
B /V
R
G
Y U V
to
R G B
to
8
8
A C M -II
yc lin k
R G B
(3x3)
Y U V
B
Adaptive
Color
Figure 19.
4.9.1 Adaptive Contrast and Color (ACC)
Digital Color Controls
Most video content is tailored for display on CRTs or in movie theatres. However, CRT monitors have a
wider dynamic range than LCD monitors. Therefore, it is desirable to enhance the dynamic range when
video is displayed using LCD monitors.
ACC enhances the contrast of the image to account for this. This makes dark colors darker, and bright
colors brighter. In addition, the contrast enhancement is adaptive. That is, dark scenes are transformed in
a way that preserves color resolution of darker colors and bright scenes are transformed in a way that
preserves the color resolution of brighter colors. This is done by calculating a running average of the
luminance content of the image, divided up into three ranges. This histogram is then used to select the
weighting coefficients between three different luminance transfer functions. The running average may be
applied over a programmable number of frames.
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ACC can be applied within a highlight window or over the full display area.
4.9.2 Active Color Management–II (ACM-II)
Active Color Management provides TV style control of global color parameters like hue, saturation and
contrast, and local color changes such as skin tone adjustment, green enhance, or blue stretch. It can be
applied within a highlight window or over the full display area.
4.9.3 Gamma Look-Up-Table (LUT)
An 8 to 10-bit look-up table (LUT) for each input color channel is intended for Gamma correction and to
compensate for a non-linear response of the LCD panel. A 10-bit output results in an improved color
depth control. The 10-bit output is then dithered down to 8 bits (or 6 bits) per channel at the display. The
LUT is user-programmable to provide an arbitrary transfer function. Gamma correction occurs after the
zoom / shrink scaling block. If bypassed, the LUT does not require programming.
4.9.4 Color Standardization and sRGB Support
Internet shoppers may be very picky about what color they experience on the display. gm5221
RealColorTM digital color controls can be used to make the color response of an LCD monitor compliant
with standard color definitions, such as sRGB. sRGB is a standard for color exchange proposed by
Microsoft and HP (see www.srgb.com). gm5221 RealColor controls can be used to make LCD monitors
sRGB compliant, even if the native response of the LCD panel itself is not. For more information on
sRGB compliance using Genesis devices please refer to the sRGB application brief C5115-APB-02A.
4.9.5 Video Windowing
Often video content (e.g. movie from DVD) is displayed in a portion of the display while the operating
system’s desktop appears in the remainder. In this case it is desirable to have different color controls in
the various regions of the display. For example, the user may desire that the desktop is sRGB compliant
while performing hue or saturation adjustments in the region containing the video content. To perform
such adjustments the 3x3 color controls and the gamma tables may be separately controlled inside and
outside a defined rectangle. The coordinates of the rectangle may be provided by the operating system
(and communicated using DDC2Bi) or selected by the user (using the OSD).
4.10 Display Output Interface
The Display Output Port provides data and control signals that permit the gm5221 to connect to a variety
of flat panel devices using an LVDS interface. The output interface is configurable for single or dual
wide LVDS in 18 or 24-bit RGB pixels format. All display data and timing signals are synchronous with
the DCLK display clock. The integrated LVDS transmitter is programmable to allow the data and control
signals to be mapped into any sequence depending on the specified receiver format. DC balanced
operation is supported as described in the Open LDI standard.
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4.10.1 Display Synchronization
The gm5221 supports the following display synchronization modes:
•
Frame Sync Mode: The display frame rate is synchronized to the input frame or field rate. This mode
is used for standard operation.
•
Free Run Mode: No synchronization. This mode is used when there is no valid input timing (i.e. to
display OSD messages or a splash screen) or for testing purposes. In free-run mode, the display
timing is determined only by the values programmed into the display window and timing registers.
4.10.2 Display Timing Programming
Horizontal values are programmed in single-pixel increments relative to the leading edge of the horizontal
sync signal. Vertical values are programmed in line increments relative to the leading edge of the vertical
sync signal.
DH_BKGND_START
DH_BKGND_END
DV_VS_END
VSYNC Region
Vertical Blanking (Back Porch)
DV_BKGND_START
DV_ACTIVE_START
Display Background Window
Display Active Window
DV_ACTIVE_LENGTH
DV_BKGND_END
Vertical Blanking (Front Porch)
DH_TOTAL
DHS
DEN **
DH_HS_END
** DEN is not asserted during vertical blanking
DH_ACTIVE_WIDTH
DH_ACTIVE_START
Figure 20.
Display Windows and Timing
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4.10.3 Output Dithering
The Gamma LUT outputs a 10-bit value for each color channel. This value is dithered down to either 8-
bits for 24-bit per pixel panels, or 6-bits for 18-bit per pixel panels. In this way it is possible to display
16.7 million colors on a LCD panel with 6-bit column drivers.
The benefit of dithering is that the eye tends to average neighboring pixels and a smooth image free of
contours is perceived. Dithering works by spreading the quantization error over neighboring pixels both
spatially and temporally. Two dithering algorithms are available: random or ordered dithering. Ordered
dithering is recommended when driving a 6-bit panel.
All gray scales are available on the panel output whether using 8-bit panel (dithering from 10 to 8 bits per
pixel) or using 6-bit panel (dithering from 10 down to 6 bits per pixel).
4.10.4 Dual Four-Channel LVDS Transmitter
gm5221 implements the industry standard flexible four channel dual LVDS transmitter. The LVDS
transmitter can support the following:
•
•
•
•
•
•
Single pixel mode
24-bit panel mapping to the LVDS channels
18-bit panel mapping to the LVDS channels
Programmable channel swapping (the clocks are fixed)
Programmable channel polarity swapping
Supports up to SXGA 75Hz output
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Table 13. Supported LVDS 24-bit Panel Data Mappings
Channel 0
Channel 1
Channel 2
Channel 3
R0, R1, R2, R3, R4, R5, G0
G1, G2, G3, G4, G5, B0, B1
B2, B3, B4, B5, PHS, PVS, PDE
R6, R7, G6, G7, B6, B7, RES
Channel 0
Channel 1
Channel 2
Channel 3
R2, R3, R4, R5, R6, R7, G2
G3, G4, G5, G6, G7, B2, B3
B4, B5, B6, B7, PHS, PVS, PDE
R0, R1, G0, G1, B0, B1, RES
Table 14. Supported LVDS 18-bit Panel Data Mapping
Channel 0
Channel 1
Channel 2
Channel 3
R0, R1, R2, R3, R4, R5, G0
G1, G2, G3, G4, G5, B0, B1
B2, B3, B4, B5, PHS, PVS, PDE
Disabled for this mode
4.10.5 Single Pixel TTL Output
DCLK (Output)
DEN (Output)
ER/EG/EB
(Output)
XXX
rgb0
rgb1
rgb2
rgb3
rgb4
Figure 21.
Single Pixel Width Display Data
4.10.6 Panel Power Sequencing (PPWR, PBIAS)
The gm5221 has two dedicated outputs PPWR and PBIAS to control LCD power sequencing once data
and control signals are stable. The timing of these signals is fully programmable.
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TMG1
TMG2
TMG3
TMG4
PPWR Output
Panel Data and Control Signals
PBIAS Output
<State0>
<State1>
<State2>
<State3>
<State2>
<State1> <State0>
POWER_SEQ_EN = 1
POWER_SEQ_EN = 0
Figure 22.
Panel Power Sequencing
4.11 Energy Spectrum Management (ESM)
High spikes in the EMI power spectrum may cause LCD monitor products to violate emissions standards.
The gm5221 has many features that can be used to reduce electromagnetic interference (EMI). These
include drive strength control and clock spectrum modulation. These features help to eliminate the costs
associated with EMI reducing components and shielding.
4.12 On-Screen Display (OSD)
The gm5221 has a fully programmable, high-quality OSD controller. The graphics are divided into “cells”
of programable size. The cells are stored in an on-chip static RAM (16K bytes) and can be stored as 1-bit
per pixel data, 2-bit per pixel data or 4-bit per pixel data.
Some general features of the gm5221 OSD controller include:
•
Two OSD Rectangles – The OSD can appear in two separately defined rectangular regions.
OSD Position – The OSD menu can be positioned anywhere on the display region. The
•
reference point is Horizontal and Vertical Display Background Start (DH_BKGND_START and
DV_BKGND_START).
•
OSD Stretch – The OSD image can be stretched horizontally and/or vertically by a factor of two.
Pixel and line replication is used to stretch the image.
•
OSD Blending – Sixteen levels of blending are supported for selected colors in the character-
mapped.
4.12.1 On-Chip OSD SRAM
The on-chip static RAM (16K bytes) stores the cell map, cell definitions, and attribute map. The OSD
SRAM is shared by the on-chip microcontroller as part of its normal addressable memory space.
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In memory, the cell map is organized as an array of words, each defining the attributes of one visible
character on the screen starting from upper left of the visible character array. These attributes specify
which character to display, whether it is stored as 1, 2 or 4 bits per pixel, the foreground and background
colors, blinking, etc.
Registers are used to define the visible area of the OSD image. For example, Figure 23 shows an example
of a cell map.
Address 1:
Address 25:
Attributes for
Cell Attributes for
upper-left hand cell
upper-right hand cell
OSD_R_WIDTH
Address26:
Cell attributes for
1st cell, 2nd row
Brightness
Contrast
OSD_R_HEIGHT
Figure 23.
OSD Cell Map
Cell definitions are stored as bit map data. On-chip registers point to the start of 1-bit per pixel
definitions, 2-bit per pixel definitions and 4-bit per pixel definitions respectively.
Note that the cell map and the cell definitions share the same on-chip RAM. Thus, the size of the cell map
can be traded off against the number of different cell definitions. In particular, the size of the OSD image
and the number of cell definitions must fit in RA<.
4.12.2 Color Look-up Table (LUT)
Each pixel of a displayed cell is resolved to an 8-bit color code. This selected color code is then
transformed to a 24-bit value using a 256 x 24-bit look up table.
4.13 On-Chip Microcontroller (OCM)
The OCM executes a firmware program running from external ROM. A parallel port with separate
address and data busses is available for this purpose. Alternatively, a serial peripheral interface (SPI) may
be used with a serial FLASH ROM and a cache controller inside gm5221. This port connects directly to
standard, commercially available ROM or programmable FLASH ROM devices. Normally 64KB or
128KB of ROM is required.
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4.13.1 Compiling firmware
To program the gm5221 the content of the external ROM is generated using Genesis software
development tools G-Wizard and OSD-Workbench. G-Wizard is a GUI-based tool for capturing system
information such as panel timing, support modes, system configuration, etc. OSD-Workbench is a GUI
based tool for defining OSD menus and functionality.
G-Wizard
OSD Workbench
gm5221 Driver
gm5221 Driver
Firmware source files (*.c *.h)
Compiler
External ROM
Image File (.hex)
Controller
Board
gm5220/21
ROM
OCM
Figure 24.
Programming the OCM
Genesis recommends using Paradigm compiler (http://www.devtools.com) to compile the firmware
source code into a hex file. This hex file is then downloaded into the external ROM using In-System-
Programming (Genesis debug software G-Probe communicates with the OCM which in turn programs a
FLASH ROM in the system using the ROM_WEn signal) or using commercially available ROM
programmers.
4.13.2 Embedded Bootstrap Function
gm5221 is equipped with an embedded ROM bootstrap function from which to boot when external ROM
is not present or it does not contain data. It is always recommended to boot from embedded ROM (see
description of ROM_ADDR16 in Table 16).
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The bootstrap function works in the following way. The embedded ROM firmware first looks for a
‘signature’ in external ROM (either parallel ROM or serial ROM depending on the programming of
ROM_ADDR15 – see Table 16). The ‘signature’ is the ASCII values for the character string “xROM”
starting at address 0x800F0. If this signature is found then it performs a CRC check. If CRC is valid then
it jumps to external ROM address 0x80100.
If the signature is not present (or bootstrap value of ROM_ADDR7 is one) then the embedded firmware
does not jump to external ROM. In this case it runs in its own loop that supports debugging commands
(using G-Probe debugging software available from Genesis) over either the UART port (see section
4.13.6) or the DDC2Bi port (see section 4.13.5).
Note that the bootstrap values of ROM_ADDR7 and ROM_ADDR8 (see Table 16) can be used to
override the signature checking. In addition, a DDC2Bi command (as configured using bootstrap value of
ROM_ADDR12 – see Table 16) can be used to override the signature checking.
4.13.3 In-System-Programming (ISP) of External FLASH ROM
The gm5221 has hardware to program FLASH ROM devices. In particular, the ROM_WEn pin can be
connected to the write enable of the FLASH ROM. The embedded boot firmware (see section 4.13.2
above) performs the writes.
4.13.4 UART Interface
The gm5221 OCM has an integrated Universal Asynchronous Remote Terminal (UART) port that can be
used as a factory debug port. In particular, the UART can be used to 1) read / write chip registers, 2) read
/ write to NVRAM, and 3) read / write to FLASH ROM (In-System-Programming).
4.13.5 DDC2Bi Interface
Hardware support is provided for DDC2Bi communication over the DDC channel of either the analog or
DVI input ports. The specification for the DDC2Bi standard can be obtained from VESA
(www.vesa.org). The DDC2Bi port can be used as a factory debug port or for field programming. In
particular, the DDC2Bi port can be used to 1) read / write chip registers, 2) read / write to NVRAM, and
3) read / write to FLASH ROM (In-System-Programming).
The factory programming or test station connects to the gm5221 through the Direct Data Channel (DDC)
of the DSUB15 or DVI connectors. For example, the PC can make gm5221 display test patterns (see
section 4.5). A camera can be used to automate the calibration of the LCD panel.
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DDC
Factory Station
Device-Under-Test
Camera
Figure 25.
Factory Calibration and Test Environment
Two pairs of pins are available for DDC2Bi communication. For DDC2Bi communication over the
analog VGA connector pins DDC_SCL_VGA and DDC_SDA_VGA should be connected to the DDC
clock and data pins of the analog DSUB15 VGA connector. For DDC2Bi communication over the DVI
connector pins DDC_SCL_DVI and DDC_SDA_DVI should be connected to the DDC clock and data
pins of the DVI connector. The gm5221 contains serial to parallel conversion hardware that is then
accessed by firmware for interpretation and execution of the DDC2Bi command set.
Note that DDC2Bi can only be activated on only one of the inputs at a time. The port activated by default
is specified using the bootstrap value of ROM_ADDR12 (see Table 16). Firmware may change this
default setting using an on-chip register.
4.13.6 JTAG Interface
A JTAG interface is provided to allow in-circuit firmware debugging. This is done using a JTAG port.
This port is available on the following signals:
•
•
•
•
•
JTAG_RESET
JTAG_TDO
JTAG_TDI
HOST_SCL (JTAG_CLK)
HOST_SDA (JTAG_MODE)
Also, a 2-wire to JTAG bridge circuit is provided to allow JTAG commands to be issued using only two
pins HOST_SCL and HOST_SDA.
4.13.7 General Purpose Inputs and Outputs (GPIO)
The gm5221 has 23 potential general-purpose input/output (GPIO) pins. Not all may be available
depending on shared functionality of particular pins. These are used by the OCM to communicate with
other devices in the system such as keypad buttons, NVRAM, LED’s, audio DAC, etc. Each GPIO has
independent direction control and open drain enable for reading and writing. Note that the GPIO pins
have alternate functionality as described in Table 15.
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Table 15. GPIO and Alternate Functions
Pin Name
Pin Number Alternate function
GPIO0
81
82
No alternative functions.
GPIO1
GPIO2
83
GPIO3
84
GPIO4
85
GPIO5
88
GPIO6
89
GPIO7/IRQin
GPIO8/IRQout
GPIO9/SCL
90
Can be used to trigger an OCM interrupt.
Level reflects an on-chip status change.
91
92
Data and clock lines for master 2-wire serial interface to NVRAM, or other devices such as video
decoder or audio amplifier.
GPIO10/SDA
GPIO11/PWM0
GPIO12/PWM1
GPIO13/PWM2
GPIO14/PWM3
GPIO16/VDATA7
GPIO17/VDATA6
GPIO18/VDATA5
GPIO19/VDATA4
GPIO20/VDATA3
GPIO21/VDATA2
GPIO22/VDATA1
GPIO23/VDATA0
93
98
General purpose PWM outputs (back light intensity control, etc.)
NTSC/PAL Video input port.
99
100
101
102
103
106
107
108
109
110
111
4.13.8 Low-Bandwidth ADC (LBADC)
A general-purpose ADC is integrated to allow for functions such as keypad scanning or for monitoring
system temperature or voltage sensors. The ADC has 8 bits of resolution, and can perform a conversion
in 13 TCLK periods (approximately 1 µsec). An analog multiplexer selects one of three analog input pins
as the input to the ADC.
4.13.9 Low Power State
The gm5221 provides a low power state in which the clocks to selected parts of the chip may be disabled. In
addition, the OCM_CLK may be reduced (by a factor of up to 510) so that the OCM itself consumes less
power.
4.13.10 Pulse Width Modulation (PWM)
Many of today’s LCD back light inverters require both a PWM input and variable DC voltage to
minimize flickering (due to the interference between panel timing and inverter’s AC timing), and adjust
brightness.
There are four pins available for PWM outputs: PWM0 (GPIO11), PWM1 (GPIO12), PWM2 (GPIO13)
and PWM3 (GPIO14). The duty cycle of these signals is programmable. They may be connected to an
external RC integrator to generate a variable DC voltage for a LCD back light inverter. Panel HSYNC is
used as the clock for a counter generating this output signal.
PWM0 has an additional option for 10-bit duty cycle control.
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4.14 Bootstrap Configuration Pins
During hardware reset, the external ROM address pins ROM_ADDR[17:0] are configured as inputs. On
the negating edge of RESETn, the value on these pins is latched and stored. This value is readable by the
on-chip microcontroller (or an external microcontroller via the host interface). Install a 10K pull-up
resistor to indicate a ‘1’, otherwise a ‘0’ is indicated because ROM_ADDR[17:0] have a 50KΩ internal
pull-down resistor.
Table 16. Bootstrap Signals
Bootstrap
DEV_ADDR(6:0}
FORCEIROM
FORCEXROM
Pin Name
ROM_ADDR6:0
ROM_ADDR8
ROM_ADDR7
Description
These pins specify the device address for serial host interface.
Forces execution from external or internal ROM (see section 4.13.2):
00 = Check for signature in external ROM and if present jump to external ROM.
01 = Jump to external ROM regardless of whether signature or CRC are present.
10 = Jump to internal ROM regardless of whether signature or CRC are present.
11 = Check for signature and CRC and if present jump to external ROM (recommended).
Forces OCM (when executing from embedded boot firmware) to operate using TCLK (see Figure 8):
0 = OCM_CLK = FCLK (see Figure 7). UART baud rate is 115200 baud.
1 = OCM_CLK = TCLK. UART baud rate is 19200 baud.
OCM_USES_TCLK
ROM_ADDR9
TCLKSEL1
TCLKSEL0
ROM_ADDR11
ROM_ADDR10
Used by the embedded boot firmware to specify the TCLK frequency:
00 = for TCLK = 14.3 MHz
01 = for TCLK = 20 MHz
10 = for TCLK = 24 MHz
11 = for TCLK = 14.3 MHz
Note: The embedded firmware uses these bootstraps to program RCLK to 200MHz (or as close as
possible in multiples of TCLK) and FCLK to 100MHz.
DDCHANSEL
ROM_ADDR12
Specifies the default DDC2Bi channel when executing from embedded boot firmware:
0 = Use DDC_SCL_DVI/DDC_SDA_DVI pin pair.
1 = Use DDC_SCL_VGA/DDC_SDA_VGA pin pair.
Operating Mode: Selects external register access method.
00 = UART (normal operation)
OP_MODE1
OP_MODE0
ROM_ADDR14
ROM_ADDR13
01 = 2-wire to JTAG Bridge
10 = 5-wire JTAG port
11 = Reserved
SPI_EN
ROM_ADDR15
ROM_ADDR16
ROM_ADDR17
SPI serial ROM interface enable
0 = Parallel ROM Interface
1 = SPI serial ROM and cache controller
Selects the initial state of internal OCM ROM
0 = Internal ROM on at top of 1M in X86 address space (normal operation)
1 = Internal ROM off (debug mode – illegal when SPI_EN bootstrap value on ROM_ADDR15 = 1)
Selection of TCLK source. Program to 0 when using external crystal connected to TCLK and XTAL.
OCM_ROM
OSC_SEL
Note: There is an internal pull-down resistor of 50KΩ to ground for each signal.
4.15 Electrostatic Discharge (ESD)
The gm5221 integrates ESD diodes to protect the device during handling. However, external on-board
ESD diodes are required on the analog RGB inputs, DVI inputs, and DDC inputs for protection against
electrical overstress (EOS).
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5 Electrical Specifications
The following targeted specifications have been derived by simulation.
5.1 Preliminary DC Characteristics
Table 17. Absolute Maximum Ratings
PARAMETER
SYMBOL
VVDD_3.3
VVDD_1.8
VIN5Vtol
VIN
MIN
-0.3
-0.3
-0.3
-0.3
TYP
MAX
3.6
1.98
5.5
UNITS
3.3V Supply Voltages (1,2)
1.8V Supply Voltages (1.2)
Input Voltage (5V tolerant inputs) (1,2)
Input Voltage (non 5V tolerant inputs) (1,2)
Electrostatic Discharge
V
V
V
V
kV
3.6
VESD
ILA
TA
TSTG
±2.0
±100
70
150
125
Latch-up
Ambient Operating Temperature
Storage Temperature
mA
0
-40
0
°C
°C
°C
Operating Junction Temp.
TJ
Thermal Resistance (Junction to Air) Natural Convection
gm5221 on 4-layer PCB
34.6
θ
°C/W
JA_4L
Thermal Resistance (Junction to Case) Convection (3)
gm5221
θ
JC
17.0
TBD
TBD
°C/W
°C
°C
Soldering Temperature (30 sec.)
Vapor Phase Soldering (30 sec.)
TSOL
TVAP
NOTE (1): All voltages are measured with respect to GND.
NOTE (2): Absolute maximum voltage ranges are for transient voltage excursions.
NOTE (3): Based on the figures for the Operating Junction Temperature, θJC and Power Consumption in Table 18, the maximum allowed case
temperature is calculated as TC(MAX) = TJ(MAX) - P(MAX) x θJC. For SXGA operation this is 125-1.1x17=106°C.
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Table 18. DC Characteristics
PARAMETER
SYMBOL
POWER
MIN
TYP
MAX
UNITS
Power Consumption @ 135 MHz
Power Consumption @ Low Power Mode (1)
3.3V Supply Voltages (AVDD and RVDD)
1.8V Supply Voltages (VDD and CVDD)
Supply Current @ CLK =135MHz (gm5221)
• 1.8V digital supply (2)
PSXGA
PLP
VVDD_3.3
VVDD_1.8
I
IVDD_1.8
IAVDD_1.8
IVDD_3.3
IAVDD_3.3
1.1
50
3.3
1.8
600
W
mW
V
V
mA
3.15
3.45
300
60
40
200
• 1.8V analog supply (3)
• 3.3V digital supply (4)
• 3.3V analog supply (5)
Supply Current @ Low Power Mode*
ILP
50
mA
INPUTS
High Voltage
VIH
2.0
GND
2.4
GND
-25
VDD
0.8
VDD
0.4
25
25
8
V
V
Low Voltage
VIL
Clock High Voltage
Clock Low Voltage
High Current (VIN = 5.0 V)
Low Current (VIN = 0.8 V)
Capacitance (VIN = 2.4 V)
VIHC
VILC
IIH
IIL
CIN
V
V
µA
µA
pF
-25
OUTPUTS
High Voltage (IOH = 7 mA)
Low Voltage (IOL = -7 mA)
Tri-State Leakage Current
VOH
VOL
IOZ
2.4
GND
-25
VDD
0.4
25
V
V
µA
NOTE (1): Low power figures result from setting the ADC, DVI, and clock power down bits so that only the micro-controller is running.
NOTE (2): Includes all CVDD_1.8 pins.
NOTE (3): Includes VDD_RX0_1.8, VDD_RX1_1.8, VDD_RX2_1.8, VDD_RXPLL_1.8, VDD_RPLL_1.8 and VDD1_ADC_1.8 pins.
NOTE (4): Includes all RVDD_3.3, AVDD _LV_E_3.3 and AVDD _LV_O_3.3 pins.
NOTE (5): Includes pins AVDD_RED_3.3, AVDD_GREEN_3.3, AVDD_BLUE_3.3, AVDD_IMB_3.3, AVDD_RX0_3.3,
AVDD_RX1_3.3, AVDD_RX2_3.3, AVDD_RXC_3.3, AVDD_RPLL_3.3, AVDD_ADC_3.3, AVDD_LV_3.3 and LBADC_VDD_3.3.
NOTE (6): Maximum current figures are provided for the purposes of selecting a power supply circuit.
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5.2 Preliminary AC Characteristics
All timing is measured to a 1.5V logic-switching threshold. The minimum and maximum operating
conditions used were: TDIE = 0 to 125° C, Vdd = 2.35 to 2.65V, Process = best to worst, CL = 16pF for all outputs.
Table 19. Maximum Speed of Operation
Clock Domain
Max Speed of Operation
25 MHz (14.3MHz recommended)
165 MHz
Main Input Clock (T_CLK)
DVI Differential Input Clock (DVI_CLK)
ADC Clock (S_CLK)
165 MHz
Input Clock (IP_CLK)
165 MHz
220MHz (200MHz recommended)
100 MHz
Reference Clock (R_CLK)
On-Chip Microcontroller Clock (OCM_CLK)
Display Clock (D_CLK)
165 MHz
TsVCLK PL
TsVCLK PH
VCLK
TVP SU
TVP HD
VDATA
Figure 26.
Timing Diagram for ITU656 Video Port
Table 20. Input Timing for ITU656 Video Port
Symbol
Parameter
Min
Max Units
TVP_SU
Setup time for data signals valid before VCLK edge. VCLK edge is
2
nsec.
programmable to be either rising or falling.
TVP_HD
Hold time for data/control signals to remain valid after VCLK edge.
VCLK high pulse width period
VCLK low pulse width period
VCLK maximum operating frequency.
1
3
3
nsec
nsec
nsec
TVCLK_PH
TVCLK_PL
FVCLK
28
Mhz
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Read Cycle
Write Cycle
ROM_ADDR (17:0)
ROM_OEn
TRAS
TRLPW
TRAH
TWAH
TWAS
TWLPW
ROM_WEn
ROM_CSn
TWHZ
TWDH
TWLZ
TRDH
TWDS
TRDD
ROM_DATA (7:0)
FROM EXTERNAL DEVICE
TO EXTERNAL DEVICE
Figure 27.
OCM ROM Interface Timing Diagram
Table 21. OCM ROM Interface Timing
Symbol Parameter
Min
Max
Units
TOCMCLK
On chip OCM clock period.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
TOCM_WAS
TOCM_WAH
TOCM_WLPW
TOCM_WDS
TOCM_WDH
TOCM_WLZ
TOCM_WHZ
TOCM_RAS
TOCM_RAH
TOCM_RLPW
TOCM_RDD
TOCM_RDH
Address setup time provided to falling edge of OCM_WR.
Address hold time provided from rising edge of OCM_WR.
OCM_WR active low pulse width
OCM_DATA valid time to OCM_WR rising edge (data set-up time provided)
OCM_DATA held valid from OCM_WR rising edge. (data hold time provided)
OCM_DATA Low-Z after OCM_WEn falling edge.
OCM_DATA Hi-Z after OCM_WEn rising edge.
Address setup time provided to falling edge of OCM_RD.
Address hold time provided from rising edge of OCM_RD.
OCM_RD low pulse width
Read data valid before OCM_RD rising edge.
Read data hold after OCM_RD rising edge.
K1(TOCMCLK) – 3
TOCMCLK – 3
K2 (TOCMCLK
)
K2(TOCMCLK) – 3
TOCMCLK – 3
3
-2
TOCMCLK – 3
0
TOCMCLK + 3
TOCMCLK – 3
K3 (TOCMCLK
)
10
0
NOTE: Conditions: For ROMC the CLOAD = 16 pF. For ROM_ADDR[17:0] and ROM_DATA[7:0] the CLOAD = 32 pF.
NOTE: K1, K2 and K3 are programmable in units of OCM_CLK.
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6 Ordering Information
Order Code
Application
Package Temperature
Range
2
2
√
√
√
√
√
√
√
√
gm5221-LF-BC
gm5221H-LF-BC (1)
SXGA
SXGA
0-70°C
208-pin
PQFP
√
Note (1): gm5221H is sold to HDCP licensed customers only.
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7 Mechanical Specifications
Figure 28.
gm5221 208-pin PQFP Mechanical Drawing
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