ISP1106W [STMICROELECTRONICS]
IC,LINE TRANSCEIVER,CMOS,1 DRIVER,1 RCVR,LLCC,16PIN,PLASTIC;
| 型号： | ISP1106W |
| 厂家： | 
ST |
| 描述： | IC,LINE TRANSCEIVER,CMOS,1 DRIVER,1 RCVR,LLCC,16PIN,PLASTIC 驱动 接口集成电路 驱动器 |
| 文件： | 总31页 (文件大小：833K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IMPORTANT NOTICE
Dear customer,
As from February 2nd 2009, ST and Ericsson have merged Ericsson Mobile
Platforms and ST‐NXP Wireless into a 50/50 joint venture "ST‐Ericsson".
As a result, the following changes are applicable to the attached
document.
● Company name ‐ ST‐NXP Wireless is replaced with ST‐Ericsson.
● Copyright ‐ the copyright notice at the bottom of each page “© ST‐NXP
Wireless 200x ‐ All rights reserved”, shall now read: “© ST‐Ericsson, 2009 ‐
All rights reserved”.
● Web site ‐ http://www.stnwireless.com is replaced with
www.stericsson.com
● Contact information ‐ the list of sales offices previously obtained at
http://www.stnwireless.com , is now found at www.stericsson.com
under Contacts
If you have any questions related to the document, please contact our
nearest sales office.
Thank you for your cooperation and understanding.
ISP1105/1106
Advanced USB transceivers
Rev. 09 — 19 January 2009
Product data sheet
1. General description
The ISP1105/1106 range of Universal Serial Bus (USB) transceivers are compliant with
the Universal Serial Bus Specification Rev. 2.0. They can transmit and receive serial data
at both full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) data rates. The ISP1105/1106
range can be used as a USB device transceiver or a USB host transceiver.
They allow USB Application Specific ICs (ASICs) and Programmable Logic Devices
(PLDs) with power supply voltages from 1.65 V to 3.6 V to interface with the physical layer
of the Universal Serial Bus. They have an integrated 5 V-to-3.3 V voltage regulator for
direct powering via the USB supply VBUS
.
ISP1105 allows single-ended and differential input modes selectable by a MODE input
and it is available in HVQFN16 and HBCC16 packages. ISP1106 allows only differential
input mode and is available in both TSSOP16 and HBCC16 packages.
The ISP1105/1106 are ideal for portable electronics devices such as mobile phones,
digital still cameras, Personal Digital Assistants (PDA) and Information Appliances (IA).
2. Features
Complies with Universal Serial Bus Specification Rev. 2.0
Can transmit and receive serial data at both full-speed (12 Mbit/s) and low-speed
(1.5 Mbit/s) data rates
Integrated bypassable 5 V-to-3.3 V voltage regulator for powering via USB VBUS
VBUS disconnection indication through VP and VM
Used as a USB device transceiver or a USB host transceiver
Stable RCV output during SE0 condition
Two single-ended receivers with hysteresis
Low-power operation
Supports an I/O voltage range from 1.65 V to 3.6 V
±12 kV ESD protection at the D+, D−, VCC(5.0) and GND pins
Full industrial operating temperature range from −40 °C to +85 °C
Available in small HBCC16, HVQFN16 (only ISP1105) and TSSOP16 (only ISP1106)
packages; HBCC16 and HVQFN16 are lead-free and halogen-free packages.
34ꢀ.80 7IRELESS
ISP1105/1106
34ꢀ.80 7IRELESS
Advanced USB transceivers
3. Applications
Portable electronic devices, such as:
Mobile phone
Digital still camera
Personal Digital Assistant (PDA)
Information Appliance (IA).
4. Ordering information
Table 1.
Ordering information
Type number Package
Name
Description
Version
ISP1105BS
HVQFN16
plastic thermal enhanced very thin quad flat package; no leads;
SOT758-1
16 terminals; body 3 × 3 × 0.85 mm
ISP1105W
HBCC16
plastic thermal enhanced bottom chip carrier; 16 terminals;
SOT639-2
body 3 × 3 × 0.65 mm
ISP1106DH
ISP1106W
TSSOP16
HBCC16
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
SOT639-2
plastic thermal enhanced bottom chip carrier; 16 terminals;
body 3 × 3 × 0.65 mm
4.1 Ordering options
Table 2.
Product
ISP1105
Selection guide
Package
Description
HVQFN16 and HBCC16 supports both single-ended and differential input modes; see Table 5 and
Table 6.
ISP1106
TSSOP16 and HBCC16 supports only the differential input mode; see Table 6.
ISP1105_1106_9
© ST-NXP Wireless 2009. All rights reserved.
Product data sheet
Rev. 09 — 19 January 2009
2 of 30
ISP1105/1106
34ꢀ.80 7IRELESS
Advanced USB transceivers
5. Block diagram
3.3 V
VOLTAGE
REGULATOR
V
V
V
CC(5.0)
reg(3.3)
CC(I/O)
V
pu(3.3)
SOFTCON
OE
(1)
1.5 kΩ
33 Ω (1%)
33 Ω (1%)
D+
D−
SPEED
(2)
VMO/FSE0
(2)
VPO/VO
(3)
MODE
LEVEL
SHIFTER
SUSPND
RCV
ISP1105
ISP1106
VP
VM
mbl301
GND
(1) Connect to D− for low-speed operation.
(2) Pin function depends on device type.
(3) Only for ISP1105.
Fig 1. Block diagram (combined ISP1105 and ISP1106).
ISP1105_1106_9
© ST-NXP Wireless 2009. All rights reserved.
Product data sheet
Rev. 09 — 19 January 2009
3 of 30
ISP1105/1106
34ꢀ.80 7IRELESS
Advanced USB transceivers
6. Pinning information
6.1 Pinning
5
6
7
8
6
7
8
D−
SUSPND
VM
5
9
9
D−
4
3
2
1
VM
VP
D+
4
3
2
10
11
12
10 D+
ISP1105W
ISP1105BS
VPO/VO
VMO/FSE0
VP
RCV
VPO/VO
11
GND
(exposed diepad)
GND
(exposed diepad)
RCV
12 VMO/FSE0
OE
V
13
1
16
15
14
reg(3.3)
OE
14
15
13
16
004aaa314
Bottom view
Bottom view
MBL303
Fig 2. Pin configuration ISP1105BS (HVQFN).
Fig 3. Pin configuration ISP1105W (HBCC16).
V
V
V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CC(5.0)
reg(3.3)
pu(3.3)
6
7
8
D−
SUSPND
VM
5
9
SOFTCON
OE
VMO
VPO
D+
D+
4
3
2
10
11
12
RCV
ISP1106DH
ISP1106W
VPO
VMO
VP
VP
RCV
VM
D−
SUSPND
GND
SPEED
V
13
1
16
15
14
reg(3.3)
OE
V
CC(I/O)
Bottom view
MBL304
MBL302
Fig 4. Pin configuration ISP1106DH (TSSOP16).
Fig 5. Pin configuration ISP1106W (HBCC16).
ISP1105_1106_9
© ST-NXP Wireless 2009. All rights reserved.
Product data sheet
Rev. 09 — 19 January 2009
4 of 30
ISP1105/1106
34ꢀ.80 7IRELESS
Advanced USB transceivers
6.2 Pin description
Table 3.
Symbol[1]
Pin description
Pin
Type Description
ISP1105
ISP1106
BS
W
DH
W
OE
1
1
3
1
I
output enable input (CMOS level with respect to VCC(I/O), active LOW);
enables the transceiver to transmit data on the USB bus
input pad; push pull; CMOS
RCV
2
3
2
3
4
2
3
O
differential data receiver output (CMOS level with respect to VCC(I/O));
driven LOW when input SUSPND is HIGH; the output state of RCV is
preserved and stable during an SE0 condition
output pad; push pull; 4 mA output drive; CMOS
VP
5
6
O
O
single-ended D+ receiver output (CMOS level with respect to VCC(I/O)); for
external detection of single-ended zero (SE0), error conditions, speed of
connected device; driven HIGH when no supply voltage is connected to
VCC(5.0) and Vreg(3.3)
output pad; push pull; 4 mA output drive; CMOS
VM
4
4
4
single-ended D− receiver output (CMOS level with respect to VCC(I/O)); for
external detection of single-ended zero (SE0), error conditions, speed of
connected device; driven HIGH when no supply voltage is connected to
VCC(5.0) and Vreg(3.3)
output pad; push pull; 4 mA output drive; CMOS
SUSPND
MODE
5
6
5
6
7
-
5
-
I
I
suspend input (CMOS level with respect to VCC(I/O)); a HIGH level enables
low-power state while the USB bus is inactive and drives output RCV to a
LOW level
input pad; push pull; CMOS
mode input (CMOS level with respect to VCC(I/O)); a HIGH level enables the
differential input mode (VPO, VMO) whereas a LOW level enables a
single-ended input mode (VO, FSE0); see Table 5 and Table 6
input pad; push pull; CMOS
ground supply[2]
GND
die die
pad pad
8
9
6
7
-
-
VCC(I/O)
7
7
supply voltage for digital I/O pins (1.65 V to 3.6 V). When VCC(I/O) is not
connected, the (D+, D−) pins are in three-state; this supply pin is totally
independent of VCC(5.0) and Vreg(3.3) and must never exceed the Vreg(3.3)
voltage
SPEED
8
8
10
8
I
speed selection input (CMOS level with respect to VCC(I/O)); adjusts the
slew rate of differential data outputs D+ and D− according to the
transmission speed
LOW — low-speed (1.5 Mbit/s)
HIGH — full-speed (12 Mbit/s)
input pad; push pull; CMOS
D−
9
9
11
12
9
AI/O
negative USB data bus connection (analog, differential); for low-speed
mode connect to pin Vpu(3.3) via a 1.5 kΩ resistor
D+
10
10
10 AI/O
positive USB data bus connection (analog, differential); for full-speed mode
connect to pin Vpu(3.3) via a 1.5 kΩ resistor
ISP1105_1106_9
© ST-NXP Wireless 2009. All rights reserved.
Product data sheet
Rev. 09 — 19 January 2009
5 of 30
ISP1105/1106
34ꢀ.80 7IRELESS
Advanced USB transceivers
Table 3.
Symbol[1]
Pin description …continued
Pin
Type Description
ISP1105
ISP1106
BS
11
-
W
11
-
DH
W
-
VPO/VO
VPO
-
13
-
I
I
-
driver data input (CMOS level with respect to VCC(I/O), Schmitt trigger); see
Table 5 and Table 6
11
-
input pad; push pull; CMOS
VO
-
-
VMO/FSE0
VMO
12
-
12
-
-
-
driver data input (CMOS level with respect to VCC(I/O), Schmitt trigger); see
Table 5 and Table 6
14
-
12
-
input pad; push pull; CMOS
FSE0
-
-
Vreg(3.3)
13
13
15
13
internal regulator option: regulated supply voltage output (3.0 V to 3.6 V)
during 5 V operation; a decoupling capacitor of at least 0.1 μF is required
regulator bypass option: used as a supply voltage input for 3.3 V ± 10 %
operation
VCC(5.0)
14
15
14
15
16
1
14
15
-
-
internal regulator option: supply voltage input (4.0 V to 5.5 V); can be
connected directly to USB supply VBUS
regulator bypass option: connect to Vreg(3.3)
Vpu(3.3)
pull-up supply voltage (3.3 V ± 10 %); connect an external 1.5 kΩ resistor
on D+ (full-speed) or D− (low-speed); pin function is controlled by input
SOFTCON
SOFTCON = LOW — Vpu(3.3) floating (high impedance); ensures zero
pull-up current
SOFTCON = HIGH — Vpu(3.3) = 3.3 V; internally connected to Vreg(3.3)
SOFTCON
16
16
2
16
I
software controlled USB connection input; a HIGH level applies 3.3 V to pin
Vpu(3.3), which is connected to an external 1.5 kΩ pull-up resistor; this
allows USB connect/disconnect signalling to be controlled by software
input pad; push pull; CMOS
[1] Symbol names with an overscore (e.g. NAME) indicate active LOW signals.
[2] ISP1105: ground terminal is connected to the exposed die pad (heat sink).
ISP1105_1106_9
© ST-NXP Wireless 2009. All rights reserved.
Product data sheet
Rev. 09 — 19 January 2009
6 of 30
ISP1105/1106
34ꢀ.80 7IRELESS
Advanced USB transceivers
7. Functional description
7.1 Function selection
Table 4.
Function table
SUSPND OE
(D+, D−)
RCV
VP/VM
Function
L
L
driving and
receiving
active
active
normal driving (differential
receiver active)
L
H
L
receiving[1]
active
inactive[2]
active
active
receiving
driving during ‘suspend’[3]
H
driving
(differential receiver inactive)
H
H
high-Z[1]
inactive[2]
active
low-power state
[1] Signal levels on (D+, D−) are determined by other USB devices and external pull-up/down resistors.
[2] In ‘suspend’ mode (SUSPND = HIGH) the differential receiver is inactive and output RCV is always LOW.
Out-of-suspend (‘K’) signalling is detected via the single-ended receivers VP and VM.
[3] During suspend, the slew-rate control circuit of low-speed operation is disabled. The (D+, D−) lines are still
driven to their intended states, without slew-rate control. This is permitted because driving during suspend
is used to signal remote wake-up by driving a ‘K’ signal (one transition from idle to ‘K’ state) for a period of
1 to 15 ms.
7.2 Operating functions
Table 5.
Driving function (pin OE = L) using single-ended input data interface for ISP1105
(pin MODE = L)
FSE0
VO
L
Data
L
differential logic 0
differential logic 1
SE0
L
H
H
H
L
H
SE0
Table 6.
Driving function (pin OE = L) using differential input data interface for ISP1105
(pin MODE = H) and ISP1106
VMO
VPO
L
Data
L
SE0
L
H
differential logic 1
differential logic 0
illegal state
H
H
L
H
Table 7.
Receiving function (pin OE = H)
RCV
(D+, D−)
VP[1]
VM[1]
Differential logic 0
Differential logic 1
SE0
L
L
H
L
H
L
L
H
RCV*[2]
[1] VP = VM = H indicates the sharing mode (VCC(5.0) and Vreg(3.3) are disconnected).
[2] RCV* denotes the signal level on output RCV just before SE0 state occurs. This level is stable during the
SE0 period.
ISP1105_1106_9
© ST-NXP Wireless 2009. All rights reserved.
Product data sheet
Rev. 09 — 19 January 2009
7 of 30
ISP1105/1106
34ꢀ.80 7IRELESS
Advanced USB transceivers
7.3 Power supply configurations
The ISP1105/1106 can be used with different power supply configurations, which can be
changed dynamically. An overview is given in Table 9.
Normal mode — Both VCC(I/O) and VCC(5.0) or (VCC(5.0) and Vreg(3.3)) are connected. For
5 V operation, VCC(5.0) is connected to a 5 V source (4.0 V to 5.5 V). The internal voltage
regulator then produces 3.3 V for the USB connections. For 3.3 V operation, both VCC(5.0)
and Vreg(3.3) are connected to a 3.3 V source (3.0 V to 3.6 V). VCC(I/O) is independently
connected to a voltage source (1.65 V to 3.6 V), depending on the supply voltage of the
external circuit.
Disable mode — VCC(I/O) is not connected, VCC(5.0) or (VCC(5.0) and Vreg(3.3)) are
connected. In this mode, the internal circuits of the ISP1105/1106 ensure that the (D+, D−)
pins are in three-state and the power consumption drops to the low-power (suspended)
state level. Some hysteresis is built into the detection of VCC(I/O) lost.
Sharing mode — VCC(I/O) is connected, (VCC(5.0) and Vreg(3.3)) are not connected. In this
mode, the (D+, D−) pins are made three-state and the ISP1105/1106 allows external
signals of up to 3.6 V to share the (D+, D−) lines. The internal circuits of the ISP1105/1106
ensure that virtually no current (maximum 10 μA) is drawn via the (D+, D−) lines. The
power consumption through pin VCC(I/O) drops to the low-power (suspended) state level.
Both the VP and VM pins are driven HIGH to indicate this mode. Pin RCV is made LOW.
Some hysteresis is built into the detection of Vreg(3.3) lost.
Table 8.
Pins
Pin states in disable or sharing mode
Disable mode state
Sharing mode state
VCC(5.0) / Vreg(3.3)
5 V input / 3.3 V output;
3.3 V input / 3.3 V input
not present
VCC(I/O)
Vpu(3.3)
(D+, D−)
(VP, VM)
RCV
not present
1.65 V to 3.6 V input
high impedance (off)
high impedance
H
high impedance (off)
high impedance
invalid[1]
invalid[1]
L
Inputs (VO/VPO, FSE0/VMO, SPEED, high impedance
MODE[2], SUSPND, OE, SOFTCON)
high impedance
[1] High impedance or driven LOW.
[2] ISP1105 only.
Table 9.
Power supply configuration overview
VCC(5.0) or Vreg(3.3) VCC(I/O)
Configuration
normal mode
disable mode
Special characteristics
Connected
Connected
connected
-
not connected
(D+, D−) and Vpu(3.3) high
impedance; VP, VM, RCV:
invalid[1]
Not connected
connected
sharing mode
(D+, D−) and Vpu(3.3) high
impedance;
VP, VM driven HIGH; RCV driven
LOW
[1] High impedance or driven LOW.
ISP1105_1106_9
© ST-NXP Wireless 2009. All rights reserved.
Product data sheet
Rev. 09 — 19 January 2009
8 of 30
ISP1105/1106
34ꢀ.80 7IRELESS
Advanced USB transceivers
7.4 Power supply input options
The ISP1105/1106 range has two power supply input options.
Internal regulator — VCC(5.0) is connected to 4.0 V to 5.5 V. The internal regulator is
used to supply the internal circuitry with 3.3 V (nominal). The Vreg(3.3) pin becomes a 3.3 V
output reference.
Regulator bypass — VCC(5.0) and Vreg(3.3) are connected to the same supply. The internal
regulator is bypassed and the internal circuitry is supplied directly from the Vreg(3.3) power
supply. The voltage range is 3.0 V to 3.6 V to comply with the USB specification.
The supply voltage range for each input option is specified in Table 10.
Table 10. Power supply input options
Input option
VCC(5.0)
Vreg(3.3)
VCC(I/O)
Internal regulator supply input for internal voltage reference output supply input for digital
regulator (4.0 V to 5.5 V) (3.3 V, 300 μA)
I/O pins (1.65 V to 3.6 V)
Regulator bypass connected to Vreg(3.3)
supply input
supply input for digital
with maximum voltage
drop of 0.3 V
(3.0 V to 3.6 V)
I/O pins (1.65 V to 3.6 V)
(2.7 V to 3.6 V)
ISP1105_1106_9
© ST-NXP Wireless 2009. All rights reserved.
Product data sheet
Rev. 09 — 19 January 2009
9 of 30
ISP1105/1106
34ꢀ.80 7IRELESS
Advanced USB transceivers
8. Electrostatic discharge (ESD)
8.1 ESD protection
The pins that are connected to the USB connector (D+, D−, VCC(5.0) and GND) have a
minimum of ±12 kV ESD protection. The ±12 kV measurement is limited by the test
equipment. Capacitors of 4.7 μF connected from Vreg(3.3) to GND and VCC(5.0) to GND are
required to achieve this ±12 kV ESD protection (see Figure 6).
R
1 MΩ
R
D
1500 Ω
C
charge current
limit resistor
discharge
resistance
DEVICE UNDER
TEST
V
CC(5V0)
A
B
VREG3V3
HIGH VOLTAGE
DC SOURCE
storage
capacitor
C
S
4.7 μF
4.7 μF
100 pF
GND
004aaa145
Fig 6. Human Body ESD test model.
8.2 ESD test conditions
A detailed report on test set-up and results is available on request.
ISP1105_1106_9
© ST-NXP Wireless 2009. All rights reserved.
Product data sheet
Rev. 09 — 19 January 2009
10 of 30
ISP1105/1106
34ꢀ.80 7IRELESS
Advanced USB transceivers
9. Limiting values
Table 11. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VCC(5.0)
VCC(I/O)
Vreg(3.3)
VI
Parameter
Conditions
Min
−0.5
−0.5
−0.5
−0.5
-
Max
Unit
V
supply voltage
+6.0
I/O supply voltage
regulated supply voltage
DC input voltage
+4.6
V
+4.6
V
VCC(I/O) + 0.5
100
V
Ilu
latch-up current
VI = −1.8 V to 5.4 V
ILI < 1 μA
mA
[1][2]
Vesd
electrostatic discharge voltage
on pins D+, D−,
−12000
+12000
V
VCC(5.0) and GND
on other pins
−2000
−40
+2000
+125
V
Tstg
storage temperature
°C
[1] Testing equipment limits measurement to only ±12 kV. Capacitors needed on VCC(5.0) and Vreg(3.3); see Section 8.
[2] Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ resistor (Human Body Model).
10. Recommended operating conditions
Table 12. Recommended operating conditions
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCC(5.0)
supply voltage (internal
regulator option)
5 V operation
4.0
5.0
5.5
V
Vreg(3.3)
supply voltage (regulator
bypass option)
3.3 V operation
3.0
3.3
3.6
V
VCC(I/O)
VI
I/O supply voltage
input voltage
1.65
0
-
-
-
3.6
V
V
V
VCC(I/O)
3.6
VI(AI/O)
input voltage on analog I/O
0
pins (D+/D−)
Tamb
operating ambient temperature
−40
-
+85
°C
ISP1105_1106_9
© ST-NXP Wireless 2009. All rights reserved.
Product data sheet
Rev. 09 — 19 January 2009
11 of 30
ISP1105/1106
34ꢀ.80 7IRELESS
Advanced USB transceivers
11. Static characteristics
Table 13. Static characteristics: supply pins
VCC = 4.0 V to 5.5 V or Vreg(3.3) = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; VGND = 0 V; see Table 10 for valid voltage level
combinations; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[1][2]
[3]
Vreg(3.3)
regulated supply voltage
output
internal regulator option;
Iload ≤ 300 μA
3.0
3.3
3.6
V
ICC
operating supply current
full-speed transmitting and
receiving at 12 Mbit/s; CL = 50 pF
on D+/D−
-
4
8
mA
[3]
[4]
ICC(I/O)
ICC(idle)
operating I/O supply current full-speed transmitting and
receiving at 12 Mbit/s
-
-
1
-
2
mA
supply current during
full-speed idle: VD+ > 2.7 V,
500
μA
full-speed idle and SE0
V
V
D− < 0.3 V; SE0: VD+ < 0.3 V,
D− < 0.3 V
ICC(I/O)(static)
ICC(susp)
ICC(dis)
static I/O supply current
suspend supply current
full-speed idle, SE0 or suspend
SUSPND = HIGH
-
-
-
-
-
-
-
-
20
20
20
20
μA
μA
μA
μA
[4]
[4]
disable mode supply current VCC(I/O) not connected
ICC(I/O)(sharing) sharing mode I/O supply
current
VCC(5.0) or Vreg(3.3) not connected
IDx(sharing)
sharing mode load current
on pins D+ and D−
VCC(5.0) or Vreg(3.3) not connected;
SOFTCON = LOW; VDx = 3.6 V
-
-
10
μA
Vreg(3.3)th
regulated supply voltage
detection threshold
1.65 V ≤ VCC(I/O) ≤ Vreg(3.3)
2.7 V ≤ Vreg(3.3) ≤ 3.6 V
;
supply lost
-
-
0.8
V
V
V
[5]
supply present
VCC(I/O) = 1.8 V
2.4
-
-
-
-
Vreg(3.3)hys
VCC(I/O)th
regulated supply voltage
detection hysteresis
0.45
I/O supply voltage detection Vreg(3.3) = 2.7 V to 3.6 V
threshold
supply lost
-
-
0.5
V
V
V
supply present
1.4
-
-
-
-
VCC(I/O)hys
I/O supply voltage detection Vreg(3.3) = 3.3 V
hysteresis
0.45
[1] Iload includes the pull-up resistor current via pin Vpu(3.3)
.
[2] In ‘suspend’ mode, the minimum voltage is 2.7 V.
[3] Maximum value is characterized only, not tested in production.
[4] Excluding any load current and Vpu(3.3)/Vsw source current to the 1.5 kΩ and 15 kΩ pull-up and pull-down resistors (200 μA typ.).
[5] When VCC(I/O) < 2.7 V, the minimum value for Vth(reg3.3)(present) is 2.0 V.
ISP1105_1106_9
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Table 14. Static characteristics: digital pins
VCC(I/O) = 1.65 V to 3.6 V; VGND = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCC(I/O) = 1.65 to 3.6 V
Input levels
VIL
LOW-level input voltage
-
-
-
0.3VCC(I/O)
-
V
V
VIH
HIGH-level input voltage
LOW-level output voltage
HIGH-level output voltage
0.6VCC(I/O)
Output levels
VOL
IOL = 100 μA
IOL = 2 mA
-
-
-
-
-
0.15
V
V
V
V
-
0.4
VOH
IOH = 100 μA
IOH = 2 mA
VCC(I/O) − 0.15
VCC(I/O) − 0.4
-
-
Leakage current
ILI
input leakage current
−1
-
+1
μA
Example 1: VCC(I/O) = 1.8 V ± 0.15 V
Input levels
VIL
LOW-level input voltage
HIGH-level input voltage
-
-
-
0.5
-
V
V
VIH
1.2
Output levels
VOL
LOW-level output voltage
HIGH-level output voltage
IOL = 100 μA
IOL = 2 mA
-
-
-
-
-
0.15
V
V
V
V
-
0.4
VOH
IOH = 100 μA
IOH = 2 mA
1.5
1.25
-
-
Example 2: VCC(I/O) = 2.5 V ± 0.2 V
Input levels
VIL
LOW-level input voltage
HIGH-level input voltage
-
-
-
0.7
-
V
V
VIH
1.7
Output levels
VOL
LOW-level output voltage
HIGH-level output voltage
IOL = 100 μA
IOL = 2 mA
-
-
-
-
-
0.15
V
V
V
V
-
0.4
VOH
IOH = 100 μA
IOH = 2 mA
2.15
1.9
-
-
Example 3: VCC(I/O) = 3.3 V ± 0.3 V
Input levels
VIL
LOW-level input voltage
HIGH-level input voltage
-
-
-
0.9
-
V
V
VIH
2.15
Output levels
VOL
LOW-level output voltage
HIGH-level output voltage
IOL = 100 μA
IOL = 2 mA
-
-
-
-
-
0.15
V
V
V
V
-
0.4
VOH
IOH = 100 μA
IOH = 2 mA
2.85
2.6
-
-
Capacitance
CIN
input capacitance
pin to GND
-
-
10
pF
ISP1105_1106_9
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Product data sheet
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ISP1105/1106
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Table 15. Static characteristics: analog I/O pins (D+, D−)
VCC = 4.0 V to 5.5 V or Vreg(3.3) = 3.0 V to 3.6 V; VGND = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Input levels
Differential receiver
VDI
differential input sensitivity
|VI(D+) − VI(D−)
|
0.2
0.8
-
-
-
V
V
VCM
differential common mode
voltage
includes VDI range
2.5
Single-ended receiver
VIL
LOW-level input voltage
-
-
-
-
0.8
-
V
V
V
VIH
HIGH-level input voltage
hysteresis voltage
2.0
0.4
Vhys
0.7
Output levels
VOL
VOH
LOW-level output voltage
HIGH-level output voltage
RL = 1.5 kΩ to +3.6 V
RL = 15 kΩ to GND
-
-
-
0.3
3.6
V
V
[1]
2.8
Leakage current
ILZ
OFF-state leakage current
−1
-
-
+1
20
μA
Capacitance
CIN
transceiver capacitance
pin to GND
-
pF
Resistance
ZDRV
[2]
driver output impedance
input impedance
steady-state drive
34
10
-
39
-
44
-
Ω
ZINP
MΩ
Ω
RSW
internal switch resistance at
pin Vpu(3.3)
-
10
Termination
[3][4]
VTERM
termination voltage for
3.0
-
3.6
V
upstream port pull-up (RPU
)
[1] VOH(min) = Vreg(3.3) − 0.2 V.
[2] Includes external resistors of 33 Ω ± 1 % on both D+ and D−.
[3] This voltage is available at pins Vreg(3.3) and Vpu(3.3)
[4] In ‘suspend’ mode the minimum voltage is 2.7 V.
.
ISP1105_1106_9
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Product data sheet
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14 of 30
ISP1105/1106
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12. Dynamic characteristics
Table 16. Dynamic characteristics: analog I/O pins (D+, D−)
VCC = 4.0 V to 5.5 V or Vreg(3.3) = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; VGND = 0 V; see Table 10 for valid voltage level
combinations; Tamb = −40 °C to +85 °C; unless otherwise specified.[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Driver characteristics
Full-speed mode
tFR
rise time
CL = 50 pF to 125 pF; 10 % to 90 %
of |VOH − VOL|; see Figure 7
4
-
-
-
-
20
ns
ns
%
V
tFF
fall time
CL = 50 pF to 125 pF; 90 % to 10 %
of |VOH − VOL|; see Figure 7
4
20
FRFM
VCRS
differential rise/fall time
matching (tFR/tFF
excluding the first transition from idle
state
90
1.3
111.1
2.0
)
[2]
output signal crossover
voltage
excluding the first transition from idle
state; see Figure 10
Low-speed mode
tLR
rise time
CL = 50 pF to 600 pF; 10 % to 90 %
of |VOH − VOL|; see Figure 7
75
75
80
1.3
-
-
-
-
300
300
125
2.0
ns
ns
%
V
tLF
fall time
CL = 50 pF to 600 pF; 90 % to 10 %
of |VOH − VOL|; see Figure 7
LRFM
VCRS
differential rise/fall time
matching (tLR/tLF
excluding the first transition from idle
state
)
[2]
output signal crossover
voltage
excluding the first transition from idle
state; see Figure 10
Driver timing
Full-speed mode
tPLH(drv)
driver propagation delay LOW-to-HIGH; see Figure 10
(VO/VPO, FSE0/VMO to
D+,D−)
-
-
-
-
18
18
ns
ns
tPHL(drv)
driver propagation delay HIGH-to-LOW; see Figure 10
(VO/VPO, FSE0/VMO to
D+,D−)
tPHZ
tPLZ
tPZH
tPZL
driver disable delay (OE HIGH-to-OFF; see Figure 8
to D+,D−)
-
-
-
-
-
-
-
-
15
15
15
15
ns
ns
ns
ns
driver disable delay (OE LOW-to-OFF; see Figure 8
to D+,D−)
driver enable delay (OE OFF-to-HIGH; see Figure 8
to D+,D−)
driver enable delay (OE OFF-to-LOW; see Figure 8
to D+,D−)
Low-speed mode
Not specified: low-speed delay timings are dominated by the slow rise/fall times tLR and tLF.
ISP1105_1106_9
© ST-NXP Wireless 2009. All rights reserved.
Product data sheet
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15 of 30
ISP1105/1106
34ꢀ.80 7IRELESS
Advanced USB transceivers
Table 16. Dynamic characteristics: analog I/O pins (D+, D−) …continued
VCC = 4.0 V to 5.5 V or Vreg(3.3) = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; VGND = 0 V; see Table 10 for valid voltage level
combinations; Tamb = −40 °C to +85 °C; unless otherwise specified.[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Receiver timings (full-speed and low-speed mode)
Differential receiver
tPLH(rcv)
propagation delay
(D+,D− to RCV)
LOW-to-HIGH; see Figure 9
HIGH-to-LOW; see Figure 9
-
-
-
-
15
15
ns
ns
tPHL(rcv)
propagation delay
(D+,D− to RCV)
Single-ended receiver
tPLH(se) propagation delay
LOW-to-HIGH; see Figure 9
HIGH-to-LOW; see Figure 9
-
-
-
-
18
18
ns
ns
(D+,D− to VP, VM)
tPHL(se)
propagation delay
(D+,D− to VP, VM)
[1] Test circuit: see Figure 13.
[2] Characterized only, not tested. Limits guaranteed by design.
1.8 V
logic
0.9 V
0.9 V
input
t
, t
FR LR
t
, t
FF LF
0 V
t
t
V
t
PZH
PHZ
OH
90 %
90 %
t
PLZ
PZL
V
OH
V
− 0.3 V
OH
differential
data lines
V
CRS
10 %
10 %
V
V
+ 0.3 V
OL
OL
V
004aaa572
004aaa574
OL
Fig 7. Rise and fall times.
Fig 8. Timing of OE to D+, D−.
2.0 V
1.8 V
differential
data lines
V
V
CRS
CRS
0.9 V
logic input 0.9 V
0 V
0.8 V
t
t
t
PLH(rcv)
PHL(rcv)
t
t
PHL(drv)
t
PHL(se)
PLH(drv)
PLH(se)
V
OH
V
OH
differential
data lines
0.9 V
0.9 V
V
logic output
V
CRS
CRS
V
OL
V
OL
004aaa575
004aaa573
Fig 9. Timing of D+, D− to RCV, VP, VM.
Fig 10. Timing of VO/VPO, FSE0/VMO to D+, D−.
ISP1105_1106_9
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Product data sheet
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16 of 30
ISP1105/1106
34ꢀ.80 7IRELESS
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13. Test information
test point
33 Ω
500 Ω
D.U.T.
50 pF
V
MBL142
V = 0 V for tPZH, tPHZ
V = Vreg(/3.3) for tPZL, tPLZ
Fig 11. Load for enable and disable times.
test point
D.U.T.
25 pF
MGS968
Fig 12. Load for VM, VP and RCV.
V
pu(3.3)
(1)
test point
1.5 kΩ
D.U.T.
D+/D−
33 Ω
15 kΩ
C
L
MGS967
Load capacitance:
(1) CL = 50 pF or 125 pF (full-speed mode, minimum or maximum timing)
(2) CL = 50 pF or 600 pF (low-speed mode, minimum or maximum timing)
(1) Full-speed mode: connected to D+; low-speed mode: connected to D−.
Fig 13. Load for D+, D−.
ISP1105_1106_9
© ST-NXP Wireless 2009. All rights reserved.
Product data sheet
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17 of 30
ISP1105/1106
34ꢀ.80 7IRELESS
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14. Package outline
HBCC16: plastic thermal enhanced bottom chip carrier; 16 terminals; body 3 x 3 x 0.65 mm
SOT639-2
b
v
M
M
C
C
A B
D
B
A
E
w
f
v
M
C
A
B
w
M
C
terminal 1
index area
b
1
b
3
v
M
M
C
C
A B
w
b
v
M
M
C
A B
2
w
C
detail X
e
1
C
D
h
e
y
y
C
1
5
9
e
e
4
E
e
h
2
1/2 e
4
1
13
16
A
X
1
1/2 e
3
A
2
e
3
A
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
A
A
b
E
e
e
w
b
b
b
D
D
E
e
e
3
e
f
v
y
y
1
UNIT
1
2
h
1
1
2
3
h
2
4
max.
0.10 0.7 0.33 0.33 0.38 0.38 3.1 1.45 3.1 1.45
0.05 0.6 0.27 0.27 0.32 0.32 2.9 1.35 2.9 1.35
0.23
0.17
mm
0.8
0.1 0.05 0.2
0.5
2.5
2.5 2.45 2.45
0.08
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
01-11-13
03-03-12
SOT639-2
MO-217
Fig 14. HBCC16 package outline.
ISP1105_1106_9
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Product data sheet
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18 of 30
ISP1105/1106
34ꢀ.80 7IRELESS
Advanced USB transceivers
HVQFN16: plastic thermal enhanced very thin quad flat package; no leads;
16 terminals; body 3 x 3 x 0.85 mm
SOT758-1
B
A
D
terminal 1
index area
A
E
A
1
c
detail X
e
C
1
1/2 e
y
y
v
M
C
A B
C
1
e
b
w
M
C
5
8
L
4
9
e
e
E
2
h
1/2 e
12
1
16
13
terminal 1
index area
D
h
X
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
e
2
D
D
E
L
y
1
v
w
y
1
h
1
h
max.
0.05 0.30
0.00 0.18
3.1 1.75
2.9 1.45
3.1
2.9
1.75
1.45
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
1.5
1.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-03-25
02-10-21
SOT758-1
- - -
MO-220
- - -
Fig 15. HVQFN16 package outline.
ISP1105_1106_9
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Product data sheet
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19 of 30
ISP1105/1106
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TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig 16. TSSOP16 package outline.
ISP1105_1106_9
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Product data sheet
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15. Packing information
The ISP1105/1106W (HBCC16 package) is delivered on a type A carrier tape, see
Figure 17. The tape dimensions are given in Table 17.
The reel diameter is 330 mm. The reel is made of polystyrene (PS) and is not designed for
use in a baking process.
The cumulative tolerance of 10 successive sprocket holes is ±0.02 mm. The camber must
not exceed 1 mm in 100 mm.
4
A0
K0
W
B0
P1
Type A
direction of feed
A0
K0
4
W
B0
elongated
sprocket hole
P1
direction of feed
MLC338
Type B
Fig 17. Carrier tape dimensions.
Table 17. Type A carrier tape dimensions for ISP1105/1106W
Dimension
Value
3.3
Unit
mm
mm
mm
mm
mm
A0
B0
K0
P1
W
3.3
1.1
8.0
12.0 ± 0.3
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16. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
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Product data sheet
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22 of 30
ISP1105/1106
34ꢀ.80 7IRELESS
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16.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 18) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 18 and 19
Table 18. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
220
< 2.5
235
220
≥ 2.5
220
Table 19. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 18.
ISP1105_1106_9
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Product data sheet
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ISP1105/1106
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Advanced USB transceivers
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 18. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
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ISP1105/1106
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Advanced USB transceivers
17. Additional soldering information
17.1 (H)BCC packages: footprint
The surface material of the terminals on the resin protrusion consists of a 4-layer metal
structure (Au, Pd, Ni and Pd). The Au + Pd layer (0.1 μm min.) ensures solderability, the
Ni layer (5 μm min.) prevents diffusion, and the Pd layer on top (0.5 μm min.) ensures
effective wire bonding.
Terminal
PCB land
Solder resist mask
Stencil mask
All dimensions in mm
Solder land
Normal
0.05
0.05
b
1
b
1
Solder resist
Solder stencil
b
b
0.05
0.05
For exact dimensions
see package outline
drawing (SOT639-2)
Corner
0.05
0.05
b
b
2
2
b
b
2
2
0.05
0.3 (8×)
0.05
Cavity
0.05
Stencil print thickness:
0.1 to 0.12 mm
0.1
(4×)
E
E
h
h
004aaa123
D
D
h
h
0.05
Cavity: exposed die pad, either functioning as heat sink or as ground connection; only for HBCC packages.
Fig 19. (H)BCC footprint and solder resist mask dimensions.
17.2 (H)BCC packages: reflow soldering profile
The conditions for reflow soldering of (H)BCC packages are as follows:
• Preheating time: minimum 90 s at T = 145 to 155 °C
• Soldering time: minimum 90 s (BCC) or minimum 100 s (HBCC) at T > 183 °C
• Peak temperature:
– Ambient temperature: Tamb(max) = 260 °C
– Device surface temperature: Tcase(max) = 255 °C.
ISP1105_1106_9
© ST-NXP Wireless 2009. All rights reserved.
Product data sheet
Rev. 09 — 19 January 2009
25 of 30
ISP1105/1106
34ꢀ.80 7IRELESS
Advanced USB transceivers
18. Revision history
Table 20. Revision history
Document ID
ISP1105_1106_9
Modifications:
Release date Data sheet status
20090119 Product data sheet
Change notice
Supersedes
-
ISP1105_1106-08
• Globally changed Philips Semiconductors and Philips to ST-NXP Wireless. Also updated the
legal text.
• Section 8.1 “ESD protection”: removed the second paragraph.
ISP1105_1106-08
(9397 750 09529)
20040219
Product data
Product data
Product data
Product data
Preliminary data
Preliminary data
ISP1105_1106_1107-07
ISP1105_1106_1107-06
ISP1105_1106_1107-05
ISP1105_1106_1107-04
ISP1105_1106_1107-03
ISP1107-02
ISP1105_1106_1107-07 20020329
(9397 750 08872)
ISP1105_1106_1107-06 20011130
(9397 750 08681)
ISP1105_1106_1107-05 20010903
(9397 750 08643)
ISP1105_1106_1107-04 20010802
(9397 750 08515)
ISP1105_1106_1107-03 20010704
(9397 750 07879)
-
-
ISP1107-02
(9397 750 06899)
20010205
Objective specification; ISP1107
stand-alone data sheet only
ISP1107-01
ISP1107-01
(9397 750 08643)
20000223
Objective specification; ISP1107 --
stand-alone data sheet only
-
ISP1105_1106_9
© ST-NXP Wireless 2009. All rights reserved.
Product data sheet
Rev. 09 — 19 January 2009
26 of 30
ISP1105/1106
34ꢀ.80 7IRELESS
Advanced USB transceivers
19. Tables
Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2
Table 2. Selection guide . . . . . . . . . . . . . . . . . . . . . . . . .2
Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table 4. Function table . . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 5. Driving function (pin OE = L) using single-ended
input data interface for ISP1105
(pin MODE = L) . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 6. Driving function (pin OE = L) using differential
input data interface for ISP1105 (pin MODE = H)
and ISP1106 . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 7. Receiving function (pin OE = H) . . . . . . . . . . . .7
Table 8. Pin states in disable or sharing mode . . . . . . . .8
Table 9. Power supply configuration overview . . . . . . . .8
Table 10. Power supply input options . . . . . . . . . . . . . . . .9
Table 11. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 12. Recommended operating conditions . . . . . . . .11
Table 13. Static characteristics: supply pins . . . . . . . . . .12
Table 14. Static characteristics: digital pins . . . . . . . . . . .13
Table 15. Static characteristics: analog I/O pins (D+, D−) 14
Table 16. Dynamic characteristics: analog I/O pins
(D+, D−) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 17. Type A carrier tape dimensions for
ISP1105/1106W . . . . . . . . . . . . . . . . . . . . . . . .21
Table 18. SnPb eutectic process (from J-STD-020C) . . .23
Table 19. Lead-free process (from J-STD-020C) . . . . . .23
Table 20. Revision history . . . . . . . . . . . . . . . . . . . . . . . .26
ISP1105_1106_9
© ST-NXP Wireless 2009. All rights reserved.
Product data sheet
Rev. 09 — 19 January 2009
27 of 30
ISP1105/1106
34ꢀ.80 7IRELESS
Advanced USB transceivers
20. Figures
Fig 1. Block diagram (combined ISP1105 and ISP1106). 3
Fig 2. Pin configuration ISP1105BS (HVQFN). . . . . . . . .4
Fig 3. Pin configuration ISP1105W (HBCC16). . . . . . . . .4
Fig 4. Pin configuration ISP1106DH (TSSOP16). . . . . . .4
Fig 5. Pin configuration ISP1106W (HBCC16). . . . . . . . .4
Fig 6. Human Body ESD test model.. . . . . . . . . . . . . . .10
Fig 7. Rise and fall times. . . . . . . . . . . . . . . . . . . . . . . .16
Fig 8. Timing of OE to D+, D-. . . . . . . . . . . . . . . . . . . . .16
Fig 9. Timing of D+, D- to RCV, VP, VM. . . . . . . . . . . . .16
Fig 10. Timing of VO/VPO, FSE0/VMO to D+, D-.. . . . . .16
Fig 11. Load for enable and disable times. . . . . . . . . . . .17
Fig 12. Load for VM, VP and RCV. . . . . . . . . . . . . . . . . .17
Fig 13. Load for D+, D-. . . . . . . . . . . . . . . . . . . . . . . . . . .17
Fig 14. HBCC16 package outline. . . . . . . . . . . . . . . . . . .18
Fig 15. HVQFN16 package outline. . . . . . . . . . . . . . . . . .19
Fig 16. TSSOP16 package outline. . . . . . . . . . . . . . . . . .20
Fig 17. Carrier tape dimensions. . . . . . . . . . . . . . . . . . . .21
Fig 18. Temperature profiles for large and small
components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Fig 19. (H)BCC footprint and solder resist mask
dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
ISP1105_1106_9
© ST-NXP Wireless 2009. All rights reserved.
Product data sheet
Rev. 09 — 19 January 2009
28 of 30
ISP1105/1106
34ꢀ.80 7IRELESS
Advanced USB transceivers
21. Contents
1
General description. . . . . . . . . . . . . . . . . . . . . . 1
2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3
4
4.1
5
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
7
Functional description . . . . . . . . . . . . . . . . . . . 7
Function selection. . . . . . . . . . . . . . . . . . . . . . . 7
Operating functions . . . . . . . . . . . . . . . . . . . . . 7
Power supply configurations. . . . . . . . . . . . . . . 8
Power supply input options. . . . . . . . . . . . . . . . 9
7.1
7.2
7.3
7.4
8
8.1
8.2
Electrostatic discharge (ESD). . . . . . . . . . . . . 10
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . 10
ESD test conditions . . . . . . . . . . . . . . . . . . . . 10
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 11
Recommended operating conditions. . . . . . . 11
Static characteristics. . . . . . . . . . . . . . . . . . . . 12
Dynamic characteristics . . . . . . . . . . . . . . . . . 15
Test information. . . . . . . . . . . . . . . . . . . . . . . . 17
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18
Packing information . . . . . . . . . . . . . . . . . . . . 21
10
11
12
13
14
15
16
Soldering of SMD packages . . . . . . . . . . . . . . 22
Introduction to soldering . . . . . . . . . . . . . . . . . 22
Wave and reflow soldering . . . . . . . . . . . . . . . 22
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 22
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 23
16.1
16.2
16.3
16.4
17
17.1
17.2
Additional soldering information . . . . . . . . . . 25
(H)BCC packages: footprint . . . . . . . . . . . . . . 25
(H)BCC packages: reflow soldering profile. . . 25
18
19
20
21
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 26
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
30
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© ST-NXP Wireless 2009.
All rights reserved.
For more information, please visit: http://www.stnwireless.com
Date of release: 19 January 2009
Document identifier: ISP1105_1106_9
ISP1105/1106
34ꢀ.80 7IRELESS
Advanced USB transceivers
Please Read Carefully:
Information in this document is provided solely in connection with ST-NXP products. ST-NXP Wireless NV and its subsidiaries (“ST-NXP”)
reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described
herein at any time, without notice.
All ST-NXP products are sold pursuant to ST-NXP’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST-NXP products and services described herein, and ST-NXP
assumes no liability whatsoever relating to the choice, selection or use of the ST-NXP products and services described herein. No license,
express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document
refers to any third party products or services it shall not be deemed a license grant by ST-NXP for the use of such third party products or
services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third
party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST-NXP’S TERMS AND CONDITIONS OF SALE ST-NXP DISCLAIMS ANY EXPRESS OR
IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST-NXP PRODUCTS INCLUDING WITHOUT LIMITATION
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE
LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST-NXP REPRESENTATIVE, ST-NXP PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST-NXP PRODUCTS WHICH ARE NOT SPECIFIED AS
"AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST-NXP products with provisions different from the statements and/or technical features set forth in this document shall immediately
void any warranty granted by ST-NXP for the ST-NXP product or service described herein and shall not create or extend in any manner
whatsoever, any liability of ST-NXP.
ST-NXP and the ST-NXP logo are trademarks or registered trademarks of ST-NXP in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST-NXP logo is a registered trademark of ST-NXP Wireless. All other names are the property of their respective owners.
© 2009 ST-NXP Wireless - All rights reserved
ST-NXP Wireless group of companies
Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - India - Italy - Japan - Korea - Malaysia - Mexico -
Netherlands - Singapore - Sweden - Switzerland - Taiwan - United Kingdom - United States of America
www.stnwireless.com
Date of release: 19 January 2009
Document identifier: ISP1105_1106_9
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