L5955 [STMICROELECTRONICS]
Multiple multifunction voltage regulator for car radio; 汽车收音机的多功能多电压调节器
| 型号： | L5955 |
| 厂家： | 
ST |
| 描述： | Multiple multifunction voltage regulator for car radio |
| 文件： | 总17页 (文件大小：204K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L5955
Multiple multifunction voltage regulator for car radio
Features
■ 2 stand-by regulators:
3.3V (125mA)
1.5V (300mA)
■ 6 regulators:
10V (40mA)
8.5V (200mA)
3.3V (850mA)
8/10V (1A)
Flexiwatt27
5/3.3/1.8V (200mA)
1.8/2.5V(200mA)
■ All regulators are low dropout outputs
■ The different outputs voltage are controlled by
■ Independent current limiting
■ Short circuit protection
2
I C Bus.
■ Reg3 on/off controlled by enable
■ Load dump protection and overvoltage
■ Reg1, Reg2, Reg4, Reg5, Reg6 on/off
shutdown
2
controlled by I CBus.
■ 3 high side drivers:
2A (HSD1)
Description
0.45A (HSD2 & HSD3)
The L5955 is an integration of three high side
drivers, six regulators and two stand-by regulators
with RESET function developed to provide the
power to a complete audio system.
■ No external charge pump capacitors are
required
2
■ Stand-by mode controlled by EN pin for I C
2
Bus and Reg1, Reg2, Reg3, Reg4, Reg5,
Reg6, HSD1, HSD2, HSD3
The outputs of the IC are controlled by I C bus
and Enable pin.
■ LVW function externally selectable
■ Individual thermal shutdown
The device is equipped with sequencing and slew
rate controls for the st-by regulators.
Table 1.
Device summary
Order code
Package
Flexiwatt27
Packing
L5955
Tube
August 2007
Rev 1
1/17
www.st.com
17
Contents
L5955
Contents
1
2
Block and pin connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
2.2
2.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
3.2
3.3
Write mode: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Chip address byte: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Data byte: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4
5
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/17
L5955
Block and pin connection diagrams
1
Block and pin connection diagrams
Figure 1.
Block diagram
VBAT1
ST-By REG 3.3V
VSTBY1
BG1
BG2
VBG
CSLEW
And
VSTBY2
BANDGAP
St_By REG 1.5V
Sequencing
CSLEW
VBAT3_1/2
MRST*
10V Linear
REG1
Vstby1
Vstby2
Regulator
Standby Regulators
POR Logic
MRSTDLY
SDA
8.5V Linear
Regulator
REG2
I2C Interface
SCL
EN
3.3V Linear
Regulator
REG3
VBAT1
VBG
LVWIN
LVW*
Low Voltage
Warning
8V Linear Regulator
10V selectable
REG4
REG5
REG6
High Side
Driver
HSD1
HSD2
5V Linear Regulator
1.8-3.3V selectable
High Side
Driver
1.8V Linear Regulator
2.5V selectable
HSD3
High Side
Driver
GND
VBAT2
PGND
Figure 2.
Pin connection (top view)
27
26
25
24
23
TAB2
REG4
V
BAT3_2
REG3
V
BAT2
REG6
SCL
22
21
20
19
18
17
16
15
14
13
12
11
10
9
STBY2
V
BAT1
STBY1
MRST
REG5
MRSTDLY
GND
LVW
REG1
LVW_IN
REG2
Cslew
HSD3
EN
8
7
6
HSD2
V
5
4
3
2
1
BAT3_1
HSD1
PGND
SDA
TAB1
D04AU1548
3/17
Electrical specification
L5955
2
Electrical specification
2.1
Absolute maximum ratings
Table 2.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
VS1,
VS2,
VS3_1,
VS3_2
DC operating supply voltage
Transient supply over voltages,
0.6 to 26.5
V
VS1,
VS2,
VS3_1,
VS3_2
rise time = 10ms
34
V
delay time = 115ms
VS1,2,3_1,3
Overvoltage shutdown
27
V
V
_2,ovs
Input voltages (EN, SDA, SCL, LVW, MRST, MRSTDLY,
CSLEW)
Vin
-0.6 to 5.5
Vout
Top
Output control voltage
-0.6 to 18
-40 to 85
-40 to 150
V
Operating temperature range
Storage temperature range
°C
°C
Tstg
2.2
Thermal data
Table 3.
Symbol
Thermal data
Parameter
Value
Unit
Rth j-case Thermal resistance junction to case
1
°C/W
4/17
L5955
Electrical specification
2.3
Electrical characteristics
Table 4.
Electrical characteristics
(Refer to the application circuit, Vbat =V
+V
+V
= 14V, IST-BY1 = 0.5mA, IST-BY2 =
bat3
bat1
bat2
0.5mA, IREG1 = IREG2 = IREG3 = IREG4 = IREG5 = IREG6 = 5mA, RHSD1 = RHSD2 = RHSD3 = 16Ω)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
Vbat = 14V, EN = 0.
IqST-BY Stand-by quiescent current
170
μA
IST-BY1 = Istby2=100uA,
IQ(Vbat)=Ivbat1+Ivabt2+Ivbat3
Vbat = 14V, EN=VSTBY1
Istby1=125mA Istby2=300mA
IREG1 = 40mA
IREG2 = 200mA, IREG3 = 850mA
IREG4 = 1A, IREG5 = 250mA
Iq
Maximum quiescent current
100
mA
IREG6 = 200mA, IHSD1 = 2A
IHSD2,3 = 450mA
μA
IEN
Enable input current
Vbat = 14V; 5V<Enable ≥ 0V;
10
VIL
V
V
Enable threshold voltage
Vbat = 14V;
0.8
VIH
2
VST-BY1 = 0.5V to VTH (ST-BY1)
VST-BY2 = 0.5V to VTH (ST-BY2)
Rising
0
0
0.4
0.4
VL MRST
V
MRST output voltage
VST-BY1 = VTH (ST-BY1) to 0.5V
VST-BY2 = VTH (ST-BY2) to 0.5V
Falling
0
0
0.4
0.4
VH MRST
V
V
VST-BY2
· 0.93
VST-BY2
· 0.97
Force VST-BY1 & VST-BY2
Low until MRST asserted
VTH MRST MRST output voltage threshold
VST-BY1
· 0.93
VST-BY1
· 0.97
V
td MRST MRST delay time
see Figure 4
13
μs
CMRSTLY = 220nF
tpor MRST Power on reset delay time
20
6
ms
see Figure 4
RRST = 47kΩ, CRST = 50pF
tf MRST MRST fall time
1
12
6
μs
μA
μA
see Figure 4
ISCR MRST MRSTDLY current
MRSTDLY = 0
MRSTDLY = 5V
ILKG
MRSTDLY leakage current
MRSTDLY
Vsat
MRSTDLY saturation voltage
IMRSTDLY =0.5mA
1.25 V (nominal)
0
0.4
V
MRSTDLY
VTH
LVWIN input voltage threshold
lvwin input leakage current
1.22
1.28
2
V
ILKG
µA
VSTBY1
-0.2
VOH
LVW output voltage
IOH=-100µA
VSTBY1
V
5/17
Electrical specification
L5955
Table 4.
Electrical characteristics (continued)
(Refer to the application circuit, Vbat =V
+V
+V
= 14V, IST-BY1 = 0.5mA, IST-BY2 =
bat3
bat1
bat2
0.5mA, IREG1 = IREG2 = IREG3 = IREG4 = IREG5 = IREG6 = 5mA, RHSD1 = RHSD2 = RHSD3 = 16Ω)
Symbol
Parameter
Test condition
IOL = 100µA
Min.
Typ.
Max.
Unit
VOL
LVW output voltage
0
0.2
V
HSDS, REGS, VST-BY1, VST-BY2
min. load.
Thermal shutdown for HSDS,
TS
170
10
°C
°C
REGS, V
, V
Increase Tamb until HSDS,
REGS, VST-BY1,2 Disabled
ST-BY1 ST-BY2
HSDS, REGS, VST-BY1, VST-BY2
min. load.
Thermal shutdown hysteresis for
HSDS, REGS, VST-BY1, VST-BY2
TS HYS
Decrease Tamb until HSDS,
REGS, VST-BY1,2 Disabled
Io
CSLEW output current
7
14
µA
ms
ST-BY1, ST-BY2. minimum turn
on time
ton
CSLEW=7nF; see Figure 5
1.6
3.3V/125mA VST-BY1
VST-BY1 Output voltage
IST-BY1 = 125mA
3.14
3.46
10
V
7V ≤ VBAT ≤ 18V
(Measure ΔVreg1 across VBAT
range)
ΔVline Line regulation
ΔVload Load regulation
mV
0.5mA ≤ IST-BY1 ≤ 125mA
50
mV
(Measure
range)
ΔVreg1 across V
BAT
Δ Quiescent current
IST-BY1 = 2mA, VBAT = 14V,
IST-BY1 = 125mA, VBAT = 14V
150
10
μA
mA
Iq1
(measure ΔIBAT
)
IST-BY1 = 125mA
IST-BY1 = 5mA
2.6
1.2
V
V
Dropout voltage (measure VBAT
VST-BY1 when VST-BY1drops 0.1V)
-
VDROPOUT
Ilim1
Current limit
160
350
2.5
mA
V
force VST-BY2 Low; Measure
VST-BY1 - VST-BY2
ΔVlead
VST-BY1 absolute differential
output voltage
force VST-BY1 Low; Measure
VST-BY1 - VST-BY2
ΔVlag
0.25
V
fo = 120-10kHz, VBAT = 14V
with 1.0Vp-p AC,
50
45
dB
dB
SVR1 Supply voltage rejection ST-BY1
fo = 20-20kHz, VBAT = 14V
with 1.0Vp-p AC
1.5V/300mA VST-BY2
VST-BY2 Output voltage
IST-BY2 = 300mA
1.425
1.575
50
V
7V ≤ VBAT ≤ 18V
(measure Δ VST-BY2 across VBAT
ΔVline Line regulation
mV
range)
6/17
L5955
Electrical specification
Table 4.
Electrical characteristics (continued)
(Refer to the application circuit, Vbat =V
+V
+V
= 14V, IST-BY1 = 0.5mA, IST-BY2 =
bat3
bat1
bat2
0.5mA, IREG1 = IREG2 = IREG3 = IREG4 = IREG5 = IREG6 = 5mA, RHSD1 = RHSD2 = RHSD3 = 16Ω)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
ΔVload Load regulation
Dropout voltage (measure VBAT
0.5mA ≤ IST-BY2 ≤ 300mA
100
mV
IST-BY2 = 300mA
IST-BY2 = 5mA
4.1
3
V
V
-
VDROPOUT
VST-BY2 when VST-BY2 drops0.1V)
Ilim2
Current limit
360
50
700
mA
dB
fo = 120-10kHz, VBAT = 14V
with 1.0Vp-p AC,
SVR3 Supply voltage rejection ST-BY2
fo = 20-20kHz, VBAT = 14V
with 1.0Vp-p AC
45
dB
10V/40mA REG1 output
VREG1 Output voltage
IREG1 = 40mA
9.50
10
10.5
55
V
11.4V
≤
V
≤ 18V (measure Δ
BAT
ΔVline Line regulation
ΔVload Load regulation
mV
mV
V
across V
range)
REG1
BAT
5mA ≤ IREG1 ≤ 40mA
55
IREG1 = 40mA
IREG1 = 5mA
1200
300
mV
mV
Dropout voltage (measure VBAT
VREG1 when VREG1 drops 0.1V)
-
VDROPOUT
Ilim1
Current limit
60
50
200
mA
Supply voltage rejection
(guaranteed by characterization-
test at 1kHz with 50dB Limit)
SVR
dB
8.5V/200mA REG2 output
VREG2 Output voltage
IREG2 = 200mA
8.3
8.5
8.7
50
50
V
9.6V
across V
≤
V
≤
18V (measure
Δ
V
REG2
BAT
BAT
ΔVline Line regulation
ΔVload Load regulation
mV
mV
range)
5mA ≤ IREG2 ≤ 200mA
IREG2 = 200mA
IREG2 = 5mA
1100
600
mV
mV
Dropout voltage (measure VBAT
-
VDROPOUT
VREG2 when VREG2 drops 0.1V)
Ilim2
Current limit
225
50
525
mA
Ripple rejection (guaranteed By
characterization-test at 1kHz with
50dB limit)
SVR
dB
3.3V/850mA REG3 output
VREG3 Output voltage
IREG3 = 850mA
3.14
3.46
40
V
7V
Across V
≤
V
≤
18V (Measure
range)
Δ
V
BAT
REG2
ΔVline Line regulation
ΔVload Load regulation
mV
mV
BAT
5mA ≤ IREG3 ≤ 850mA
100
IREG3 = 850mA
-
3.46
2.86
V
V
Dropout voltage (measure VBAT
VREG3 when VREG3 drops 0.1V)
VDROPOUT
I
REG3 = 5mA
7/17
Electrical specification
L5955
Table 4.
Electrical characteristics (continued)
(Refer to the application circuit, Vbat =V
+V
+V
= 14V, IST-BY1 = 0.5mA, IST-BY2 =
bat3
bat1
bat2
0.5mA, IREG1 = IREG2 = IREG3 = IREG4 = IREG5 = IREG6 = 5mA, RHSD1 = RHSD2 = RHSD3 = 16Ω)
Symbol
Parameter
Current limit
Test condition
Min.
Typ.
Max.
Unit
Ilim4
1.25
2.5
A
Ripple rejection (guaranteed by
characterization-test at 1kHz with
50dB Limit)
SVR
50
dB
8V/10V/1A REG4 output
7.6
8.4
V
V
VREG4 Output voltage
IREG4 = 1A
9.50
10.5
11.4V ≤ VBAT ≤ 18V, For
VREG4=10V
50
50
mV
mV
ΔVline Line regulation
ΔVload Load regulation
9.3V<VBAT<18V For VREG4=8V
(measure Δ VREG4 across VBAT
range)
5mA ≤ IREG4≤ 1A
150
mV
IREG4 = 1A
-
1.100
600
mV
mV
Dropout voltage (measure VBAT
VREG4 when VREG4 drops 0.1V)
VDROPOUT
IREG4 = 5mA
Ilim4
Current limit
1.5
50
3
A
Ripple rejection (guaranteed By
characterization-test at 1kHz with
50dB Limit)
SVR
dB
1.8-3.3-5V/250mA REG5 output
1.71
3.14
4.75
1.89
3.46
5.25
V
V
V
VREG5 Output voltage
IREG5 = 250mA
7V ≤ VBAT ≤ 18V for VREG5=1.8V,
3.3V
ΔVline Line regulation
ΔVload Load regulation
9V<VBAT>18V for VREG5=5V
40
mV
(measure Δ VREG5 across VBAT
range)
5mA ≤ IREG5 ≤ 250mA
100
mV
IREG5 = 250mA @ VREG5=1.8V
IREG5 = 5mA @ VREG5=1.8V
IREG5 = 250mA @ VREG5=3.3V
IREG5 = 5mA @ VREG5=3.3V
IREG5 = 250mA @ VREG5=5V
IREG5 = 5mA @ VREG5=5V
4.89
4.29
3.46
2.86
1.85
1.25
V
V
V
V
V
V
Dropout voltage (measure VBAT
VREG5 when VREG5 drops 0.1V)
-
VDROPOUT
Ilim5
Current limit
300
50
700
mA
Ripple rejection (guaranteed by
characterization-test at 1kHz with
50dB limit)
SVR
dB
8/17
L5955
Electrical specification
Table 4.
Electrical characteristics (continued)
(Refer to the application circuit, Vbat =V
+V
+V
= 14V, IST-BY1 = 0.5mA, IST-BY2 =
bat3
bat1
bat2
0.5mA, IREG1 = IREG2 = IREG3 = IREG4 = IREG5 = IREG6 = 5mA, RHSD1 = RHSD2 = RHSD3 = 16Ω)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
1.8-2.5V/200mA REG6 output
1.71
2.38
1.89
2.62
V
V
VREG6 Output voltage
IREG6 = 200mA
7V ≤ VBAT ≤ 18V (measure Δ
VREG6 across VBAT range)
ΔVline Line regulation
ΔVload Load regulation
40
50
mV
mV
5mA ≤ IREG6 ≤ 200mA
IREG6 = 200mA @ VREG6=1.8V
IREG6 = 5mA @ VREG6=1.8V
IREG6 = 200mA @ VREG6=2.5V
IREG6 = 5mA @ VREG6=2.5V
4.89
4.29
4.22
3.62
V
V
V
V
Dropout voltage (measure VBAT
VREG6 when VREG6 drops 0.1V)
-
VDROPOUT
Ilim6
Current limit
240
50
600
mA
Ripple rejection (guaranteed by
characterization-test at 1kHz with
50dB limit)
SVR
dB
2A HSD1
IHSD1 = 1A
0.6
V
Vsat
Output saturation voltage
continuous time operation
IHSD1=2A t=5seconds
1.2
50
4
V
μA
A
Ileak1
Ilim
Output leakage current
Current limiting
All Driver Outputs are Off
RHSD1 = 0.5Ω
2.4
0.45A HSD2 & HSD3
IHSD2,3 = 300mA
0.6
V
Vsat
Output saturation voltage
continuous time operation
IHSD2,3=450mA t=5 seconds
1.2
50
1
V
μA
A
Ileak2,3 Output leakage current
All driver outputs are Off
Ilim
Current limiting
RHSD2,3 = 0.5Ω
0.550
Characteristics for I2C
VIL
VIH
LOW level input voltage
1.5
V
V
V
V
HIGH level input voltage
Input hysteresis
3
VHYS
VOL1
0.2
Sink current = 3mA
0.4
LOW level output
VOL1
I1
Sink current = 6mA
0.6
10
V
Input current
0.5V ≤ VI ≤ 4.5V
μA
fSCL
SCL clock frequency
400
kHz
9/17
Functional description
L5955
3
Functional description
The three high side drivers are one 2A output (HSD1) and two 450mA outputs (HSD2 & 3).
The six regulator outputs are 10V at 40mA (REG1), 8.5V at 200mA (REG2), 3.3V at 850mA
(REG3), 8/10V at 1A (REG4), 1.8V/3.3V/5V at 250mA (REG5) and 1.8V/2.5V at 200mA
(REG6).
The two stand-by regulators are 3.3V at 125mA (ST-BY1) and 1.5V at 300mA (ST-BY2).
ST-BY1 and ST-BY2 are equipped with Reset function.
ST-BY1 and ST-BY2 share one Reset output (MRST).
A slew rate limiter and a sequencing function control ST-BY1 and ST-BY2 turn on/off.
The 8.5V regulator output (REG2) has a tighter tolerance output than the other regulator
outputs.
The 8.5V output is a 2.5% (5% total range) output over temperature to improve
performance and reduce cost on the 8.5V output. The other outputs are 5% over
temperature.
The two STAND-BY regulators are switched on/off from battery line.
2
The REG3 is switched on/off by Enable pin which also activate the I C BUS.
2
The other Regulators and HSD’s are turned on/off independently by I C BUS, which also
controls the regulators' output voltages.
With ENABLE pin set to 0 the total current sunk from the battery line minimized.
Figure 3.
Reset and power-on reset schematic
5V
rst*
RST*
1μA
RESET DRIVER
LATCH
IVCP(1FAULT)
S
Q
VSTBY1
VSTBY2
FF1
MA
5.6pF
R
Q
5V
1μA
FOR MRST
CRSTDLY
REG6
FOR RSTR6
PULL DOWN
LATCH
S
Q
MB
0.22
μF
FF2
R
Q
WINDOW
COMPARATOR
D02AU1401
10/17
L5955
Functional description
Figure 4.
Reset timing
<td MRST
<td RSTR6
td MRST
td RSTR6
tpor
VREG6
VSTBY1 or 2
tf MRST
tf RSTR6
MRST*
RSTR6
D02AU1402
Figure 5.
SLEW function
V
VSTBY1
VSTBY2
3.3V
1.5V
t
tON
Figure 6.
Sequencing function
V
VBAT
t
V
STBY1
STBY2
dVlead
dVIag
dVIag
D02AU1404
t
11/17
Functional description
L5955
Figure 7.
Definition of timing on the I2C Bus.
SDA
t
BUP
t
R
t
F
t
t
SP
HD;STA
t
LOW
SCL
t
t
t
t
t
t
SU;STO
HD;DAT
HD;DAT
HIGH
SU;DAT
SU;STA
P
S
Sr
D99AU1007
P
Figure 8.
Typical application circuit
8 x 10μF
VBAT1
19
STBY1
18
20
VBAT2
23
STBY2
REG1
REG2
REG3
REG4
REG5
REG6
VBAT3_1
5
12
VBAT3_2
25
10
24
26
EN
7
SCL
21
16
22
SDA
2
Cslew
9
MRSTDLY
15
4
HSD1
T.B.D.
0.1μF
6
8
HSD2
HSD3
13
LVW
STBY1
10K
GND
14
3
PGND
TAB1
TAB2
VBAT1
MRST
17
11
1
T.B.D.
27
LVW_IN
T.B.D.
3.1
Write mode:
Chip address
Data byte
S
0
A
A
.. ..
P
MSB
LSB
MSB
LSB
S = START condition - SDA goes from high to low while SCL is high
A = Acknowledge - the device being written to, pulls down on data line (SDA) during the
acknowledge clock pulse.
P = STOP condition - SDA goes from low to high while SCL is high.
12/17
L5955
Functional description
3.2
Chip address byte:
Table 5.
Chip address byte
Chip address
Read/write
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
1
0
0
0
0
3.3
Data byte:
Table 6.
b7
Data byte
b6
b5
b4
b3
b2
b1
b0
Data byte 0
REG6 SET REG5 SET2 REG5 SET1 REG4 SET
Data byte 1
REG4EN
HSD3EN
REG2EN
HSD2EN0
REG1EN
HSD1EN0
REG6EN
REG5EN
Default mode is 0000 0000 which corresponds to all outputs being off, low power mode.
Table 7.
Data byte 0 description
Name
Description
State
Definition
bit
0
1
1.8V
2.5V
5.0V
3.3V
1.8V
x
b7
b7
REG6 SET
REG6 output voltage configuration
00
01
10
11
0
b5, b6
b5, b6
b5, b6
b5, b6
b4
REG5 SET1
REG5 SET2
REG5 output voltage configuration
8.0V
10.0V
Off
REG4 SET
HSD3EN
HSD2EN
HSD1EN
REG4 output voltage configuration
HSD3 Enable
1
b4
0
b2
1
On
b2
0
Off
b1
HSD2 Enable
1
On
b1
0
Off
b0
HSD1 Enable
1
On
b0
13/17
Functional description
L5955
Table 8.
Data byte 1 description
Name
Description
State
Definition
bit
0
1
0
1
0
1
0
1
0
1
Off
On
Off
On
Off
On
Off
On
Off
On
REG6 EN
REG6 Enable
b6
b5
b4
b2
b1
REG5 EN
REG4 EN
REG2 EN
REG1 EN
REG5 Enable
REG4 Enable
REG2 Enable
REG1 Enable
14/17
L5955
Package information
4
Package information
®
In order to meet environmental requirements, ST offers these devices in ECOPACK
packages. These packages have a lead-free second level interconnect. the category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 9. Flexiwatt27 (vertical) mechanical data and package dimensions
mm
inch
TYP. MAX.
DIM.
MIN. TYP. MAX. MIN.
OUTLINE AND
MECHANICAL DATA
A
B
C
D
E
4.45
1.80
4.50
1.90
1.40
0.90
0.39
4.65 0.175 0.177 0.183
2.00 0.070 0.074 0.079
0.055
1.05 0.029 0.035 0.041
0.42 0.014 0.015 0.016
0.75
0.37
F (1)
G
0.57
0.022
0.80
1.00
1.20 0.031 0.040 0.047
G1
25.75 26.00 26.25 1.014 1.023 1.033
H (2) 28.90 29.23 29.30 1.139 1.150 1.153
H1
H2
H3
17.00
12.80
0.80
0.669
0.503
0.031
L (2) 22.07 22.47 22.87 0.869 0.884 0.904
L1 18.57 18.97 19.37 0.731 0.747 0.762
L2 (2) 15.50 15.70 15.90 0.610 0.618 0.626
L3
L4
L5
M
M1
N
7.70
7.85
5
3.5
4.00
4.00
2.20
2
7.95 0.303 0.309 0.313
0.197
0.138
3.70
3.60
4.30 0.145 0.157 0.169
4.40 0.142 0.157 0.173
0.086
0.079
O
R
1.70
0.5
0.3
1.25
0.50
0.067
0.02
0.12
0.049
R1
R2
R3
R4
V
V1
V2
V3
0.019
5˚ (Typ.)
3˚ (Typ.)
20˚ (Typ.)
45˚ (Typ.)
Flexiwatt27 (vertical)
(1): dam-bar protusion not included
(2): molding protusion included
V
C
B
V
H
H1
V3
A
H2
R3
H3
R4
V1
R2
R
L
L1
V1
V2
D
R2
R1
R1
M
R1
E
L5
Pin 1
G
F
G1
FLEX27ME
M1
7139011
15/17
Revision history
L5955
5
Revision history
Table 9.
Date
29-Aug-2007
Document revision history
Revision
Changes
1
Initial release.
16/17
L5955
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