L5993D [STMICROELECTRONICS]
CONSTANT POWER CONTROLLER; 恒功率控制器
| 型号： | L5993D |
| 厂家： | 
ST |
| 描述： | CONSTANT POWER CONTROLLER |
| 文件： | 总22页 (文件大小：201K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L5993
CONSTANT POWER CONTROLLER
CURRENT-MODE CONTROL PWM
SWITCHING FREQUENCY UP TO 1MHz
MULTIPOWER BCD TECHNOLOGY
LOW START-UP CURRENT (< 120 A)
µ
CONSTANT OUTPUT POWER VS. SWITCH-
ING FREQUENCY
HIGH-CURRENT OUTPUT DRIVE SUITABLE
FOR POWER MOSFET (1A)
FULLY LATCHED PWM LOGIC WITH DOU-
BLE PULSE SUPPRESSION
DIP16
SO16N
PROGRAMMABLE DUTY CYCLE
100%AND 50%MAXIMUMDUTY CYCLELIMIT
ORDERING NUMBERS: L5993 (DIP16)
L5993D (SO16)
PROGRAMMABLE SOFT START
PRIMARY OVERCURRENT FAULT DETEC-
TION WITH RE-START DELAY
PWM UVLO WITH HYSTERESIS
IN/OUT SYNCHRONIZATION
LATCHED DISABLE
INTERNAL 100ns LEADING EDGE BLANK-
ING OF CURRENT SENSE
PACKAGE:DIP16 AND SO16N
line or DC-DC power supply applications using a
fixed frequencycurrent mode control.
Based on a standard current mode PWM control-
ler this device includes some features such as
programmable soft start, IN/OUT synchronization,
disable (to be used for over voltage protection and
for power management), precise maximum Duty
Cycle Control, 100ns leading edge blanking on
current sense, pulse by pulse current limit, over-
current protection with soft start intervention and
”constant power” function for cotrolling throughput
power in multisync monitor SMPS.
DESCRIPTION
This primary controller I.C., developed in BCD60II
technology, has been designed to implement off
BLOCK DIAGRAM
VCC
SYNC
1
DC-LIM
15
VREF
4
8
2
RCT
TIMING
25V
Vref
+
-
3
+
-
DC
T
15V/10V
PWM UVLO
14
9
-
DIS
DIS
VC
+
2.5V
+
-
13V
C-POWER
10
16
OUT
BLANKING
S
Q
R
PWM
OVER CURRENT
VREF OK
CLK
DIS
11
5
13
7
PGND
VFB
FAULT
SOFT-START
ISEN
SS
+
-
1.2V
+
E/A
-
2.5V
2R
1V
R
12
6
D97IN765
SGND
COMP
1/22
July 1999
L5993
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Supply Voltage (ICC < 50mA) (*)
Output Peak Pulse Current
Value
selflimit
1.5
Unit
V
VCC
IOUT
A
Analog Inputs & Outputs (6,7)
-0.3 to 8
-0.3 to 6
V
Analog Inputs & Outputs (1,2,3,4,5,15,14, 13, 16)
V
Ptot
Power Dissipation @ Tamb = 70 C (DIP16)
1
0.83
W
W
°
@ Tamb = 50°C (SO16)
Junction Temperature, Operating Range
Storage Temperature, Operating Range
Tj
-40 to 150
-55 to 150
°C
°C
Tstg
(*) maximum package power dissipation limits must be observed
PIN CONNECTION
SYNC
RCT
DC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
C-POWER
DC-LIM
DIS
VREF
VFB
ISEN
SGND
PGND
OUT
COMP
SS
VCC
VC
D97IN783
THERMAL DATA
Symbol
Parameter
Value
Unit
Rth j-amb
Thermal Resistance Junction -Ambient (DIP16)
Thermal Resistance Junction -Ambient (SO16)
80
120
C/W
°
°C/W
PIN FUNCTIONS
N.
1
Name
SYNC
RCT
Function
Synchronization. A synchronization pulse terminates the PWM cycle and discharges Ct
Oscillator pin for external Ct, Rt components
Duty Cycle control
2
3
DC
4
VREF
VFB
5.0V +/-1.5% reference voltage at 25°C
Error Amplifier Inverting input
5
6
COMP
SS
Error Amplifier Output
7
Soft start pin for external capacitor Css
Supply for internal ”Signal” circuitry
Supply for Power section
8
VCC
9
VC
10
11
12
13
14
15
OUT
PGND
SGND
ISEN
DIS
High current totem pole output
Power ground
Signal ground
Current sense
Disable. It must never be left floating. Tie to SGND if not used.
DC-LIM
Connecting this pin to Vref, DC is limited to 50%. If it is left floating or grounded no limitation is
imposed
16
C-POWER Constant Power vs. Switching Frequency. Connect a capacitor to SGND. The pin must be
connected to VREF if not used.
2/22
L5993
ELECTRICAL CHARACTERISTICS CC
j
°
Ω
(V = 15V; T = 0 to 105 C; RT = 13.3k ; CT = 1nF
unless otherwisespecified.)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
REFERENCE SECTION
VRef
Output Voltage
Tj = 25°C; IO = 1mA
4.925
5.0
2.0
2.0
0.4
5.0
5.075
10
V
mV
mV
mV/°C
V
Line Regulation
VCC = 12 to 20V; Tj = 25°C
IO = 1 to 10mA; Tj = 25°C
Load Regulation
Temperature Stability
Total Variation
10
TS
Line, Load, Temperature
Vref = 0V
4.80
30
5.130
150
IOS
Short Circuit Current
Power Down/UVLO
mA
V
VCC = 8.5V; Isink = 0.5mA
0.2
0.5
OSCILLATOR SECTION
Initial Accuracy
pin 15 = Vref
Tj = 25°C
CC = 12 to 20V
95
93
100
100
105
107
kHz
kHz
V
Duty Cycle
Duty Cycle
pin 3 = 0,7V, pin 15 = Vref
pin 3 = 0.7V, pin 15 = OPEN
0
0
%
%
pin 3 = 3.2V, pin 15 = Vref
pin 3 = 3.2V, pin 15 = OPEN
47
93
%
%
Duty Cycle Accuracy
pin 3 = 2.79V, pin 15 = OPEN
75
2.8
80
3.0
0.9
85
3.2
%
V
Oscillator Ramp Peak
Oscillator Ramp Valley
0.75
1.05
V
ERROR AMPLIFIER SECTION
Input Bias Current
V
FB to GND
0.2
2.5
90
3.0
A
µ
VI
Input Voltage
VCOMP = VFB
2.42
60
2.58
V
GOPL
SVR
VOL
VOH
IO
Open Loop Gain
VCOMP = 2 to 4V
dB
dB
V
Supply Voltage Rejection
Output Low Voltage
Output High Voltage
Output Source Current
Output Sink Current
Unit Gain Bandwidth
Slew Rate
VCC = 12 to 20V
85
Isink = 2mA, VFB = 2.7V
Isource = 0.5mA, VFB = 2.3V
VCOMP > 4V, VFB = 2.3V
VCOMP > 1.1V, VFB = 2.7V
1.1
2.5
5
6
1.3
6
V
0.5
2
mA
mA
MHz
1.7
4
SR
8
V/ s
µ
PWM CURRENT SENSE SECTION
Ib
Input Bias Current
Maximum Input Signal
Delay to Output
Gain
Isen = 0
3
1.0
70
3
15
A
µ
IS
VCOMP = 5V
0.92
2.85
1.08
100
3.15
V
ns
V/V
SOFT START
ISSC
SS Charge Current
SS Discharge Current
SS Saturation Voltage
SS Clamp Voltage
14
5
20
10
26
15
µA
µA
V
ISSD
VSS = 0.6V, Tj = 25°C
VSSSAT
DC = 0%
0.6
VSSCLAMP
7
V
LEADING EDGE BLANKING
Internal Masking Time
OUTPUT SECTION
100
ns
VOL
VOH
Output Low Voltage
Output High Voltage
IO = 250mA
1.0
V
V
V
V
IO = 20mA; VCC = 12V
IO = 200mA; VCC = 12V
IO = 5mA; VCC = 20V
10
9
10.5
10
VOUT CLAMP Output Clamp Voltage
13
3/22
L5993
ELECTRICAL CHARACTERISTICS
(continued.)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
OUTPUT SECTION
Collector Leakage
VCC = 20V VC = 24V
2
20
60
µA
Fall Time
CO = 1nF
CO = 2.5nF
20
35
ns
ns
Rise Time
CO = 1nF
CO = 2.5nF
50
70
100
1.0
ns
ns
UVLO Saturation
VCC = 0V to VCCON; Isink = 10mA
V
SUPPLY SECTION
VCCON
VCCOFF
Vhys
Startup voltage
14
9
15
10
5
16
11
V
V
Minimum Operating Voltage
ULVO Hysteresis
4.5
40
V
IS
Start Up Current
Before Turn-on at:
CC = VCCON - 0.5V
75
120
13
µA
V
Iop
Iq
Operating Current
Quiescent Current
Zener Voltage
CT = 1nF,R = 13.3k , C
9
mA
mA
V
Ω
T
O
=1nF
(After turn on), CT = 1nF,
RT = 13.3kΩ, CO = 0nF
7.0
25
10
VZ
I8 = 20mA
21
30
SYNCHRONIZATION SECTION
Master Operation
ISOURCE = 0.8mA
Vclock = 3.5V
Slave Operation
Low Level
V1
I1
Clock Amplitude
4
3
V
Clock Source Current
7
mA
V1
I1
Sync Pulse
1
V
V
High Level
3.5
0.5
Sync Pulse Current
VSYNC = 3.5V
mA
OVER CURRENT PROTECTION
Vt Fault Threshold Voltage
DISABLE SECTION
Shutdown threshold
Shutdown Current
CONSTANT POWER
1.1
2.4
1.2
1.3
2.6
V
2.5
V
ISH
VCC = 15V
330
µA
Figure 1. Quiescent current vs. input voltage.
Figure 2. Quiescent current vs. input voltage
(after disable).
Iq [mA]
30
Iq [µA]
350
V14 = 0, Pin2 = open
Tj = 25°C
20
8
300
250
200
150
6
4
0.2
V14 = Vref
Tj = 25 °C
0.15
0.1
100
50
0
0.05
0
0
4
8
12
16
20
24
12
16
20
24
0
4
8
28
Vcc [V]
Vcc [V]
4/22
L5993
Figure 3. Quiescent current vs. input voltage.
Figure 4. Quiescentcurrent vs. input voltage
and switching frequency.
Iq [mA]
9.0
Iq [mA]
36
V 14 = 0, V5 = Vref
30
24
18
12
6
R t = 4.5Kohm,Tj = 25°C
C o = 1nF, Tj = 25°C
8.5
DC = 0%
1M hz
500Khz
300Khz
1M Hz
8.0
100Khz
50 0KHz
30 0KHz
7.5
1 00KHz
7.0
0
8
10
12
14
16
18
20
22
8
10
12
14
16
18
20
22
24
Vc c [V]
Vcc [V]
Figure 5. Quiescent current vs. input voltage
and switching frequency.
Iq [mA]
Figure 6. Reference voltage vs. load current.
Vref [V]
5.1
36
Co = 1nF, Tj = 25°C
30
Vcc=15V
DC = 100%
5.05
Tj = 25°C
1MHz
24
5
500KHz
18
300KHz
4.95
4.9
12
100KHz
6
0
0
5
10
Iref [mA]
15
20
25
8
10
12
14
Vcc [V]
16
18
20
22
Figure 7. Vref vs. junction temperature.
Figure 8. Vref vs. junction temperature.
Vref [V])
5.1
Vref [V]
5.1
Vcc = 15V
Vcc = 15V
5.05
5.05
Iref= 20mA
Iref = 1mA
5
5
4.95
4.9
4.95
4.9
-50
-25
0
25
50
75
100 125 150
-50
-25
0
25
50
Tj (°C)
75
100 125 150
5/22
Tj (°C)
L5993
Figure 10. Output saturation.
Figure 9. Vref SVRR vs. switching frequency.
Vsat = V [V]
SVRR (dB)
10
16
Vcc = Vc = 15V
Vcc=15V
Vp-p=1V
120
14
12
10
8
Tj = 25°C
80
40
0
6
0
0.2
0.4
0.6
Isource [A]
0.8
1
1.2
1
10
100
1000
10000
fsw (Hz)
Figure 12. UVLO Saturation
Figure 11. Output saturation.
Vsat = V [V]
Ipin10 [mA]
50
10
2.5
Vcc < Vccon
40
2
Vcc = Vc = 15V
Tj = 25°C
beforeturn-on
1.5
30
1
0.5
0
20
10
0
0
0.2
0.4
0.6
0.8
1
1.2
0
200 400 600 800 1,000 1,200 1,400
Vpin10 [mV]
Isink [A]
Figure 14. Switching frequency vs. tempera-
ture
Figure 13. Timing resistor vs. switching fre-
quency.
fsw (KHz)
fsw (KHz)
320
5000
Vcc = 15V, V15 =0V
2000
Rt= 4.5Kohm, Ct = 1nF
Tj = 25°C
1000
500
310
Vcc = 15V, V15=Vref
100pF
220pF
470pF
200
100
50
300
290
280
1nF
2.2nF
5.6nF
20
10
10
20
Rt (kohm)
30
40
-50
-25
0
25
50
75
100
125
150
Tj (°C)
6/22
L5993
Figure 15. Switching frequency vs. temperature.
Figure 16. Dead time vs Ct.
Dead time [ns]
fsw (KHz)
320
1,500
1,200
900
Rt =4.5Kohm
Rt= 4.5Kohm, Ct = 1nF
V15 = 0V
310
Vcc = 15V, V15= 0
300
290
280
V15 = Vref
600
300
-50
-25
0
25
50
75
100
125 150
2
4
6
8
10
Tj (°C)
Timingcapacitor Ct [nF]
Figure 17. Maximum Duty Cycle vs Vpin3.
Figure 18. Delay to output vs junction tem-
perature.
DC Control Voltage Vpin3 [V]
3.5
Delay to output (ns)
42
V15 = 0V
V15 = Vref
3
2.5
2
40
38
36
34
Rt = 4.5Kohm,
Ct = 1nF
32
PIN10 = OPEN
1V pulse
on PIN13
1.5
1
30
28
-50
-25
0
25
50
75
100
125
150
0
10 20 30 40 50 60 70 80 90 100
Duty Cycle [%]
Tj (°C)
Figure 19. E/A frequency response.
Phase
140
G [dB]
150
120
100
80
100
50
0
60
40
20
0.01
0.1
1
10
100
1000 10000 100000
f (KHz)
7/22
L5993
CONSTANT POWER FUNCTION
APPLICATION INFORMATION
Detailed Pin Functions Description
Pulse-by-pulse current limitation prevents peak
primary current from exceeding a given level.
This, in turn, limits the maximum power deliver-
able to the output or, in other words, the power
capability of a converter. The capability, however,
depends on switching frequency: for example, in
a discontinuouscurrent mode flyback they are just
proportional.
In SMPS’ of raster-scanned CRT displays the
switching frequency is usually synchronized to the
raster line scan signal of the display in order to in-
crease noise immunity. More and more often,
CRT displays are required to operate within a
range of different video frequencies (e.g. from 31
kHz to 64 kHz), thus also the switching frequency
of the SMPS will vary in that range.
In case of some failure, the power throughputmay
be excessive without necessarily tripping the
pulse-by-pulsecurrent limitation circuit because of
a highoperating frequency.
For the sake of safety, it would be then desirable
to design the power stage of a converter (power
MOSFET, transformer, catch diode) so as to be
able to withstand the maximum power throughput
under failure conditions. However, this is a con-
siderable increase of size and cost.
Pin 1. SYNC (In/Out Synchronization). This func-
tion allows the IC’s oscillator either to synchronize
other controllers (master) or to be synchronized to
an external frequency (slave).
As a master, the pin delivers positive pulses dur-
ing the falling edge of the oscillator (see pin 2). In
slave operation the circuit is edge triggered. Refer
to fig. 21 to see how it works. When several IC
work in parallel no master-slave designation is
needed because the fastest one becomes auto-
matically the master.
During the ramp-up of the oscillator the pin is
pulled low by a 600µA internal sink current gener-
ator. During the falling edge, that is when the
pulse is released, the 600µA pull-down is discon-
nected. The pin becomes a generator whose
source capability is typically 7mA (with a voltage
still higher than 3.5V).
In fig. 20, some practical examples of synchroniz-
ing the L5993 are given.
Pin 2. RCT (Oscillator). A resistor (RT) and a ca-
pacitor (CT), connected as shown in fig. 21 set the
operatingfrequencyfosc of the oscillator.
CT is charged through RT until its voltage reaches
3V, then is quickly internally discharged. As the
voltage has dropped to 1V it starts being charged
again.
The frequency can be established with the aid of
fig. 13 diagrams or considering the approximate
relationship:
The ”Constant Power” function of the L5993 al-
lows to overcome this problem. The device
changes the threshold of its pulse-by-pulse cur-
rent limitation circuit so as to maintain fairly con-
stant the power capability of a flyback converter
despite the changesof the switching frequency.
This is accomplished by clamping the output of
the error amplifier (VCOMP) to a value which de-
creases as the frequency of the signal fed into pin
1 (SYNC) builds up.
1
fosc
(1)
CT (0.693 RT + KT)
The frequency-to-voltage conversion needed to
achieve this functionality is performed by detect-
ing the peak voltage of the (synchronized) oscilla-
tor with a peak-holding circuit. One external ca-
pacitor only is required.
where KT is defined as:
=
=
90, V15 VREF
KT =
(2)
160 V15 GND/OPEN
It is important to point out that shape, amplitude
and duration of the synchronization pulses are of
no concernwith this technique.
and is linked to the duration of the falling edge of
the sawtooth:
Td 30 10-9 + KT CT (3)
Td is also the duration of the sync pulses deliv-
Figure 20. Sinchronizing the L5993.
RT
SYNC
SYNC
VREF
L5993
1
1
L4981A
4
L4981A
(SLAVE)
(MASTER)
(SLAVE)
L5993
VREF
RT
L5993
SYNC
VREF
RT
RCT
SYNC
L5993
1
(MASTER)
4
16
1
4
2
SYNC
2
2
17
18
2
17
18
16
RCT
RCT
RCT
ROSC
ROSC
CT
COSC
CT
CT
COSC
(a)
(b)
D97IN766B
(c)
8/22
L5993
Figure 21. Oscillatorand synchronization internal schematic.
SYNC
1
VREF
4
R1
R2
D
R
Q
CLAMP
600µA
RT
R3
+
-
CLK
RCT
2
D1
CT
50Ω
D97IN500B
ered at pin 1 and definesthe upper extreme of the
duty cycle range, Dx (see pin 15 for Dx definition
and calculation).
Figure 22. Duty cycle control.
In case V15 is connected to VREF, however, the
switching frequency of the system will be a half
fosc
.
VREF
4
3
If the IC is to be synchronized to an externaloscil-
lator, RT and CT should be selected for a fosc
lower than the master frequency in any condition
(typically, 10-20% ), depending on the tolerance
of RT and CT .
R1
R2
3µA
DC
23K
28K
RT
Pin 3.
DC (Duty Cycle Control). By biasing this
TO PWM LOGIC
+
-
pin with a voltage between 1 and 3 V it is possible
to set the maximum duty cycle between 0 and the
upper extreme Dx (see pin 15).
RCT
2
CT
If Dmax is the desired maximum duty cycle, the
voltage V3 to be applied to pin 3 is:
D97IN711A
quired (i.e. DMAX = DX), the pin has to be left float-
ing. An internal pull-up (see fig. 22) holds the volt-
age above 3V. Should the pin pick up noise (e.g.
during ESD tests), it can be connected to VREF
V3 = 5 - 2(2-Dmax) (4)
Dmax is determined by internal comparison be-
tween V3 and the oscillator ramp (see fig. 22),
thus in case the device is synchronized to an ex-
ternal frequency fext (and therefore the oscillator
amplitude is reduced),(4) changes into:
Ω
through a 4.7k resistor.
Pin 4. VREF (Reference Voltage). The device is
provided with an accurate voltage reference
(5V±1.5%) able to deliver some mA to an external
circuit.
Dmax
RT CT fext
V3 = 5 − 4 exp −
(5)
µ
A small film capacitor (0.1 F typ.), connected
between this pin and SGND, is recommended to
ensure the stability of the generator and to prevent
noisefrom affectingthereference.
A voltage below 1V will inhibit the driver output
stage. This could be used for a not-latcheddevice
disable, for example in case of overvoltage pro-
tection(see application ideas).
Before device turn-on, this pin has a sink current
capability of 0.5mA.
If no limitation on the maximum duty cycle is re-
9/22
L5993
Pin 5.
Figure 23. Regulation characteristicand re-
lated quantities
VFB (Error Amplifier Inverting Input). The
feedback signal is applied to this pin and is com-
pared to the E/A internal reference (2.5V). The
E/A output generates the control voltage which
fixes the duty cycle.
VOUT
IQpk
The E/A features high gain-bandwidth product,
which allows to broaden the bandwidth of the
overall control loop, high slew-rate and current ca-
pability, which improves its large signal behavior.
Usually the compensation network, which stabi-
lizes the overall control loop, is connected be-
tween this pin and COMP (pin 6).
A
D.C.M.
C.C.M.
1-2 ·IQpk
IQpk(max)
C
B
TON
D
TON(min)
Pin 6.
COMP (Error Amplifier Output). Usually,
D97IN495
ISHORT IOUT(max)
IOUT
this pin is used for frequency compensation and
the relevant network is connected between this
pin and VFB (pin 5). Compensation networks to-
wards ground are not possible since the L5993
E/A is a voltage mode amplifier (low output im-
pedance). See application ideas for some exam-
ple ofcompensationtechniques.
load. Usually, CSS is selected for a TSS in the or-
der of milliseconds.
As mentioned before, the soft-start intervenes
also in case of severe overload or short circuit on
the output. Referring to fig. 23, pulse-by-pulse
current limitation is somehow effective as long as
the ON-time of the power switch can be reduced
(from A to B). After the minimum ON-time is
reached (from B onwards) the current is out of
control.
Pin 7. SS (Soft-Start). At device start-up, a ca-
pacitor (Css) connected between this pin and
SGND (pin 12) is charged by an internal current
generator, ISSC, up to about 7V. During this
ramp, the E/A output is clamped by the voltage
across Css itself and allowed to rise linearly, start-
ing from zero, up to the steady-state value im-
posed by the control loop. The maximum time in-
terval during which the E/A is clamped, referred to
as soft-starttime, is approximately:
To prevent this risk, a comparator trips an over-
current handling procedure, named ’hiccup’ mode
operation, when a voltage above 1.2V (point C) is
detected on current sense input (ISEN, pin 13).
Basically, the IC is turned off and then soft-started
as long as the fault condition is detected. As a re-
sult, the operating point is moved abruptly to D,
creating a foldback effect. Fig. 24 illustrates the
operation.
3 Rsense IQpk
Tss
Css
(6)
I
SSC
where Rsense is the current sense resistor (see pin
13) and IQpk is the switch peak current (flowing
through Rsense), which depends on the output
The oscillation frequency appearing on the soft-
Figure 24. Hiccup mode operation.
I
OUT
SHORT
I
SEN
FAULT
SS
5V
7V
0.5V
time
D98IN986
T
hic
10/22
L5993
start capacitor in case of permanent fault, referred
to as ’hiccup” period, is approximatelygiven by:
Figure 25. Turn-on and turn-off speeds adjust-
ment
Rg’
1
SSC
1
ISSD
Thic 4.5
+
Css (7)
I
VCC
VC
9
Rg(ON)=Rg+Rg’
Rg(OFF)=Rg
8
Since the system tries restarting each hiccup cy-
cle, there is not any latchoff risk.
13V
10
DRIVE
&
”Hiccup” keeps the system in control in case of
short circuits but does not eliminate power com-
ponents overstress during pulse-by-pulse limita-
tion (from A to C). Other external protection cir-
cuits are needed if a better control of overloads is
required.
CONTROL
OUT
Rg
L5993
11
D97IN767
PGND
Figure 26. Pull-Down of the output in UVLO
Pin 8. VCC (Controller Supply). This pin supplies
the signal part of the IC. The device is enabled as
VCC voltage exceeds the start threshold and
works as long as the voltage is above the UVLO
threshold. Otherwise the device is shut down and
the current consumption is extremely low
(<150µA). This is particularly useful for reducing
the consumption of the start-up circuit (in the sim-
plest case, just one resistor), which is one of the
most significant contributions to power losses
when a converter is lightly loaded.
OUT
10
VREFOK
An internal Zener limits the voltage on VCC to
25V. The IC current consumption increases con-
siderably if this limit is exceeded.
12
SGND
D97IN538
A small film capacitor between this pin and SGND
(pin 12), placed as close as possible to the IC, is
recommendedto filter high frequency noise.
of damage for the gate oxide of the external MOS.
The clamp does not cause any additional in-
crease of power dissipation inside the chip since
the current peak of the gate charge occurs when
the gate voltage is few volts and the clamp is not
active. Besides, no current flows when the gate
voltageis 13V, steady state.
Under UVLO conditions an internal circuit (shown
in fig.26) holds the pin low in order to ensure that
the external MOS cannot be turned on acciden-
tally. The peculiarity of this circuit is its ability to
mantain the same sink capability (typically, 20mA
@ 1V) from VCC = 0V up to the start-up threshold.
When the threshold is exceeded and the L5993
starts operating,VREFOK is pulled high (refer to fig.
26) and the circuit is disabled.
Pin 9.
VC (Supply of the Power Stage). It supplies
the driver of the external switch and therefore ab-
sorbs a pulsed current. Thus it is recommendedto
place a buffer capacitor (towards PGND, pin 11,
as close as possible to the IC) able to sustain
these current pulses and in order to avoid them
inducing disturbances.
This pin can be connected to the buffer capacitor
directly or through a resistor, as shown in fig. 25,
to control separately the turn-on and turn-off
speed of the external switch, typically a Power-
MOS. At turn-on the gate resistance is Rg + Rg’, at
turn-off is Rg only.
It is then possible to omit the ”bleeder” resistor
(connected between the gate and the source of
the MOS) ordinarily used to prevent undesired
switching-on of the external MOS because of
some leakage current.
Pin 10.
OUT (Driver Output). This pin is the out-
put of the driver stage of the external power
switch. Usually, this will be a PowerMOS, al-
though the driver is powerful enough to drive
BJT’s (1.6A source, 2A sink, peak).
Pin 11.
PGND (Power Ground). The current loop
The driver is made up of a totempole with a high-
side NPN Darlington and a low-side VDMOS, thus
there is no need of an external diode clamp to
prevent voltage from going below ground. An in-
ternal clamp limits the voltage delivered to the
gate at 13V. Thus it is possible to supply the
driver (Pin 9) with higher voltages without any risk
during the discharge of the gate of the external
MOS is closed through this pin. This loop should
be as short as possible to reduce EMI and run
separatelyfrom signal currents return.
11/22
L5993
Figure 27. Internal LEB.
2V
I
3V
+
-
0
CLK
PWM
13
COMPARATOR
TO PWM
LOGIC
ISEN
+
-
FROM E/A
TO FAULT
LOGIC
+
-
1.2V
OVERCURRENT
COMPARATOR
D97IN503
Pin 12. SGND (Signal Ground). This ground refer-
ences the control circuitry of the IC, so all the
ground connections of the external parts related
to control functions must lead to this pin. In laying
out the PCB, care must be taken in preventing
switched high currents from flowing through the
SGND path.
Figure 28. Disable (Latched)
DISABLE
SIGNAL
Pin 13.
DIS
14
ISEN (Current Sense). This pin is to be
+
-
D
R
DISABLE
connected to the ”hot” lead of the current sense
resistor Rsense (being the other one grounded), to
get a voltage ramp which is an image of the cur-
rent of the switch (IQ). When this voltage is equal
to:
Q
C
2.5V
UVLO
D97IN502
V
− 1.4
COMP
mately,
=
=
( )
8
V13pk
I
Rsense
Qpk
3
RT
RT + 230
Dx
(9)
the conductionof the switch is terminated.
To increase the noise immunity, a ”Leading Edge
Blanking” of about 100ns is internally realized as
shown in fig. 27. Because of that, the smoothing
RC filter between this pin and Rsense could be re-
moved or, at least, considerably reduced.
if DC-LIM is grounded or left floating. Instead,
connecting DC-LIM to VREF (half duty cycle op-
tion), Dx will be set approximately to:
RT
Dx
(10)
Pin 14.
DIS (Device Disable). When the voltage
2 R + 260
T
on pin 14 rises above 2.5V the IC is shut down
and it is necessaryto pull VCC (IC supply voltage,
pin 8) below the UVLO threshold to allow the de-
vice to restart.
The pin can be driven by an external logic signal
in case of power management, as shown in fig.
28. It is also possible to realize an overvoltage
protection, as shown in the section ” Application
Ideas”.Ifused, bypass this pin to ground with a fil-
ter capacitor to avoid spurious activation due to
noise spikes. If not, it must be connected to
SGND.
and the output switching frequency will be halved
with respect to the oscillator one because an in-
ternal T flip-flop (see block diagram, fig. 1) is acti-
vated. Fig. 29 shows the operation.
The half duty cycle option speeds up the dis-
charge of the timing capacitor CT (in order to get
duty cycles as close as possible to 50%) so the
oscillator frequency - with the same RT and CT -
will be slightly higher.
The halving of frequency can be used to reduce
losses at light load in all those systems that must
comply with requirements regarding energy con-
sumption (e.g. monitor displays, see ”Application
Ideas”).
Pin 15. DC-LIM (Maximum Duty Cycle Limit). The
upper extreme, Dx, of the duty cycle range de-
pends on the voltage applied to this pin. Approxi-
12/22
L5993
Figure 29. Half duty cycle option.
t
d
V15=GND
V5=V13=GND
V2
V10
V2
t
c
+ t
d
D
=
X
t
c
t
c
t
d
V15=VREF
V5=V13=GND
t
c
D
=
X
2 ·t + t
c
d
V10
t
c
D97IN498
Figure 30. Constant Power circuit internal schematic
VFB
COMP
6
5
30KΩ
30KΩ
-
TO PWM
LATCH
E/A
-
+
+
2.5V
15KΩ
PWM
COMPARATOR
VREF
4
CLAMP
D2
Q2
RT
C-POWER
16
2
Q1
1V
C
CP
-
D1
+
RCT
47KΩ
C
BUFFER
T
TIMING
L5993
1
13
D97IN768A
SYNC
ISEN
Pin 16. C-POWER (Constant Power Function).
An external capacitor connected between this pin
and SGND completes the peak-holdingcircuit that
detects the peak voltage of the synchronized os-
cillator. The circuit gets a DC voltage (which de-
creases as the synchronizing frequency fed into
pin 1 (SYNC) rises) used to clamp the error ampli-
fier output (VCOMP), as shown in the detailed inter-
nal schematicof fig. 30.
In this way the pulse-by-pulse setpoint is moved
downwardsas thefrequencyrises (andvice versa for
a frequencydecrease, due to the 47kΩ dischargere-
sistor) and, as a result, the maximum power deliver-
ableto theload is held roughlyconstant.
where ƒmin (Hz)is the minimum synchronizing fre-
quency.
When this function is not used, pin 16 has to be
connecteddirectly to pin 4.
Considering the ordinary design criteria for the
transformer, the circuit usually works well without
any adjustment. Anyway, the variations of the
maximum power limit on varying the switching fre-
quency and/or the mains voltage can be mini-
mized by modifying one or more of the following
parameters:
- Primaryinductance;
- Transformer turns ratio;
- Oscillatorfree-running frequency;
- Sense resistor.
The external capacitor must be large enough to
get a real DC voltage on the pin. Considering the
spread of the internal 47kΩ resistor, the minimum
capacitancevalue (CCP) needed to have less than
1% ripple superimposed on the DC voltage is:
A trial process is required, involving the parame-
ters that are more practicable to modify. In fact,
the optimum behavior is achieved for a specific
combination of the above parameters and de-
1
CCP
>
,
330 ƒmin
13/22
L5993
pends both on the mains voltage range and the
synchronizationfrequencyrange.
rately and should be connected only at a single
ground point.
An additional ”fine tuning” can be achieved by
adding a small DC offset (in the ten mV) on the
current sense pin (13, ISEN).
For wide range mains applications it is anyway
recommendedto compensatethe propagationde-
lay of the current sense path (PWM comparator +
latch + driver) with the circuit shown in the ”Appli-
cation Ideas” section, fig. 41.
2) Noise coupling can be reduced by minimizing
the area circumscribed by current loops. This
applies particularly to loops where high pulsed
currentsflow.
3) For high current paths, the traces should be
doubled on the other side of the PCB whenever
possible: this will reduce both the resistance
and the inductanceof the wiring.
4) Magnetic field radiation (and stray inductance)
can be reduced by keeping all traces carrying
switched currentsas short as possible.
Layout hints
Generally speaking a proper circuitboard layout is
vital for correct operation but is not an easy task.
Careful component placing, correct traces routing,
appropriate traces widths and, in case of high
voltages, compliance with isolation distances are
the major issues. The L5993 eases this task by
putting two pins at disposal for separate current
returns of bias (SGND) and switch drive currents
(PGND) The matter is complex and only few im-
portant points will be here reminded.
5) In general, traces carrying signal currents
should run far from traces carrying pulsed cur-
rents or with quickly swinging voltages. From
this viewpoint, particular care should be taken
of the high impedance points (current sense in-
put, feedback input, ...). It could be a good idea
to route signal traces on one PCB side and
power traceson the other side.
6) Provide adequate filtering of some crucial
points of the circuit, such as voltage references,
IC’s supply pins, etc.
1) All current returns (signal ground, power
ground, shielding, etc.) should be routed sepa-
14/22
L5993
either improving performance or solving common
application problems of L5993 based supplies.
APPLICATION IDEAS
Here follows a series of ideas/suggestionsaimed at
Figure 31. Typical application circuitfor 15” Multisync monitor (70W)
7DIN691A
15/22
L5993
Figure 32. Isolated MOSFET Drive & Current Transformer Sensing in 2-switch Topologies
VIN
ISOLATION
BOUNDARY
VC
9
10
OUT
L5993
ISEN
13
12
11
PGND
SGND
D97IN769
Figure 33. Low consumption start-up
VIN
2.2MΩ
33KΩ
STD1NB50-1
VCC
T
VREF
SELF-SUPPLY
WINDING
8
20V
4
L5993
11
47KΩ
12
D97IN770B
Figure 34. Bipolar Transistor Drive
VIN
VCC
VC
9
8
10
13
OUT
ISEN
L5993
11
PGND
D97IN771
16/22
L5993
Figure 35. Typical E/A compensationnetworks.
+
From VO
Ri
2.5V
1.3mA
2R
+
-
VFB
Rf
5
6
EA
R
Rd Cf
COMP
12
SGND
Error Amp compensation circuit for stabilizing any current-mode topology except
for boost and flyback converters operating with continuous inductor current.
+
From VO
2.5V
1.3mA
RP
2R
+
-
Ri
VFB
Rf
5
6
EA
R
CP
Rd
Cf
COMP
12
SGND
D97IN507
Error Amp compensation circuit for stabilizing current-mode boost and flyback
topologies operating with continuous inductor current.
Figure 36. Feedback with optocoupler
VOUT
COMP
6
L5993
5
TL431
VFB
D97IN772
Figure 37. Slope compensation techniques
VREF
OUT
R
VREF
4
10
4
R
RT
RT
RCT
CT
RCT
2
2
CSLOPE
CT
RSLOPE
I
L5993
12
I
L5993
L5993
RSLOPE
RSLOPE
ISEN
ISEN
ISEN
13
13
12
13
12
RSENSE
RSENSE
RSENSE
SGND
SGND
SGND
OPTIONAL
OPTIONAL
OPTIONAL
D97IN773A
17/22
L5993
Figure 38. Protection against overvoltage/feedback disconnection (latched)
RSTART
RSTART
VCC
VCC
VZ
8
8
DIS
DIS
2.2K
14 L5993
12
14 L5993
12
11
11
SGND
PGND
SGND
PGND
D97IN774
D98IN906
Figure 39. Protection against overvol-
tage/feedbackdisconnection (not
latched)
Figure 40. Device shutdown on overcurrent
2.5
R2
Ipk max
•
1-
VREF
DIS
RSENSE
R1
RSTART
4
R1
Ipk
I
VCC
14
VREF
4
8
L5993
R2
DC
L5993
ISEN
3
13
11
12
RSENSE
PGND
SGND
12
11
OPTIONAL
D97IN776A
D97IN775A
Figure 41. Constant power in pulse-by-pulse current limitation (flyback discontinuous)
VIN
80 ÷ 400VDC
L
p
RFF
R·L
p
OUT
RFF = 6·106
R
SENSE
10
L5993
ISEN
13
11
12
R
R
SENSE
PGND
SGND
D97IN777
Figure 42. Voltage mode operation.
DC
3
10K
L5993
6
12
13
COMP
SGND
ISEN
D97IN778A
18/22
L5993
Figure 43. Device shutdown on mains undervoltage.
VIN
80÷400VDC
4.7K
R1
R2
VREF
4
L5993
3
12
11
5.1
10KΩ
SGND
PGND
D97IN779A
Figure 44. Constant power ”Fine Tuning”.
SGND
L5993 10
12
4
13
ISEN
R
VREF
RA
RSENSE
OPTIONAL
D97IN780A
Figure 45. Synchronization to flyback pulses (for monitors).
SYNC
1
L5993
1KΩ
5.1V
12
SGND
D97IN781A
Figure 46. Switching frequency halving on absence of sync. signal (for monitor).
1KΩ
1
(R1//R2)•C>>
fmin
5.1V
SYNC
VREF
1
4
R1
L5993
SGND
f
C
R2
12
15
D97IN782A
DC-LIM
19/22
L5993
mm
inch
OUTLINE AND
MECHANICAL DATA
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
a1
B
b
0.51
0.77
0.020
1.65 0.030
0.065
0.787
0.5
0.020
0.010
b1
D
E
e
0.25
20
8.5
0.335
0.100
0.700
2.54
17.78
e3
F
7.1
5.1
0.280
0.201
I
L
3.3
0.130
DIP16
Z
1.27
0.050
20/22
L5993
mm
inch
DIM.
OUTLINE AND
MECHANICAL DATA
MIN. TYP. MAX. MIN. TYP. MAX.
A
a1
a2
b
1.75
0.069
0.009
0.063
0.018
0.010
0.1
0.25 0.004
1.6
0.35
0.19
0.46 0.014
0.25 0.007
b1
C
0.5
0.020
c1
D (1)
E
45° (typ.)
9.8
5.8
10
0.386
0.228
0.394
0.244
6.2
e
1.27
8.89
0.050
0.350
e3
F (1)
G
3.8
4.6
0.4
4
0.150
0.181
0.157
0.209
0.050
0.024
5.3
L
1.27 0.016
0.62
M
SO16 Narrow
S
8°(max.)
(1) D andF do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch).
21/22
L5993
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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22/22
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