L6221AD013TR [STMICROELECTRONICS]

4 CHANNEL, BUF OR INV BASED PRPHL DRVR, PDSO20, SO-20;


型号：	L6221AD013TR
厂家：	ST
描述：	4 CHANNEL, BUF OR INV BASED PRPHL DRVR, PDSO20, SO-20 驱动光电二极管接口集成电路
文件：	总22页 (文件大小：750K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

L6221

Quad Darlington switch

Features

■ Four non-inverting inputs with enable

■ Output voltage up to 50 V

■ Output current up to 1.8 A

■ Very low saturation voltage

■ TTL compatible inputs

Power DIP 12+2+2

■ Integral fast recirculation diodes

Applications

The L6221 monolithic quad Darlington switch is

designed for high current, high voltage switching

applications.

SO16+2+2

Description

Figure 1.

Block diagram

Each of the four switches is controlled by a logic

input and all four are controlled by a common

enable input. All inputs are TTL-compatible for

direct connection to logic circuits.

Each switch consists of an open-collector

Darlington transistor plus a fast diode for

switching applications with inductive device loads.

The emitters of the four switches are commoned.

Any number of inputs and outputs of the same

device may be paralleled.

Table 1.

Device summary

Order code

Package

E-L6221AS

Power DIP

SO16+2+2

E-L6221AD

E-L6221AD013TR

E-L6221C/CD/CN

SO16+2+2 (tape and reel)

Obsolete product

March 2009

Rev 4

1/22

www.st.com

Contents

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Mounting instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2/22

Thermal data

Table 2.

Symbol

Thermal data

Parameter

SO20

Power DIP

Unit

R_{th j-pins}

R_{th j-amb}

Thermal resistance junction-pins max.

°C/W

Thermal resistance junction-ambient max.

3/22

Pin information

Figure 2.

Pin connections (top views)

E-L6221AS (Power DIP)

E-L6221AD (SO16+2+2)

4/22

Pin information

Table 3.

Truth table⁽¹⁾

Enable

Input

Power out

OFF

1. For each input: H = High level, L = Low level

Table 4.

Name

Pin description⁽¹⁾

Function

IN 1

Input to driver 1

Input to driver 2

Output of driver 1

Output of driver 2

IN 2

OUT 1

OUT 2

CLAMP A

IN 3

Diode clamp to driver 1 and driver 2

Input to driver 3

IN 4

Input to driver 4

OUT 3

OUT 4

CLAMP B

ENABLE

^VS

Output of driver 3

Output of driver 4

Diode clamp to driver 3 and driver 4

Enable input to all drivers

Logic supply voltage

Common ground

GND

1. See Figure 1: Block diagram

5/22

Absolute maximum ratings

Table 5.

Symbol

Absolute maximum ratings

Parameter

Value

Unit

V_o

V_s

Output voltage

Logic supply voltage

V_IN, V_ENInput voltage, enable voltage

V_S

1.8

2.5

3.2

I_C

Continuous collector current (for each channel)

I_C

Collector peak current (repetitive, duty cycle = 10% t_on= 5 ms)

Collector peak current (non repetitive, t = 10 μ s)

Operating temperature range (junction)

Storage temperature range

I_C

T_op

T_stg

I_sub

-40 to +150 °C

-55 to +150 °C

Output substrate current

350

Total power dissipation at:

_pins= 90 °C (Power DIP)

_case= 90°C (SO20)

4.3

3.5

P_tot

T_amb= 70 °C (Power DIP)

_amb= 70°C (SO20)

6/22

Electrical characteristics

Note:

Refer to the test circuits Figure 3 to Figure 10 (V_S= 5 V, T_amb= 25 °C unless otherwise

specified).

Table 6.

Electrical characteristics

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

V_S

I_s

Logic supply voltage

4.5

5.5

All outputs ON, I_C= 0.7A

All outputs OFF

Logic supply current

V_IN= V_INL, V_EN= V_EN

V_CE(sus)

Output sustaining voltage

Output leakage current

I_C= 100 mA

V_CE= 50V

I_CEX

_IN= V_INL, V_EN= V_EN

V_s= 4.5 V

_IN= V_INH, V_EN= V_EN

Collector emitter saturation

V_CE(sat)

voltage (one input on, all others I_C= 0.6 A

inputs off.)

I_C= 1 A

1.2

1.6

I_C= 1.8 A

V_INL, V_EN

Input low voltage

Input low current

Input high voltage

Input high current

0.8

I_INL, I_EN

V_INL, V_EN

I_INH, I_EN

V_IN= V_INL, V_EN= V_ENL

V_IN= V_INH, V_EN= V_EN

V_R= 50 V, V_EN= V_EN

_IN= V_INL

-100 μA

2.0

μA

I_R

Clamp diode leakage current

Clamp diode forward voltage

100 μA

I_F= 1A

1.6

2.0

V_F

I_F= 1.8A

t_{d (on)}

t_{d (off)}

Turn-on delay time

Turn-off delay time

V_p= 5V, R_L= 10Ω

V_IN= 5V, V_EN= 5V

μs

ΔI_s

Logic supply current variation

120 mA

_out= -300 mA for each

channel

7/22

Test circuits

Note:

Pin numbers without parentheses apply to the Power DIP package.

Pin numbers in parentheses are not applicable.

Figure 3.

Logic supply current

Set V_IN= 4.5 V, V_EN= 0.8 V, or V_IN= 0.8 V, V_EN= 4.5 V, for I_S(all outputs off)

Set V_IN= 2 V, V_EN= 2 V, for I_S(all outputs on)

Figure 4.

Output sustaining voltage

Figure 5.

Output leakage current

8/22

Test circuits

Figure 6.

Collector-emitter saturation voltage

Figure 7.

Logic input characteristics

Set S₁, S₂open, V_IN, V_EN= 0.8 V for I_INL, I_EN

Set S₁, S₂open, V_IN, V_EN= 2 V for I_INH, I_EN

Set S₁, S₂closed, V_IN, V_EN= 0.8 V for V_INL, V_EN

Set S₁, S₂closed, V_IN, V_EN= 2 V for V_INH, V_EN

Figure 8.

Clamp-diode leakage current

9/22

Test circuits

Figure 9.

Clamp-diode forward voltage

Figure 10. Switching time test circuit

Figure 11. Switching time waveforms

10/22

Test circuits

Figure 12. Allowed peak collector current versus duty cycle for 1, 2, 3 or 4

contemporary working outputs (L6221AS)

Figure 13. Collector saturation voltage versus collector current

Figure 14. Free-wheeling diode forward voltage versus diode current

11/22

Test circuits

Figure 15. Collector saturation voltage versus junction temperature at I_C= 1 A

Figure 16. Free-wheeling diode forward voltage versus junction temperature

at I_F= 1 A

Figure 17. Saturation voltage against junction temperature

12/22

Test circuits

Figure 18. Free-wheeling diode forward voltage against junction temperature

13/22

Application information

When inductive loads are driven by the L6221, a Zener diode in series with the integral free-

wheeling diodes increases the voltage across which energy stored in the load is discharged

and therefore speeds the current decay (Figure 19).

For reliability it is suggested that the Zener is chosen so that

+ V < 35 V

There are two reasons for this:

●

The Zener voltage changes in temperature and current.

●

The instantaneous power must be limited to avoid the reverse second breakdown.

Figure 19. Free-wheeling diode connection when driving inductive loads

Care must be taken to ensure that the collectors are placed close together to avoid different

current partitioning at turn-off.

It is suggested to put in parallel channel 1 and 4 and channel 2 and 3 as shown in Figure 20

for the similar electrical characteristics of the logic section (turn-on and turn-off delay time)

and the power stages (collector saturation voltage, free-wheeling diode forward voltage).

14/22

Application information

Figure 20. Driver for solenoids up to 3 A

Figure 21. Saturation voltage versus collector current

Figure 22. L6221AS peak collector current versus duty cycle for 1 or 2 paralleled

outputs driven

15/22

Mounting instructions

The R_{th j-amb}of the E-L6221AS can be reduced by soldering the GND pins to a suitable

copper area of the printed circuit board (Figure 23) or to an external heat sink (Figure 24).

Figure 23. Example of PCB copper area used as heat sink

Figure 24. External heat sink mounting example

16/22

Mounting instructions

Figure 25 shows the maximum dissipable power P_totand the R_{th j-amb}as a function of the

side "α" of two equal square copper areas having a thickness of 35 µm (1.4 mils). During

soldering the pins temperature must not exceed 260 °C and the soldering time must not be

longer than 12 seconds.

The external heat sink or printed circuit copper area must be connected to electrical ground.

Figure 25. Maximum dissipable power and junction-to-ambient thermal resistance

versus side "α"

Figure 26. Maximum allowable power dissipation versus ambient temperature

17/22

Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK® is an ST trademark.

18/22

Package mechanical data

inch

DIM.

OUTLINE AND

MECHANICAL DATA

MIN. TYP. MAX. MIN. TYP. MAX.

0.51

0.85

0.020

1.40 0.033

0.055

0.50

0.020

0.38

0.50 0.015

20.0

0.020

0.787

8.80

2.54

0.346

0.100

0.700

17.78

7.10

5.10

0.280

0.201

3.30

0.130

Power DIP 16

Powerdip 16

1.27

0.050

19/22

Package mechanical data

20/22

Revision history

Table 7.

Date

Document revision history

Revision

Changes

14-Jan-2004

19-Jan-2009

30-Mars-2009

Released in EDOCS

Document reformatted.

Inserted title for Figure 19.

Removed reference to obsolete product L6221N and the associated

package (multiwatt-15).

Obsolete products E-L6221C/CD/CN added in Table 1.

21/22

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22/22

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