L6221N [STMICROELECTRONICS]

QUAD DARLINGTON SWITCH; QUAD达林顿开关管


型号：	L6221N
厂家：	ST
描述：	QUAD DARLINGTON SWITCH QUAD达林顿开关管开关
文件：	总15页 (文件大小：165K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

L6221A L6221AD

L6221N

QUAD DARLINGTON SWITCH

FOUR NON INVERTING INPUTS WITH

ENABLE

OUTPUT VOLTAGE UP TO 50 V

OUTPUT CURRENT UP TO 1.8 A

VERYLOW SATURATION VOLTAGE

TTL COMPATIBLEINPUTS

INTEGRAL FAST RECIRCULATION DIODES

Multiwatt 15

Powerdip 12 + 2 + 2

DESCRIPTION

The L6221monolithic quaddarlington switch is de-

signedforhighcurrent,highvoltageswitchingappli-

cations.Eachof thefourswitches is controlled by a

logic input and all four are controlledby a common

enableinput.AllinputsareTTL-compatiblefordirect

connectionto logic circuits.

SO16+2+2

Eachswitchconsistsofan open-collectordarlington

transistorplusafastdiodeforswitchingapplications

with inductivedeviceloads.The emittersof thefour

switchesare commoned.Anynumberof inputsand

outputsof the same device may be paralleled.

ORDERING NUMBERS:

L6221A (Powerdip)

L6221N (Multiwatt15)

L6221AD (SO16+2+2)

BLOCK DIAGRAM

1/15

July 1998

L6221A - L6221AD - L6221N

THERMAL DATA

Symbol

Parameter

SO20

Powerdip Multiwatt15 Unit

R_{th j-pins}

R_{th j-case}

R_{th j-amb}

Thermal Resistance Junction-pins

Thermal Resistance Junction-case

Thermal Resistance Junction-ambient

Max.

–

C/W

PIN CONNECTIONS

(top views)

L6221A (Powerdip)

L6221AD (SO16+2+2)

OUT4

IN4

IN3

CLAMPB

N.C.

OUT3

GND

ENABLE

GND

V_S

GND

OUT2

N.C.

IN2

CLAMPA

OUT1

IN1

D95IN231

L6221N (Multiwatt-15)

2/15

L6221A - L6221AD - L6221N

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Value

Unit

V_o

V_s

Output Voltage

Logic Supply Voltage

V_IN, V_EN

I_C

Input Voltage, Enable Voltage

V_s

Continuous Collector Current (for each channel)

Collector Peak Current (repetitive, duty cycle = 10 % t_on= 5 ms)

1.8

2.5

I_C

3.2

Collector Peak Current (non repetitive, t = 10 s)

T_op

Operating Temperature Range (junction)

Storage Temperature Range

Output Substrate Current

– 40 to + 150

– 55 to + 150

350

°C

T_stg

I_sub

P_tot

4.3

3.5

2.3

Total Power Dissipation at T_pins= 90 C

(powerdip)

(multiwatt)

(SO20)

(powerdip)

(multiwatt)

(SO20)

at T_case= 90 C

at T_amb= 70 C

at T_amb= 70 °C

TRUTH TABLE

Enable

Input

Power Out

OFF

Foreach input : H = High level

L = Low level

PIN FUNCTIONS (see block diagram)

Name

Function

IN 1

IN 2

Input to Driver 1

Input to Driver 2

OUT 1

OUT 2

CLAMP A

IN 3

Output of Driver 1

Output of Driver 2

Diode Clamp to Driver 1 and Driver 2

Input to Driver 3

IN 4

Input to Driver 4

OUT 3

OUT 4

CLAMP B

ENABLE

V_S

Output of Driver 3

Output of Driver 4

Diode Clamp to Driver 3 and Driver 4

Enable Input to All Drivers

Logic Supply Voltage

Common Ground

GND

3/15

L6221A - L6221AD - L6221N

ELECTRICAL CHARACTERISTICS

Refer to the test circuit to Fig. 1 to Fig. 9 (V_S= 5V, T_amb= 25^oC unless otherwise specified)

Symbol

Parameter

Logic Supply Voltage

Logic Supply Current

Test Conditions

Min . Typ . Max . Unit

V_S

I_s

4.5

5.5

All Outputs ON, I_C= 0.7A

All Outputs OFF

V_CE(sus)

I_CEX

Output Sustaining Voltage

Output Leakage Current

V_IN= V_INL, V_EN= V_EN

I_C= 100 mA

V_CE= 50V

V_IN= V_INL, V_EN= V_EN

V_CE(sat)

Collector Emitter Saturation Voltage

(one input on ; all others inputs off.)

V_s= 4.5V

V_IN= V_INH, V_EN= V_EN

I_C= 0.6A

1.2

1.6

I_C= 1A

I_C= 1.8A

V_INL, V_EN

Input Low Voltage

0.8

I_INL, I_EN

Input Low Current

V_IN= V_INL, V_EN= V_EN

– 100

V_INL, V_EN

Input High Voltage

2.0

I_INH , I_EN

Input High Current

V_IN= V_INH, V_EN= V_EN

I_R

Clamp Diode Leakage Current

V_R= 50 V, V_EN= V_EN

100

V_IN= V_INL

V_F

Clamp Diode Forward Voltage

I_F= 1A

I_F= 1.8A

1.6

2.0

t_{d (on)}

t_{d (off)}

Turn on Delay Time

V = 5V, R = 10

Ω

Turn off Delay Time

V_p= 5V, R_L= 10Ω

µ s

Logic Supply Current Variation

V_IN= 5V, V_EN= 5V

I_out= – 300 mA for Each Channel

120

m A

∆

4/15

L6221A - L6221AD - L6221N

TEST CIRCUITS

(X) = Referred to Multiwatt package

X = Referred to Powerdippackage

Figure 1 : Logic supply current.

S_etV _IN= 4.5V,V _EN= 0.8V,or V _IN= 0.8V,V _EN= 4.5V, for I _S(all outputs off)

S_etV _IN= 2V, V _EN= 2V, for I _S(alloutputs on)

Figure 2 : Output Sustaining Voltage.

Figure 3 : Output Leakage Current.

5/15

L6221A - L6221AD - L6221N

Figure 4 :

Collector-emitter Saturation

Voltage

Figure 5 : Logic InputCharacteristics

S_etS₁, S₂open, V_IN, V_EN= 0.8Vfor I_INL,I_EN

S_etS₁, S₂open, V_IN, V_EN= 2V for I_INH, I_EN

S_etS₁, S₂close, V_IN, V_EN= 0.8V for V_INL, V_EN

S_etS₁, S₂close, V_IN, V_EN= 2V for V_INH, V_EN

Figure 6 : Clamp Diode Leakage Current.

Figure 7 : Clamp Diode Forward Voltage.

6/15

L6221A - L6221AD - L6221N

Figure 8 : Switching Times Test Circuit.

Figure 9 : Switching TImes Waveforms.

Figure 10 : Allowed Peak Collector Current ver-

sus Duty Cycle for 1, 2, 3 or 4 Con-

Figure 11 : Allowed Peak Collector Current ver-

sus Duty Cycle for 1, 2, 3 or 4 Con-

temporary Working Outputs

(L6221N)

temporaryWorking Outputs(L6221A)

7/15

L6221A - L6221AD - L6221N

Figure 12 : CollectorSaturationVoltageversus

Figure 13 : Free-wheeling Diode Forward Voltage

Collector Current

versus Diode Current

Figure 14 :

Figure 15 :

CollectorSaturationVoltageversus

Junction Temperatureat IC = 1A

Free-wheeling Diode Forward Voltage

versus JunctionTemperature

at IF = 1A

Figure 16 :

Figure 17 :

Saturation Voltage vs. Junc-

Free-wheeling Diode Forward

8/15

L6221A - L6221AD - L6221N

APPLICATION INFORMATION

Figure 18.

When inductive loads are driven by L6221A/N, a

zenerdiodeinseries with the integralfree-wheeling

diodes increases the voltage across which energy

stored in the load is discharged and therefore

speedsthe current decay(fig. 18).

Forreliabilityit issuggestedthatthezenerischosen

so that V_p+ V_z< 35 V.

The reasonsfor this are two fold :

1) The zener voltage changes in temperature and

current.

2)Theinstantaneouspowermustbelimitedtoavoid

the reverse second breakdown.

Figure 19 :

Driver for Solenoids up to 3A

Somecare must be takento ensurethatthe collec-

torsareplaced closetogethertoavoiddifferentcur-

rent partitioningat turn-off.

We suggest to put in parallel channel 1 and 4 and

channel2and 3 asshownin figure19 forthesimilar

electricalcharacteristicsofthelogicsection(turn-on

and turn-off delay time) and the power stages(col-

lector saturation voltage, free-wheeling diode for-

ward voltage).

9/15

L6221A - L6221AD - L6221N

Figure 20 : SaturationVoltageversus Collector

Figure 21 : Peak Collector Current versus Duty

Cycle for 1 or 2 ParalleledOutputs

Driven(L6221A)

Current

Figure 22 : Peak Collector Current versus Duty

Cycle for 1 or 2 ParalleledOutputs

Driven (L6221N)

10/15

L6221A - L6221AD - L6221N

MOUNTING INSTRUCTION

The R_{th j-amb}of the L6221Acan be reduced by sol-

deringtheGNDpinstoa suitablecopperareaofthe

printed circuit board (Fig. 23) or to an external

heatsink (Fig. 24).

ing a thickness of 35µ (1.4 mils). During soldering

the pins temperaturemust not exceed 260 °C and

the soldering time must not be longer than 12 sec-

onds.

The diagram of figure 25 shows the maximum dis-

sipable power P_totand the R_{th j-amb}as a function of

theside ” α” oftwo equal squarecopperareas hav-

The externalheatsinkor printedcircuit copperarea

must be connectedto electrical ground.

Figure 23 : Exampleof P.C. Board Copper Area

Figure 24 : External Heatsink MountingExample

Which is Used as Heatsink

Figure 25 : Maximum Dissipable Powerand Junc-

tion to Ambient Thermal Resistance

versus Side ” α”

Figure 26 : Maximum Allowable Power Dissipa-

tion versus Ambient Temperature

11/15

L6221A - L6221AD - L6221N

POWERDIP 16 PACKAGE MECHANICAL DATA

inch

DIM.

MIN.

0.51

0.85

TYP.

MAX.

MIN.

0.020

0.033

TYP.

MAX.

1.40

0.055

0.50

0.020

0.38

0.50

20.0

0.015

0.020

0.787

8.80

2.54

0.346

0.100

0.700

17.78

7.10

5.10

0.280

0.201

3.30

0.130

1.27

0.050

12/15

L6221A - L6221AD - L6221N

MULTIWATT 15 PACKAGE MECHANICAL DATA

inch

DIM.

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

0.197

0.104

0.063

2.65

1.6

0.039

0.49

0.66

1.02

17.53

19.6

0.55

0.75

0.019

0.026

0.040

0.690

0.772

0.022

0.030

0.060

0.710

1.27

1.52

0.050

0.700

17.78

18.03

20.2

22.5

18.1

17.75

10.9

2.9

0.795

0.886

0.713

0.699

0.429

0.114

0.191

0.218

0.102

0.152

21.9

21.7

17.65

17.25

10.3

2.65

4.25

4.63

1.9

22.2

22.1

0.862

0.854

0.695

0.679

0.406

0.104

0.167

0.182

0.075

0.144

0.874

0.870

17.5

10.7

0.689

0.421

4.55

5.08

4.85

5.53

2.6

0.179

0.200

Dia1

1.9

2.6

3.65

3.85

13/15

L6221A - L6221AD - L6221N

SO20 PACKAGE MECHANICAL DATA

inch

DIM.

MIN.

2.35

0.1

TYP.

MAX.

2.65

0.3

MIN.

0.093

0.004

0.013

0.009

0.496

0.291

TYP.

MAX.

0.104

0.012

0.020

0.013

0.512

0.299

0.33

0.23

12.6

7.4

0.51

0.32

7.6

1.27

0.050

0.25

0.4

10.65

0.75

1.27

0.394

0.010

0.016

0.419

0.030

0.050

0 (min.)8 (max.)

h x 45°

SO20MEC

14/15

L6221A - L6221AD - L6221N

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the conse-

quences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No

license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this

publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMi-

croelectronics products are not authorized for use as critical components in life support devices or systems without express written

approval of STMicroelectronics.

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