L6228Q [STMICROELECTRONICS]
DMOS driver for bipolar stepper motor; DMOS驱动程序双极步进电机
| 型号： | L6228Q |
| 厂家： | 
ST |
| 描述： | DMOS driver for bipolar stepper motor |
| 文件： | 总32页 (文件大小：385K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L6228Q
DMOS driver for bipolar stepper motor
Features
■ Operating supply voltage from 8 to 52 V
■ 2.8A output peak current (1.4 A RMS)
■ R
0.73 Ω typ. value @ TJ = 25 °C
DS(ON)
■ Operating frequency up to 100 kHz
■ Non dissipative overcurrent protection
VFQFPN 5x5 32L
■ Dual independent constant t
PWM
OFF
Description
current controllers
■ Fast/slow decay mode selection
■ Fast decay quasi-synchronous rectification
The L6228Q is a DMOS fully integrated stepper
motor driver with non-dissipative overcurrent
protection, realized in multipower-BCD
■ Decoding logic for stepper motor full and half
technology, which combines isolated DMOS
power transistors with CMOS and bipolar circuits
on the same chip. The device includes all the
circuitry needed to drive a two-phase bipolar
stepper motor including: a dual DMOS full bridge,
the constant off time PWM current controller that
performs the chopping regulation and the phase
sequence generator, that generates the stepping
sequence. Available in VFQFPN-32 5x5 package,
the L6228Q features a non-dissipative
step drive
■ Cross conduction protection
■ Thermal shutdown
■ Under voltage lockout
■ Integrated fast free wheeling diodes
Applications
overcurrent protection on the high side Power
MOSFETs and thermal shutdown.
■ Bipolar stepper motor
Figure 1.
Block diagram
VBOOT
VCP
VBOOT
VSA
VBOOT
VBOOT
CHARGE
PUMP
OCDA
OCDB
OVER
CURRENT
DETECTION
OUT1A
OUT2A
10V
10V
THERMAL
PROTECTION
EN
GATE
LOGIC
CONTROL
SENSEA
HALF/FULL
CLOCK
PWM
+
-
STEPPING
SEQUENCE
GENERATION
ONE SHOT
MONOSTABLE
MASKING
TIME
VREFA
RCA
RESET
SENSE
COMPARATOR
CW/CCW
BRIDGE A
VSB
OVER
OUT1B
OUT2B
SENSEB
VREFB
RCB
CURRENT
DETECTION
VOLTAGE
REGULATOR
GATE
LOGIC
10V
5V
BRIDGE B
D01IN1225
January 2008
Rev 1
1/32
www.st.com
32
Contents
L6228Q
Contents
1
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
1.2
1.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
3
4
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PWM current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Decay modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Stepping sequence generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Half step mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Normal drive mode (Full-step two-phase-on) . . . . . . . . . . . . . . . . . . . . . . 18
Wave drive mode (Full-step one-phase-on) . . . . . . . . . . . . . . . . . . . . . . . 18
Non-dissipative overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.10 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Output current capability and IC power dissipation . . . . . . . . . . . . . . 25
Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5
6
7
8
9
10
2/32
L6228Q
Electrical data
1
Electrical data
1.1
Absolute maximum ratings
Table 1.
Absolute maximum ratings
Parameter
Symbol
Parameter
VSB = VS
Value
Unit
VS
Supply voltage
V
=
=
60
V
SA
SA
Differential voltage between
V
V
GND
VSB = VS = 60 V;
VOD
VSA, OUT1A, OUT2A, SENSEA and
VSB, OUT1B, OUT2B, SENSEB
60
V
V
= V
SENSEB
=
SENSEA
VBOOT
Bootstrap peak voltage
V =
VSB = VS
VS + 10
SA
VIN,VEN
Input and enable voltage range
-0.3 to +7
-0.3 to +7
-0.3 to +7
-1 to +4
V
V
V
V
Voltage range at pins VREFA and
VREFB
VREFA, VREFB
VRCA, VRCB Voltage range at pins RCA and RCB
VSENSEA,
VSENSEB
Voltage range at pins SENSEA and
SENSEB
Pulsed supply current (for each VS
pin), internally limited by the
overcurrent protection
V
=
VSB = VS;
SA
IS(peak)
3.55
A
tPULSE < 1 ms
IS
RMS supply current (for each VS pin)
V
=
VSB = VS
1.4
A
SA
Storage and operating temperature
range
Tstg, TOP
-40 to 150
°C
1.2
Recommended operating conditions
Table 2.
Symbol
Recommended operating conditions
Parameter
Supply voltage
Parameter
Min
Max
Unit
VS
V
=
=
VSB = VS
8
52
V
SA
SA
Differential voltage between
V
V
VSB = VS;
VOD
VSA, OUT1A, OUT2A, SENSEA and
VSB, OUT1B, OUT2B, SENSEB
52
V
V
= V
SENSEB
SENSEA
Voltage range at pins VREFA and
VREFB
VREFA, VREFB
-0.1
5
(pulsed tW < trr)
(DC)
-6
-1
6
1
VSENSEA,
VSENSEB
Voltage range at pins SENSEA and
SENSEB
V
V
IOUT
Tj
RMS output current
1.4
+125
100
A
Operating junction temperature
Switching frequency
-25
°C
fsw
kHz
3/32
Electrical data
L6228Q
1.3
Thermal data
Table 3.
Symbol
Thermal data
Parameter
Thermal resistance junction-ambient max.
Value
Unit
Rth(JA)
32
°C/W
4/32
L6228Q
Pin connection
2
Pin connection
Figure 2.
Pin connection (top view)
Note:
1
2
The pins 2 to 8 are connected to die PAD.
The die PAD must be connected to GND pin.
5/32
Pin connection
L6228Q
Table 4.
N°
Pin description
Pin
Type
Function
1, 21
9
GND
GND
Ground terminals.
OUT1B
Power Output Bridge B Output 1.
RC Network Pin. A parallel RC network connected between this pin and
ground sets the Current Controller OFF-Time of the Bridge B.
11
12
13
RCB
RC Pin
Power
Supply
Bridge B Source Pin. This pin must be connected to Power Ground through a
sensing power resistor.
SENSEB
VREFB
Bridge B Current Controller Reference Voltage.
Do not leave this pin open or connected to GND.
Analog Input
Step Mode Selector. HIGH logic level sets HALF STEP Mode, LOW logic
HALF/FULL
14
15
Logic Input level sets FULL STEP Mode.
If not used, it has to be connected to GND or +5 V.
Decay Mode Selector. HIGH logic level sets SLOW DECAY Mode. LOW logic
CONTROL Logic Input level sets FAST DECAY Mode.
If not used, it has to be connected to GND or +5 V.
Chip Enable. LOW logic level switches OFF all Power MOSFETs of both
Logic Input Bridge A and Bridge B. This pin is also connected to the collector of the
16
EN
(1)
Overcurrent and Thermal Protection to implement over current protection.
If not used, it has to be connected to +5 V through a resistor.
Supply
Voltage
Bootstrap Voltage needed for driving the upper Power MOSFETs of both
Bridge A and Bridge B.
17
19
20
VBOOT
OUT2B
VSB
Power Output Bridge B Output 2.
Power
Supply
Bridge B Power Supply Voltage. It must be connected to the Supply Voltage
together with pin VSA
Power
Supply
Bridge A Power Supply Voltage. It must be connected to the Supply Voltage
together with pin VSB
22
VSA
23
24
OUT2A
VCP
Power Output Bridge A Output 2.
Output Charge Pump Oscillator Output.
Reset Pin. LOW logic level restores the Home State (State 1) on the Phase
25
RESET
Logic Input Sequence Generator State Machine.
If not used, it has to be connected to +5 V.
Bridge A Current Controller Reference Voltage.
Analog Input
26
27
VREFA
CLOCK
Do not leave this pin open or connected to GND.
Logic Input Step Clock input. The state machine makes one step on each rising edge.
Selects the direction of the rotation. HIGH logic level sets clockwise direction,
Logic Input whereas LOW logic level sets counterclockwise direction.
If not used, it has to be connected to GND or +5 V.
28
29
CW/CCW
SENSEA
Power
Bridge A Source Pin. This pin must be connected to Power Ground through a
sensing power resistor.
Supply
RC Network Pin. A parallel RC network connected between this pin and
ground sets the Current Controller OFF-Time of the Bridge A.
30
31
RCA
RC Pin
OUT1A
Power Output Bridge A Output 1.
1. Also connected at the output drain of the Over current and Thermal protection MOSFET. Therefore, it has to be driven
putting in series a resistor with a value in the range of 2.2 kΩ - 180 kΩ, recommended 100kΩ
6/32
L6228Q
Electrical characteristics
3
Electrical characteristics
Table 5.
Symbol
Electrical characteristcs (T = 25 °C, Vs = 48 V, unless otherwise specified)
A
Parameter
Test condition
Min Typ Max Unit
VSth(ON) Turn-on threshold
VSth(OFF) Turn-off threshold
5.8
5
6.3
5.5
6.8
6
V
V
All bridges OFF;
Tj = -25 °C to 125 °C(1)
IS
Quiescent supply current
Thermal shutdown temperature
5
10
mA
Tj(OFF)
165
°C
Output DMOS transistors
Tj = 25 °C
1.47 1.69
2.35 2.70
2
Ω
Ω
High-Side + Low-Side Switch ON
resistance
RDS(ON)
Tj =125 °C (1)
EN = Low; OUT = VS
EN = Low; OUT = GND
mA
mA
IDSS
Leakage current
-0.3
Source drain diodes
VSD
trr
Forward ON Voltage
ISD = 1.4 A, EN = LOW
If = 1.4 A
1.15 1.3
300
V
Reverse Recovery Time
Forward Recovery Time
ns
ns
tfr
200
Logic inputs (EN, CONTROL, HALF/FULL, CLOCK, RESET, CW/CCW)
VIL
VIH
Low level logic input voltage
High level logic input voltage
Low level logic input current
High level logic input current
Turn-on input threshold
-0.3
2
0.8
7
V
V
IIL
GND logic input voltage
7V logic input voltage
-10
µA
µA
V
IIH
10
Vth(ON)
Vth(OFF)
Vth(HYS)
1.8
1.3
2.0
Turn-off input threshold
0.8
V
Input threshold hysteresis
0.25 0.5
V
Switching characteristics
Enable to output turn-on delay
tD(ON)EN
ILOAD =1.4 A, Resistive load
500 650 800
500 800 1000
ns
time (2)
tD(OFF)EN Enable to output turn-off delay time (2)
ILOAD =1.4 A, Resistive load
ILOAD =1.4 A, Resistive load
ILOAD =1.4 A, Resistive load
ILOAD =1.4 A, Resistive load
ns
ns
ns
µs
µs
µs
tRISE
tFALL
tDCLK
Output rise time (2)
40
40
250
250
Output fall time (2)
Clock to output delay time (3)
2
tCLK(min)L Minimum clock time (4)
tCLK(min)H Minimum clock time (4)
1
1
7/32
Electrical characteristics
L6228Q
Table 5.
Symbol
Electrical characteristcs (continued) (T = 25 °C, Vs = 48 V, unless otherwise specified)
A
Parameter
Clock frequency
Test condition
Min Typ Max Unit
fCLK
100 kHz
tS(MIN)
tH(MIN)
tR(MIN)
Minimum set-up time(5)
Minimum hold time (5)
Minimum reset time (5)
1
1
1
1
µs
µs
µs
tRCLK(MIN) Minimum reset to clock delay time (5)
µs
tDT
fCP
Dead time protection
0.5
3.5
1
µs
Charge pump frequency
Tj = -25 °C to 125 °C (1)
0.6
1
MHz
PWM comparator and monostable
RCA, IRCB Source current at pins RCA and RCB
I
VRCA = VRCB = 2.5 V
VREFA, VREFB = 0.5 V
5.5
5
mA
mV
ns
Voffset
tPROP
tBLANK
tON(MIN)
Offset voltage on sense comparator
Turn OFF propagation delay (6)
Internal blanking time on SENSE pins
Minimum on time
500
1
µs
2.5
13
61
3
µs
R
OFF = 20 kΩ; COFF = 1 nF
OFF = 100 kΩ; COFF = 1 nF
µs
tOFF
PWM recirculation time
R
µs
Input bias current at pins VREFA and
VREFB
IBIAS
10
µA
Over current protection
Input supply overcurrent protection
ISOVER
Tj = -25 °C to 125 °C (1)
2.8
A
threshold
ROPDR
Open drain ON resistance
I = 4 mA
40
60
W
ns
ns
tOCD(ON) OCD turn-on delay time (7)
tOCD(OFF) OCD turn-off delay time (7)
I = 4 mA; CEN < 100 pF
I = 4 mA; CEN < 100 pF
200
100
1. Tested at 25 °C in a restricted range and guaranteed by characterization
2. See Figure 3.
3. See Figure 4.
4. See Figure 5.
5. See Figure 6.
6. Measured applying a voltage of 1 V to pin SENSE and a voltage drop from 2 V to 0 V to pin VREF.
7. See Figure 7.
8/32
L6228Q
Electrical characteristics
Figure 3.
Switching characteristic definition
EN
V
th(ON)
V
th(OFF)
t
I
OUT
90%
10%
t
D01IN1316
t
t
RISE
FALL
t
t
D(ON)EN
D(OFF)EN
Figure 4.
Clock to output delay time
CLOCK
V
th(ON)
t
I
OUT
t
D01IN1317
t
DCLK
9/32
Electrical characteristics
Figure 5.
L6228Q
Minimum timing definition; clock input
CLOCK
V
th(ON)
V
V
th(OFF)
th(OFF)
t
t
D01IN1318
CLK(MIN)L
CLK(MIN)H
Figure 6.
Minimum timing definition; logic inputs
CLOCK
V
th(ON)
LOGIC INPUTS
t
t
H(MIN)
S(MIN)
RESET
V
th(ON)
V
th(OFF)
D01IN1319
t
t
RCLK(MIN)
R(MIN)
Figure 7.
Overcurrent detection timing definition
IOUT
ISOVER
ON
BRIDGE
OFF
VEN
90%
10%
D02IN1399
tOCD(ON)
tOCD(OFF)
10/32
L6228Q
Circuit description
4
Circuit description
4.1
Power stages and charge pump
The L6228Q integrates two independent Power MOS Full Bridges. Each Power MOS has an
DS(ON) = 0.73 Ω (typical value @ 25 °C), with intrinsic fast freewheeling diode. Switching
R
patterns are generated by the PWM Current Controller and the Phase Sequence Generator
(see below). Cross conduction protection is achieved using a dead time (tDT = 1 µs typical
value) between the switch off and switch on of two Power MOSFETs in one leg of a bridge.
Pins VS and VS must be connected together to the supply voltage V . The device
A
B
S
operates with a supply voltage in the range from 8 V to 52 V. It has to be noticed that the
DS(ON) increases of some percents when the supply voltage is in the range from 8 V to 12 V.
R
Using N-Channel Power MOS for the upper transistors in the bridge requires a gate drive
voltage above the power supply voltage. The bootstrapped supply voltage VBOOT is obtained
through an internal Oscillator and few external components to realize a charge pump circuit
as shown in Figure 8. The oscillator output (VCP) is a square wave at 600 kHz (typical) with
10V amplitude. Recommended values/part numbers for the charge pump circuit are shown
in Table 6.
Table 6.
Charge pump external components values
CBOOT
220 nF
10 nF
CP
RP
D1
D2
100 Ω
1N4148
1N4148
Figure 8.
Charge pump circuit
VS
D1
D2
CBOOT
RP
CP
D01IN1328
VCP
VBOOT
VSA VSB
11/32
Circuit description
L6228Q
4.2
Logic inputs
Pins CONTROL, HALF/FULL, CLOCK, RESET and CW/CCW are TTL/CMOS and uC
compatible logic inputs. The internal structure is shown in Figure 9. Typical value for turn-on
and turn-off thresholds are respectively Vth(ON)= 1.8 V and Vth(OFF)= 1.3 V.
Pin EN (Enable) has identical input structure with the exception that the drain of the
Overcurrent and thermal protection MOSFET is also connected to this pin. Due to this
connection some care needs to be taken in driving this pin. The EN input may be driven in
one of two configurations as shown in Figure 10 or Figure 11. If driven by an open drain
(collector) structure, a pull-up resistor R and a capacitor C are connected as shown in
EN
EN
Figure 10. If the driver is a standard Push-Pull structure the resistor REN and the capacitor
EN are connected as shown in Figure 11. The resistor REN should be chosen in the range
C
from 2.2 kΩ to 180 kΩ. Recommended values for REN and CEN are respectively 100 kΩ and
5.6nF. More information on selecting the values is found in the Overcurrent Protection
section.
Figure 9.
Logic inputs internal structure
5V
ESD
PROTECTION
D01IN1329
Figure 10. EN pin open collector driving
5V
5V
REN
OPEN
COLLECTOR
OUTPUT
EN
CEN
ESD
PROTECTION
D01IN1330
Figure 11. EN pin push-pull driving
5V
REN
EN
PUSH-PULL
OUTPUT
CEN
ESD
PROTECTION
D01IN1331
12/32
L6228Q
Circuit description
4.3
PWM current control
The L6228Q includes a constant off time PWM current controller for each of the two bridges.
The current control circuit senses the bridge current by sensing the voltage drop across an
external sense resistor connected between the source of the two lower power MOS
transistors and ground, as shown in Figure 12. As the current in the motor builds up the
voltage across the sense resistor increases proportionally. When the voltage drop across
the sense resistor becomes greater than the voltage at the reference input (VREFA or
VREFB) the sense comparator triggers the monostable switching the bridge off. The power
MOS remain off for the time set by the monostable and the motor current recirculates as
defined by the selected decay mode, described in the next section. When the monostable
times out the bridge will again turn on. Since the internal dead time, used to prevent cross
conduction in the bridge, delays the turn on of the power MOS, the effective off time is the
sum of the monostable time plus the dead time.
Figure 12. PWM current controller simplified schematic
VSA (or B
)
TO GATE LOGIC
BLANKING TIME
MONOSTABLE
1µs
FROM THE
LOW-SIDE
GATE DRIVERS
5mA
2H
1H
MONOSTABLE
SET
2 PHASE
STEPPER MOTOR
S
R
BLANKER
I
OUT
Q
(0)
(1)
OUT2
A(or B)
DRIVERS
DRIVERS
+
+
-
DEAD TIME
DEAD TIME
+
5V
OUT1
A(or B)
2.5V
SENSE
COMPARATOR
2L
1L
+
-
COMPARATOR
OUTPUT
RC
VREF
SENSE
A(or B)
A(or B)
ROFF
A(or B)
COFF
R
SENSE
D01IN1332
Figure 13 shows the typical operating waveforms of the output current, the voltage drop
across the sensing resistor, the RC pin voltage and the status of the bridge. More details
regarding the Synchronous Rectification and the output stage configuration are included in
the next section.
Immediately after the Power MOS turns on, a high peak current flows through the sensing
resistor due to the reverse recovery of the freewheeling diodes. The L6228Q provides a 1µs
Blanking Time tBLANK that inhibits the comparator output so that this current spike cannot
prematurely re-trigger the monostable.
13/32
Circuit description
Figure 13. Output current regulation waveforms
L6228Q
I
OUT
V
REF
R
SENSE
t
t
t
OFF
OFF
ON
1µs t
1µs t
BLANK
V
BLANK
SENSE
V
REF
0
Slow Decay
Slow Decay
t
t
V
RCRISE
RCRISE
RC
5V
2.5V
t
t
RCFALL
RCFALL
1µs t
1µs t
DT
DT
ON
SYNCHRONOUS OR QUASI
SYNCHRONOUS RECTIFICATION
OFF
B
C
D
A
B
C
D
D01IN1334
Figure 14 shows the magnitude of the Off Time t
versus C
and R
values. It can be
OFF
OFF
OFF
approximately calculated from the equations:
t
t
= 0.6 · R
· C
RCFALL
OFF OFF
= t
+ t = 0.6 · R
· C
+ t
OFF DT
OFF
RCFALL
DT
OFF
where R
and C
are the external component values and t is the internally generated
OFF DT
OFF
Dead Time with:
20 kΩ ≤ R
≤ 100 kΩ
OFF
0.47 nF ≤ C
≤ 100 nF
OFF
t
= 1 µs (typical value)
DT
Therefore:
t
t
= 6.6 µs
= 6 ms
OFF(MIN)
OFF(MAX)
These values allow a sufficient range of t
to implement the drive circuit for most motors.
OFF
The capacitor value chosen for C
also affects the Rise Time t
of the voltage at the
RCRISE
OFF
pin RCOFF. The Rise Time t
will only be an issue if the capacitor is not completely
RCRISE
charged before the next time the monostable is triggered. Therefore, the on time t , which
ON
depends by motors and supply parameters, has to be bigger than t
for allowing a
RCRISE
good current regulation by the PWM stage. Furthermore, the on time t can not be smaller
ON
than the minimum on time t
.
ON(MIN)
14/32
L6228Q
Circuit description
t
ON > tON(MIN) = 2.5µs
ON > tRCRISE – tDT
(typ. value)
⎧
⎨
⎩
t
t
= 600 · C
OFF
RCRISE
Figure 15 shows the lower limit for the on time t for having a good PWM current regulation
ON
capacity. It has to be said that tON is always bigger than t
because the device imposes
ON(MIN)
this condition, but it can be smaller than t
- t . In this last case the device continues
RCRISE DT
to work but the off time t
is not more constant.
OFF
So, small C
value gives more flexibility for the applications (allows smaller on time and,
OFF
therefore, higher switching frequency), but, the smaller is the value for C , the more
OFF
influential will be the noises on the circuit performance.
Figure 14. t
versus C
and R
OFF
OFF
OFF
4
.
1 10
= 100k
Ω
Roff
3
.
1 10
= 47k
Ω
Roff
= 20kΩ
Roff
100
10
1
0.1
1
10
100
Coff [nF]
15/32
Circuit description
Figure 15. Area where t can vary maintaining the PWM regulation.
L6228Q
ON
100
10
1
2.5µs (typ. value)
0.1
1
10
100
Coff [nF]
4.4
Decay modes
The CONTROL input is used to select the behavior of the bridge during the off time. When
the CONTROL pin is low, the Fast Decay mode is selected and both transistors in the bridge
are switched off during the off time. When the CONTROL pin is high, the Slow Decay mode
is selected and only the low side transistor of the bridge is switched off during the off time.
Figure 16 shows the operation of the bridge in the Fast Decay mode. At the start of the off
time, both of the power MOS are switched off and the current recirculates through the two
opposite free wheeling diodes. The current decays with a high dI/dt since the voltage across
the coil is essentially the power supply voltage. After the dead time, the lower power MOS in
parallel with the conducting diode is turned on in synchronous rectification mode. In
applications where the motor current is low it is possible that the current can decay
completely to zero during the off time. At this point if both of the power MOS were operating
in the synchronous rectification mode it would then be possible for the current to build in the
opposite direction. To prevent this only the lower power MOS is operated in synchronous
rectification mode. This operation is called Quasi-Synchronous Rectification Mode. When
the monostable times out, the power MOS are turned on again after some delay set by the
dead time to prevent cross conduction.
Figure 17 shows the operation of the bridge in the Slow Decay mode. At the start of the off
time, the lower power MOS is switched off and the current recirculates around the upper half
of the bridge. Since the voltage across the coil is low, the current decays slowly. After the
dead time the upper power MOS is operated in the synchronous rectification mode. When
the monostable times out, the lower power MOS is turned on again after some delay set by
the dead time to prevent cross conduction.
16/32
L6228Q
Circuit description
Figure 16. Fast decay mode output stage configurations
A) ON TIME
B) 1µs DEAD TIME
C) QUASI-SYNCHRONOUS
RECTIFICATION
D) 1µs SLOW DECAY
D01IN1335
Figure 17. Slow decay mode output stage configurations
A) ON TIME
B) 1µs DEAD TIME
C) SYNCHRONOUS
RECTIFICATION
D) 1µs DEAD TIME
D01IN1336
4.5
4.6
Stepping sequence generation
The phase sequence generator is a state machine that provides the phase and enable
inputs for the two bridges to drive a stepper motor in either full step or half step. Two full step
modes are possible, the Normal Drive Mode where both phases are energized each step
and the Wave Drive Mode where only one phase is energized at a time. The drive mode is
selected by the HALF/FULL input and the current state of the sequence generator as
described below. A rising edge of the CLOCK input advances the state machine to the next
state. The direction of rotation is set by the CW/CCW input. The RESET input resets the
state machine to state 1.
Half step mode
A HIGH logic level on the HALF/FULL input selects Half Step Mode. Figure 18 shows the
motor current waveforms and the state diagram for the Phase Sequencer Generator. At
Start-Up or after a RESET the Phase Sequencer is at state 1. After each clock pulse the
state changes following the sequence 1,2,3,4,5,6,7,8,… if CW/CCW is high (Clockwise
movement) or 1,8,7,6,5,4,3,2,… if CW/CCW is low (Counterclockwise movement).
17/32
Circuit description
L6228Q
4.7
Normal drive mode (Full-step two-phase-on)
A LOW level on the HALF/FULL input selects the Full Step mode. When the low level is
applied when the state machine is at an ODD numbered state the Normal Drive Mode is
selected. Figure 19 shows the motor current waveform state diagram for the state machine
of the Phase Sequencer Generator. The Normal Drive Mode can easily be selected by
holding the HALF/FULL input low and applying a RESET. At start -up or after a RESET the
State Machine is in state 1. While the HALF/FULL input is kept low, state changes following
the sequence 1,3,5,7,… if CW/CCW is high (Clockwise movement) or 1,7,5,3,… if CW/CCW
is low (Counterclockwise movement).
4.8
Wave drive mode (Full-step one-phase-on)
A LOW level on the pin HALF/FULL input selects the Full Step mode. When the low level is
applied when the state machine is at an EVEN numbered state the Wave Drive Mode is
selected. Figure 20 shows the motor current waveform and the state diagram for the state
machine of the Phase Sequence Generator. To enter the Wave Drive Mode the state
machine must be in an EVEN numbered state. The most direct method to select the Wave
Drive Mode is to first apply a RESET, then while keeping the HALF/FULL input high apply
one pulse to the clock input then take the HALF/FULL input low. This sequence first forces
the state machine to state 1. The clock pulse, with the HALF/FULL input high advances the
state machine from state 1 to either state 2 or 8 depending on the CW/CCW input. Starting
from this point, after each clock pulse (rising edge) will advance the state machine following
the sequence 2,4,6,8,… if CW/CCW is high (Clockwise movement) or 8,6,4,2,… if CW/CCW
is low (Counterclockwise movement).
Figure 18. Half step mode
I
OUTA
OUTB
3
2
1
4
5
6
7
I
8
Start Up or Reset
CLOCK
1
2
3
4
5
6
7
8
D01IN1320
Figure 19. Normal drive mode
IOUTA
3
2
1
4
5
6
7
IOUTB
8
CLOCK
Start Up or Reset
1
3
5
7
1
3
5
7
D01IN1322
18/32
L6228Q
Circuit description
Figure 20. Wave drive mode
I
I
OUTA
3
2
1
4
5
6
7
OUTB
8
CLOCK
2
4
6
8
2
4
6
8
Start Up or Reset
D01IN1321
4.9
Non-dissipative overcurrent protection
The L6228Q integrates an Overcurrent Detection Circuit (OCD) for full protection. This
circuit provides protection against a short circuit to ground or between two phases of the
bridge. With this internal over current detection, the external current sense resistor normally
used and its associated power dissipation are eliminated. Figure 21 shows a simplified
schematic of the overcurrent detection circuit.
To implement the over current detection, a sensing element that delivers a small but precise
fraction of the output current is implemented with each high side power MOS. Since this
current is a small fraction of the output current there is very little additional power
dissipation. This current is compared with an internal reference current I . When the
REF
output current reaches the detection threshold (typically 2.8 A) the OCD comparator signals
a fault condition. When a fault condition is detected, the EN pin is pulled below the turn off
threshold (1.3 V typical) by an internal open drain MOS with a pull down capability of 4 mA.
By using an external R-C on the EN pin, the off time before recovering normal operation can
be easily programmed by means of the accurate thresholds of the logic inputs.
19/32
Circuit description
Figure 21. Overcurrent protection simplified schematic
L6228Q
OUT1A VSA OUT2A
POWER SENSE
1 cell
HIGH SIDE DMOSs OF
THE BRIDGE A
I1A
I2A
POWER SENSE
1 cell
POWER DMOS
n cells
POWER DMOS
n cells
TO GATE
LOGIC
+
µC or LOGIC
I1A / n
I2A / n
OCD
COMPARATOR
VDD
(I1A+I2A) / n
IREF
REN
CEN
.
.
EN
INTERNAL
OPEN-DRAIN
RDS(ON)
40Ω TYP.
OVER TEMPERATURE
FROM THE
BRIDGE B
OCD
COMPARATOR
D01IN1337
Figure 22 shows the Overcurrent Detection operation. The Disable Time t
before
DISABLE
recovering normal operation can be easily programmed by means of the accurate
thresholds of the logic inputs. It is affected whether by C and R values and its
EN
EN
magnitude is reported in Figure 23. The Delay Time t
before turning off the bridge
DELAY
when an overcurrent has been detected depends only by C value. Its magnitude is
EN
reported in Figure 24.
C
is also used for providing immunity to pin EN against fast transient noises. Therefore
EN
the value of C should be chosen as big as possible according to the maximum tolerable
EN
Delay Time and the R value should be chosen according to the desired Disable Time.
EN
The resistor R should be chosen in the range from 2.2 kΩ to 180 kΩ. Recommended
EN
values for R and C are respectively 100 kΩ and 5.6 nF that allow obtaining 200 µs
EN
EN
Disable Time.
20/32
L6228Q
Circuit description
Figure 22. Overcurrent protection waveforms
IOUT
ISOVER
VEN
VDD
Vth(ON)
Vth(OFF)
VEN(LOW)
ON
OCD
OFF
ON
tDELAY
tDISABLE
BRIDGE
OFF
tOCD(ON) tEN(FALL)
tOCD(OFF)
tEN(RISE)
tD(ON)EN
tD(OFF)EN
D02IN1400
21/32
Circuit description
Figure 23. t
L6228Q
versus C and R (V = 5 V).
DISABLE
EN
EN
DD
Ω
Ω
R E N = 100 k
R E N = 220 k
3
.
Ω
Ω
R E N = 47 k
R E N = 33 k
1
10
Ω
R E N = 10 k
100
10
1
1
10
100
C E N [nF ]
Figure 24. t
versus C (V = 5V).
DELAY
EN
DD
10
1
0.1
1
10
Cen [nF]
100
4.10
Thermal protection
In addition to the Ovecurrent Protection, the L6228Q integrates a Thermal Protection for
preventing the device destruction in case of junction over temperature. It works sensing the
die temperature by means of a sensible element integrated in the die. The device switch-off
when the junction temperature reaches 165 °C (typ. value) with 15 °C hysteresis
(typ. value).
22/32
L6228Q
Application information
5
Application information
A typical Bipolar Stepper Motor Driver application using L6228Q is shown in Figure 25.
Typical component values for the application are shown in Table 7. A high quality ceramic
capacitor in the range of 100 to 200 nF should be placed between the power pins (VS and
A
VS ) and ground near the L6228Q to improve the high frequency filtering on the power
B
supply and reduce high frequency transients generated by the switching. The capacitor
connected from the EN input to ground sets the shut down time when an over current is
detected (see Overcurrent Protection). The two current sensing inputs (SENSE and
A
SENSE ) should be connected to the sensing resistors with a trace length as short as
B
possible in the layout. The sense resistors should be non-inductive resistors to minimize the
dI/dt transients across the resistor. To increase noise immunity, unused logic pins (except
EN) are best connected to 5 V (High Logic Level) or GND (Low Logic Level) (see pin
description). It is recommended to keep Power Ground and Signal Ground separated on
PCB.
Table 7.
Component values for typical application
Component
Value
C1
C2
100µF
100nF
1nF
CA
CB
1nF
CBOOT
CP
220nF
10nF
CEN
CREF
D1
5.6nF
68nF
1N4148
1N4148
39kΩ
39kΩ
100kΩ
100Ω
0.6Ω
D2
RA
RB
REN
RP
RSENSEA
RSENSEB
0.6Ω
23/32
Application information
Figure 25. Typical application
L6228Q
Note:
To reduce the IC thermal resistance, therefore improve the dissipation path, the NC pins can
be connected to GND.
24/32
L6228Q
Output current capability and IC power dissipation
6
Output current capability and IC power dissipation
In Figure 26, Figure 27, Figure 28 and Figure 29 are shown the approximate relation
between the output current and the IC power dissipation using PWM current control driving
a two-phase stepper motor, for different driving sequences:
●
●
●
●
HALF STEP mode (Figure 26) in which alternately one phase / two phases are
energized.
NORMAL DRIVE (FULL-STEP TWO PHASE ON) mode (Figure 27) in which two
phases are energized during each step.
WAVE DRIVE (FULL-STEP ONE PHASE ON) mode (Figure 27) in which only one
phase is energized at each step.
MICROSTEPPING mode (Figure 29), in which the current follows a sine-wave profile,
provided through the V pins.
ref
For a given output current and driving sequence the power dissipated by the IC can be
easily evaluated, in order to establish which package should be used and how large must be
the on-board copper dissipating area to guarantee a safe operating junction temperature
(125 °C maximum).
Figure 26. IC power dissipation versus output current in HALF STEP mode
HALF STEP
10
IA
IOUT
8
IB
6
PD [W]
IOUT
4
Test Conditions:
Supply Voltage= 24V
No PWM
2
0
0 0.25 0.5 0.75 1 1.25 1.5
IOUT [A]
fSW = 30 kHz (slow decay)
25/32
Output current capability and IC power dissipation
L6228Q
Figure 27. IC power dissipation versus output current in NORMAL mode
(full step two phase on)
NORMAL DRIVE
IA
10
IOUT
8
IB
6
IOUT
PD [W]
4
2
0
Test Conditions:
Supply Voltage =24V
No PWM
fSW = 30kHz (slow decay)
0
0.25 0.5 0.75 1 1.25 1.5
IOUT [A]
Figure 28. IC power dissipation versus output current in WAVE mode
(full step one phase on)
WAVE DRIVE
10
IA
IOUT
8
IB
6
PD [W]
IOUT
4
2
0
Test Conditions:
Supply Voltage = 24V
No PWM
0 0.25 0.5 0.75 1 1.25 1.5
fSW = 30 kHz (slow decay)
I
OUT [A]
Figure 29. IC power dissipation versus output current in MICROSTEPPING mode
MICROSTEPPING
IA
IOUT
10
8
IOUT
6
IB
PD [W]
4
2
Test Conditions:
Supply Voltage = 24V
0
0 0.25 0.5 0.75 1 1.25 1.5
IOUT [A]
fSW = 30 kHz (slow decay)
fSW = 50 kHz (slow decay)
26/32
L6228Q
Thermal management
7
Thermal management
In most applications the power dissipation in the IC is the main factor that sets the maximum
current that can be delivered by the device in a safe operating condition. Therefore, it has to
be taken into account very carefully. Besides the available space on the PCB, the right
package should be chosen considering the power dissipation. Heat sinking can be achieved
using copper on the PCB with proper area and thickness.
For instance, using a VFQFPN32L 5x5 package the typical R
is about 32 °C/W.
th(j-amb)
27/32
Package mechanical data
L6228Q
8
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
Table 8.
VFQFPN 5x5x1.0 32L pitch 0.50
Dim.
Databook (mm)
Typ
Min
Max
A
b
0.80
0.18
0.165
4.85
3.00
1.10
4.85
4.20
0.60
0.85
0.25
0.175
5.00
3.10
1.20
5.00
4.30
0.70
0.50
0.40
0.95
0.30
0.185
5.15
3.20
1.30
5.15
4.40
0.80
b1
D
D2
D3
E
E2
E3
e
L
0.30
0.50
0.08
ddd
Note:
VFQFPN stands for Thermally Enhanced Very thin profile Fine pitch Quad Flat Package No
lead. Very thin profile: 0.80 < A < 1.00mm.
Details of terminal 1 are optional but must be located on the top surface of the package by
using either a mold or marked features.
28/32
L6228Q
Package mechanical data
Figure 30. Package dimensions
29/32
Order codes
L6228Q
9
Order codes
Table 9.
Order codes
Part number
Package
Packaging
L6228Q
VFQFPN 5x5x1.0 32L
Tube
30/32
L6228Q
Revision history
10
Revision history
Table 10. Document revision history
Date
Revision
Changes
14-Jan-2008
1
First release
31/32
L6228Q
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