L6245 [STMICROELECTRONICS]
5V HARD DISK DRIVE POWER COMBO; 5V硬盘驱动器宝瓶
| 型号： | L6245 |
| 厂家： | 
ST |
| 描述： | 5V HARD DISK DRIVE POWER COMBO |
| 文件： | 总15页 (文件大小：192K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L6245
5V HARD DISK DRIVE POWER COMBO
PRODUCT PREVIEW
General
+5V OPERATION
MULTIPOWER BCD TECHNOLOGY
REGISTER BASED ARCHITECTURE
MINIMUM EXTERNAL COMPONENTS
SLEEP AND IDLE MODES FOR LOW
POWER CONSUMPTION
SELECTABLE GAINS FOR BOTH VCM AND
SPINDLE Gm LOOP
LINEAR CURRENT CONTROL LOOPS FOR
BOTH VCM AND SPINDLE
8 BIT D/A FOR ACTUATOR DRIVER AND
SPINDLE DRIVER
PQFP64
VCM Driver
ORDERING NUMBER: L6245
CURRENT SENSE CONTROL (VOLTAGE
PROPORTIONAL TO CURRENT)
VOLTAGE SENSE CONTROL (VOLTAGE
PROPORTIONAL
TO
THE
VOLTAGE
ACROSS THE VCM)
TWO CURRENT RANGES FOR SEEKING
AND TRACKING
INTERNAL REGISTER FOR POWER AMP
CONTROL LINES
SPEED OUTPUT (VOLTAGE PROPOR-
TIONAL TO BEMF)
DESCRIPTION
The L6245 contains in a single chip all the func-
tions to operate a sensorless brushless (DC) mo-
tor and a voice coil motor, suitable for hard disk
drive applications.
The device is configured to interface directly to
an 8 bit parallel microprocessor bus, and has a
register based architecture to reduce number of
interconnection lines. All the positioning loop for
sensorless spindle is integrated, including BEMF
sensing, digital masking, digital delay and se-
quencing. All timing function are performed digi-
tally, thus no external filtering componentsare re-
quired.
Spindle Driver
BEMF PROCESSING FOR SENSORLESS
MOTOR COMMUTATION
PROGRAMMABLE COMMUTATION PHASE
DELAY
PROGRAMMABLE SLEW-RATE FOR RE-
DUCED EMI
The VCM driver is a transconductance amplifier,
able to provide 2 different current ranges, suitable
for seeking or tracking of the head actuator.
When a low voltage is detected, a monitor, in se-
quence, resets the internal registers, puts in tris-
tate the spindle powers, retracts the actuator, and
applies the dynamic brake of the spindle.
The L6245 is realized in Multipower-BCD 2 tech-
nology, which combine isolate DMOS power tran-
sistors with CMOS and Bipolar circuits in the
same monolithic layer, and is assembled in a 64-
pin PQFP.
0.7Ω TYP. FOR ANY HALF BRIDGE
CROSS CONDUCTION PROTECTION
SYNTHESIZED HALL OUTPUT
Other Functions
POWER UP SEQUENCING
POWER DOWN SEQUENCING
LOW VOLTAGE SENSE
ACTUATOR RETRACTION
DYNAMIC BRAKE
THERMAL SHUTDOWN
October 1992
1/15
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
L6245
BLOCK DIAGRAM
2/15
L6245
PIN CONNECTION (Top view)
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Peak Output Sustaining Voltage
VP; Vcc Supply Voltage
Value
Unit
Vds sus
14
V
Power (VP)
Logic (VCC
8
6
V
V
)
Vi
Vcp
Ip
Logic input Voltage
0 to 6
V
V
Charge Pump Input Voltage
18
Sink-Source Peak Output Current
Sink-Source DC Output Current
Total Power Dissipation (Tamb = 60°C)
Storage and Junction Temperature
1.5
A
IO
1
1
A
Ptot
Tstg, Tj
W
°C
–40 to 150
THERMAL DATA
Symbol
Parameter
Thermal Resistance Junction-ambient (*)
Value
Unit
Rthj-amb
max.
90
°C/W
(*) Mounted on a typical PCB layout (see Fig. 7)
3/15
L6245
PIN DESCRIPTION [Pin Types: I = Input, O = Output, P = Power, A = Analog (passive)]
Power
Pin Number
Pin Name
Pin Type
Description
Positive supply, nominally 5V.
12, 17
24,
VPOWER
VDIG
P
3
VCC
7, 42, 64
10
GND
VREF
POR
P
I
Ground.
All analog signals are referenced to this voltage, nominally 2V.
59
0
POWER ON RESET - Goes low when the supply voltage is below the
VOLTAGE GOOD threshold. POR is an open collector output with an
internal 20kΩ pull-up.
61
62
POR_DLY
POR_FILT
A
A
POR DELAY. An external parallel RC network from this pin to ground
sets the time the POR signal stays active after voltage good.
An external capacitor from this pin to ground provides filtering for the
V
CC sense input of the POR circuit.
5
6
CPC
CPL
A
A
Charge pump capacitor
Charge pump inductor
Microprocessor Interface
Pin Number
Pin Name
Pin Type
Description
25
26
27
28
29
30
31
32
D7
D6
D5
D4
D3
D2
D1
D0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
An 8-bit bidirectional data bus which is connected to the internal
registers.
38
39
35
RD
WR
I
I
I
READ A low level on this pin allows the bus to be driven by the IC.
A low level on WRITE allows the IC to read data from the system bus.
MC_CS
CHIP SELECT A low level on this pin selects the IC for bus
transactions.
41
SYSCLK
I
Microprocessor clock used for internal timing.
33
34
35
A0
A1
A2
I
I
I
The lowest three bits of the system address bus; used to address
internal registers
37
AS
I
ADDRESS STROBE The address appearing on A [0:2] is latched on
the falling edge of the AS pulse.
43
MC_ERR
O
A maskable interrupt signal which is asserted low when an error flag in
the Status Register is set. The output is open-drain with an internal
20KΩ pull-up.
40
DTACK
O
An open drain, active low signal used for asynchronous bus
transactions.
Brushless, Sensorless Motor Driver and 8 bit D/A
Pin Number
Pin Name
SPIN_DAC
SPIN_CMD
COIL_CT
Pin Type
Description
47
48
45
O
I
The output of an 8 bit D/A used for the command to the spindle driver.
The input to the spindle driver transconductance amplifier.
The center tap of the motor is connected to this pin.
I
53
57
60
COIL_U
COIL_V
COIL_W
O
The motor coils are driven by these outputs. Back EMF is also sensed
at these pins.
4/15
L6245
PIN DESCRIPTION (continued)
Pin Number
Pin Name
Pin Type
Description
44
SYNTH_HALL
O
A TTL compatible signal that emulates one of the Hall signals.
SYNTH_HALL is an open drain output with an internal 20KΩ pull-up.
49, 50,
58
SPIN SENSE
1,2,3
A
The current sensing resistors is connected from these pins to ground.
46
56
51
PWM_OFFT
SLEW
A
A
A
A parallel R-C from this pin to ground sets the PWM mode OFF time.
A resistor from this pin to ground sets the slew rate of the driver.
S_COMP
An R-C network from this pin to GND sets the spin driver
compensation.
VCM Driver and 8 bit D/A
Pin Number
Pin Name
VCM_DAC
VCM_CMD
VCM_COMP
VCM_RS1
VCM_RS2
Pin Type
Description
8
O
I
The output of an 8 bit D/A used to command the VCM driver.
9
VCM driver input command which is relative to VREF.
21
14
23
A
A
A
An R-C network from this pin to ground compensates the VCM driver.
The high gain current sense resistor is attached from this pin to ground.
The low gain current sense resistor is connected from this pin to
VCM_RS1
13
15
20
VCM+
VCM-
O
O
O
One end of the load is attached to this pin (Positive).
The other end of the load is attached to this pin (Negative).
A voltage which is proportional to the voltage across the load,
OV_VOLT
referenced to VREF
A voltage which is proportional to the current through the load,
referenced to VREF
.
19
OV_CUR
O
.
16
18
OV_SUM–
I
Over-velocity summing op-amp inverting input.
Over-velocity summing op-amp output.
OV_SUM_OUT
O
22
54
ISENSE
O
I
A voltage which is proportional to the current through the VCM load as
sensed by the sense resistor. This signal is enabled by setting bit 2 in
the VCM Control Register.
VCM_STRB
The 8 bit input to the VCM D/A is updated on the rising edge of
VCM_STRB.
Solenoid Pre-drivers and Power Down Sequencing
Pin Number
Pin Name
Pin Type
Description
11,55,
63
V_RECIR
P
Under normal conditions, power is supplied to various blocks via the
V_RECIR pin. When external power is removed, energy stored in the
rotating spindle is converted to a voltage which supplies the park circuit.
2
1
LOAD_SOL
O
O
When a logic one is written to bit 3 of the VCM Control Register,
current is sourced from the LOAD_SOL pin. Otherwise, the pin is high
impedance.
UNLOAD_SOL
When a logic one is written to bit 4 of the VCM Control Register,
current is sourced from the UNLOAD_SOL pin. Otherwise, the pin is
high impedance.
4
PD_SEQ_CAP
BRK_DLY
A
A
When power is removed, the charge stored on this capacitor keeps
selected blocks alive long enough to effect an orderly power down.
52
An external parallel RC network from this point to ground delays
activation of the dynamic brake after power is removed.
5/15
L6245
ELECTRICAL CHARACTERISTICS (VS = 5V, Tj = 25°C; unlessotherwise specified)
Power Supply Characteristics
Symbol
Parameter
Supply Voltage
Test Condition
VS = VP = VCC
Min.
Typ.
Max.
5.5
Units
V
VS
4.5
ID-READY Quiescent Current Dissipation No load attached VCM and Spin
drivers enab.
25
mA
ID_IDLE
VCM driver disabled Spin driver
enabled
20
4
mA
mA
ID_SLEEP
VCM and Spin drivers disabled
VCM Driver (Notes 1, 2)
IOS
IOT
RDS(on)
RDS(on)
Maximum Load Current
(Seeking)
Output Devices A, B, E, F (Fig. 1)
Output Devices C, D (Fig. 1)
0.3
0.1
1
A
A
Ω
Ω
Maximum Load Current
(Traking)
Source & Sink Out ON
Resistance
Output Devices A, B, E, F
Tj = 125°C (Fig. 1)
Sink Out On Resistance
Output Devices C, D
2.4
Tj = 125°C (Fig. 1)
RDS(on)
VF
Sink Out On Resistance
Body Diode Forward Drop
Jump Discontinuity (**)
Deadband Discontinuity (*)
Offset (***)
Parking Device Tj = 125°C
I = 0.3A
12
1.5
30
6
Ω
V
Vjump
VDB
Rsense = 2.01Ω
Rsense = 2.01Ω
Rsense = 2.01Ω
mV
mV
mV
VCMOS
40
(*) The range of input voltages applied to the VCM_CMD pin (with respect to VREF) for which only negligible current is present in the load. This
deadband voltage (VDB) can be expressed either in mV or in LSBs, where one LSB is equal to 11.7mV.
(**) A condition in which the transfer characteristic (i.e., load current vs. VCM_CMD-VREF) exhibits a slope which is significantly grater than the
desired value. The range of currents for which this condition exists is termed IJUMP. This current is referred o the VCM_CMD input according
to the following equation: VJUMP = IJUMP x 3 x RSENSE
In this document, RSENSE is assumed to be 2.01Ω. VJUMP can be expressed either in mV or in LSBs, where one LSB is equal to 11.7mV.
(***) The value of VCM_CMD (with respect to VREF) for which the load current is zero. In parts which exihibit a DEADBAND dicontinuity, the
offset is defined to be at the midpoint of the deadband region. RSENSE is assumed to br 2.01Ω.
VCM Current sense amplifier (ISENSE
)
Voff
Output Offset Voltage
VCM_RS2 Shorted to GND O/S is
(Isense) - Vref
–50
50
mV
V
G
Closed Loop Voltage Gain
3V/V nominal
2.85
50
3.15
V/V
dB
PSRR
BW
Power Supply Rejection Ratio at DC
Banwwidth
200
–0.2
KHz
V
VOR
Output Range
VCC = 4.5V (note 4)
3.5
VCM Full wave rectifying amplifier
IB
Input Bias Current
Input Impedance
VCM_CMD = Vref
2
µA
Iimp
Impedance seen at VCM_CMD
wrt Vref
5
KΩ
G
Closed Loop Gain
0.320
50
0.347
V/V
dB
KHz
V
PSRR
GBW
CMR
VOR
Power Supply Rejection Ratio at DC
Unity Gain Bandwidth
200
0.3
0
Input Common Mode Range
Output Range
VCM_CMD pin
3.7
1
V
6/15
L6245
ELECTRICAL CHARACTERISTICS (Continued)
VCM DAC (Notes 5, 6)
Symbol
Res
Parameter
Resolution
Test Condition
Min.
Typ.
Max.
Units
bit
8
N.L.
Differential Nonlinearity
Integral Nonlinearity
Conversion Time
±0.5
±0.5
2
LSB
LSB
µs
I.N.L.
CT
From 50% point of WR falling to
1% settling
ZO
FSTC
VOH
Output Z
100
200
Ω
ppm/°C
V
Full Scale Temp. Coeff.
High Output Voltage
Low Output Voltage
Zero Scale Offset
Relative to Vref Input Code = 7Fh
Relative to Vref Input Code = 80h
Relative to Vref Input Code = 00
1.46
1.52
–1.47
±10
VOL
–1.53
V
VZSO
mV
Over velocity detector, coil voltage sense amplifier
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Units
VO
Output Offset Voltage
VCM+ = VCM–, within input
common mode range.
Measure wrt to Vref
–50
+50
mV
IBC
G
Input Bias Current
(Note 3)
10
µA
V/V
dB
Closed Loop Voltage Gain
Av = 0.25V/V nominal
0.242
50
0.258
PSRR
BW
Power Supply Rejection Ratio at DC
Bandwidth
200
0
KHz
V
CMR
Input Common Mode Range
Above and below these values
VPOWER
the op amp will be in saturation
and will not invert sign.
VDR
VOR
IO
Input Differential Range
Output Range
0
VPOWER
3.5
V
V
0.3
Output Current
æ400
µA
Over velocity detector, coil current sense amplifier
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Units
VO
Output Offset Voltage
VCM_RS1 shorted to GND for:
(a) VCM_CMD < Vref and
b) VCM_CMD > Vref. Measure wrt
Vref
–50
+50
mV
G
PSRR
Bw
Closed Loop Voltage Gain
Av = 2.5V/V nominal
2.425
50
2.575
V/V
dB
KHz
V
Power Supply Rejection Ratio at DC
Bandwidth
200
–0.1
0.5
CMR
VR
Input Common Mode Range
Output Range
2
3.5
V
IO
Output Current
+400
mA
7/15
L6245
ELECTRICAL CHARACTERISTICS (Continued)
Over velocity detector, summing amplifier
Symbol
VO
Parameter
Input Offset Voltage
Input Bias Current
Test Condition
Min.
Typ.
Max.
10
Units
mV
µA
IBC
1
G
Open Loop Gain
60
50
dB
PSRR
GBW
VR
Power Supply Rejection Ratio at DC
Unity Gain Bandwidth
Output Range
dB
200
0.5
KHz
V
3.5
IO
Output Current
+400
µA
Over velocity detector, window comparator
Symbol
tS
Parameter
Switching Time
Test Condition
Min.
Typ.
Max.
50
Units
µs
VTL
Low Threshold
High Threshold
Relative to Vref
Relative to Vref
–1.32
1.18
–1.18
1.32
V
VTH
V
Solenoid pre-driver (Note 7)
Symbol
Parameter
Output Current
Test Condition
Min.
Typ.
Typ.
Max.
Units
IOH
VOH = 1.5V, VCC = 4.4V
10
mA
Three phase sensorless motor driver
Symbol
IO
Parameter
Max. Load Current
Out On Resistance
Slew Rate
Test Condition
Tj = 125°C
Min.
Max.
0.5
Units
A
RDS(on)
dV/dt
VF
0.75
Ω
0.05
V/µs
V
Body Diode Forward Drop
I = 0.5A
1.2
Motor Current Sense Amplifier
Symbol
Parameter
Input Bias Current
Test Condition
Min.
Typ.
Max.
Units
IBC
G
1
µA
Closed Loop Voltage Gain
Low Gain mode
High Gain mode
19.4
4.85
20.6
5.15
V/V
V/V
PSRR
BW
IO
Power Supply Rejection Rate at DC
Bandwidth
50
200
0
dB
KHz
V
Output Range
3.2
Spin DAC (Notes 8, 9)
Symbol
Res
NL
Parameter
Test Condition
Min.
Typ.
Max.
Units
bit
Resolution
8
Differential Nonlinearity
Integral Nonlinearity
Conversion Time
±0.5
±0.5
5
LSB
LSB
µs
INL
CT
From 50% point of –WR falling to
1% settling
Zo
FSTC
VOH
Output Z
14
200
3.15
20
KΩ
ppm/°C
V
Full Scale Temp. Coeff.
High Output Voltage
Low Output Voltage
2.85
0
VOL
Unloaded
mV
8/15
L6245
ELECTRICAL CHARACTERISTICS (Continued)
Step-up converter
Symbol
Parameter
Step-up Voltage
Test Condition
Relative to VCC
Min.
Typ.
Typ.
Max.
Units
VSU
7
11
V
Microprocessor interface (Note 10)
Symbol
VIH
Parameter
Test Condition
Min.
Max.
Units
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
3
V
V
V
V
VIL
0.8
VOH
VCC = 5V, IOH = 400µA
4.4
VOL1
–MCERR, –POR, –DTACK
IOL = 4mA
0.4
0.4
1
VOL2
IIN1
Low Level Output Voltage
Input Leakage Current
Input Leakage Current
SYNT_ALL
IOL = 0.5mA
V
–RD, –WR, AS, –MC_CS,
SYSCLK, A [0:2]
µA
µA
IIN2
D [0:7]
10
Microprocessor interface timing
Trddh
Trddt
Twrdt
Read Data Hold
5
40
40
40
ns
ns
ns
–RD High to –DTACK high
–WR High to –DTACK High
Power on reset
VCCHL
VCCHL
TPLH
RT
VCC Good, HL
VCC falling
VCC rising
4.2
4.4
4.5
200
50
V
V
VCC Good, LH
Rise Time
4.26
CLoad = 100pF
ns
µs
Response Time
Notes:
1) The minimum voltage available from the brushless DC motor after power has been removed is 2.7V
2) The voltage available for actuator etraction shall be greater than 0.7V.
3) Sum of Ibias+(Vref/internal resistor + power leakage).
4) Minimum output voltage is set to Vref by a resistor network.
5) The VCM DAC shall be monotonic over its full range.
6) The coding of the digital input shall be 2’s complement.
7) The voltage available for solenoid operation shall be greater than 1.9V.
8) The Spin DAC shall be monotonic over its full range.
9) The coding of the digital input shall be uniplar (unsigned binary).
10) SYNTH_HALL, MC_ERR, DTACK and POR shall have open drain (collector) outputs and internal pull-up resistors. The minimum value of
these pull-up resistors shall be 20KΩ..
Reset (POR) signal is held low. The POR signal is
FUNCTIONAL DESCRIPTION
held low from the time the applied voltage
Inside the system is the sensorless Spindle driver
reaches 0.7V and the VGT. The POR delay is
(Spin), the Voice Coil Motor driver (VCM), the
programmable changing the value of a capacitor.
Head load/unload predrivers, power sequencing,
The VCM driver is driven via a D/A and it can be
actuator over-velocity detection, actuator retrac-
enabled through the VCM driver register. The
tion and dynamic braking. The architecture of the
VCM driver has a gain capability too. This func-
system is configured to interface directly to an 8
tion is to be accomplished by switching the sense
bit, parallel, microprocessor bus.
resistor used such that the current sensing feed-
During the application of power to the system
back in the VCM driver has more information and
(power-on), the output drivers are held in a disabled
therefore results in lower deadband, offset cur-
state until the applied voltage reaches the Voltage
rent, and gain error. An actuator over velocity
Good Threshold (VGT). During this period of time
sensing circuit is incorporated in the system,
the output drivers are disabled, the internal register
which is accomplished by measuring BEMF volt-
are set to predetermined states, and the Power On
age and comparing to a threshold.
9/15
L6245
The head load /unload mechanisms are just buff-
ers for driving external power transistors. Control-
led internally by Bit 3 and Bit 4 of the VCM Driver
Register, each output has a current surcing capa-
bility of 10mA.
A Step-up Converter is used to generate a 15V
internal supply to drive the upper DMOSs and a
regulated 11.6V internal supply to power internal
circuits which have voltage head room problem,
as well as to drive the lower DMOSs.
The Sensorless Spindle Driver function can be
accessed from the microprocessor over the data
bus to the Spin Register and Spin D/A. The Spin
D/A is in Binary format. The operation of the Spin-
dle system is controlled entirely by the microproc-
essor from start-up to speed regulaton. The spin
system is accessible by selecting the Spin Control
Register with the address 011 on the 3 bit ad-
dress bus and has the following functions:
A Low Voltage Detector (LVD) is incorporated to
sense a severely low value of applied voltage so
as to shunt-down the VCM and Spindle drivers.
The LVD is activated when the applied voltage
drops below 4.3V (+/-0.1V). When a voltage drop
is sensed, the LVD:
1. asserts POR, which resets the internal register ;
2. retracts the actuator ;
1)Enable (Bit 0): high to enable the spin sys-
tem, while a low asserts braking of the
spindle motor (if VCR enable is low.)
2)Sense amplifier gain (Bit 1): high implies
high current mode which is equivalent to
low sense amp gain, while a low selects
3. applies the dynamic brake.
When a severe low value of applied voltage is
sensed, the motor control system goes into reset
mode and also asserts the POR line to reset
other circuits. The sub-circuit which get affected
by the reset mode in the motor control system are
the Spin Control Register, the VCM Driver Regis-
ter, the Spindle D/A and the VCM D/A. This effec-
tively disables the spin driver, VCM driver, head
load/unload driver and initializes the D/A’s at zero
output command value.
An Over Velocity Detector circuit is integrated to
sense when head arms are moving at a speed
which could cause a damaging condition. When
an over velocity condition is detected sensing the
actuator BEMF, the actuator driver is shut off and
held off until the microprocessor has detected this
condition and then resets the error and retries the
access.
low current mode
gain.
or high sense amp
3)Unipolar/Bipolar (Bit 2): High selects the
Unipolar driving mode.
4)Run/Search Mode (Bit 3): high selects the
run mode whereby the Hall synthesizer
output gives speed information while a low
asserts the search mode whereby the se-
quencer is under µP control (stepper func-
tion).
5)Reset State (Bit 4): a low level resets the
commutation state sequencer.
6)Incremental state (Bit 5): toggling of the bit
increments the sequencer to drive the
output stage when search mode is se-
lected.
The microprocessor has the possibility to put the
device in sleep mode, which is asserted when
both the VCM and Spindle drivers are disabled
through the internal registers (Enable VCM and
Enable Spindle). Under this condition, only the
POR circuit is kept ”alive”, thus power consump-
tion is kept at minimal. Before sleep mode is acti-
vated, the microprocessor must move the actua-
tor to the unload zone, unload the recording
heads, and apply dynamic braking.
All bits of all the registers are readable by the mi-
croprocessor interface. Also there are certain bits
of the internal registers which are writable as de-
fined in the Register Definition Tables (Tables 1 -
7).
7)Linear/PWM (Bit 6): high selects linear
mode of driving for current (speed) regu-
lation while a low sets to PWM mode used
during start-up.
Start-up current limiting is accomplished by the
output of the microprocessor commanded D/A
value. Jammed or stuck rotor detection is also
done as part of the microprocessor algorithm. In-
tegrated diode are present in the power bridge for
BEMF rectification. This rectified voltage is used
to retract the actuator and unload or latch the
head assembly.
A conventional Bandgap is used to generate in-
ternal biasing for the device as well as the refer-
ence voltage for the D/A converters.
An internal register monitors the internal work of
the system and latches certain error condition that
are detected.
10/15
L6245
REGISTER DEFINITION and 3bit Address Code
Table 5: Spin D/A Register (A.C. 101)
Table 1: Status Register (A.C. 001)
POR Initial
Bit
Name
Value
POR Initial
Bit
Name
7
6
5
4
3
2
1
0
Most Significant Bit
0
0
0
0
0
0
0
0
Value
7
6
5
4
3
2
1
0
NC
NC
NC
NC
REVERSE SPIN
OVER TEMP.
SPIN SENSE
1
1
0
1
Least Significant Bit
OVER VEL SET
Table 6: Interrupt Mask Register (A.C. 110)
Table 2: VCM Driver Register (A.C. 010)
POR Initial
Value
Bit
Name
POR Initial
Value
Bit
Name
7
6
5
4
3
2
1
0
NC
NC
NC
NC
NC
7
6
5
4
3
2
1
0
NC
NC
NC
UNLOAD HD
LOAD HD
ENABLE ISENSE
HIGH GAIN VCM
ENABLE VCM
0
0
0
0
0
MASK REV Spin
MASK OVER TEMPERROR
MASK OVER VEL ERROR
0
0
0
Table 7: Phase Delay Register (A.C. 111)
Table 3: Spin Control Register (A.C. 011)
POR Initial
Value
Bit
Name
POR Initial
Value
Bit
Name
7
6
5
4
3
2
1
0
NC
NC
NC
NC
7
6
5
4
3
2
1
0
NC
0
0
0
0
0
0
0
0
LINEAR/PWM
INCREMENT STATE
RESET STATE
RUN/SEARCH
UNI/BI
HIGH GAIN SPIN
ENABLE Spin
Most Significant Bit
0
0
0
0
Least Significant Bit
SYSTEM BUS DESCRIPTION
The system bus is designed as a data acknow-
ledge handshanking bus. At the beginning of the
bus cycle the address and chip select are de-
coded transparently and qualified with read or
write going low. On a read operation, data must
not be driven for 5nsec after read goes low to al-
low the bus to clear. Once data is driven, data ac-
knowledge is driven low to notify the processor
that data is on the bus and ready to be read. The
processor reads the data and responds by raising
read. This is an indication that the processor has
compleated the read and cycle is complete. Data
acknowledge and data must go to high im-
pedence within 20ns to clear the bus for the next
Table 4: VCM D/A Register (A.C. 100)
POR Initial
Value
Bit
Name
7
6
5
4
3
2
1
0
Most Significant Bit
0
0
0
0
0
0
0
0
Least Significant Bit
11/15
L6245
cycle. On a write operation, following write going
low and whatever setup time required to latch
data, data acknwledge is driven low. This notifies
the processor that the cycle can end. This proces-
sor responds by raising write, indicating the end
of the cycle. Data acknowledge must go to high
impedance within 20nsec to clear the bus for the
next cycle.
can take as much time as it needs to drive data
onto the bus, then drive DTACK low. Likewise,
the peripheral can wait as long as it needs to set
up data and latch it (or set up data if WR is used
to latch), then drive DTACK low. However, per-
formance is an issue, so even though this control
has been given to the peripheral, it must not be
abused. All delays are minimized to assure opti-
mum system speed, infact the bus can be driven
synchronously (E.G. has regarding DTACK) when
procesor clocks below 12MHz are used.
This handshaking design allows a peripheral to
control the length of the bus cycle. The peripheral
Figure 1: System Bus Timing (see Table 8)
Table 8: System Bus Timing
Symbol
Description
TAS
Address Setup Time (non MUX bus; (MUX bus)
TCS
TASW
System Select to Address Strobe
Address Strobe Width
Address Strobe to RD
RD to Data Driven
TASRD
TRDDV
TRDDH
TRDCS
TDVDT
TDTRD
TRDDT
TASWR
TDVWR
TWRDTL
TDTWR
TWRCS
TWRDT
TWRDH
Read Data Hold
RD High to CS High
Data Valid to DTACK
DTACK to RD High
RD High to DTACH High
Address Strobe to WR
Write Data Valid to WR
WR to DTACK
DTACK to WR High
WR High to CS High
WR High to DTACK High
Write Data Hold
12/15
L6245
THERMAL CHARACTERISTICS
Fig. 9 shows the increase of the Rth j-amb when
the Dissipated Power decreases.
Practically, very useful information is the change
of the thermal resistance (Thermal Impedance)
versus a single pulse of power width or versus the
time the dissipation begins.
On the application, the L6245 must be soldered
on a PCB system. The Traks Area, depending on
the lenght and the width of each track, must be
between 2 to 10 square mm. An area of 10 mm2
can give a typ. Thermal Resistance Junction-to-
Ambient value of 85°C/W (See Fig. 2): this value
refer3 to a Total Power Dissipated Power of 1W.
Fig. 4 shows this Thermal Impedancetrend.
Figure 3: Typical Junction-to-Ambient Thermal
Resistance vs. Total Dissipated
Power. (L6245 mounted on a typical
PCB)
Figure 2: Typical Rth j-amb vs. Tracks Area on PCB
Figure 4: Typical Transient Thermal Impedance
vs. Time or Pulse Width. (L6245
mounted on a typical PCB)
13/15
L6245
PQFP64 PACKAGE MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
TYP.
MAX.
MIN.
MAX.
A
A1
A2
B
3.40
0.134
0.25
2.55
0.010
0.100
0.0118
0.005
0.667
0.547
2.80
3.05
0.45
0.110
0.120
0.0177
0.009
0.687
0.555
0.30
C
0.13
0.23
D
16.95
13.90
17.20
14.00
12.00
0.80
17.45
14.10
0.677
0.551
0.472
0.0315
0.677
0.551
0.472
D1
D3
e
E
16.95
13.90
17.20
14.00
12.00
17.45
14.10
0.667
0.547
0.687
0.555
E1
E3
K
0°(min.), 7°(max.)
L
0.65
0.80
1.60
0.95
0.026
0.0315
0.063
0.0374
L1
D
D1
D3
A
A2
A1
48
33
49
32
0.10mm
Seating Plane
17
64
1
16
C
e
K
PQFP64
14/15
L6245
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications men-
tioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without ex-
press written approval of SGS-THOMSON Microelectronics.
1994 SGS-THOMSON Microelectronics - All RightsReserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
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15/15
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