L6393D [STMICROELECTRONICS]
Half-bridge gate driver; 半桥栅极驱动器
| 型号： | L6393D |
| 厂家： | 
ST |
| 描述： | Half-bridge gate driver |
| 文件： | 总20页 (文件大小：462K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L6393
Half-bridge gate driver
Preliminary Data
Features
■ High voltage rail up to 600 V
■ dV/dt immunity ꢀ0 V/nsec in full temperature
range
■ Driver current capability:
– 270 mA source,
– 430 mA sink
SO-14
DIP-14
■ Switching times 7ꢀ/3ꢀ nsec rise/fall with 1 nF
load
■ 3.3 V, ꢀ V CMOS/TTL inputs comparators with
hysteresys
■ Integrated bootstrap diode
■ Uncommitted comparator
■ Adjustable dead-time
Description
The L6393 is a high-voltage device manufactured
with the BCD "OFF-LINE" technology. It has a
monolithic half-bridge gate driver for N-channel
Power MOSFET or IGBT.
■ Compact and simplified layout
■ Bill of material reduction
■ Flexible, easy and fast design
The high side (floating) section is designed to
stand a voltage rail up to 600 V.
The logic inputs are CMOS/TTL compatible down
to 3.3 V for easy of interfacing µC/DSP.
Application
Motor driver for home appliances, factory
automation, industrial drives and fans. HID
ballasts, power supply units.
The IC embeds an uncommited comparator
available for protections against over-current,
over-temperature, etc.
Table 1.
Device summary
Order codes
Package
Packaging
L6393
L6393D
DIP-14
SO-14
SO-14
Tube
Tube
L6393D013TR
Tape and reel
March 2008
Rev 2
1/20
This is preliminary information on a new product now in development or undergoing evaluation.
Details are subject to change without notice.
www.st.com
20
Contents
L6393
Contents
1
2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
4
Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1
4.2
4.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
ꢀ.1
ꢀ.2
AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6
7
8
Waveforms definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8.1
CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
10
2/20
L6393
Block diagram
1
Block diagram
Figure 1.
Block diagram
BOOTSTRAP DRIVER
FLOATING STRUCTURE
14
4
VCC
BOOT
from LVG
UV
DETECTION
UV
DETECTION
HVG
DRIVER
S
R
13
1
LEVEL
SHIFTER
HVG
PHASE
LOGIC
12
OUT
SHOOT
THROUGH
PREVENTION
3
BRAKE
VCC
LVG
DRIVER
LVG
10
2
SD
6
5V
10
CPOUT
9
COMPARATOR
+
CP+
-
CP-
8
DEAD
TIME
5
DT
7
GND
3/20
Pin connection
L6393
2
Pin connection
Figure 2.
Pin connection (top view)
PHASE
14
13
12
11
10
9
1
2
3
4
5
6
7
BOOT
HVG
OUT
NC
SD
BRAKE
VCC
DT
LVG
CP+
CPOUT
GND
CP-
8
2.1
Pin description
Table 2.
Pin N#
Pin description
Pin name
Type
Function
1
2
PHASE
SD (1)
BRAKE
VCC
I
I
Driver logic input (active high)
Shut down input (active low)
Driver logic input (active low)
Lower section supply voltage
Dead time setting
3
I
4
P
I
ꢀ
DT
6
CPOUT
GND
O
P
I
Comparator output (open drain)
Ground
7
8
CP-
Comparator negative input
Comparator positive input
Low side driver output
9
CP+
I
10
11
12
13
14
LVG (1)
O
NC
Not connected
OUT
P
O
P
High side (floating) common voltage
High side driver output
HVG (1)
BOOT
Bootstrapped supply voltage
1. The circuit guarantees less than 1 V on the LVG and HVG pins (@ Isink = 10 mA), with VCC > 3 V. This
allows omitting the "bleeder" resistor connected between the gate and the source of the external MOSFET
normally used to hold the pin low; the gate driver assures low impedance also in SD condition.
4/20
L6393
Truth table
3
Truth table
Table 3.
Truth table
INPUTS
PHASE
OUTPUTS
SD
BRAKE
LVG
HVG
L
H
H
H
H
X
L
X
L
L
H
H
H
L
L
L
L
L
H
L
H
L
H
H
H
Note:
X: don’t care
In the L6393 IC the two input signals PHASE and BRAKE are fed into an AND logic port and
the resulting signal is in phase with the high side output HVG and in opposition of phase with
the low side output LVG. This means that if BRAKE is kept to high level, the PHASE signal
drives the half-bridge in phase with the HVG output and in opposition of phase with the LVG
output. If BRAKE is set to low level the low side output LVG is always ON and the high side
output HVG is always OFF, whatever the PHASE signal. This kind of logic interface provides
the possibility to control the power stages using the PHASE signal to select the current
direction in the bridge and the BRAKE signal to perform current slow decay on the low sides.
From the point of view of the logic operations the two signals PHASE and BRAKE are
completely equivalent, that means the two signals can be exchanged without any change in
the behavior on the resulting output signals (see the Block Diagram in Fig.1).
Note: the dead time between the turn OFF of one power switch and the turn ON of the other
power switch is defined by the resistor connected between DT pin and the ground.
ꢀ/20
Electrical data
L6393
4
Electrical data
4.1
Absolute maximum ratings
Table 4.
Symbol
Absolute maximum rating
Parameter
Value
Unit
Vout
Vcc
Output voltage
Vboot - 21 to Vboot + 0.3
- 0.3 to + 21
V
V
V
V
V
Supply voltage
Vcp-
Vcp+
Vboot
Comparator negative input voltage
Comparator positive input voltage
Floating supply voltage
-0.3 to VCC + 0.3
-0.3 to VCC + 0.3
VCC - 0.3 to 620
High side gate output voltage
output voltage
Vhvg
Vout - 0.3 to Vboot + 0.3
-0.3 to Vcc +0.3
V
V
High side gate output voltage
output voltage
VIvg
Vi
Logic input voltage
-0.3 to 1ꢀ
-0.3 to 1ꢀ
ꢀ0
V
V
Vcpout Open drain voltage
dVout/dt Allowed output slew rate
V/ns
mW
°C
Ptot
TJ
Total power dissipation (TA = 8ꢀ °C)
TBD
Junction temperature
Storage temperature
1ꢀ0
Tstg
-ꢀ0 to 1ꢀ0
°C
Note:
ESD immunity for pins 12, 13 and 14 is guaranteed up to V (Human Body Model)
4.2
Thermal data
Table 5.
Symbol
Thermal data
Parameter
SO-14
DIP-14
Unit
Rth(JA) Thermal resistance junction to ambient max.
16ꢀ
100
°C/W
6/20
L6393
Electrical data
4.3
Recommended operating conditions
Table 6.
Recommended operating conditions
Parameter Test condition
Symbol Pin
Min
Max
Unit
Vout
12 Output voltage (1)
ꢀ80
V
V
(2)
VBS
14 Floating supply voltage (1)
TBD
TBD
HVG, LVG load
CL = 1 nF
fsw
Switching frequency
800
kHz
Vcc
Tj
4
Supply Voltage
TBD
40
TBD
12ꢀ
V
Junction Temperature
°C
1. If the condition TBD V < Vboot - Vout < TBD V and Vboot < TBD V are guaranteed, Vout can range from TBD
V to ꢀ80 V
2. VBS = Vboot -Vout
7/20
Electrical characteristics
L6393
5
Electrical characteristics
5.1
AC operation
Table 7.
AC operation electrical characteristics (V = 15 V, T = +25 °C)
CC J
Symbol Pin
Parameter
Test condition
Min
Typ
Max
Unit
AC operation
High/low side driver turn-
on propagation delay
1,3
ton
12ꢀ
12ꢀ
ns
ns
Vout = 0 V
Vboot = Vcc
CL = 1 nF
vs
10,
High/low side driver turn-
off propagation delay
toff
13
Vi = 0 to 3.3 V
2 vs
10,
13
Shut down to high/low
side propagation delay
see Figure 3 on page 9
tsd
12ꢀ
ns
ns
Delay matching, HS & LS
turn-ON/OFF
MT
40
R
dt = 0, CL = 1 nF, CDT = 100 nF
0.1ꢀ
0.ꢀ
1.ꢀ
2.8
µs
µs
µs
µs
Rdt = 37 kΩ, CL = 1 nF, CDT = 100 nF
Rdt = 136 kΩ, CL = 1 nF, CDT = 100 nF
Rdt = 260 kΩ, CL = 1 nF, CDT = 100 nF
dt
ꢀ
Dead time setting range
Matching dead time
Rdt = 0 Ω; CL = 1 nF; CDT = 100 nF
Rdt = 37 kΩ;CL = 1 nF;CDT = 100 nF
Rd = 136 kΩ;CL = 1 nF;CDT = 100 nF
Rdt = 260 kΩ;CL = 1 nF;CDT = 100 nF
60
ns
ns
ns
ns
TBD
TBD
TBD
MDT
tr
tf
Rise time
Fall time
CL = 1000 pF
CL = 1000 pF
7ꢀ
3ꢀ
ns
ns
10,
13
8/20
L6393
Electrical characteristics
Figure 3.
Timing
50%
50%
Logic Input
(PHASE or BRAKE)
tr
tf
90%
90%
10%
10%
HVG
ton
toff
50%
50%
Logic Input
(PHASE or BRAKE)
tf
tr
90%
90%
10%
10%
ton
LVG
toff
50%
50%
SD
tr
tf
90%
90%
10%
10%
LVG/HVG
ton
toff
9/20
Electrical characteristics
L6393
5.2
DC operation
Table 8.
Symbol
DC opereation electrical characteristics (V = 15 V; T = +25 °C)
CC J
Pin
Parameter
Test condition
Min
Typ
Max
Unit
Low supply voltage section
Vcc_hys
Vcc_thON
Vcc_thOFF
Vcc UV hysteresis
600
1ꢀ00
9.ꢀ
mV
V
Vcc UV Turn ON threshold
Vcc UV Turn OFF threshold
8.0
V
VCC = 8 V
SD = ꢀ V; PHASE and
BRAKE = GND;
Undervoltage quiescent
supply current
Iqccu
110
600
1ꢀ0
µA
µA
4
RDT = 0 Ω;
CP + = GND; CP - = 0.ꢀ V
VCC = 1ꢀ V
SD = ꢀ V; PHASE and
BRAKE = GND;
Iqcc
Quiescent current
1000
RDT = 0 Ω;
CP + = GND; CP - = 0.ꢀ V
Bootstrapped supply voltage section
VBS_hys
V
BS UV hysteresis
600
1000
9.1
mV
V
VBS_thON
VBS UV turn ON Threshold
VBS UV turn OFF
Threshold
VBS_thOFF
8.1
V
VBS = 7 V
SD = ꢀ V; PHASE and
BRAKE = ꢀ V;
Undervoltage Vboot
quiescent current
IQBSU
60
110
µA
14
RDT = 0 Ω;
CP + = GND; CP - = 0.ꢀ V
VBS = 1ꢀ V
SD = ꢀ V; PHASE and
BRAKE = ꢀ V;
IQBS
Vboot quiescent current
140
120
210
10
µA
RDT = 0 Ω;
CP + = GND; CP - = 0.ꢀ V
High voltage leakage
current
ILK
Vhvg = Vout = Vboot = 600 V
µA
Bootstrap driver on
resistance (1)
Rdson
LVG ON
Ω
10/20
L6393
Electrical characteristics
Table 8.
Symbol
DC opereation electrical characteristics (V = 15 V; T = +25 °C) (continued)
CC J
Pin
Parameter
Test condition
Min
Typ
Max
Unit
Driving buffers section
High/low side source short
circuit current
Iso
Isi
VIN = Vih (tp < 10 µs)
270
430
mA
mA
10, 13
High/low side sink short
circuit current
VIN = Vil (tp < 10 µs)
Logic inputs
Low level logic threshold
voltage
Vil
0.83
V
1, 2, 3
High level logic threshold
voltage
Vih
2.21
V
PHASE logic “1” input bias
current
IPHASEh
IPHASEl
IBRAKEh
IBRAKEl
ISDh
PHASE = 1ꢀ V
PHASE = 0 V
BRAKE = 1ꢀ V
BRAKE = 0 V
SD = 1ꢀ V
17ꢀ
17ꢀ
30
260
1
µA
µA
µA
µA
µA
µA
1
3
2
PHASE logic “0” input bias
current
BRAKE logic “1” input bias
current
260
1
BRAKE logic “0” input bias
current
SD logic “1” input bias
current
100
1
SD logic “0” input bias
current
ISDl
SD = 0 V
1. RDSon is tested in the following way:
DSon = [(VCC - VCBOOT1) - (VCC - VCBOOT2)] / [I1(VCC,VCBOOT1) - I2(VCC,VCBOOT2)]
where I1 is pin 14 current when VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2
R
.
Table 9.
Sense comparator
Symbol
Pin
Parameter
Test conditions
Min
Typ
Max
Unit
Vio
Iib
Input offset voltage
Input bias current
10
TBD
1
mV
8, 9
µA
Open drain low level
Output voltage
Vol
6
6
Iod = - 3 mA
0.ꢀ
V
CPOUT pulled to ꢀ V
through 100kΩ resistor
td_comp
SR
Comparator delay
Slew rate
110
210
ns
CL = 180 nF, Rpu = ꢀ kΩ
TBD
V/µs
11/20
Waveforms definition
L6393
6
Waveforms definition
Figure 4.
Dead time waveform definition
PHASE
BRAKE
LVG
DT
DT
DT
DT
HVG
12/20
L6393
Typical application diagram
7
Typical application diagram
Figure 5.
Application diagram
BOOTSTRAP DRIVER
FLOATING STRUCTURE
14
VCC
BOOT
4
from LVG
UV
DETECTION
UV
DETECTION
Cboot
H.V.
HVG
DRIVER
S
R
HVG
13
1
LEVEL
SHIFTER
PHASE
BRAKE
LOGIC
SHOOT
THROUGH
PREVENTION
3
12
10
OUT
LVG
TO LOAD
VCC
LVG
DRIVER
SD
2
6
CPOUT
5V
10
9
COMPARATOR
CP+
CP-
+
-
8
DT
DEAD
TIME
5
7
GND
13/20
Bootstrap driver
L6393
8
Bootstrap driver
A bootstrap circuitry is needed to supply the high voltage section. This function is normally
accomplished by a high voltage fast recovery diode (Figure 6.a). In the L6393 a patented
integrated structure replaces the external diode. It is realized by a high voltage DMOS,
driven synchronously with the low side driver (LVG), with diode in series, as shown in Figure
6.b.
An internal charge pump (Figure 6.b) provides the DMOS driving voltage.
The diode connected in series to the DMOS has been added to avoid undesirable turn on of
it.
8.1
CBOOT selection and charging
To choose the proper CBOOT value the external MOS can be seen as an equivalent
capacitor. This capacitor CEXT is related to the MOS total gate charge:
Qgate
CEXT = -------------
Vgate
The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss.
It has to be:
C
>>> C
EXT
BOOT
e.g.: if Qgate is 30nC and Vgate is 10 V, CEXT is 3 nF. With CBOOT = 100 nF the drop would be
300 mV.
If HVG has to be supplied for a long time, the CBOOT selection has to take into account also
the leakage and quiescent losses.
e.g.: HVG steady state consumption is lower than 200 µA, so if HVG TON is ꢀ ms, CBOOT has
to supply 1 µC to CEXT. This charge on a 1 µF capacitor means a voltage drop of 1 V.
The internal bootstrap driver gives a great advantage: the external fast recovery diode can
be avoided (it usually has great leakage current).
This structure can work only if VOUT is close to GND (or lower) and in the meanwhile the
LVG is on. The charging time (Tcharge ) of the CBOOT is the time in which both conditions are
fulfilled and it has to be long enough to charge the capacitor.
The bootstrap driver introduces a voltage drop due to the DMOS RDSon (typical value:
120 Ω). At low frequency this drop can be neglected. Anyway increasing the frequency it
must be taken in to account.
The following equation is useful to compute the drop on the bootstrap DMOS:
Qgate
------------------
Rdson
Vdrop = IchargeRdson → Vdrop
=
Tcharge
14/20
L6393
Bootstrap driver
where Qgate is the gate charge of the external power MOS, RDSon is the on resistance of the
bootstrap DMOS, and Tcharge is the charging time of the bootstrap capacitor.
For example: using a power MOS with a total gate charge of 30 nC the drop on the
bootstrap DMOS is about 1 V, if the Tcharge is ꢀ µs. In fact:
30nC
ꢀµs
--------------
⋅ 120Ω ∼ 0.7V
Vdrop
=
V
drop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop
is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode
can be used.
Figure 6.
Bootstrap driver
DBOOT
VS
BOOT
H.V.
BOOT
H.V.
VS
HVG
LVG
HVG
LVG
CBOOT
CBOOT
VOUT
VOUT
TO LOAD
TO LOAD
D99IN1067
a
b
1ꢀ/20
Package mechanical data
L6393
9
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
16/20
L6393
Package mechanical data
DIP-14 mechanical data and package dimensions
Figure 7.
mm
inch
DIM.
OUTLINE AND
MECHANICAL DATA
MIN. TYP. MAX. MIN. TYP. MAX.
a1
B
b
0.ꢀ1
0.020
1.39
1.6ꢀ 0.0ꢀꢀ
0.06ꢀ
0.ꢀ
0.020
0.010
b1
D
E
e
0.2ꢀ
20
0.787
8.ꢀ
2.ꢀ4
1ꢀ.24
0.33ꢀ
0.100
0.600
e3
F
7.1
ꢀ.1
0.280
I
0.201
L
3.3
0.130
DIP-14
Z
1.27
2.ꢀ4 0.0ꢀ0
0.100
17/20
Package mechanical data
Figure 8. SO-14 mechanical data and package dimensions
L6393
mm
inch
DIM.
OUTLINE AND
MECHANICAL DATA
MIN. TYP. MAX. MIN.
TYP. MAX.
0.069
A
A1
A2
B
1.3ꢀ
0.10
1.10
0.33
0.19
8.ꢀꢀ
1.7ꢀ 0.0ꢀ3
0.30 0.004
1.6ꢀ 0.043
0.ꢀ1 0.013
0.2ꢀ 0.007
8.7ꢀ 0.337
0.012
0.06ꢀ
0.020
C
0.01
(1)
0.344
D
E
e
3.80
4.0
0.1ꢀ0
0.1ꢀ7
0.0ꢀ0
1.27
H
ꢀ.8
6.20 0.228
0.ꢀ0 0.01
0.244
h
0.2ꢀ
0.40
0.02
L
1.27 0.016
0° (min.), 8° (max.)
0.10
0.0ꢀ0
k
ddd
0.004
SO-14
(1) “D” dimension does not include mold flash, protusions or gate
burrs. Mold flash, protusions or gate burrs shall not exceed
0.1ꢀmm per side.
0016019 D
18/20
L6393
Revision history
10
Revision history
Table 10. Document revision history
Date
Revision
Changes
03-Mar-2008
18-Mar-2008
1
2
Initial release
Cover page updated
19/20
L6393
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2008 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
20/20
相关型号：
©2020 ICPDF网 联系我们和版权申明