L6615N [STMICROELECTRONICS]
HIGH/LOW SIDE LOAD SHARE CONTROLLER; 高/低侧负载分享控制器
| 型号： | L6615N |
| 厂家： | 
ST |
| 描述： | HIGH/LOW SIDE LOAD SHARE CONTROLLER |
| 文件： | 总20页 (文件大小：393K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L6615
HIGH/LOW SIDE LOAD SHARE CONTROLLER
■ SSI SPECS COMPLIANT
BCD TECHNOLOGY
■ HIGH/LOW SIDE CURRENT SENSING
■ FULLY COMPATIBLE WITH REMOTE
OUTPUT VOLTAGE SENSING
■ FULL DIFFERENTIAL LOW OFFSET
CURRENT SENSE
■ 2.7V TO 22V V OPERATING RANGE
CC
■ 32kΩ SHARE SENSE AMPLIFIER INPUT
IMPEDANCE
■ HYSTERETIC UVLO
DIP8
SO8
ORDERING NUMBERS:
L6615N
L6615D
L6615DTR(T & Reel)
APPLICATION
■ DISTRIBUTED POWER SYSTEMS
■ HIGH DENSITY DC-DC CONVERTERS
■ (N+1) REDUNDANT SYSTEMS, N UP TO 20
■ SMPS FOR (WEB) SERVERS
achieve load sharing of paralleled and indepen-
dent power supply modules in distributed power
systems, by adding only few external components.
Current sharing is achieved through a single wire
connection (share bus) common to all of the paral-
leled modules.
DESCRIPTION
This controller IC is specifically designed to
TYPICAL APPLICATION DIAGRAM
RSENSE
( )
*
+OUT
+OUT_S
RADJ
-OUT_S
-OUT
RG1
RG2
PS #1
1
2
GND
CS-
VCC
CGA
8
7
CS+
ADJ
3
4
SHARE
COMP
6
5
L6615
CC
RC
RCGA
RSENSE
( )
*
+OUT
+OUT_S
+OUT
RADJ
-OUT_S
-OUT
LOAD
GND
PS #N
RG1
RG2
SHARE BUS
1
2
GND
CS-
VCC
CGA
8
7
6
5
CS+
ADJ
3
4
SHARE
COMP
( ) OR-ing FET can
be used to reduce
power dissipation
RCGA
CC
RC
*
L6615
July 2003
1/20
L6615
DESCRIPTION (continued)
Load sharing is a technique used in all the systems in which the load requires low voltage, high current
and/or redundancy; for this reason a modular power system is necessary in which two or more power sup-
plies or DC-DC converters are paralleled.
The device is able to perform both high side and low side current sensing, that is the sense current resistor
can be placed either in series to the power supplies output or on the ground return.
The L6615 then drives the share bus to a voltage proportional to the output current of the master that is
to the highest amongst the output currents delivered by the paralleled power supplies.
The share bus dynamics is independent of the power supply output voltage and is clamped only by the
device supply voltage (V ).
CC
The output voltage of the other paralleled power supplies (slaves) is then trimmed by the ADJ pin so that
they can support their amount of load current. The slave power supplies work as current-controlled current
sources.
Sharing the output currents is useful for equalizing also the thermal stress of the different modules and
providing an advantage in term of reliability.
Moreover the paralleled supplies architecture allows achieving redundancy; the failure of one of the mod-
ules can be tolerated until the capability of the remaining power supplies is enough to provide the required
load current.
PIN DESCRIPTION
N°
1
Pin
GND
CS-
Function
Ground.
2
Input of current sense amplifier; it is connected to the negative side of the sense resistor through
a resistor (R ).
G2
3
4
CS+
ADJ
Input of current sense amplifier. A resistor (R , of the same value as R ) is placed between
G1 G2
this pin and the positive side of the sense resistor: its value defines the transconductance gain
between I and V
.
SENSE
CGA
Output of Adjust amplifier; it is connected to both the load (through a resistor R
) and to the
ADJ
positive remote sense pin of the power system. This pin is an open collector diverting (from the
feedback path) a current proportional to the difference between the current supplied to the load
by the relevant power supply and the current supplied by the master.
5
6
COMP Output of the current sharing (transconductance) error amplifier and input of ADJ amplifier.
Typically, a compensation network is placed between this pin and ground. The maximum voltage
is internally clamped to 1.5V (typ.)
SH
Share bus pin. During the power supply slave operation, this pin acts as positive input from
share bus. During power supply master operation, it drives the share bus to a voltage
proportional to the load current.
The share bus connects the SH pins of all the paralleled modules. A capacitor between this pin
and GND could be useful to reduce the noise present on the share bus.
7
8
CGA
Current Gain Adjust pin; current sense amplifier output. A resistor connected between this pin
and ground defines the maximum voltage on the share bus and sets the gain of the current
sharing system.
V
CC
Supply voltage of the IC.
2/20
L6615
ABSOLUTE MAXIMUM RATINGS
Symbol
Pin
Parameter
Value
selflimit
10
Unit
V
V
CC
8
Supply Voltage (*) (I <50mA)
CC
I
+, I
-
Sense pin current
mA
V
CS
CS
V
-, V
, V
,
2, 3, 6, 4, 7
5
-0.3 to V
CC
CS
V
CS+
SH
, V
ADJ CGA
V
Error amplifier output
-0.3 to 1.5
-0.7 to 0.7
V
V
COMP
(V
) - (V
)
Differential input voltage (V + from 0V to 22V)
CS+
CS-
CS
Ptot
Total power dissipation @ Tamb = 70°C
SO8
DIP8
0.45
0.6
W
Tj
Junction temperature range
Storage temperature
-40 to +125
-55 to +150
°C
°C
Tstg
All voltages are with respect to pin 1. Currents are positive into, negative out of the specified terminal.
(*) Maximum package power dissipation limits must be observed
PIN CONNECTION
8
7
6
5
1
2
VCC
GND
CS-
CGA
SH
CS+ 3
4
ADJ
COMP
THERMAL DATA
Symbol
Parameter
MINIDIP
SO8
Unit
R
Thermal Resistance junction to ambient
90
120
°C/W
th j-amb
3/20
L6615
ELECTRICAL CHARACTERISTCS
(Tj = -40 to 85°C, Vcc=12V, V
= 12V, C
= 5nF to GND, R
= 16kΩ, unless otherwise specified;
CGA
ADJ
COMP
V
= I * R
, R = R = 200Ω)
SENSE G1 G2
SENSE
L
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Vcc
V
Operating range
2.7
22
6
V
mA
V
cc
I
cc
Quiescent current
Turn-on voltage
Turn-off voltage
Hysteresis
V
= 1V, V
= 0V
SENSE
5
SH
SH
V
V
= 0.2V, V
= 0V
2.45
2.35
2.60
2.5
100
26
2.75
2.65
CC, ON
SENSE
V
V
CC,OFF
V
mV
V
H
Vz
I
= 20mA
24
CC
CURRENT SENSE AMPLIFIER
V
Input offset voltage
Out high voltage
0.1V ≤ V ≤ 10.0V
-1.5
0.0
1.5
mV
V
OS
SH
V
CGA
V
V
V
= 0.25V
V -2.2
cc
SENSE
I
Short circuit current
= 0V, V = 0.45V
SENSE
-1.5
-2.0
mA
µA
CGAS
CGA
I
Input bias current (high side
sensing)
= 0V, V
=+12V
1.0
B(CS-)
SENSE
CS+
I
Input bias current (low side
sensing)
V
= 0V, V
=0V
-1.0
µA
B(CS+)
SENSE
CS+
CMR Common mode dynamics range
V
V
V
0
V
V
V
CS-, CS+
CC
VTH
Switchover threshold low side to
high side sensing
1.6
CS+
CS+
SW
Switchover hysteresis
0.16
V
H
SHARE DRIVE AMPLIFIER
HV
SH high output voltage
SH low output voltage
V
V
= 250mV, I = -1mA
V -2.2
cc
V
SH
SENSE
SH
LV
45
mV
SH
= 0mV, R = 200Ω
CGA
SH
High side sensing mirror accuracy
(*)
±1
±1
±5
±5
%
%
α(+)
α(-)
Low side sensing mirror accuracy
(*)
V
Load regulation
Short circuit current
Slew rate
-1.0mA ≤ I
≤ -4mA
20
-8
mV
mA
SH, load
SDA(OUT)
I
SC
V
= 0V, V = 25mV
SENSE
-20
0.8
-13.5
1.5
SH
SR
V
R
= -10mV to 90mV step,
= 200Ω to GND
2.2
V/µs
SENSE
SH
V
R
= 90mV to –10mV step,
= 200Ω to GND
2
3
4
V/µs
kΩ
SENSE
SH
SHARE SENSE AMPLIFIER
R
Input impedance
22.4
32
41.6
i
ERROR AMPLIFIER
G
Transconductance
Input offset voltage
3
4
5
mS
mV
m
V
os
V
=1V
30
50
70
CGA
4/20
L6615
ELECTRICAL CHARACTERISTCS (continued)
(Tj = -40 to 85°C, Vcc=12V, V = 12V, C
= 5nF to GND, R = 16k
CGA
Ω
, unless otherwise specified;
ADJ
COMP
V
= I * R
, R = R = 200Ω)
G2
SENSE
L
SENSE G1
Parameter
Source current
Symbol
Test Condition
Min.
Typ.
Max.
Unit
I
V
=1.5V, V ≥ 300mV,
SH
-150
-350
-400
µA
OH
COMP
V
=-10mV
SENSE
I
Sink current
V
= 1.5V, V =-10mV
SENSE
100
200
300
µA
OL
COMP
200Ω resistor SH to GND
V
Low voltage
0.05
0.15
1.5
0.25
COMP(L
)
V
Clamp Zener voltage
I = 1mA
Z
V
Z
ADJ AMPLIFIER
I
Max. ADJ output current
Threshold voltage
V
= 1V, V = 0V
SENSE
6.5
60
10
0.7
100
13
mA
V
ADJ
SH
V
R
I
=10µA
T
A
ADJ
Emitter resistor
Guaranteed by design
140
1
Ω
V
Low saturation voltage
I
I
=5mA
=1mA
V
ADJ(MIN)
ADJ
0.4
V
ADJ
VSH
----------------------------------------- – 1 100
RCGA
--------------
=
(*) Mirror accuracy is defined as :
VSENSE
RG
and it represents the accuracy of the transfer between the voltage sensed and the voltage imposed on the
share bus.
BLOCK DIAGRAM
CS-
CS+
3
2
8
6
VCC
ICGA
CURRENT SENSE
AMPLIFIER (CSA)
CGA
7
24V
UVLO
BIAS
R
R
R
R
R
+
_
SH
R
_
+
+
_
SHARE SENSE
AMPLIFIER (SSA)
SHARE DRIVE
AMPLIFIER (SDA)
R
R
+
COMP
5
_
Gm ERROR
AMPLIFIER (E/A)
40 mV
ADJ
4
1.5V
+
_
0.7V
ADJ OUTPUT
AMPLIFIER (AOA)
RA
1
GND
5/20
L6615
Figure 1. Turn-on and turn-off voltage
Figure 4. Max CGA current
VCC(ON), VCC(OFF) [V]
3
ICGA(max) [mA]
2.8
2.6
2.4
2.2
2
2.6
1. 8
2.2
- 50
0
50
100
-50
0
50
100
TJ [
OC]
TJ [OC]
Figure 5. High side/low side sensing
switchover threshold
Figure 2. Supply current vs. supply voltage
ICC [mA]
VTH [V]
1.9
100
10
1
1.7
1.5
1.3
0.1
0.01
- 50
0
50
100
0.1
1
10
100
TJ [
OC]
VCC [V]
Figure 3. Supply current
Figure 6. Max. share bus voltage at no load
ICC [mA]
VSH(LOW) [mV]
4.7
50
45
40
35
30
25
20
15
4.3
3.9
3.5
3.1
2.7
10
- 50
0
50
100
-50
0
50
100
TJ [
OC]
TJ [OC]
6/20
L6615
Figure 7. Share bus input impedance
Figure 8. ADJ maximum current
RI [k
50
]
IAD J[MAX] [mA]
15
45
40
35
30
25
20
13
11
9
7
5
- 50
0
50
100
-50
0
50
100
TJ [OC]
TJ [
OC]
7/20
L6615
APPLICATION INFORMATION
Index
page
1. Introduction
2. Current sense section
8
9
3. Share drive section, error amplifier and adjust amplifier 10
4. Designing with L6615
5. Current sense methods
6. Application ideas
7. Low voltage buses
8. Offset Trimming
10
13
14
15
16
1
INTRODUCTION
Power supply systems are often designed by paralleling converters in order to improve performance and
reliability.
To ensure uniform distribution of stresses, the total load current should be shared appropriately among
the converters.
A typical application is showed in fig. 9 for a series of N paralleled modules (PS#1 to PS#N): each of them
exhibits 4 terminals: two for the power output (+OUT, -OUT) and two for the remote sense signals
(+OUT_S, -OUT_S).
On the power lines are placed the sense resistors R
(for the current sensing) and the OR-ing diodes
SENSE
(to avoid that the failure of one module shorts the load out)
L6615 allows attaining an automatic master-slave current sharing architecture: one L6615 is associated to each
power supply and all these IC's are linked each other through the share bus (referred to the common ground).
This kind of system configuration is preferred to the systems in which a single current sharing controller is
used because of robustness, reliability and flexibility.
To configure a load share controller, few passive components are used. A brief device explanation will
follow with the formulas useful to set these external components.
Figure 9. Typical high side connection
RSENSE
+OUT
+OUT_S
RADJ
-OUT_S
-OUT
PS #1
RG1
RG2
1
2
GND
CS-
VCC
CGA
8
7
CS+
ADJ
3
4
SHARE
COMP
6
5
L6615
CC
RC
RCGA
RSENSE
+OUT
+OUT_S
+OUT
GND
RADJ
-OUT_S
-OUT
LOAD
PS #N
RG1
RG2
SHARE BUS
1
2
GND
CS-
VCC
CGA
8
7
CS+
ADJ
3
4
SHARE
COMP
6
5
RCGA
CC
RC
L6615
8/20
L6615
2
CURRENT SENSE SECTION
A sense resistor is typically used to generate the voltage drop, proportional to the load current, measured
by the CSA (Current Sense Amplifier), whose input pins (pins #2 and #3) are connected across of R
through two identical resistors (RG1 and RG2).
SENSE
The CSA consists of 2 sections (see fig. 10), one responsible for the high side sensing, the other for low
side sensing. An internal comparator activates the relevant section in accordance with the voltage present
at CS+ pin: if this voltage is higher than 1.6V (typ), then the high side sensing section will be activated
(fig10.a) otherwise the low side sensing one will (fig 10.b). For the sake of simplicity we will consider R
=
G1
R
= R .
G2
G
As the voltage drop I
*R
is present at the input of the Sense Amplifier section, its output forces
OUT SENSE
the controlled current mirror to:
– sink current from the CS+ pin in case of high side sensing (neglecting input bias current, no current flows
through CS- pin);
– source current from the CS- pin in case of low side sensing (neglecting input bias current, no current
flows through CS- pin).
The local feedback imposes the same voltage at the current sense input pins, so under closed loop con-
dition V
=VR .
SENSE
G
The current
I
RSENSE
I
CS= ---O----U---T----------------------------
RG
(IC in case of high side, I
in case of low side) is then internally mirrored and sent to the CGA pin caus-
CS-
S+
ing a drop across the R
external resistor: two internal buffers transfer V
signal on the share pin so:
CGA
CGA
V
SNS
--------------
V
=
R
SH
CGA
R
G
Only the L6615 V limits the upper voltage at the CGA and SH pin, independently of the voltage present
CC
at the current sense pins.
In noisy applications, two capacitors of small value (e.g. 1nF) connected between current sense pins and
ground could be useful to clean the signal at the input of the current sense amplifier.
For low voltage buses application, see paragraph 7.
Figure 10. Current sense section
LOAD(-) / GND
PS+
ICS+
CSA
RG
RG
SINK
+
+
CS+
HSA
CS+
HSA
1:1
CONTROLLED
CURRENT
MIRROR
-
VRG
IOUT
-
IOUT
ICGA
CGA
COMPARE
VSENSE
VSENSE
COMPARE
RSENSE
RSENSE
1.6V
1.6V
CONTROLLED
CURRENT
MIRROR
CGA
RCGA
ICGA
VRG
-
RCGA
-
CS-
LSA
1:1
SOURCE
CS-
LSA
+
+
RG
RG
CSA
L6615
ICS-
PS-
LOAD(+)
L6615
a) high side sensing
b) low side sensing
9/20
L6615
3
SHARE DRIVE SECTION, ERROR AMPLIFIER AND ADJUST AMPLIFIER
The gain between the output of CSA (CGA pin) and output of SDA (SH pin) is 1 (typ.) so, for the master
power supply, V
= V ; the voltage on the share bus is imposed by the master.
CGA
SH
In the slave converters, being V
< V
, the diode at the output of SDA (see block
CGA(MASTER)
CGA(SLAVE)
diagram) isolates the output this amplifier from the share bus.
The Share Sense Amplifier (SSA) reads the bus voltage transferring the signal to the non-inverting input
of the error amplifier where it is compared with CGA voltage.
Whenever a controller acts as the master in the system, the voltage difference between the E/A inputs is
zero. To guarantee its output low in such condition, a 40mV offset is inserted in series with the inverting
input.
Instead in the slave converters the input voltage difference is proportional to the difference between the
master load current and the relevant slave load current.
The transconductance E/A converts the ∆V at its inputs in a current equal to
IOUT = GM ∆V
flowing in the compensation network connected between COMP pin and ground.
The E/A output voltage drives the adjust amplifier to sink current from the ADJ pin that is connected to the
output voltage through a small resistor along the sense path. The current sunk by ADJ pin is deviated from
feedback path of the slave power supply that reacts increasing its duty cycle.
In steady state the current sunk by the ADJ pin is proportional to the value of error amplifier output.
4
DESIGNING WITH L6615
The first design step is usually the choice of the sense resistor whose maximum value is limited by power
dissipation; this constraint must be traded off against the precision of L6615 current sensing. In fact a small
sense resistance value lowers the power dissipation but reduces the signal available at the inputs of the
L6615 current sense amplifier.
Once fixed R
then the values for R and R
will be chosen in accordance with the application
GCA
SENSE
G
specs: usually these specs define the share bus voltage (V
) and the number of paralleled power
SH(MAX)
supplies.
Their value must comply with the constraints imposed by the L6615:
Figure 11. Simplified feedback block diagram.
IOUT(2)
IOUT(1)
VOUT
RSENSE
RSENSE
POWER
POWER
ILOAD
ZL
STAGE 1
STAGE 2
SHARE BUS
α * RCGA / RG
α * RCGA / RG
PWM
PWM
CONTROLLER
CONTROLLER
-
-
+
+
Σ
Σ
+
+
GM*ZCOMP(s)*RADJ
RA
+
+
GM*ZCOMP(s)*RADJ
RA
VREF
VREF
Σ
Σ
-
-
(*) K depends on the
feedback divider ratio
K*VOUT (*)
K*VOUT (*)
10/20
L6615
– maximum share bus voltage is internally limited up to 2.2V below L6615 V voltage (pin#8);
CC
– V
represents an upper limit but the designer should select the full scale share bus voltage
SH(MAX)
keeping in mind that every Volt on the share bus will increase the master controller's supply current
by approximately 45µA for each slave unit connected in parallel; this total current, provided by the
master share drive amplifier, must be lower than its minimum output capabilty (8mA) so
R
i(MIN)
-------------------
V
<
8mA
SH(MAX)
N
This condition is not tough to meet in normal applications, as one can easily see by using sensible
values for N (number of paralleled power supplies) and V . For example, with V
SH(MAX)
solving for N, we obtain Nmax=20;
=8V,
SH(MAX)
– maximum share drive amplifier current capability (I
=2mA);
CGA(MAX)
– for safety reasons the following relation must be met:
V
1
2
out
--
R
>
-------------- – 40
10mA
G
in this way no fault will cause I
(or I ) to overcome its absolute maximum ratings.
CS-
CS+
At full load, ∆V
= I
) · R
OUT(MAX
is the maximum voltage drop across the resistor
SENSE(MAX)
SENSE(MAX)
R
(typically few hundreds of millivolt).
SENSE
I
is the maximum current carried by each of the paralleled power supply; in non redundant sys-
OUT(MAX)
tems composed by N power supplies, each of them works at its nominal current, so:
I
LOAD
I
= ---------------
OUT(MAX)
N
This relationship is true also in N+M redundant system, even if under normal condition each power supply
provides I /(N+M).
LOAD
For example in a system composed by two paralleled power supplies 100% redundant (N=M=1), each
module is sized to sustain the entire load current (in normal operation it carries only one half): for this rea-
son the sense resistor must be sized considering the whole load current.
The temperature variation of the sense resistor (hence of its resistance value) has to be taken into ac-
count, so R
is the value at maximum operating temperature to avoid saturating the share bus.
SENSE(MAX)
Once fixed V
culated:
, the ratio R
SENSE(MAX)
/R (gain from the sensing section to the share bus) can be cal-
CGA G
R
V
SH(MAX)
CGA
--------------- = -------------------------------------
R
V
SENSE(MAX)
G
where V
is defined by the application.
SH(MAX)
A small capacitor in parallel to R
is useful to reduce the noise.
CGA
The effect of current sharing feedback loop is to force the voltages of the slave's CGA pins to be equal to
(that is to reduce the voltage difference at the inputs of the L6615 error amplifier). For the sake of
V
SH
simplicity we consider 2 paralleled power supplies (as in fig. 11): under closed loop condition:
R
R
SNS(2)
SNS(1)
---------------------
---------------------
I
R
= I
R
CGA(2)
OUT(1)
CGA(1)
OUT(2)
R
R
G(1)
G(2)
Ideally all the external component and α are matched so:
= I
I
LOAD
I
= ---------------
OUT(2)
OUT(1)
2
Any mismatch will have repercussion on the sharing precision: in particular the maximum difference be-
tween the output currents (sharing error) will be given by the sum of the mismatches amongst the relevant
values.
11/20
L6615
Figure 12. ADJ network
VOUT
RADJ
VOUT
RADJ
IADJ
IADJ
to L6615
ADJ pin
to L6615
ADJ pin
Off the shelf
POWER SUPPLY
R1
E/A
E/A
VREF
b)
R2
VREF
a)
To set the R
value it is necessary to know the tolerance required of the power supply output voltage
ADJ
(V
OUT
±∆V ); the maximum difference between master and slave output voltage is 2*∆V and this amount
O
O
represents the voltage that the L6615 must be able to correct.
Now two different approaches are feasible depending on whether the SMPS (whose output current must
be shared) has to be completely designed or it is an "off the shelf" component and only the current sharing
section must be designed.
In the first case, the adjustment resistor (R
) can be considered as a fraction of the high resistor of the
ADJ
feedback divider R (see fig.12.a): typically the first step consist of fixing the current flowing, under steady
H
state condition, through the feedback divider I ; by choosing the value for R :
FB
2
V
REF
I
= --------------
FB
R
2
we will have:
V
OUT
R
= R + R
=
-------------- – 1
R
2
H
1
ADJ
V
REF
It can be an useful rule of thumb to use R
worst case condition, it will be:
lower than (or equal to) one tenth of R1, considering that, in
ADJ
∆V
OUT
I
= ------------------
ADJ(max)
R
ADJ
This value must not exceed the one indicated in the "Electrical characteristic section" but this is very easy
to meet, as one can easily see by using sensible values for ∆V and R .
OUT
2
In the second case (fig 12.b), the feedback divider has been already designed by the SMPS manufacturer
and it is not possible to modify it: the design of R must be done to make the L6615 able to correct the
ADJ
maximum spread without significantly shifting the SMPS regulation point. A minimum R
value can be
ADJ
found by:
∆V
OUT
R
= -------------------------
ADJ(min)
I
ADJ(max)
where I
is 8mA.
ADJ(max)
Especially for low voltage output buses it is important to avoid adjustment network saturation; the design
must satisfy the following relationship:
V
– R
(I
+ I ) > V
ADJ FB ADJ(MIN)
OUT
ADJ
where V
12/20
can be found in the "Electrical characteristic section" for different I
values.
ADJ
ADJ(MIN)
L6615
The last point is the design of the compensation network Z (s) connected between the COMP pin and
C
ground.
Besides the power supply feedback loop, the current sharing system introduces another, outer loop. To
avoid interaction between them it is important to design the bandwidth of the sharing loop at least one or-
der of magnitude lower than the bandwidth of the power supply loop.
For the total system, the loop gain is:
R
R
ADJ
1
CGA
---------------
-------------
------------------
G
= R
G
Z (s )
A (s)
PWR
LOOP(s)
SENSE
M
C
R
R
R
G
A
LOAD
where
A
(s) is the transfer function of PWM controller and power stage (see fig. 11)
PWR
R
is the equivalent load resistance
LOAD
Typically the compensation network is built by a R-C series.
A resistor in series with C is required to boost the phase margin of the load share loop. The zero is placed
C
at the load share loop crossover frequency, f
.
C(SH)
If f
is the share loop crossover frequency, then:
C(SH)
R
G
R
R
ADJ SENSE
1
CGA
M
------------------------------- ---------------------------- ------------- ---------------------
C
=
A
PWR(f
C
)
C(SH)
2 π f
R
R
R
LOAD
C(SH)
G
A
1
R
= --------------------------------------------
C
2 π f
C
C
C(SH)
5
CURRENT SENSE METHODS
Several are the methods to sense the power supply output current; the simplest one is to use a power
resistor (fig. 13a) but increasing load current could require expensive resistor to support the inherent pow-
er dissipation, imposing the use of several paralleled resistor.
Other methods to sense the output current are showed in fig. 13b and 13c:
1. R
: a power MOS is placed in series to the output and its channel resistance (R
DS(ON)
) is used
DS(ON)
as sense resistor (fig 13a): the L6615 sense pins will be connected, through R resistors to the drain
G
and to the source of the MOS. Besides providing the sense resistor, the FET is used as "ORing" el-
ement: driving properly its gate, it is possible isolate the power supply output from the load (the body
diode is reversed biased so it doesn't conduct).
This is useful whenever features like hot swap or hot plug are required; compared with the well-known
solution using ORing diode, the ORing FET greatly reduces the power dissipation, in particular:
P (DIODE) = VF
I
OUT + RSENSE I2OUT
P(MOS) = RDS(ON) I2OUT
where V is the forward drop across the diode.
F
2. Current transformer: in case of very high load currents, a transformer allows sensing a smaller cur-
rent, obtained through a scaling factor equal to the transformer turn ratio. In this way, the sense re-
sistor power dissipation requirements can be less tight: obviously this is paid with the cost of the
transformer.
In fig. 13c it is showed the simplified output stage of a power supply in forward configuration: through
two current transformers the load current is reproduced in the sensing circuit scaled by a factor N.
R
will read a ripple (at the switching frequency) superimposed on the average current value
SENSE
that doesn't affect the correct behaviour of the current sharing system because its loop gain is de-
signed with a low bandwidth - at least 2 order of magnitude lower than the switching frequency - that
will cut this high frequency.
13/20
L6615
Figure 13. Current sense methods.
CS+
CS-
RG
RG
L6615
L6615
CS+
CS-
CS+
CS-
L6615
RSNS
1:N
1:N
RG
RG
RG
RG
ORing FET
SENSING
CIRCUIT
RSNS
IOUT
IOUT
IOUT
L
O
A
D
L
O
A
D
L
POWER
SUPPLY
POWER
SUPPLY
GATE
CONTROL
O
A
D
a)
b)
c)
6
APPLICATION IDEAS
In fig. 14 is showed a single section of a system in which several DC to DC modules can be paralleled,
typical solution whenever the load requires high current at low voltage; the converter is designed for a step
down configuration using a synchronous rectification controller (for example L6910 [1] or L6911 [2] ST de-
vice).
The L6615 reads the drop across the Rds(ON) of the OR-ing FET and the LM293 drives its gate, pulling
it down whenever a fault condition (e.g. short on the low side) appears.
A charge pump could be necessary to be sure that the ORing FET V is higher than V
(depending
GS
GS(TH)
on the input and output voltage).
Figure 14. 0.9 to 5V DC-Dc converter with Current Sharing and output hot-pluggability
VIN
4
8
LM293
7
6
5
BOOT
UGATE
PHASE
VCC
VOUT
GND
SS
LGATE
PGND
+S_OUT
SH
CS-
CS+
Vcc
SH
ADJ
GND
COMP
L6910
L6615
VIN
CGA
COMP
VFB
R1
Q1
-SOUT
P_GND
14/20
L6615
Figure 15. Distributed power system for +48V bus
+48V
+48V
+48V (*)
feedback
+48V (*)
feedback
L
IOUT1
IOUT2
O
A
D
AC
Mains
AC
Mains
RSNS
RSNS
+48V GND
+12V
+48V GND
+12V
RG
RG
RG
RG
DPS2
DPS1
(*) the center of the
output feedback divider
is usually connected to
CS+
SH
CS-
ADJ
CS-
CS+
SH
SH bus
ADJ
GND
a
voltage compatible
GND
Vcc
Vcc
with L6615 AMR
L6615
L6615
In this application is inserted also a circuit for the square current limit protection in case of overcurrent (R1-
Q1): being the voltage at the CGA pin directly proportional to the current carried by the relevant section,
it is possible to set the CGA resistor such that, until the output current is in the right range, the CGA voltage
is lower than V
+0.7. As soon as this value is overcome, then the bipolar pushes current in the feedback
REF
path, reducing the duty cycle and consequently the output voltage.
Current sharing can be required in AC to DC application like distributed power system (DPS) for telecom
applications: if the output voltage is higher than the absolute maximum rating for the current sense pins
(CS+ and CS-) high side sensing can not be performed unless adding other components; the current
sense is performed on the ground return.
To maintain high side sensing two resistor dividers (between the edge of R
and ground) could be
SENSE
introduced to translate the sense signal in the L6615 input pin common mode range.
In fig.15 two AC-DC converters supply the same load through a +48V bus; these converters usually exhibit
also a +12V auxiliary output useful to supply the L6615 whose ADJ pin works on the +48V feedback sec-
tion (COMP pin and CGA pin connections are not showed) in figure 15.
7
LOW VOLTAGE BUSES
The L6615 has a "doubled" sense structure, designed to perform both high side and low side sensing: the
first solution is usually considered more convenient. Actually low side sensing means to split the ground
return as many times as the power supplies paralleled are: on each of these paths it is then necessary to
place the sense resistor introducing a drop between the power supply ground and the common load neg-
ative reference.
The voltage at CS+ pin is read by an internal comparator and compared with a reference corresponding
to the switchover threshold V
whose value is typically 1.6V. If such value is overcome, then the com-
THcs+
parator triggers the High Side Amplifier (HSA); being the threshold provided by hysteresis, then the Low
Side Amplifier (LSA) will be triggered as VCS+ is lower than 1.44V (typ.).
Hence V
defines the threshold between the operating range of LSA, (referring to fig.10) and the op-
THcs+
erating range of HSA; usually LSA is operating when the sense resistor is placed on the ground return,
between the negative load terminal and the negative power supply output (fig 10.b) and HSA when the
sense resistor is placed between the power supply positive output and the load.
It is however possible to perform high side sensing for applications whose output voltage is close to V
threshold (or even lower) exploiting the low sense internal structure (LSA).
THcs+
15/20
L6615
Consider, for example an application with V
at CS+:
= 1.2V and the sense resistor placed high side; the voltage
OUT
V
= V - ∆V
OUT SENSE
CS+
is lower than 1.6V so the internal comparator triggers on the LSA structure and the pin CS- sources the
current I (see paragraph "2. CURRENT SENSE SECTION"). The IC works properly because the dy-
CS
namics of LSA spreads down to zero: in this case it is necessary to pay attention to the design of ADJ
network.
Now consider, for example, an application with V
=1.5V where, because of the drop across R
, the
OUT
SNS
voltage at CS+ pin could be very close to the threshold: if such voltage is overcome (start-up, load regu-
lation, overvoltage,…) , then the HSA structure will be activated; as nominal conditions are restored, the
hysteresis will then keep HSA active (unless V
falls under the lower threshold).
CS+
8
OFFSET TRIMMING
The current sharing accuracy strongly depends on the unbalance between the relevant parameters of the
paralleled sections. Each percentage point on the relevant parameters tolerance introduces a maximum
error equal to the double of the tolerance.The L6615 introduces an inherent error in current sharing due
to the 40mV offset at the negative input of the error amplifier; this offset is necessary to guarantee the low
value of the master COMP pin.
Considering perfectly matched all other parameters, the offset introduces a percentage error equal to 4%
divided by the voltage on the share bus. In particular:
40mA
I
= I
– ---------------
SLAVE
MASTER
V
SH
Being V directly proportional to the load current and fixed the ratio R
/R , higher are the currents
CGA G
SH
involved in the sharing, lower is the error.
Another error is introduced by the current sense amplifier due to its input offset whose amplitude can be
±1mV: being typically the drop across R
error of some percentage point.
about one hundred mV at full load, the offset could lead to an
SNS
Whenever the application requires very high current sharing accuracy, it is possible to correct these offsets
through a triggering process, introducing a trimmer (R ) between current sense input pins.
K
Referring to fig. 16, in case of high side sensing, the equations governing the circuit are:
V
– V
V
M
OUT
M
---------------------------- = ----------------------------
R
(1 – δ ) R
– V V
P
G
K
V
+ V
OUT
SENSE
P
-------------------------------------------------------- – -------------- = I
G
R
δ R
K
G
V = V + V
O
P
M
where V is the current sense amplifier input offset.
O
Solving for I , we get:
G
δ R + R
V
2 δ – 1
δ [R (1 – δ) + R ]
K
G
SENSE
-----------------------------
V + V
O OUT
-------------------------------------------------------
I
= --------------------- –
G
δ R
R
R
K
G
K
G
G
Ideally I should be equal only to the first term: this current will be sunk by CS+ pin, internally mirrored
G
with 1:1 ratio and sent to CGA pin.
Imposing that the sum of two latter terms is zero it is possible to find the value of δ deleting the effect of
the offset:
2
2
G
2
O
2
K
2
O
2 V
R
–
4 V
R
+ V
R
+ 4 V
R
R
G K
1
2
OUT
G
OUT
δ
= -- – -----------------------------------------------------------------------------------------------------------------------------------------------------------
OPT
2 V
R
O K
16/20
L6615
Figure 16. Offset Trimming
ILOAD
VOUT
VOUT+VSENSE
_
+
RSNS
RG
RG
δ RK
(1-δ) RK
VM
CS-
IG
VP
CS+
CGA
L6615
RCGA
Because of the tolerance of the output voltage, it is not possible to delete completely the effect of the offset
on CGA pin on all the allowed output voltage range: if the trimming operation is performed at V
,
OUT(MIN)
then on pin CGA the maximum residual voltage will be present at V
and its value will be:
OUT(MAX)
1 – 2 δ
OPT
-----------------------------------------------------------------------------
)
OUT(MIN)
R
(V
– V
CGA
OUT(MAX)
δ
(R
δ
– R – R )
OPT K G
OPT
K
To simplify the procedure, the following step-by step process can be used:
■ a trimmer has to be placed between sense pins of each section: the value of the trimmer resistance
must be at least one order of magnitude higher than R and it has to be set at one half of its range
G
(δ=0.5);
■ once the application is running at a load defined by the designer based on the required sharing
accuracy, the master section has to be located;
■ on the slave sections it is then necessary to operate on the trimmer to make equal the output currents.
REFERENCE
[1] "L6910 - Adjustable step down controller with synchronous rectification" (Datasheet)
[2] "L6911 - 5 bit programmable step down controller with synchronous rectification" (Datasheet
17/20
L6615
mm
inch
DIM.
OUTLINE AND
MECHANICAL DATA
MIN.
TYP. MAX. MIN.
3.32
TYP. MAX.
0.131
A
a1
B
0.51
1.15
0.020
1.65 0.045
0.55 0.014
0.304 0.008
10.92
0.065
0.022
b
0.356
0.204
b1
D
E
0.012
0.430
7.95
9.75 0.313
2.54
0.384
e
0.100
e3
e4
F
7.62
0.300
7.62
0.300
6.6
0.260
I
5.08
0.200
L
3.18
3.81 0.125
1.52
0.150
Minidip
Z
0.060
18/20
L6615
mm
inch
DIM.
OUTLINE AND
MECHANICAL DATA
MIN. TYP. MAX. MIN. TYP. MAX.
A
a1
a2
a3
b
1.75
0.069
0.010
0.065
0.033
0.019
0.010
0.020
0.1
0.25 0.004
1.65
0.65
0.35
0.19
0.25
0.85 0.026
0.48 0.014
0.25 0.007
b1
C
0.5
0.010
c1
D (1)
E
45° (typ.)
4.8
5.8
5.0
6.2
0.189
0.228
0.197
0.244
e
1.27
3.81
0.050
0.150
e3
F (1)
L
3.8
0.4
4.0
0.15
0.157
0.050
0.024
1.27 0.016
0.6
M
SO8
S
8° (max.)
(1) D and F do not include mold flash or protrusions. Mold flash or
potrusions shall not exceed 0.15mm (.006inch).
19/20
L6615
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2003 STMicroelectronics - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
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20/20
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