L6660 [STMICROELECTRONICS]
MILLI-ACTUATOR DRIVER; MILLI-传动装置驱动器
| 型号： | L6660 |
| 厂家： | 
ST |
| 描述： | MILLI-ACTUATOR DRIVER |
| 文件： | 总9页 (文件大小：105K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L6660
®
MILLI-ACTUATOR DRIVER
PRODUCT PREVIEW
90V BCD MIXED TECHNOLOGY
SO24 PLASTIC SMD PACKAGE
4.5 TO 13.2V OPERATIVE VOLTAGE
±25 TO ±35V OUTPUT VOLTAGE RANGE
SELECTABLE BY EXTERNAL RESISTORS
FULL-WAVE RESONANT DC-DC CON-
VERTER USING SINGLE COIL FOR DUAL
HIGH VOLTAGE GENERATOR WITH OUT-
PUT SLEW RATE CONTROL AND SELF
CURRENT LIMITING FOR LOW EMI
SO24(Shrink)
±35V OR 0/+70V OPERATIVE VOLTAGE
DRIVING CONFIGURATION MODES:
1. SINGLE ENDED VOLTAGE MODE
2. DIFFERENTIAL VOLTAGE MODE
3. SINGLE ENDED CHARGE MODE
DOUBLE OPERATIONAL AMPLIFIERS WITH
500KHZ GAIN BANDWIDTH PRODUCT AND
LOAD DRIVING CAPABILITY FROM 0.4nF
UP TO 24nF
INTERNAL 2.5V VOLTAGE REFERENCE
POWER SAVING SLEEP MODE
USER SPECIFIED INPUT REFERENCE
(2.25V DC)
DESCRIPTION
The L6660 is a piezoelectric actuator driver.
ANALOG VOLTAGE SHIFTING CIRCUITRY
BLOCK AND APPLICATION DIAGRAM
[24] HVP
HVP
[7] SLEEP
SLEEP
1
K
-
[17] INB(inv)
[18] OUTK-B
[19] OUT1-B
B
[16] INB(not inv)
+
[10] Vosh
1
K
HVM
HVP
Shifter
Vosh=Vin-Vref
[23] HVM
[11] Vin0-5
1
K
From DAC
OUTPUT
[8] INA(inv)
V512
-
[6] OUTK-A
A
[9] INA(not inv)
[5] OUT1-A
+
2.2nF
1
K
HVM
47µH
V5/12
[15] WENA
[4] AorB
MUX
+35V
[3] COIL
Controll
Logic
A-GND
[1] AandB
Internal
Current
Bias
DC-DC LOGIC
Back-Up
Oscill.
[20] V5/12AP
[14] IN Vref
Rfdb1
220nF
+
-
Rs
Digital
Rfdb2
68nF
Pwr Supply
HVM
[13] Vref out
Internal Band-gap
and 2.5 reference Voltage
-35V
220nF
:5
[12] GND-A
[21] Vfdb
[22] RCcomp
[2] GND-P
100nF
47nF
HVP=VrefIN(1+Rfdb1/Rfdb2)
December 2000
1/9
This is preliminary information on a new product now in development. Details are subject to change without notice.
L6660
PIN CONNECTION SO24-SHIRINK (Top view)
A and B
1
24
23
22
21
20
19
18
17
16
15
14
13
HVP
HVM
GND-P
COIL
2
3
RC comp
VFDB
A or B.
4
OUT1-A
OUTK-A
5
V5/12-AP
OUT1-B
OUTK-B
INB(inv)
INB(not inv)
WENA
6
SLEEP
INA(inv)
7
8
INA(not inv)
VOSH
9
10
11
12
Vin 0-5
GND-A
Vref IN
Vref OUT
PINCON
PIN FUNCTIONS
N.
1
Name
AandB
Description
MUX Enable (see Tab. 1).
Power ground.
2
GND-P
COIL
3
Coil for positive step UP and capacitor for negative charge.
MUX command Aor B input selection (0 = A; 1 = B).
Output ampl.A.
4
AorB
5
OUT1-A
OUTK-A
SLEEP
INA (inv)
INA (not inv)
Vosh
6
Hi current output ampl.A.
7
Sleep mode for stand-by condition (0=SLEEP 1=operative).
Inverting input of A-amplifier.
8
9
Non Inverting input of A-amplifier.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Analog level shifter output Vin-Vref (-2.5 to +2.5 dynamic range)
Analog level shifter input positive voltage.
Analog ground.
Vin 0-5
GND-A
Vref OUT
Precise 2.5V reference voltage.
V
ref IN
Input for external reference voltage.
Multiplexer Enable, Falling Edge sensitive.
Non Inverting input of B-amplifier.
WENA
INB (not inv)
INB (inv)
OUTK-B
OUT1-B
V5/12-AP
Vfdb
Inverting input of B-amplifier.
Hi current output ampl.B.
Output ampl.B.
Analog&Power voltage supply 5 to 12V.
Feedback voltage for HVP regulator.
DC-DC converter compensation network.
Negative High voltage generated op. amp. supply.
Positive High voltage generated op. amp. supply.
RC comp
HVM
HVP
2/9
L6660
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
14
Unit
V
V512
HVP
Supply voltage pin 17 referred to Ground
Positive high voltage referred to HVM
Negative high voltage referred to Ground
Amplifier input voltage common mode
Maximum difference between pin 20 and pins 8, 9, 16 & 17
Operative Ambient Temperature
75
V
HVM
-38
V
IN A&B
6
V
±
V
∆
17
V
Tamb
Tstg
-20 to +80
-40 to +125
°C
°C
Storage Temperature
All the voltage value are referred to ground unless otherwise specified.
ELECTRICAL CHARACTERISTICS
(All the following parameters are specified @ 27°C and V5/12 = 12V 5%, unless otherwise specified.)
±
Symbol
V5/12
HVP (1)
Parameter
Main power supply
Test Condition
Min.
4.5
Typ.
Max.
13.2
Unit
V
Output positive Voltage
Double Supply Voltage V512
Double Supply Voltage V512 < 8
8
27
18
35
35
V
V
≥
Single Supply Voltage V512
Single Supply Voltage V512 < 8
8
27
18
70
35
V
V
≥
HVripple
HVP, HVM ripple
Characterized only, Not Tested
External filter cap. 100nF
ILOAD = 0mA
0.8
V
I, hvp
I, hvm
Top
Output current (see figure 1)
Time to operating condition
Switching Frequency
5
ms
(2)
Fswitch
Refer to Block diagram
page1/10
300
kHz
Rds, on
Iboost
Vsup
Boost transistor ON resistance
Boost transistor current limiting
4
Ω
mA
V
850
Minimum OpAmp supply
Voltage (HVP if externally
given)
Double Supply
Single Supply
V512
+4
V512
+4
V
DC gain
GBW
OpAmp DC gain
130
500
dB
OpAmp Gain Bandwidth
product
Cload 0.4nF to 24nF
Double Supply Voltage
KHz
DCinp
OpAmp Input dynamic voltage
Double supply
Single supply
-3.5
1.2
4.5
5
V
V
Vout
OpAmp Output dynamic voltage Capacitive load
HVM
HVP
9
V
DC, Ibias
OpAmp Bias supply current
(both)
|HVP| = |HVM| = 35V
mA
Iout (3)
OpAmp Dynamic Output
Average current with external
supply
-75
+75
mA
PSRR,P
PSRR,N
Cload
OpAmp Positive power supply
rejection ratio
@ 50kHz not tested in production
-50
-50
dB
dB
nF
nF
OpAmp Negative power supply @ 50kHz not tested in production
rejection ratio
OpAmp Load capacitance
range
Voltage mode Gain min 20dB
0.4
24
Cint
K
OpAmp Integration capacitance Charge mode Gain min 20dB
0.4
9.8
24
OpAmp Current ratio
OUTK/OUT1
10
10.2
3/9
L6660
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Vout0
OpAmp Output Voltage with 0V External feedback programmed
-1
+1
V
Input Voltage
for DC gain value <30V/V
VrefOUT
Ivref
Reference Voltage PIN13
Reference Voltage Output Current
Filter capacitor at PIN13
Voltage shift value
2.4
-1
2.5
2.6
+1
V
mA
nF
V
Vref, cap
Vshifted
10
100
1.0V Vin0-5 3.5V
VrefIN
-2%
VrefIN
1.00
VrefIN
+2%
≤
≤
(VPIN11 - VPIN10
)
Shifter Gain Analog Voltage Shifter DC
Voltage Gain
VPIN11 = VREFIN
V’
10
0.975
1.025
→
VPIN11 = VREFIN + 0.1V
V"
10
→
V
∆
10
V’’ − V’
10
10
G =
0.1
∆V11
BWVshift
VrefIN
Shifter circuitry Band Width
External reference voltage
(PIN14)
3dB amplitude drop
2
MHz
V
2.0
-12
2.6
Isleep
Total current in Sleep Mode
PIN7 at 0 logic
VrefIN = 2.25V
800
+12
A
µ
EAoff
DC-DC converter Error
mV
Amplifier Input voltage Offset
(VPIN14-VPIN21
)
IEA
Error amplifier Current
Capability
100
±
A
µ
HVP%
Vlogic0
Total HVP precision
Vref = 2.25V 0%
-4
+4
%
±
Voltage level for 0 logic at
digital input pin (Pin 1-4-7-15)
0.9
V
Vlogic1
Ztime
Top
Voltage level for 1 logic at
digital input pin (Pin 1-4-7-15)
1.6
V
Decay period for V = |19V|
Vref (Pin14) = 2.25V See Fig. 3
0°C < Tcase < 80°C
140
340
4
s
∆
µ
µ
Operative period from Not
Selected phase to Selected
phase for each driver
s
Note 1: Selectable by external resistors.
Note 2: Set by external Coil and Capacitor from 80 to 550KHz.
Note 3: Take into account the total power dissipation.
OPERATIONAL AMPLIFIERS DESCRIPTION
Each driver has two output stages scaled in cur-
rent by a factor K = 10.
Figure 1. Load Regulation
In voltage mode configuration the two outputs are
shorted.
36
In charge mode configuration OUT1 drives a ca-
pacitor Cint and is closed in feedback, while
OUTK drives the piezo, mirroring the current sup-
plied to Cint, with a current multiplied by a K fac-
tor (see Fig.2).
The supply voltage can be internally generated
by the DC-DC converter, or external, maintaining
the DC-DC converter in sleep mode (PIN3
shorted to ground), in this case the supply volt-
age can be 0 to V5/12+4 minimum value up to
70V in single supply or V5/12+4 to 35V symmetri-
cal to ground.
12V
34
32
30
28
26
24
22
10V
11V
9V
8V
7V
6V
5V
The drivers have 130dB DC gain and the Band-
width is 500KHz. Stability is guaranteed with a
minimum gain of 20dB, for a capacitive load in
the range 0.4nF up to 24nF.
5
9
13 17 21 25 29 33 37 41 45 49 53 57 61 65
1
Load DC Current (mA)
4/9
L6660
The drivers can be supplied with HVP-HVM (dou-
ble supply mode) or with HVP-Ground (single
supply mode). In both cases they can achieve a
rail-to rail output dynamic range with an average
In double supply mode the input stage has -
5V/+5V common mode dynamic range, while in
single supply configuration it has 1.2V up to 10V
input common mode dynamic range.
load current up to 75mA.
±
Figure 2. Charge Mode Configuration (configuration example; the final application depends on
user needs according with Electrical Characteristics).
Qpiezo=K*[Cint*(1+Ra/Rb)+C]*Vdac
Qpiezo=Cost*Vdac
Cost=k*[Cint*(1+Ra/Rb)+C]
HVP
HVM
1
1
K
K
Vdac
+
-
Cpiezo
RP
Ra
Rb
C
Cint
D98IN970A
Input Multiplexer
MULTIPLEXER is controlled by internal logic with 3 digital inputs, supplied by IntVref (2.5V), it is com-
patible to 3.3V and 5V logic command signals, it allows to perform the following configuration:
Table 1.
AandB AorB WENA
(PIN1) (PIN4) (PIN15)
INA+Status
INB+Status
Comment
0
0
1
1
1
1
1
0
1
0
1
0
X
INA+
INB+
Both drv. inp. are disconnected from ext
connected to AGND connected to AGND PIN and are connected to AGND
X
INA+
connected to PIN9
INB+
Both drv. inp. are accesible
connected to PIN16 (MUX is transparent)
1
INA+
connected to PIN9
INB+
connected to AGND
INA is selected
1
INA+
INB+
INB is selected
connected to AGND connected to PIN16
(F.E.)
(F.E.)
INA+
connected to PIN9
INB+
From WENA Falling Edge, changes on
connected to AGND AorB (pin 4) will not change MUX state.
INA+
INB+ From WENA Falling Edge, changes on
connected to AGND connected to PIN16 AorB (pin 4) will not change MUX state.
F.E. = Falling Edge
The MUX is at NOT inv. Inputs, and NO current flows through the MUX switches, because the driver in-
put stage is designed with high impedance stage.
5/9
L6660
Figure 3. Not selected driver return to Zero Output voltage. Both drivers have the same behavior.
The device is in operative condition and AandB (Pin1) and WENA (Pin15) are at 1 logic
condition. The external feedback programmed for a DC gain value <30V/V.
Drivers
OUTPUT
Voltage
+20V
Deselected
Driver Output
Voltage
+2V
0
t
AorB
(PIN4)
Ztime
AorB
(PIN4)
Ztime
Drivers
OUTPUT
Voltage
0
t
-2V
Deselected
Driver Output
Voltage
-20V
6/9
L6660
PIN21. The HVP voltage is programmed by two
external resistors as shown in the block diagram,
its value is:
Not selected Output return to 0V
Using the Multiplexer features and selecting just
one driver, the second one, leaves its output volt-
age and "goes" to 0V (have showed in Fig. 3), in
"long time" with controlled slope see table 1.
Rfdb1
VHVP
V
PIN21
1
( +
=
)
Rfdb2
Voltage reference
The DC-DC control loop precision will be im-
proved lower than 4% respect external refer-
±
An internal 2.5V voltage reference generator is
connected to PIN13 (VrefOUT); it is based on an
internal Band-Gap reference with a total precision
ence voltage and resistor voltage divider.
In Sleep Mode HVM is shorted to GND. When in
single supply, HVM must be connected to GND.
of 4% and a current capability of 1.0mA, it is al-
±
±
ways present even in sleep mode condition.
The topology is a standard resonant full-wave
boost one: the LC oscillation is kept running all
the time and a set of comparators is used to syn-
chronize turning on and off of the power MOS in
order to have zero current and zero voltage
switching and furthermore controlled rectification.
The step-up converter is designed to work in Lin-
ear mode, and an AC compensation network is
required (RC-comp) to guarantee the stability in a
wide operative range (i.e. changing coil, load,
output and input voltage...).
This voltage is used to supply the internal MUX
logic, allowing both 3.3V or 5V logic input signals,
also the internal bias current is based on this ref-
erence.
The DC-DC converter reference voltage comes
from PIN14 (VrefIN), so that the user can use an
external voltage reference (from 2.0V up to 2.6V)
or the internal one, in this case, just shorting to-
gether VrefOUT and VrefIN (PIN13 and PIN14).
According to the ouput voltage, the current
loaded into the coil is changing like a Voltage
Loop-Current Controlled system, and in every
pulse there is a regulated power transfer to the
load.
The resonant LC topology has been chosen in or-
der to limit the voltage slew-rate across the coil
within reasonable values and so, to minimize ra-
diation problems.
The negative converter is a simple charge trans-
fer: it is supplied by the positive high voltage and
it capacitively translates this positive voltage
down to a negative one, obviously to limit radia-
tion problems also the charge output has a lim-
ited slew-rate; moreover to reduce intermodula-
tion phoenomenas the charge output is
synchronized with the LC oscillations of the reso-
nant boost.
Voltage Shifter
A voltage shifter is inserted to allow a ground
symmetrical driving voltage on the piezo, starting
from a positive (0V up to 5V) input signal coming
from a positive supplied DAC. The DC Input-Out-
put typical tranfer function is plotted in Fig. 4. This
block works only in Double Supply mode, obvi-
ously it doesn’t work if no negative supply is pre-
sent. The voltage shifter output has not DC-cur-
rent capability.
For more details see the application note.
DC-DC CONVERTER DESCRIPTION
The DC-DC converter inside the chip can be sup-
plied from 5V up to 12V and has two parts, one to
supply the positive and one to supply the nega-
tive voltage.
This negative voltage is (not counting drops on
external rectification diodes) in tracking with the
positive one and so the negative output controller
is not required.
The DC-DC converter loop "measures" the HVP
voltage by the EXTERNAL voltage divider and
Figure 4. Shifter DC transfer function
If the drivers are supplied by HVP & HVM gener-
ated by external power supply the error amplifier
output has to be connected to V5/12.
In the external supply configuration the maximum
voltage between HVP and HVM (|HVP| + |HVM|)
must not exceed 70V and maximum voltage be-
tween GND and HVM must be lower than 35V.
Vosh
PIN10
VIN,MAX - VrefIN
0
VIN,MAX
Vin0-5
PIN11
VrefIN
0-VrefIN
5.0V IF V5/12 > 5.5V
VIN,MAX =
{
V5/12 - 0.5V IF V5/12 ≤ 5.5V
7/9
L6660
mm
inch
OUTLINE AND
DIM.
MECHANICAL DATA
MIN. TYP. MAX. MIN.
TYP. MAX.
0.079
A
A1
A2
B
2.00
0.25
0.010
1.51
0.25
0.10
8.35
7.60
5.02
2.00 0.060
0.079
0.30
0.35 0.010 0.012 0.014
C
0.35 0.004
0.014
0.37
D
9.35
8.70
6.22
0.33
0.30
0.20
E
0.34
E1
e
6.10
0.65
0.24 0.244
0.025
k
0˚ (min), 10˚ (max)
SSO24 (SHRINK)
L
0.25
0.50
0.80 0.010 0.020 0.031
A2
A1
A
K
B
e
C
0.10mm
.004
L
E1
Seating Plane
D
24
13
12
E
1
SSO24ME
8/9
L6660
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
© 2000 STMicroelectronics – Printed in Italy – All Rights Reserved
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