L6717A [STMICROELECTRONICS]
Dynamic phase management;
| 型号： | L6717A |
| 厂家： | 
ST |
| 描述： | Dynamic phase management |
| 文件： | 总57页 (文件大小：1935K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L6717A
High-efficiency hybrid controller
with I2C interface and embedded drivers
Datasheet
-
production data
Applications
• Hybrid high-current VRM / VRD for desktop /
server / workstation / IPC CPUs supporting PVI
and SVI interface
• High-density DC-DC converters
VFQFPN48
Description
L6717A is a hybrid CPU power supply controller
embedding 2 high-current drivers for the CORE
section and 1 driver for the NB section - requiring
up to 2 external drivers when the CORE section
works at 4 phase to optimize the application over-
all cost.
I2C interface is provided to manage offset for
CORE section, switching frequency and dynamic
phase management saving in component count
and space consumption.
Features
• Hybrid controller for both PVI and SVI CPUs
G34 compliant
• Dual controller with embedded high current
drivers: 2 phases for CPU CORE + 2 PWM for
ext drivers, 1 phase for NB
• Dynamic phase management (DPM)
• I2C interface to control offset, switching
frequency and PSI_L
Dynamic phase management automatically
adjusts phase-count according to CPU load
optimizing the system efficiency under all load
conditions.
• Dual-edge asynchronous architecture with LTB
Technology®
• PSI management to increase efficiency in light-
load conditions
The dual-edge asynchronous architecture is
®
• Dual overcurrent protection: total and per-
optimized by LTB technology allowing fast load-
phase compatible with Itdc and IddSpike
transient response minimizing the output
capacitor and reducing the total BOM cost.
• Voltage positioning
• Dual remote sense
Fast protection against load overcurrent is
provided for both the sections. Feedback
disconnection protection prevents from damaging
the load in case of misconnections in the system
board. L6717A is available in VFQFPN48
package.
• Feedback disconnection protection
• Programmable OV protection
• Oscillator internally fixed at 200 kHz externally
adjustable
• LSLess startup to manage pre-biased output
• VFQFPN48 package
Table 1. Device summary
Order codes
Package
Packing
L6717A
Tray
VFQFPN48
L6717ATR
Tape and reel
April 2013
DocID024465 Rev 1
1/57
This is information on a product in full production.
www.st.com
57
Contents
L6717A
Contents
1
2
3
Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 5
1.1
1.2
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 9
2.1
2.2
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1
3.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4
5
Device description and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Hybrid CPU support and CPU_TYPE detection . . . . . . . . . . . . . . . . . . 19
5.1
5.2
5.3
5.4
PVI - parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PVI start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SVI - serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SVI start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
Set VID command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PWROK de-assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
PSI_L and efficiency optimization at light-load . . . . . . . . . . . . . . . . . . . 24
HiZ management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Hardware jumper override - V_FIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6
Power manager I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1
Power manager commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
Overspeeding command (OVRSPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Overvoltage threshold adjustment (OV_SET) . . . . . . . . . . . . . . . . . . . . 30
Switching frequency adjustment (FSW_ADJ) . . . . . . . . . . . . . . . . . . . . 30
Droop function adjustment (DRP_ADJ) . . . . . . . . . . . . . . . . . . . . . . . . . 31
Power management flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.2
Dynamic phase management (DPM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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Output voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
CORE section - phase # programming . . . . . . . . . . . . . . . . . . . . . . . . . . 35
CORE section - current reading and current sharing loop . . . . . . . . . . . . 35
CORE section - defining load-line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
CORE section - analog offset (Optional - I2CDIS = 3.3 V) . . . . . . . . . . . . 37
NB section - current reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
NB section - defining load-line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
On-the-fly VID transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.8.1
LS-Less start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8
Output voltage monitoring and protections . . . . . . . . . . . . . . . . . . . . . 41
8.1
8.2
8.3
8.4
Programmable overvoltage (I2DIS = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . 41
Feedback disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
PWRGOOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Overcurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.4.1
8.4.2
8.4.3
CORE section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
IddSpike and IddTDC support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
NB section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9
Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10
High current embedded drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.1 Boot capacitor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.2 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
11
System control loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
11.1 Compensation network guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
12
13
LTB Technology
Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
13.1 Power components and connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
13.2 Small signal components and connections . . . . . . . . . . . . . . . . . . . . . . . 53
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L6717A
VFQFPN48 mechanical data and package dimensions . . . . . . . . . . . . 54
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
15
4/57
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L6717A
Typical application circuit and block diagram
1
Typical application circuit and block diagram
1.1
Application circuit
Figure 1. Typical 4+1 application circuit
CHF
CHF
LIN
V
IN
CBULK_IN
3
2
49
42
3.3V
VCC
48
BOOT
BOOT1
CHF
CHF
47
46
45
HS1
LS1
HS3
LS3
UGATE
PHASE
LGATE
GND
EN
PWRGOOD
PWROK
UGATE1
PHASE1
LGATE1
35
1
L1
L3
PWM
VID0 / VFIX
34
33
32
31
30
29
R
R
VID1 / CORE_TYPE
PVI / SVID Bus
C
C
VID2 / SVD
VID3 / SVC
15
CS1P
CS1N
VID4 / I2C_DIS
VID5 / ADDRESS
R
G
G
16
20
CS3N
CS3P
R
19
28
R
R
C
OSC
ILIM
ILIM
3.3V
OSC / EN / FLT
ILIM
PWM3
VCC
14
13
39
BOOT
BOOT2
CHF
CHF
40
41
44
HS2
LS2
HS4
LS4
UGATE
PHASE
LGATE
GND
EN
UGATE2
PHASE2
LGATE2
L2
L4
PWM
R
R
C
C
SCL / OS
26
25
17
Power Manager I2C
CS2P
CS2N
SDA / OVP
R
G
G
18
22
CS4N
CS4P
R
21
27
PWM4
COMP
4
C
F
F
36
CP
NB_BOOT
CHF
R
37
38
43
HS_NB
LS_NB
NB_UGATE
NB_PHASE
NB_LGATE
FB
L_NB
PVI / SVID AM2 CPU
5
8
CMLCC
COUT
COUT_NB
LTB
R_NB
C
I
I
C
R
LTB
C_NB
CMLCC_NB
RFB
SVI/PVI Interface
23
R
NB_CSP
NB_CSN
LTB
24
12
R
G_NB
VSEN
FBG
6
NB_FBG
7
9
10
11
CF_NB
RF_NB
RFB_NB
ST L6717A (4+1) Reference Schematic
DocID024465 Rev 1
5/57
Typical application circuit and block diagram
L6717A
Figure 2. Typical 3+1 application circuit
CHF
CHF
LIN
V
IN
CBULK_IN
3
2
49
42
3.3V
VCC
48
BOOT
BOOT1
CHF
L1
R
CHF
47
46
45
HS1
LS1
HS3
LS3
UGATE
PHASE
LGATE
GND
EN
PWRGOOD
PWROK
UGATE1
PHASE1
LGATE1
35
1
L3
PWM
VID0 / VFIX
34
33
32
31
30
29
R
VID1 / CORE_TYPE
PVI / SVID Bus
C
C
VID2 / SVD
VID3 / SVC
15
CS1P
CS1N
VID4 / I2C_DIS
VID5 / ADDRESS
RG
RG
16
20
CS3N
CS3P
19
28
ROSC
OSC / EN / FLT
ILIM
PWM3
14
13
39
BOOT2
RILIM
CILIM
CHF
L2
R
40
41
44
HS2
LS2
UGATE2
PHASE2
LGATE2
C
SCL / OS
26
25
17
Power Manager I2C
CS2P
CS2N
SDA / OVP
RG
RG
18
22
CS4N
CS4P
21
27
PWM4
COMP
4
CF
36
C
NB_BOOT
CHF
RF
37
38
43
HS_NB
LS_NB
NB_UGATE
NB_PHASE
NB_LGATE
FB
L_NB
R_NB
PVI / SVID AM2 CPU
5
8
CMLCC
COUT
COUT_NB
CMLCC_NB
LTB
CI
RI
CLTB
C_NB
RFB
SVI/PVI Interface
23
NB_CSP
NB_CSN
RLTB
24
12
RG_NB
VSEN
FBG
6
7
NB_FBG
9
10
11
CF_NB RF_NB
RFB_NB
ST L6717A (3+1) Reference Schematic
6/57
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L6717A
Typical application circuit and block diagram
Figure 3. Typical 2+1 application circuit
CHF
CHF
LIN
V
IN
CBULK_IN
3
2
49
42
48
BOOT1
CHF
L1
R
47
46
45
HS1
LS1
PWRGOOD
PWROK
UGATE1
PHASE1
LGATE1
35
1
VID0 / VFIX
34
33
32
31
30
29
VID1 / CORE_TYPE
PVI / SVID Bus
C
VID2 / SVD
VID3 / SVC
15
CS1P
CS1N
VID4 / I2C_DIS
VID5 / ADDRESS
RG
RG
16
20
CS3N
CS3P
19
28
ROSC
OSC / EN / FLT
ILIM
PWM3
14
13
39
BOOT2
RILIM
CILIM
CHF
L2
R
40
41
44
HS2
LS2
UGATE2
PHASE2
LGATE2
C
SCL / OS
26
25
17
Power Manager I2C
CS2P
CS2N
SDA / OVP
RG
RG
18
22
CS4N
CS4P
21
27
PWM4
COMP
4
CF
36
C
NB_BOOT
CHF
RF
37
38
43
HS_NB
LS_NB
NB_UGATE
NB_PHASE
NB_LGATE
FB
L_NB
R_NB
PVI / SVID AM2 CPU
5
8
CMLCC
COUT
COUT_NB
CMLCC_NB
LTB
CI
RI
CLTB
C_NB
RFB
SVI/PVI Interface
23
NB_CSP
NB_CSN
RLTB
24
12
RG_NB
VSEN
FBG
6
7
NB_FBG
9
10
11
CF_NB RF_NB
RFB_NB
ST L6717A (2+1) Reference Schematic
DocID024465 Rev 1
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Typical application circuit and block diagram
L6717A
1.2
Block diagram
Figure 4. Block diagram
VCCDR
GND_PAD
EMBEDDED DRIVER
CORE PHASE #2
EMBEDDED DRIVER
CORE PHASE #1
DIFFERENTIAL
CURRENT SENSE
PWM2
VID0 / V_FIX
VID1 / CORE_TYPE
VID2 / SVD
VID3 / SVC
VID4 / I2CDIS
VID5 / ADDR
LTB
COMP
FB
PWROK
PWRGOOD
OSC / EN
ILIM
DUAL CHANNEL
OSCILLATOR (4+1)
IDROOP
ILIM
SDA / OVP
SCL / OS
FBG
VSEN
NB_CS+
NB_CS-
NB_PWM
64k
64k
64k
EMBEDDED DRIVER
CORE NB PHASE
REMOTE
BUFFER
ERROR
AMPLIFIER
64k
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Pins description and connection diagrams
2
Pins description and connection diagrams
Figure 5. Pins connection (top view)
36 35 34 33 32 31 30 29 28 27 26 25
NB_UGATE
NB_PHASE
BOOT2
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
NB_CSN
NB_CSP
CS4N
UGATE2
PHASE2
VCCDRV
NB_LGATE
LGATE2
CS4P
CS3N
CS3P
L6717A
PAD (GND)
CS2N
CS2P
LGATE1
CS1N
PHASE1
UGATE1
BOOT1
CS1P
OSC / EN /FLT
ILIM
1
2
3
4
5
6
7
8
9 10 11 12
2.1
Pin descriptions
Table 2. Pin description
Function
System-wide power good input (Ignored in PVI mode).
Pin#
Name
Internally pulled-low by 10μA. When low, the device will decode the two SVI bits SVC
and SVD to determine the Pre-PWROK Metal VID. When high, the device will actively
run the SVI protocol.
1
PWROK
Pre-PWROK Metal VID are latched after EN is asserted and re-used in case of
PWROK de-assertion. Latch is reset by VCC or EN cycle.
Device signal ground.
All the internal references are referred to this pin. Connect to the PCB signal ground.
2
3
SGND
VCC
Device power supply.
Operative voltage is 12 ±15%. Filter with 1μF MLCC to SGND.
CORE error amplifier output.
4
COMP
Connect with an RF - CF to FB.
The CORE section and/or the device cannot be disabled by grounding this pin.
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Pins description and connection diagrams
L6717A
Table 2. Pin description (continued)
Function
Pin#
Name
CORE error amplifier inverting input.
5
6
FB
Connect with a resistor RFB to VSEN and with an RF - CF to COMP. Droop current for
voltage positioning is sourced from this pin.
CORE output voltage monitor.
It manages OVP and UVP protections and PWRGOOD. Connect to the positive side
of the load for remote sensing. See Section 8 for details.
VSEN
FBG
LTB
CORE remote ground sense.
7
Connect to the negative side of the load for remote sensing. See Section 11 for proper
layout of this connection.
LTB Technology® input pin.
Connect through an RLTB - CLTB network to the regulated voltage (CORE section) to
8
detect load transient. See Section 12 for details.
NB error amplifier output.
9
NB_COMP Connect with an RF_NB - CF_NB to NB_FB.
The NB section and/or the device cannot be disabled by grounding this pin.
NB error amplifier inverting input.
10
NB_FB
NB_VSEN
NB_FBG
Connect with a resistor RFB_NB to NB_VSEN and with an RF_NB - CF_NB to NB_COMP.
Droop current for Voltage Positioning is sourced from this pin.
NB output voltage monitor.
It manages OVP and UVP protections and PWRGOOD. Connect to the positive side
of the NB load to perform remote sensing. See Section 11 for proper layout of this
connection.
11
12
NB remote ground sense.
Connect to the negative side of the load to perform remote sense. See Section 11 for
proper layout of this connection.
CORE overcurrent pin.
A current ILIM=DCR/RG*IOUT proportional to the current delivered by the CORE
section is sourced from this pin. The OC threshold is programmed by connecting a
resistor RILIM to SGND. When the generated voltage crosses the OC_TOT threshold
(VOC_TOT = 2.5V Typ) the device latches with all MOSFETs OFF (to recover, cycle
VCC or the EN pin).
13
ILIM
This pin is monitored for dynamic phase management.
Filter with proper capacitor to provide OC masking time (0.5mSec typ time constant).
See Section 8.4.1 for details.
OSC: It allows programming the switching frequency FSW of both Sections. Switching
frequency can be increased according to the resistor ROSC connected to SGND with a
gain of 10kHz/μA (see Section 9 for details). If floating, the switching frequency is
200kHz per phase.
OSC / EN / EN: Pull-low to disable the device. When set free, the device immediately checks for
14
FLT
the VID1 status to determine the SVI / PVI protocol to be adopted and configures itself
accordingly.
FLT: The pin is forced high (3.3V) in case of an OV / UV fault. To recover from this
condition, cycle VCC or the EN pin.
Drive with open drain circuit. See Section 8 for details.
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Pins description and connection diagrams
Table 2. Pin description (continued)
Function
Pin#
Name
CORE error amplifier inverting input.
5
FB
Connect with a resistor RFB to VSEN and with an RF - CF to COMP. Droop current for
voltage positioning is sourced from this pin.
CORE output voltage monitor.
6
7
VSEN
FBG
LTB
It manages OVP and UVP protections and PWRGOOD. Connect to the positive side
of the load for remote sensing. See Section 8 for details.
CORE remote ground sense.
Connect to the negative side of the load for remote sensing. See Section 11 for proper
layout of this connection.
LTB Technology® input pin.
Connect through an RLTB - CLTB network to the regulated voltage (CORE section) to
8
detect load transient. See Section 12 for details.
NB error amplifier output.
9
NB_COMP Connect with an RF_NB - CF_NB to NB_FB.
The NB section and/or the device cannot be disabled by grounding this pin.
NB error amplifier inverting input.
10
NB_FB
NB_VSEN
NB_FBG
Connect with a resistor RFB_NB to NB_VSEN and with an RF_NB - CF_NB to NB_COMP.
Droop current for Voltage Positioning is sourced from this pin.
NB output voltage monitor.
It manages OVP and UVP protections and PWRGOOD. Connect to the positive side
of the NB load to perform remote sensing. See Section 11 for proper layout of this
connection.
11
12
NB remote ground sense.
Connect to the negative side of the load to perform remote sense. See Section 11 for
proper layout of this connection.
CORE overcurrent pin.
A current ILIM=DCR/RG*IOUT proportional to the current delivered by the CORE
section is sourced from this pin. The OC threshold is programmed by connecting a
resistor RILIM to SGND. When the generated voltage crosses the OC_TOT threshold
(VOC_TOT = 2.5V Typ) the device latches with all MOSFETs OFF (to recover, cycle
VCC or the EN pin).
13
ILIM
This pin is monitored for dynamic phase management.
Filter with proper capacitor to provide OC masking time (0.5mSec typ time constant).
See Section 8.4.1 for details.
OSC: It allows programming the switching frequency FSW of both Sections. Switching
frequency can be increased according to the resistor ROSC connected to SGND with a
gain of 10kHz/μA (see Section 9 for details). If floating, the switching frequency is
200kHz per phase.
OSC / EN / EN: Pull-low to disable the device. When set free, the device immediately checks for
14
FLT
the VID1 status to determine the SVI / PVI protocol to be adopted and configures itself
accordingly.
FLT: The pin is forced high (3.3V) in case of an OV / UV fault. To recover from this
condition, cycle VCC or the EN pin.
Drive with open drain circuit. See Section 8 for details.
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Pins description and connection diagrams
L6717A
Table 2. Pin description (continued)
Function
Channel 1 current sense positive input.
Pin#
Name
15
16
17
18
CS1P
Connect through an R-C filter to the phase-side of the channel 1 inductor. See
Section 11 for proper layout of this connection.
Channel 1 current sense negative input.
Connect through a RG resistor to the output-side of the channel inductor. Filter the
Vout-side of RG resistor with 100nF to GND.
CS1N
CS2P
CS2N
See Section 11 for proper layout of this connection.
Channel 2 current sense positive input.
Connect through an R-C filter to the phase-side of the channel 2 inductor. See
Section 11 for proper layout of this connection.
Channel 2 current sense negative input.
Connect through a RG resistor to the output-side of the channel inductor. Filter the
Vout-side of RG resistor with 100nF to GND.
See Section 11 for proper layout of this connection.
Channel 3 current sense positive input.
Connect through an R-C filter to the phase-side of the channel 3 inductor. When
19
20
21
22
CS3P
CS3N
CS4P
CS4N
working at 2 phase, directly connect to Vout_CORE
.
See Section 11 for proper layout of this connection.
Channel 3 current sense negative input.
Connect through a RG resistor to the output-side of the channel inductor. When
working at 2 phase, connect through RG to CS3+. Filter the Vout-side of RG resistor
with 100nF to GND.
See Section 11 for proper layout of this connection.
Channel 4 current sense positive input.
Connect through an R-C filter to the phase-side of the channel 4 inductor. When
working at 2 or 3 phase, directly connect to Vout_CORE
.
See Section 11 for proper layout of this connection.
Channel 4 current sense negative input.
Connect through a RG resistor to the output-side of the channel inductor. When
working at 2 or 3 phase, connect through RG to CS4+.Filter the Vout-side of RG
resistor with 100nF to GND.
See Section 11 for proper layout of this connection.
NB channel current sense positive input.
23
24
NB_CSP
NB_CSN
Connect through an R-C filter to the phase-side of the NB channel inductor. See
Section 11 for proper layout of this connection.
NB channel current sense negative input.
Connect through a RG resistor to the output-side of the channel inductor. Filter the
Vout-side of RG resistor with 100nF to GND.
See Section 11 for proper layout of this connection.
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DocID024465 Rev 1
L6717A
Pin#
Pins description and connection diagrams
Table 2. Pin description (continued)
Function
Name
SDA - power manager I2C data.
When power manager I2C is enabled, this is the data connection.
See Section 6 for details.
OVP - over voltage setting.
25
SDA / OVP
When power manager I2C is disabled (VID4 / I2CDIS to 3.3V) this pin sources a
constant 10μA current. By connecting a resistor ROVP to GND, the OV threshold for
both Sections is defined.
See Section 8.1 for details.
SCL - power manager I2C clock.
When power manager I2C is enabled, this is the clock connection.
See Section 6 for details.
OS - CORE section offset.
26
SCL / OS
When power manager I2C is disabled (VID4 / I2CDIS to 3.3V) this pin is internally set
to 1.24V(2.0V): connecting a ROS resistor to GND (3.3V) allows setting a current that
is mirrored into FB pin in order to program a positive (negative) offset according to the
selected RFB. Short to GND to disable the function. See Section 7.4 for details.
PWM output for external drivers.
Connect to external drivers PWM inputs. The device is able to manage HiZ status by
setting the pins floating.
By shorting to GND PWM4 or PWM3 and PWM4, it is possible to program the CORE
section to work at 3 or 2 phase respectively.
PWM4,
PWM3
27, 28
See Section 5.4.4 for details about HiZ management.
Voltage identification pin - I2C address pin.
VID5 /
ADDR
Internally pulled-low by 10μA, it programs the output voltage in PVI mode. In SVI
mode, the pin is monitored on the EN pin rising-edge to modify the I2C address. See
Section 5 for details.
Voltage identification pin - I2C disable pin.
Internally pulled-low by 10μA, it programs the output voltage in PVI mode. In SVI
mode, the pin is monitored on the EN pin rising-edge to enable/disable the I2C. See
Section 5 for details.
29
30
VID4 /
I2CDIS
Voltage IDentification Pin - SVI Clock Pin.
31
32
VID3 / SVC
VID2 / SVD
Internally pulled-low by 10μA, it programs the output voltage in both SVI and PVI
modes. In SVI mode, the 10μA pull down is disabled. See Section 5 for details.
Voltage identification pins - SVI data pin.
Internally pulled-low by 10μA, it programs the output voltage in both SVI and PVI
modes. In SVI mode, the 10μA pull down is disabled. See Section 5 for details.
Voltage identification pin.
VID1 /
CORETYPE
Internally pulled-low by 10μA, it programs the output voltage in PVI mode. The pin is
monitored on the EN pin rising-edge to define the operative mode of the controller
(SVI or PVI). See Section 5 for details.
33
34
Voltage identification pin.
Internally pulled-low by 10μA, it programs the output voltage in PVI mode. If the pin is
pulled to 3.3V, the device enters V_FIX mode and SVI commands are ignored.
See Section 5 for details.
VID0 / VFIX
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Pins description and connection diagrams
L6717A
Table 2. Pin description (continued)
Function
Pin#
Name
VCORE and NB power good.
It is an open-drain output set free after SS as long as both the voltage planes are
within specifications. Pull-up to 3.3V (typ) or lower, if not used it can be left floating.
35
PWRGOOD
When in PVI mode, it monitors the CORE section only.
NB section high-side driver supply.
This pin supplies the high-side floating driver. Connect through CBOOT capacitor to the
NB_PHASE pin.
36
NB_BOOT
See Section 10 for guidance in designing the capacitor value.
NB Section High-Side Driver Output.
37
38
NB_UGATE
NB_PHASE
Connect to NB Section High-Side MOSFET gate. A small series resistor may help in
reducing NB_PHASE pin negative spike as well as cooling the device.
NB section high-side driver return path.
Connect to the NB section high-side MOSFET source.
This pin is also monitored for the adaptive dead-time management.
CORE section, phase 2 high-side driver supply.
This pin supplies the high-side floating driver. Connect through CBOOT capacitor to the
PHASE2 pin.
39
BOOT2
See Section 10 for guidance in designing the capacitor value.
High-Side Driver Output.
40
41
UGATE2
Connect to Phase2 High-Side MOSFET gate. A small series resistor may help in
reducing PHASE2 pin negative spike as well as cooling the device.
CORE section, phase 2 high-side driver return path. Connect to the phase2 high-side
MOSFET source.
This pin is also monitored for the adaptive dead-time management.
PHASE2
VCCDRV
Supply voltage for low-side embedded drivers.
Operative voltage is flexible from 5V ±5% to 12 ±15%. Filter with 1μF MLCC to GND.
42
Low-side driver output.
NB_LGATE,
LGATE2,
LGATE1
43 to
45
Connect directly to the low-side MOSFET gate of the related section. A small series
resistor can be useful to reduce dissipated power especially in high frequency
applications.
CORe section, phase 1 high-side driver return path. Connect to the phase1 high-side
MOSFET source.
This pin is also monitored for the adaptive dead-time management.
46
47
PHASE1
UGATE1
High-side driver output.
Connect to phase1 high-side MOSFET gate. A small series resistor may help in
reducing PHASE1 pin negative spike as well as cooling the device.
CORE section, phase 1 high-side driver supply.
This pin supplies the high-side floating driver. Connect through CBOOT capacitor to the
PHASE1 pin.
See Section 10 for guidance in designing the capacitor value.
48
BOOT1
GND
Thermal
PAD
All internal references, logic, and the silicon substrate are referenced to this pin.
Connect to the PCB GND ground plane by multiple vias to improve heat dissipation.
14/57
DocID024465 Rev 1
L6717A
Pins description and connection diagrams
2.2
Thermal data
Table 3.Thermal data
Parameter
Symbol
Value
Unit
Thermal resistance junction to ambient
(Device soldered on 2s2p PC board)
RTHJA
40
°C/W
RTHJC
TMAX
TSTG
TJ
Thermal resistance junction to case
Maximum junction temperature
Storage temperature range
1
°C/W
°C
150
-40 to 150
0 to 125
°C
Junction temperature range
°C
DocID024465 Rev 1
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Electrical specifications
L6717A
3
Electrical specifications
3.1
Absolute maximum ratings
Table 4. Absolute maximum ratings
Parameter
Symbol
Value
Unit
VCC,VCCDRV
to GND
-0.3 to 15
V
to GND
to PHASEx
41
15
VBOOTx
VUGATEx
,
V
(VCC=VCCDR=12V )
To GND
-0.3 to 26
VPHASEx
V
Negative spike to GND, t < 400ns
Positive spike to GND, t < 200 ns
-8
30
to GND
to GND, t < 100nsec.
-0.3 to VCCDRV + 0.3
-3
VLGATEx
V
V
All other pins to GND
-0.3 to 3.6
Maximum withstanding voltage range test
condition: CDF-AEC-Q100-002- “Human Body
Model” acceptance “Normal Performance”
±1750
V
3.2
Electrical characteristics
VCC=12V±15%, TJ = 0°C to 70°C unless otherwise specified.
Table 5. Electrical characteristics
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Supply current and power-on
ICC
VCC supply current
VCCDR supply current
BOOTx supply current
VCC turn-ON
15
4
mA
mA
mA
V
ICCDR
IBOOTx
OSC = GND
1.5
VCC rising
VCC falling
4.5
UVLOVCC
Oscillator
FSW
VCC turn-OFF
4
V
Main oscillator accuracy
Oscillator adjustability
PWM ramp amplitude
Voltage at Pin OSC
Turn-OFF threshold
180
425
200
500
1.5
220
575
kHz
kHz
V
ROSC = 36kΩ
ΔVOSC
FAULT
EN
CORE and NB section
OVP, UVP latch active
OSC/EN falling
3
3.6
V
0.3
V
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DocID024465 Rev 1
L6717A
Electrical specifications
Table 5. Electrical characteristics (continued)
Parameter Test conditions Min.
Symbol
PVI / SVI interface
Typ.
Max.
Unit
Input high
1.3
V
V
PWROK
Input low
0.80
Input high
(SVI mode)
(SVI mode)
SINK = -5mA
0.95
V
VID2,/SVD
VID3/SVC
Input low
0.65
250
V
SVD
Voltage low (ACK)
Input high
I
mV
V
(PVI mode)
1.3
3
VID0 to
VID5
Input low
(PVI mode)
0.80
V
V_FIX
Entering V_FIX mode
VID0/V_FIX rising
V
Power manager I2C
Input high
1.3
V
V
SDA, SCL
SDA
Input low
0.8
Voltage low (ACK)
I
SINK = -5mA
250
mV
Voltage positioning (CORE and NB section)
CORE
NB
VSEN to VCORE; FBG to GNDCORE
-8
-10
1.190
0
8
10
mV
mV
V
Output voltage accuracy
NBVSEN to VNB; NBFBG to GNDFB
I2DIS=3.3V, IOS = 0 to 250μA
I2DIS=3.3V
OFFSET bias voltage
OFFSET current range
1.24
1.290
250
2.25
9
μA
μA
μA
μA
μA
dB
OS
I2DIS=3.3V, IOS = 0μA
-2.25
-9
OFFSET - IFB accuracy
DROOP accuracy
I2DIS=3.3V, IOS = 250μA
IDROOP = 0 to 25μA, kDRP = 1/4
-3
3
DROOP
I
NB_DROOP = 0 to 6μA, kNBDRP = 1/4
-1
1
A0
EA DC gain
Slew rate
100
20
SR
COMP, NB_COMP to SGND = 10pF
V/μs
PWM outputs (CORE only) and embedded drivers
Output high
Output low
Test current
I = 1mA
I = -1mA
3
3.6
0.2
V
V
PWM3,
PWM4
IPWMx
10
μA
High current embedded drivers
RHIHS
HS source resistance
HS source current
BOOT - PHASE = 12V; 100mA
2.3
2
2.8
Ω
BOOT - PHASE = 12V; (1)
CUGATE to PHASE = 3.3nF
IUGATE
A
RLOHS
RHILS
HS sink resistance
BOOT - PHASE = 12V; 100mA
100mA
2
2.5
1.8
Ω
Ω
LS source resistance
1.3
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Electrical specifications
L6717A
Unit
Table 5. Electrical characteristics (continued)
Symbol
ILGATE
Parameter
Test conditions
Min.
Typ.
Max.
LS source current
LS sink resistance
CLGATE to GND = 5.6nF; (1)
100mA
3
1
A
RLOLS
1.5
Ω
Protections
I2C enabled, no commands issued,
wrt VID, CORE & NB section
I2C enabled, V_FIX mode;
VSEN, NB_VSEN rising
+200
+250
+300
mV
V
Overvoltage protection
OVP
1.800
SDA/OVP bias current
Undervoltage protection
PGOOD threshold
Voltage low
I2CDIS = 3.3V
9
11
13
μA
mV
mV
V
UVP
VSEN, NB_VSEN falling; wrt Ref.
VSEN, NB_VSEN falling; wrt Ref
IPWRGOOD = -4mA
-450
-285
-400
-250
-350
-215
0.4
PWRGOOD
VCSN rising, above VSEN
CORE and NB sections
VFB-DISC
FB disconnection
600
mV
VFBG DISC
VOC_TOT
FBG disconnection
EA NI input wrt VID
500
mV
V
2.425
0
2.500
2.575
4
CORE OC
ILIM = 0μA
μA
μA
kIILIM
I
LIM = 100μA
100
1. Parameter(s) guaranteed by designed, not fully tested in production
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DocID024465 Rev 1
L6717A
Device description and operation
4
Device description and operation
L6717A is a hybrid CPU power supply controller compatible with both parallel (PVI) and
serial (SVI) protocols for AMD processors. The device provides complete control logic and
protections for a high-performance step-down DC-DC voltage regulator, optimized for
advanced microprocessor power supply supporting both PVI and SVI communication. It
embeds two independent controllers for CPU CORE and the integrated NB, each one with
its own set of protections. NB phase (when enabled) is automatically phase-shifted with
respect to the CORE phases in order to reduce the total input rms current amount.
The device features an additional power manager I2C interface to easy the system design
for enthusiastic application where the main parameters of the voltage regulator have to be
modified. L6717A is able to adjust the regulated voltage, the switching frequency and also
the OV protection threshold through the power manager I2C bus while the application is
running assuring fast and reliable transitions.
Dynamic phase management (DPM) allows the device to automatically adjust the phase
count according to the current delivered to the load. This feature allow the system to keep
alive only the phases really necessary to sustain the load saving in power dissipation so
optimizing the efficiency over the whole current range of the application. DPM can be
enabled through the power manager I2C bus.
L6717A is able to detect which kind of CPU is connected in order to configure itself to work
as a single-plane PVI controller or dual-plane SVI controller.
The controller performs a single-phase control for the NB section and a programmable 2-to-
4 phase control for the CORE section featuring dual-edge non-latched architecture: this
allows fast load-transient response optimizing the output filter consequently reducing the
total BOM cost. Further reduction in output filter can be achieved by enabling LTB
®
Technology .
PSI_L Flag is sent to the VR through the SVI bus. The controller monitors this flag and
selectively modifies the phase number in order to optimize the system efficiency when the
CPU enters low-power states. This causes the over-all efficiency to be maximized at light
loads so reducing losses and system power consumption.
Both sections feature programmable overvoltage protection and adjustable constant
overcurrent protection. Voltage positioning (LL) is possible thanks to an accurate fully-
differential current-sense across the main inductors for both sections.
L6717A features dual remote sensing for the regulated outputs (CORE and NB) in order to
recover from PCB voltage drops also protecting the load from possible feedback network
disconnections.
LSLess start-up function allows the controller to manage pre-biased start-up avoiding
dangerous current return through the main inductors as well as negative undershoot on the
output voltage if the output filter is still charged before start-up.
L6717A supports V_FIX mode for system debugging: in this particular configuration the SVI
bus is used as a static bus configuring 4 operative voltages for both the sections and
ignoring any serial-VID command.
When working in PVI mode, the device features On-the-Fly VID management: VID code is
continuously sampled and the reference update according to the variation detected,
L6717A is available in VFQFPN48 package.
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Hybrid CPU support and CPU_TYPE detection
L6717A
5
Hybrid CPU support and CPU_TYPE detection
L6717A is able to detect the type of the CPU-core connected and to configure itself
accordingly. At system Start-up, on the rising-edge of the EN signal, the device monitors the
status of VID1 and configures the PVI mode (VID1 = 1) or SVI mode (VID1 = 0).
When in PVI mode, L6717A uses the information available on the VID[0: 5] bus to address
the CORE section output voltage according to Table 6. NB section is kept in HiZ mode, both
MOSFETs are kept OFF.
When in SVI mode, L6717A DAC ignores the information available on VID0, VID4 and VID5
and uses VID2 and VID3 as a SVI bus addressing the CORE and NB sections according to
the SVI protocol. The device supports 3.4MHz bus rate frequency.
Caution:
To avoid any risk of errors in CPU type detection (i.e. detecting SVI CPU when PVI CPU is
installed on the socket and vice versa), it is recommended to carefully control the start-up
sequencing of the system hosting L6717A in order to ensure than on the EN rising-edge,
VID1 is in valid and correct state. Typical connections consider VID1 connected to CPU
CORE_TYPE through a resistor to correctly address the CPU detection.
5.1
PVI - parallel interface
PVI is a 6-bit-wide parallel interface used to address the CORE section reference.
According to the selected code, the device sets the CORE section reference and regulates
its output voltage as reported into Table 6.
NB section is always kept in HiZ; no activity is performed on this section and both the high-
side and low-side of this section are kept OFF. Furthermore, PWROK information is ignored
as well since the signal only applies to the SVI protocol.
5.2
PVI start-up
Once the PVI mode has been detected, the device uses the whole code available on the
VID[0:5] lines to define the reference for the CORE section. NB section is kept in HiZ. Soft-
start to the programmed reference is performed regardless of the state of PWROK.
See Section 7.8 for details about soft-start.
Figure 6. System start-up: SVI (to Metal-VID; left) and PVI (right)
PGOOD
PGOOD
EN
EN
V_CORE
V_CORE
V_NB
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DocID024465 Rev 1
L6717A
Hybrid CPU support and CPU_TYPE detection
Table 6. Voltage identifications (VID) codes for PVI mode
Output
voltage
Output
voltage
VID5 VID4 VID3 VID2 VID1 VID0
VID5 VID4 VID3 VID2 VID1 VID0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.5500
1.5250
1.5000
1.4750
1.4500
1.4250
1.4000
1.3750
1.3500
1.3250
1.3000
1.2750
1.2500
1.2250
1.2000
1.1750
1.1500
1.1250
1.1000
1.0750
1.0500
1.0250
1.0000
0.9750
0.9500
0.9250
0.9000
0.8750
0.8500
0.8250
0.8000
0.7750
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.7625
0.7500
0.7375
0.7250
0.7125
0.7000
0.6875
0.6750
0.6625
0.6500
0.6375
0.6250
0.6125
0.6000
0.5875
0.5750
0.5625
0.5500
0.5375
0.5250
0.5125
0.5000
0.4875
0.4750
0.4625
0.4500
0.4375
0.4250
0.4125
0.4000
0.3875
0.3750
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Hybrid CPU support and CPU_TYPE detection
L6717A
5.3
SVI - serial interface
SVI is a two wire, clock and data, bus that connects a single master (CPU) to one slave
(L6717A). The master initiates and terminates SVI transactions and drives the clock, SVC,
and the data, SVD, during a transaction. The slave receives the SVI transactions and acts
accordingly. SVI wire protocol is based on fast-mode I2C.
SVI interface also considers two additional signal needed to manage the system start-up.
These signals are EN and PWROK. The device return a PWRGOOD signal if the output
voltages are in regulation.
5.4
SVI start-up
Once the SVI mode has been detected on the EN rising-edge, L6717A checks for the status
of the two serial VID pins, SVC and SVD, and stores this value as the Pre-PWROK Metal
VID. The controller initiate a soft-start phase regulating both CORE and NB voltage planes
to the voltage level prescribed by the Pre-PWROK Metal VID. See Table 7 for details about
Pre-PWROK Metal VID codifications. The stored Pre-PWROK Metal VID value are re-used
in any case of PWROK de-assertion.
After bringing the output rails into regulation, the controller asserts the PWRGOOD signal
and waits for PWROK to be asserted. Until PWROK is asserted, the controller regulates to
the Pre-PWROK Metal VID ignoring any commands coming from the SVI interface.
After PWROK is asserted, the processor has initialized the serial VID interface and L6717A
waits for commands from the CPU to move the voltage planes from the Pre-PWROK Metal
VID values to the operative VID values. As long as PWROK remains asserted, the controller
will react to any command issued through the SVI interface according to SVI protocol.
See Section 7.8 for details about soft-start.
Table 7. V_FIX mode and Pre-PWROK MetalVID
Output voltage [V]
SVC
SVD
Pre-PWROK Metal VID
V_FIX mode
0
0
1
1
0
1
0
1
1.1V
1.0V
0.9V
0.8V
1.4V
1.2V
1.0V
0.8V
5.4.1
Set VID command
The set VID command is defined as the command sequence that the CPU issues on the SVI
bus to modify the voltage level of the CORE Section and/or the NB section.
During a set VID Command, the processor sends the start (START) sequence followed by
the address of the Section which the set VID command applies. The processor then sends
the write (WRITE) bit. After the write bit, the voltage regulator (VR) sends the acknowledge
(ACK) bit. The processor then sends the VID bits code during the data phase. The VR
sends the acknowledge (ACK) bit after the data phase. Finally, the processor sends the stop
(STOP) sequence. After the VR has detected the stop, it performs an On-the-Fly VID
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transition for the addressed section(s) or, more in general, react to the sent command
accordingly. Refer to Figure 7, Table 8 and Table 9 for details about the set VID command.
L6717A is able to manage individual power OFF for both the sections. The CPU may issue
a serial VID command to power OFF or power ON one section while the other one remains
powered. In this case, the PWRGOOD signal remains asserted.
Figure 7. SVI communications - send byte
ACK
STOP
START
SLAVE ADDRESSING + W
ACK
DATA PHASE
6
5
4
3
0
7
6
0
SVC
SVD
ACK
ACK
110b
START
Slave Addressing
WRITE ACK
(1Ck) (1Ck)
Data Phase
(8 Clocks)
ACK
(1Ck)
STOP
(7 Clocks)
BUS DRIVEN BY L6717
BUS DRIVEN BY MASTER (CPU)
Table 8. SVI send byte - address and data phase description
Description
bits
Address phase
6:4
3
Always 110b.
Not applicable, ignored.
2
Not applicable, ignored.
CORE section(1)
If set then the following data byte contains the VID code for CORE section.
NB section(1)
.
1
.
0
If set then the following data byte contains the VID code for NB section.
Data phase
PSI_L flag (Active low).When asserted, the VR is allowed to enter power-saving
mode. See Section 5.4.3.
7
6:0
VID code. See Table 9.
1. Assertion in both bit 1 and 0 will address the VID code to both CORE and NB simultaneously.
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Table 9. Data phase - serial VID codes
Output
voltage
Output
voltage
Output
voltage
Output
voltage
SVI [6:0]
SVI [6:0]
SVI [6:0]
SVI [6:0]
000_0000
000_0001
000_0010
000_0011
000_0100
000_0101
000_0110
000_0111
000_1000
000_1001
000_1010
000_1011
000_1100
000_1101
000_1110
000_1111
001_0000
001_0001
001_0010
001_0011
001_0100
001_0101
001_0110
001_0111
001_1000
001_1001
001_1010
001_1011
001_1100
001_1101
001_1110
001_1111
1.5500
1.5375
1.5250
1.5125
1.5000
1.4875
1.4750
1.4625
1.4500
1.4375
1.4250
1.4125
1.4000
1.3875
1.3750
1.3625
1.3500
1.3375
1.3250
1.3125
1.3000
1.2875
1.2750
1.2625
1.2500
1.2375
1.2250
1.2125
1.2000
1.1875
1.1750
1.1625
010_0000
010_0001
010_0010
010_0011
010_0100
010_0101
010_0110
010_0111
010_1000
010_1001
010_1010
010_1011
010_1100
010_1101
010_1110
010_1111
011_0000
011_0001
011_0010
011_0011
011_0100
011_0101
011_0110
011_0111
011_1000
011_1001
011_1010
011_1011
011_1100
011_1101
011_1110
011_1111
1.1500
1.1375
1.1250
1.1125
1.1000
1.0875
1.0750
1.0625
1.0500
1.0375
1.0250
1.0125
1.0000
0.9875
0.9750
0.9625
0.9500
0.9375
0.9250
0.9125
0.9000
0.8875
0.8750
0.8625
0.8500
0.8375
0.8250
0.8125
0.8000
0.7875
0.7750
0.7625
100_0000
100_0001
100_0010
100_0011
100_0100
100_0101
100_0110
100_0111
100_1000
100_1001
100_1010
100_1011
100_1100
100_1101
100_1110
100_1111
101_0000
101_0001
101_0010
101_0011
101_0100
101_0101
101_0110
101_0111
101_1000
101_1001
101_1010
101_1011
101_1100
101_1101
101_1110
101_1111
0.7500
0.7375
0.7250
0.7125
0.7000
0.6875
0.6750
0.6625
0.6500
0.6375
0.6250
0.6125
0.6000
0.5875
0.5750
0.5625
0.5500
0.5375
0.5250
0.5125
0.5000
0.4875
0.4750
0.4625
0.4500
0.4375
0.4250
0.4125
0.4000
0.3875
0.3750
0.3625
110_0000
110_0001
110_0010
110_0011
110_0100
110_0101
110_0110
110_0111
110_1000
110_1001
110_1010
110_1011
110_1100
110_1101
110_1110
110_1111
111_0000
111_0001
111_0010
111_0011
111_0100
111_0101
111_0110
111_0111
111_1000
111_1001
111_1010
111_1011
111_1100
111_1101
111_1110
111_1111
0.3500
0.3375
0.3250
0.3125
0.3000
0.2875
0.2750
0.2625
0.2500
0.2375
0.2250
0.2125
0.2000
0.1875
0.1750
0.1625
0.1500
0.1375
0.1250
0.1125
0.1000
0.0875
0.0750
0.0625
0.0500
0.0375
0.0250
0.0125
OFF
OFF
OFF
OFF
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5.4.2
PWROK de-assertion
Anytime PWROK de-asserts while EN is asserted, the controller uses the previously stored
Pre-PWROK Metal VID and regulates all the planes to that level performing an on-the-fly
transition to that level.
PWRGOOD is treated appropriately being de-asserted in case the Pre-PWROK Metal VID
voltage is out of the initial voltage specifications.
5.4.3
PSI_L and efficiency optimization at light-load
PSI_L is an active-low flag (i.e. low logic level when asserted) that can be set by the CPU to
allow the VR to enter power-saving mode to maximize the system efficiency when in light-
load conditions. The status of the flag is communicated to the controller through the SVI
bus.
When the PSI_L flag is asserted by the CPU through the SVI bus, the device adjusts the
phase number and interleaving according to the strategy programmed. Default strategy,
when enabled, consists in working in single phase. PSI strategy can be disabled as well as
re-configured through specific power manager I2C commands. See Section 6 for details.
In case the phase number is changed, the device will set HiZ on the related phase and re-
configure internal phase-shift to maintain the interleaving. Furthermore, the internal current-
sharing will be adjusted to consider the phase number reduction.
When PSI_L is de-asserted, the device will return to the original configuration. Start-up is
performed with all the configured phases enabled. In case of on-the-fly VID transitions, the
device will maintain the phase configuration set before.
NB section is not impacted by PSI_L status change. Figure 8 shows an example of the
efficiency improvement that can be achieved by enabling the PSI management.
Figure 8. System efficiency enhancement by PSI
5.4.4
HiZ management
L6717A is able to manage HiZ for internal drivers and for the external drivers through the
PWMx signals. When the controller wants to set in high impedance the output of one
section, it sets the relative PWM floating and, at the same time, turn OFF the embedded
drivers of the related section.
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5.4.5
Hardware jumper override - V_FIX
Anytime the pin VID0/V_FIX is driven high, the controller enters V_FIX mode.
When in V_FIX mode, both NB and CORE Section voltages are governed by the information
shown in Table 7. Regardless of the state of PWROK, the device will work in SVI mode.
SVC and SVD are considered as static VID and the output voltage will change according to
their status. Dynamic SVC/SVD-change management is provided in this condition.
V_FIX mode is intended for system debug only.
Protection management differs in this case, see Section 8.1 for details.
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6
Power manager I2C
L6717A features a secondary power manager I2C bus to easy the implementation of power
management features as well as overspeeding for “enthusiastic” users. The power manager
I2C bus is operative after the PWRGOOD signal is driven high at the end of the soft-start.
Power manager I2C is a two wire, SCL (Clock) and SDA (Data), bus that connects a single
master to one or more slaves (L6717A) separately addressable. The master initiates and
terminates I2C transactions and drives the clock, SCL, and the data, SDA, during a
transaction. The slave receives the I2C transactions and acts accordingly. Power manager
I2C wire protocol is based on fast-mode I2C.
Power manager I2C Address configuration can be programmed through ADDR pin while
I2CDIS pin allow disabling the bus See Table 10.
Power manager I2C and SVI bus are two independent buses working in parallel. In case two
commends are issued in the same time on the two buses, L6717A performs them in the
same time.
Table 10. Power manager I2C configuration
I2CDIS
ADDR
Description
Power manager I2C disabled.
SDA/OVP now becomes OVP to program the OV threshold for
both Sections.
3.3V
n/a
SCL/OS now becomes OS to program offset for the CORE
Section.
3.3V
It sets I2C address to 1100111.
It sets I2C address to 1100110 (default).
OPEN
OPEN
6.1
Power manager commands
Power manager I2C master issues different command sequences to modify several
parameters in the CORE section and/or the NB section of L6717A. In the same way, power
manager I2C command are able to configure DPM and other power-saving-related features.
During a power manager command:
– The bus master sends the start (START) sequence followed by the Address of the
Controller which the power manager command applies. The bus master then sends
the write (WRITE) bit. After the write bit, the voltage regulator (VR, L6717A) sends the
acknowledge (ACK) bit.
– The bus master sends the command code during the command phase. The VR
(L6717A) sends the acknowledge (ACK) bit after the command phase.
– The bus master sends the data stream related to the command phase previously
issued (if applicable). The VR (L6717A) sends the acknowledge (ACK) bit after the
data stream. Finally, the bus master sends the stop (STOP) sequence.
– After the VR (L6717A) has detected the STOP sequence, it performs operations
according to the command issued by the bus master.
Refer to Figure 9, Table 11 and Table 12 for details.
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Figure 9. Power manager I2C communication format
COMMAND
Table 11. Power manager I2C - address and command phase description
bits
Description
Address phase
1:6
Always 110011b.
Slave address.
7
According to ADDR connection, the device will act if addressed by 0b or 1b.
Default address bit is 0b.
8
WRITE bit.
COMMAND PHASE
1:3
4:6
7, 8
Not applicable, ignored.
Command code
Not applicable, ignored.
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Table 12. Power manager I2C command phase and data stream
Command
code [4:6]
Data stream
[1:8]
Description
OVERSPEEDING: Adds a positive/negative offset to the regulation
according to the SIGN bit with 50mV LSB and 5bit resolution.
[3] SIGN: 1b for positive offset, 0b for negative offset.
Negative offset is applicable only to CORE section (NB does not react
to negative OS commad)
[4:8] OVRSPD: 5bit code (4:LSB to 8:MSB), defines the offset to add
to the already programmed reference (VID).
[1:2] xx
[3] SIGN
1CN
Maximum CORE output voltage reachable is limited to 2.8V.
Maximum NB output voltage reachable is limited by the Maximum NB
Offset: +600mV (over VID)
[4:8] OVRSPD
“CN” bits in command code address CORE section (“C” bit) or NB
section (“N” bit) if set to 1b. Asserting both C and N bits will apply the
command to both CORE and NB section.
See Table 13 for details about OVRSPD codification.
OV_SET: Overvoltage threshold setup for CORE and/or NB sections.
Sets the OV threshold above the programmed VID (including
OVRSPD) in with three 200mV steps from + 250mV up to +850mV.
[1:4]: ignored
[1:4] xxxx
[5:6] OV_NB
[7:8] OV_CORE
[5:6] OV_NB: NorthBridge OVP. 2bit code, defines the OV threshold
for the NB section above the already programmed reference (VID).
[7:8] OV_CORE: Core OVP. 2bit code, defines the OV threshold for
000
the CORE section above the already programmed reference (VID).
Default OV threshold is +250mV above reference for both sections.
See Table 14 for details about OV_SET codification.
FSW_ADJ: Switching frequency adjustment. Modifies the switching
frequency programmed through OSC pin according to FSW code by
+/- 10% or +/-20%.
[1:5] xxxxx
[6:8] FSW
[1:5]: ignored
001
[6:8]: FSW: Switching frequency adjustment. 3 bits code to adjust the
switching frequency with respect programmed voltage.
See Table 15 for details about FSW_ADJ codification.
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Table 12. Power manager I2C command phase and data stream (continued)
Command
code [4:6]
Data stream
[1:8]
Description
DRP_ADJ: Droop function adjustment. Modifies the slope of the
output voltage implemented through the droop function.
[1:4]: ignored
[1:4] xxxx
[5:6] kDRP
[7:8] kDRPNB
[5:6]: kDRP. Defines the kDRP factor for CORE section.
[7:8]:kDRPNB. Defines the kDRPNB factor for NB section.
Default value is kDRPx = 1/4 for both sections.
010
See Table 16 for details about DRP_ADJ codification and Section 7.3
and Section 7.6 for LoadLine definition.
Power management flags: Set of three flags to define power
management actions of the controller.
[1:3]: 000b.
[4:5]: DPM Thresholds. Default is 00b.
[6] PSI_A: PSI Action. It defines the action to take when PSI_L flag is
asserted by SVI bus. The same action is considered by DPM. Send
0b to work in single phase (default) or 1b to work at two phases.
[1:3] 000b
[4:5] DPMTH
[6] PSI_A
[7] PSI_EN: PSI Enable. It enables or disables the PSI management.
Set to 1b to manage PSI_L according to PSI_A or set to 0b (default)
to ignore PSI_L flag sent through SVI bus.
[8] DPM_ON: Dynamic Phase Management. It enables or disables
the DPM mode. Set to 1b (default) to enable DPM or set to 0b to
disable it.
011
[7] PSI_EN
[8] DPM_ON
When enabled DPM acts automatically cutting phases according to
PSI Action flag at light load.
See Section 6.2 for details about DPM.
6.1.1
Overspeeding command (OVRSPD)
This command allows adding a variable positive/negative offset to the reference
programmed by the SVI bus in order to overspeed the CPU. L6717A allows adding up to
1.550 V in 50 mV steps to the reference.
The maximum possible output voltage is internally limited to 2.8 V. In case the SVI
programmed reference plus the offset set through the OVRSPD command exceed this
value, the reference for the regulation will default to 2.8 V.
The minimum possible output voltage is internally limited to 0.5 V. In case the SVI
programmed reference minus the offset set through the OVRSPD command exceed this
value, the reference for the regulation will default to 0.5 V.
Once the controller acknowledges the command and recognizes the OVRSPD command,
the reference will step up or down until reaching the target offset performing a DVID
transition. In case a new overspeed command is issued while the output voltage is not yet
stabilized (i.e. the reference is still stepping to the target), the target is updated according to
the new offset defined.
The command address both sections through two separate bits in the command code (“CN”
bits - See Table 12). By asserting the relative bit, the subsequent data stream will apply to
the identified section. Asserting both bits (CN = 11b) will address both sections. CN = 00b
will be ignored regardless of the data stream provided.
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See Table 12 and Table 13 for details about the codification of the command and the data
stream.
Table 13. OVRSPD command - offset codification (1) (2)
Data
stream
[4:8]
Offset to
reference
[V]
Data
stream
[4:8]
Offset to
reference
[V]
Data
stream
[4:8]
Offset to
reference
[V]
Data
stream
[4:8]
Offset to
reference
[V]
00000
00001
00010
00011
00100
00101
00110
00111
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
01000
01001
01010
01011
01100
01101
01110
01111
0.40
0.45
0.50
0.55
0.60
0.65
0.70
0.75
10000
10001
10010
10011
10100
10101
10110
10111
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
11000
11001
11010
11011
11100
11101
11110
11111
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1. Offset is added with an OTF VID transition above the already programmed VID.
2. Maximum regulated output voltage is internally limited to 2.8 Vmax/0.5 Vmin regardless the offset would let
the IC regulate to higher/lower voltage.
6.1.2
Overvoltage threshold adjustment (OV_SET)
This command allows to adjust the overvoltage threshold independently for CORE and NB
Sections. The threshold is adjustable, from the default value of +250 mV, in 200 mV steps
up to +800 mV above the reference.
See Table 12 and Table 14 for details about the codification of the command and the data
stream.
Table 14. OVP_SET command - threshold codification
Data stream [5:6] and [7:8]
OVP threshold [V]
00
01
10
11
+250mV (Default)
+400mV
+600mV
+800mV
6.1.3
Switching frequency adjustment (FSW_ADJ)
This command allows to adjust the switching frequency for the system in +/-10% steps
across the main level defined by the OSC pin. Modifying the switching frequency may result
in benefit for the application from a thermal point of view.
See Table 12 and Table 15 for details about the codification of the command and the data
stream.
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Table 15. FSW_ADJ command - switching frequency adjustment codification
Data stream
Data stream
[6:8]
Fsw adjustment
Fsw adjustment
[6:8]
Reset to frequency
programmed by OSC
Reset to frequency
programmed by OSC
000
100
001
010
011
-10%
-20%
101
110
111
+10%
+20%
Ignored
Ignored
6.1.4
Droop function adjustment (DRP_ADJ)
This command allows to adjust the slope for the output voltage load line once the external
components are fixed by modifying the kDRP and kDRPNB parameters defined in Section 7.3
and Section 7.6.
See Table 12 and Table 16 for details about the codification of the command and the data
stream.
Table 16. DRP_ADJ command - droop function adjustment codification
Data stream [5:6] and [7:8]
DRP adjustment kDRP and kDRPNB
00
01
10
11
1/4
1/2
Droop disabled
6.1.5
Power management flags
This command allows to set several flags to configure L6717A power management. The
flags allows to define:
– PSI_A. This flag defines the strategy to adopt as a consequence of PSI_L assertion in
the SVI command. It is possible to program the device to work in single phase (PSI_A
= 0b - default) or two phase (PSI_A = 1b) when PSI_L is asserted through the SVI
bus. The same strategy is used for DPM mode.
See Section 5.4.3 for details about PSI management and light-load efficiency
optimizations. See Section 6.2 for details about DPM.
– PSI_EN. This flag defines whether to enable or not the PSI_L management. Default
is to manage PSI_L flag assertion through SVI bus (PSI_EN = 1b).
– DPM_ON. This flag defines whether to enable or not the DPM mode. The strategy
adopted by DPM is defined through the PSI_A flag. See Section 6.2 for details about
DPM. DPM is disabled by default (DPM_ON = 0h).
– DPMTH. Allow to program up to 4 different strategies for DPM mode by properly
adjusting the VDPM threshold. See Section 6.2 for details about DPM.
See Table 12, Table 17 and Table 19 for details about the codification of the Command and
the Data Stream.
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Table 17. Power management flags
Flag Description
n/a
Data Stream bit
[1:3]
000b.
DPM threshold. Allow to define 4 different values for VDPM
.
[4:5]
[6]
DPMTH
PSI_A
See Section 6.2 for code/thresholds correspondence.
0b (default): IC working in single phase when PSI_L asserted.
1b:IC working in two phase when PSI_L asserted.
0b (default): PSI_L flag in SVI ignored.
1b: PSI_L flag in SVI monitored and phase dropping enabled
according to PSI_A.
[7]
[8]
PSI_EN
0b: DPM disabled.
1b (default): DPM enabled.
DPM_ON
6.2
Dynamic phase management (DPM)
Dynamic phase management allows to adjust the number of working phases according to
the delivered current still maintaining the benefits of the multiphase regulation.
Phase number is reduced by monitoring the voltage level across ILIM pin: L6717A reduces
the number of working phase according to the strategy defined by the PSI_A flag when the
voltage across ILIM pin is lower than VDPM. In the same way, phase number is restored to
the original value when the voltage across ILIM pin exceeds VDPM
.
V
DPM threshold is selected through the DPMTH command. See Section 6.1.
The current at which the transition happens (IDPM) can be estimated as:
VDPM RG
IDPM = -------------- ⋅ -------------
RILIM DCR
VDPM thresholds are defined as a percentage of the voltage on ILIM pin corresponding to
the thermal design current of the application.
1.8 V on ILIM pin corresponds to 100% of the load and DPM threshold are defined as a
percentage of 1.8 V (see Table 18 for details).
An hysteresis (5 % typ) is provided for each threshold in order to avoid multiple DPM actions
triggering in steady load conditions.
Table 18. VDPM thresholds (ILIM rising - 5% hyst)
CODE
1/2 phase transition
2/3 phase transition
3/4 phase transition
00 (default)
15%
20%
25%
30%
25%
30%
35%
40%
40%
45%
50%
55%
01
10
11
DPM is enabled by default; to disable it proper command must be sent through the power
manager I2C bus. Once enabled, L6717A starts monitoring the ILIM voltage for phase
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number modification after PWRGOOD rises to logic level “1”: the soft-start is then
implemented in interleaving mode with all the available phases enabled.
DPM is reset in case of DVID transition, SVI command that affects the CORE Section and
when LTB Technology® detects a load transient. After being reset, if the voltage across ILIM
is compatible, DPM is re-enabled after proper delay.
Delay in the intervention of DPM can be adjusted by properly sizing the filer across ILIM pin.
Increasing the capacitance results in increased delay in the DPM intervention.
Filter ILIM with 0.5 msec Typ.
Table 19. DPM, PSI and PSI_A Interactions
Working
PSI_A
PSI_ON DPM_ON
Comments
mode
Automatic phase number adjustment (4/3/2/1) according to the
load conditions. PSI flag is ignored.
Default condition.
0
0
1
FullDPM1
Automatic phase number adjustment (4/3/2) according to the
load conditions. PSI flag is ignored.
1
0
1
x
0
1
0
1
1
0
1
1
1
1
1
0
0
0
FullDPM2
AutoPSI1
AutoPSI2
Automatic PSI according to the load conditions (4/1). PSI flag is
ignored.
Automatic PSI according to the load conditions (4/2). PSI flag is
ignored.
No Power
Management
DPM OFF, AutoPSI OFF, PSI PFlag ignored.
DPM and AutoPSI disabled. PSI Flag, when asserted, makes
the IC working in single phase.
PSI1
PSI2
DPM and AutoPSI disabled. PSI Flag, when asserted, makes
the IC working in dual phase.
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7
Output voltage positioning
Output voltage positioning is performed by selecting the controller operative-mode (SVI, PVI
and V_FIX) and by programming the droop function and offset to the reference of both the
sections (See Figure 10). The controller reads the current delivered by each section by
monitoring the voltage drop across the DCR inductors. The current (IDROOP / IDROOP_NB
sourced from the FB / NB_FB pin, directly proportional to the read current, causes the
related section output voltage to vary according to the external RFB / RFB_NB resistor so
implementing the desired load-line effect.
)
L6717A embeds a dual Remote-Sense Buffer to sense remotely the regulated voltage of
each Section without any additional external components. In this way, the output voltage
programmed is regulated compensating for board and socket losses. Keeping the sense
traces parallel and guarded by a power plane results in common mode coupling for any
picked-up noise.
Figure 10. Voltage positioning
Offset from Power Manager I2C
(Active when enabled)
Operative only when Power Manager I2C disabled
from SVI DAC...
Clamp to 2.8Vmax
CORE_REFERENCE
1.2V
CORE Protection
Monitor
SCL/OS
FB
COMP
CF
VSEN
FBG
ROS
RF
To VDD_CORE
(Remote Sense)
RFB
from DAC...
NB_REFERENCE
NB Protection
Monitor
NB_FB
NB_COMP
CF_NB
NB_VSEN
NB_FBG
RF_NB
To VDD_NB
(Remote Sense)
RFB_NB
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7.1
CORE section - phase # programming
CORE section implements a flexible 2 to 4 interleaved-phase converter. To program the
desired number of phase, simply short to GND the PWMx signal that is not required to be
used according to Table 20. For three phase operation, short PWM4 to GND while for two
phase operation, short PWM3 and PWM4 to GND.
Caution:
For the disabled phase(s), the current reading pins need to be properly connected to avoid
errors in current-sharing and voltage-positioning: CSxP needs to be connected to the
regulated output voltage while CSxN needs to be connected to CSxP through the same RG
resistor used for the active phases. See Figure 2 and Figure 3 for details in 3-phase and 2-
phase connections.
Table 20. CORE section - phase number programming
Phase number
PWM3
PWM4
2
3
4
GND
GND
GND
To Driver
To Driver
To Driver
7.2
CORE section - current reading and current sharing loop
L6717A embeds a flexible, fully-differential current sense circuitry for the CORE section that
is able to read across inductor parasitic resistance or across a sense resistor placed in
series to the inductor element. The fully-differential current reading rejects noise and allows
placing sensing element in different locations without affecting the measurement's accuracy.
The trans-conductance ratio is issued by the external resistor RG placed outside the chip
between CSxN pin toward the reading points. The current sense circuit always tracks the
current information, the pin CSxP is used as a reference keeping the CSxN pin to this
voltage. To correctly reproduce the inductor current an R-C filtering network must be
introduced in parallel to the sensing element. The current that flows from the CSxN pin is
then given by the following equation (See Figure 11):
DCR 1 + s ⋅ L ⁄ DCR
ICSxN = ------------- ⋅ ------------------------------------- ⋅ I
RG
1 + s ⋅ R ⋅ C
PHASEx
Considering now to match the time constant between the inductor and the R-C filter applied
(Time constant mismatches cause the introduction of poles into the current reading network
causing instability. In addition, it is also important for the load transient response and to let
the system show resistive equivalent output impedance) it results:
RL
RG
L
------------- = R ⋅ C
DCR
ICSxN = ------- ⋅ IPHASEx = IINFOx
RG resistor is typically designed in order to have an information current IINFOx in the range of
about 35μA (IOCTH) at the OC Threshold.
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Output voltage positioning
Figure 11. Current reading
IPHASEx
Lx DCRx
VOUT
ICSxN=IINFOx
R
C
CSxN
CSxP
RG
Inductor DCR Current Sense
The current read through the CSxP / CSxN pairs is converted into a current IINFOx
proportional to the current delivered by each phase and the information about the average
current IAVG = ΣIINFOx / N is internally built into the device (N is the number of working
phases). The error between the read current IINFOx and the reference IAVG is then converted
into a voltage that with a proper gain is used to adjust the duty cycle whose dominant value
is set by the voltage error amplifier in order to equalize the current carried by each phase.
7.3
CORE section - defining load-line
L6717A introduces a dependence of the output voltage on the load current recovering part
of the drop due to the output capacitor ESR in the load transient. Introducing a dependence
of the output voltage on the load current, a static error, proportional to the output current,
causes the output voltage to vary according to the sensed current.
Figure 11 shows the current sense circuit used to implement the load-line. The current
flowing across the inductor(s) is read through the R - C filter across CSxP and CSxN pins.
RG programs a trans-conductance gain and generates a current ICSx proportional to the
current of the phase. The sum of the ICSx current, with proper gain defined by the DRP_ADJ
command (kDRP), is then sourced by the FB pin (kDRP DROOP
I
). RFB gives the final gain to
program the desired load-line slope (Figure 10).
Time constant matching between the inductor (L / DCR) and the current reading filter (RC) is
required to implement a real equivalent output impedance of the system so avoiding over
and/or under shoot of the output voltage as a consequence of a load transient. See
Section 7.2. The output characteristic vs. load current is then given by:
DCR
VCORE = VID – RFB ⋅ kDRP ⋅ IDROOP = VID – kDRP ⋅ RFB ⋅ ------------- ⋅ IOUT = VID – RLL ⋅ IOUT
RG
Where RLL is the resulting load-line resistance implemented by the CORE section. kDRP
value is determined by the power manager I2C and its default value is 1/4.
R
FB resistor can be then designed according to the RLL specifications and DRP_ADJ setting
as follow:
RLL
RG
RFB = ------------- ⋅ -------------
kDRP DCR
See Section 6.2 for details about DRP_ADJ command.
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Output voltage positioning
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7.4
CORE section - analog offset (Optional - I2CDIS = 3.3 V)
When power manager I2C is disabled (I2CDIS = 3.3 V), L6717A still provide the way to add
positive/negative offset to the CORE section. In this particular conditions, the pin SCL/OS
becomes a virtual ground and allows programming a positive/negative offset (VOS) for the
CORE section output voltage by connecting a resistor ROS to SGND/VCC. The pin is
internally fixed at 1.240 V (2.0 V in case of negative offset, ROS tied to VCC) so a current is
programmed by connecting the resistor ROS between the pin and SGND/VCC: this current
is mirrored and then properly sunk/sourced from the FB pin as shown in Figure 10. Output
voltage is then programmed as follow:
VCORE = VID – RFB ⋅ (kDRP ⋅ IDROOP – IOS
)
Offset resistor can be designed by considering the following relationship (RFB is be fixed by
the droop effect):
1.240V
ROS = ------------------ ⋅ RFB (positive offset)
VOS
VCC – 2.0V
ROS = ------------------------------- ⋅ RFB (negative offset)
VOS
Caution:
Offset implementation is optional, in case it is not desired, simply short the pin to GND.
Note:
In the above formulas, RFB has to be considered being the total resistance connected
between FB pin and the regulated voltage. kDRP has to be considered having its default
value since power manager I2C is disabled.
7.5
NB section - current reading
NB section performs the same differential current reading across DCR as the CORE
Section. According to Section 7.2, the current that flows from the NB_CSN pin is then given
by the following equation (See Figure 11):
DCR(NB)
INB_CSN = ------------------------ ⋅ INB = IDROOP_NB
RG_NB
R
G_NB resistor is typically designed according to the OC threshold. See Section 8.4 for
details.
7.6
NB section - defining load-line
This method introduces a dependence of the output voltage on the load current recovering
part of the drop due to the output capacitor ESR in the load transient. Introducing a
dependence of the output voltage on the load current, a static error, proportional to the
output current, causes the output voltage to vary according to the sensed current.
Figure 11 shows the current sense circuit used to implement the load-line. The current
flowing across the inductor DCR is read through RG_NB. RG_NB programs a trans-
conductance gain and generates a current IDROOP_NB proportional to the current delivered
by the NB section that is then sourced from the NB_FB pin with proper gain defined by the
DRP_ADJ command (kDRPNB). RFB_NB gives the final gain to program the desired load-line
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Output voltage positioning
slope (Figure 10).
The output characteristic vs. load current is then given by:
VOUT_NB= VID – RFB_NB ⋅ kDRPNB ⋅ IDROOP_NB
DCR
VID – RFB_NB ⋅ kDRPNB ⋅ ---------------- ⋅ IOUT = VID – RLL_NB ⋅ IOUT_NB
RG_NB
Where RLL_NB is the resulting load-line resistance implemented by the NB section. kDRPNB
value is determined by the power manager I2C and its default value is 1/4.
R
FB_NB resistor can be then designed according to the RLL_NB specifications and DRP_ADJ
setting as follow:
RLL_NB RISEN
RFB_NB = -------------------- ⋅ ----------------
kDRPNB RdsON
7.7
On-the-fly VID transitions
L6717A manages on-the-fly VID Transitions that allow the output voltage of both sections to
modify during normal device operation for CPU power management purposes. OV, UV and
PWRGOOD signals are masked during every OTF-VID Transition and they are re-activated
with a 16 clock cycle delay to prevent from false triggering.
When changing dynamically the regulated voltage (OTF-VID), the system needs to charge
or discharge the output capacitor accordingly. This means that an extra-current IOTF-VID
needs to be delivered (especially when increasing the output regulated voltage) and it must
be considered when setting the over current threshold of both the sections. This current
results:
dVOUT
IOTF-VID = COUT ⋅ -----------------
dTVID
where dVOUT / dTVID depends on the operative mode (7 mV/μsec. in SVI or externally driven
in PVI).
Overcoming the OC threshold during the dynamic VID causes the device latch and disable.
Dynamic VID transition is managed in different ways according to the device operative
mode:
•
PVI mode.
L6717A checks for VID code modifications (See Figure 12) on the rising-edge of an
internal additional OTFVID-clock and waits for a confirmation on the following falling
edge. Once the new code is stable, on the next rising edge, the reference starts
stepping up or down in LSB increments every two OTFVID-clock cycle until the new
VID code is reached. During the transition, VID code changes are ignored; the device
re-starts monitoring VID after the transition has finished on the next rising-edge
available. OTFVID-clock frequency (FOTFVID) is 500 kHz.
If the new VID code is more than 1 LSB different from the previous, the device will
execute the transition stepping the reference with the OTFVID-clock frequency FOTFVID
until the new code has reached. The output voltage rate of change will be of 12.5 mV /
4 μsec. = 3.125 mV/μsec.
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Figure 12. PVI mode - on-the-fly VID transitions
OTFVID Clock
VID [0:5]
t
t
Int. Reference
TOTFVID
T
sw
t
t
V
out
TVID
x 4 Step VID Transition
4 x 1 Step VID Transition
Vout Slope Controlled by internal
OTFVID-Clock Oscillator
Vout Slope Controlled by external
driving circuit (TVID
)
•
SVI mode.
As soon as the controller receives a new valid command to set the VID level for one (or
both) of the two sections, the reference of the involved section steps up or down
according to the Target-VID with a 7 mV/μsec. slope (Typ). until the new VID code is
reached.
If a new valid command is issued during the transition, the device updates the Target-
VID level and performs the on-the-fly transition up to the new code.Pre-PWROK Metal
VID
OTF-VID are not managed in this case because the Pre-PWROK Metal VID are stored
after EN is asserted.
•
V_FIX mode.
L6717A checks for SVC/SVD modifications and, once the new code is stable, it steps
the reference of both sections up or down according to the Target-VID with a
7 mV/μsec. slope (Typ). until the new VID code is reached.
OV, UV and PWRGOOD are masked during the transition and re-activated with a 16 clock
cycle delay after the end of the transition to prevent from false triggering.
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Output voltage positioning
7.8
Soft-start
L6717A implements a soft-start to smoothly charge the output filter avoiding high in-rush
currents to be required to the input power supply. In SVI mode, soft-start time is intended as
the time required by the device to set the output voltages to the Pre-PWROK Metal VID.
During this phase, the device increases the reference of the enabled section(s) from zero up
to the programmed reference in closed loop regulation. Soft-start is implemented only when
VCC is above UVLO threshold and the EN pin is set free. See Section 5 for details about the
SVI interface and how SVC/SVD are interpreted in this phase.
At the end of the digital soft-start, PWRGOOD signal is set free.
Protections are active during this phase as follow:
–
–
–
Undervoltage is enabled when the reference voltage reaches 0.5 V.
Overvoltage is always enabled according to the programmed threshold (by ROVP).
FBDisconnection is enabled.
Reference is increased with fixed dV/dt; Soft-Start time depends on the programmed voltage
as follow:
TSS[ms] = Target_VID ⋅ 2.56
Figure 13. System start-up: SVI (left) and PVI (right)
PGOOD
PGOOD
EN
EN
V_CORE
V_CORE
V_NB
7.8.1
LS-Less start-up
In order to avoid any kind of negative undershoot on the load side during start-up, L6717A
performs a special sequence in enabling the drivers for both sections: during the soft-start
phase, the LS MOSFET is kept OFF (PWMx set to HiZ and ENDRV = 0) until the first PWM
pulse. After the first PWM pulse, the PWMx outputs switches between logic “0” and logic “1”
and ENDRV are set to logic “1”.
This particular sequence avoids the dangerous negative spike on the output voltage that
can happen if starting over a pre-biased output especially when exiting from a CORE-OFF
state.
Low-side MOSFET turn-on is masked only from the control loop point of view: protections
are still allowed to turn-ON the low-side MOSFET in case of over voltage if needed.
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Output voltage monitoring and protections
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8
Output voltage monitoring and protections
L6717A monitors the regulated voltage of both sections through pin VSEN and NB_VSEN in
order to manage OV, UV and PWRGOOD. The device shows different thresholds when in
different operative conditions but the behavior in response to a protection event is still the
same as described below.
Protections are active also during soft-start (See Section 7.8) while they are masked during
OTF-VID transitions with an additional delay to avoid false triggering.
Table 21.L6717A protection at a glance
Section
L6717A
CORE
North bridge
SVI / PVI: +250mV above reference, programmable by power manager I2C bus.
I2CDIS = 3.3V: Programmable through SDA/OVP pin.
V_FIX: Fixed to 1.8V.
Overvoltage
(OV)
Action: IC latch; LS=ON & PWMx = 0 (if applicable);
Other section (SVI only): HiZ; FLT driven high.
VSEN, NB_VSEN = VID -400mV. Active after Ref > 500mV
Action: IC latch; both sections HiZ; FLT driven high.
Undervoltage (UV)
PWRGOOD is the logic AND between internal CORE and NB PGOOD in SVI
mode while is the CORE section PGOOD in PVI mode.
PWRGOOD
Each PGOOD is set to zero when the related voltage falls below the
programmed reference -250mV.
Action: Section(s) continue switching, PWRGOOD driven low.
Set when VSEN > CS1N +600mV.
Action: UV-Like
Set when VSEN > NB_CSN +600mV.
Action: UV-Like (SVI only)
VSEN, NB_VSEN
disconnection
Internal comparator across the opamp to recover from GND losses.
Action: UV-Like
FBG, NB_FBG
disconnection
Current monitor across inductor DCR.
Dual protection, per-phase and
average.
Action: UV-Like
Current monitor across inductor DCR.
Constant current.
Overcurrent (OC)
Action: UV-Like
Protections masked with the exception of OC with additional 16 clock delay to
prevent from false triggering (both SVI and PVI).
On-the-fly VID
8.1
Programmable overvoltage (I2DIS = 3.3 V)
When power manager I2C is disabled, L6717A provides the possibility to adjust OV
threshold (common for both Sections) through the SDA/OVP pin. Connecting the pin to
SGND through a resistor ROVP, the OVP threshold becomes the voltage present at the pin.
Since the SDA/OVP pin sources a constant IOVP=10μA current, the programmed over
voltage threshold will be OVPTH=ROVP*10μA.
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Output voltage monitoring and protections
When the voltage sensed by VSEN and/or NB_VSEN overcomes the OV threshold, the
controller:
–
Permanently sets the PWM of the involved section to zero keeping ENDRV of that
section high in order to keep all the Low-Side MOSFETs on to protect the load of
the Section in OV condition.
–
Permanently sets the PWM of the non-involved section to HiZ while keeping
ENDRV of the non-involved section low in order to realize an HiZ condition of the
non-involved section.
–
–
Drives the OSC/ FLT pin high.
Power supply or EN pin cycling is required to restart operations.
Filter OVP pin with 100 pF(typ) to SGND.
8.2
Feedback disconnection
L6717A provides both CORE and NB sections with FB disconnection protection. This
feature acts in order to stop the device from regulating dangerous voltages in case the
remote sense connections are left floating. The protection is available for both the sections
and operates for both the positive and negative sense.
According to Figure 14, the protection works as follow:
•
CORE section:
Positive sense is performed monitoring the CORE output voltage through both VSEN
and CS1N. As soon as CS1N is more than 600 mV higher than VSEN, the device
latches in HiZ. FLT pin is driven high. A 50 μA pull-down current on the VSEN forces
the device to detect this fault condition.
Negative sense is performed monitoring the internal opamp used to recover the GND
losses by comparing its output and the internal reference generated by the DAC. As
soon as the difference between the output and the input of this opamp is higher than
500 mV, the device latches in HiZ. FLT pin is driven high.
•
NB section (SVI only)
Positive sense is performed monitoring the NB output voltage through both NB_VSEN
and NB_CSN. As soon as NB_CSN is more than 600 mV higher than NB_VSEN, the
device latches in HiZ. FLT pin is driven high. A 50 μA pull-down current on the
NB_VSEN forces the device to detect this fault condition.
Negative sense is performed monitoring the internal opamp used to recover the GND
losses by comparing its output and the internal reference generated by the DAC. As
soon as the difference between the output and the input of this opamp is higher than
500 mV, the device latches in HiZ. FLT pin is driven high.
To recover from a latch condition, cycle VCC or EN.
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Output voltage monitoring and protections
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Figure 14. FB disconnection protection
500mV
FBG DISCONNECTED
CORE_REFERENCE
from DAC...
CS1-
600mV
FB
COMP
VSEN
FBG
RF
CF
To VDD_CORE
(Remote Sense)
RFB
CORE and NB SECTION - VSEN AND FBG DISCONNECTION
8.3
8.4
PWRGOOD
It is an open-drain signal set free after the soft-start sequence has finished; it is the logic
AND between the internal CORE and NB PGOOD (or just the CORE PGOOD in PVI mode).
It is pulled low when the output voltage of one of the two sections drops 250 mV below the
programmed voltage. It is masked during on-the-fly VID transitions as well as when the
CORE section is set to OFF (from SVI bus) while the NB section is still operative.
Overcurrent
The Overcurrent threshold has to be programmed to a safe value, in order to be sure that
each section doesn't enter OC during normal operation of the device. This value must take
into consideration also the extra current needed during the OTF-VID Transition (IOTF-VID
)
and the process spread and temperature variations of the sensing elements (Inductor DCR).
Moreover, since also the internal threshold spreads, the design has to consider the
minimum/maximum values of the threshold. Considering the reading method, the two
sections will show different behaviors in OC.
8.4.1
CORE section
L6717A performs two different OC protections for the CORE section: it monitors both the
total current and the per-phase current and allows to set an OC threshold for both.
–
Per-Phase OC.
Maximum information current per-phase (IINFOx) is internally limited to 35 μA. This
end-of-scale current (IOC_TH) is compared with the information current generated
for each phase (IINFOx). If the current information for the single phase exceed the
end-of-scale current (i.e. if IINFOx > IOC_TH), the device will turn-on the LS
MOSFET until the threshold is re-crossed (i.e. until IINFOx < IOC_TH). After 4
consecutive events, the IC latches with all the MOSFETs of all the sections OFF
(HiZ).
–
Total current OC.
ILIM pin allows to define a maximum total output current for the system (IOC_TOT).
I
LIM current is sourced from the ILIM pin (not altered by DRP_ADJ command). By
connecting a resistor RILIM to SGND, a load indicator with 2.5V (VOC_TOT) end-of-
scale can be implemented. When the voltage present at the ILIM pin crosses
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VOC_TOT, the device detects an OC and immediately latches with all the MOSFETs
of all the sections OFF (HiZ).
Typical design considers the intervention of the total current OC before the Per-Phase OC,
leaving this last one as an extreme-protection in case of hardware failures in the external
components. Typical design flow is the following:
–
Define the maximum total output current (IOC_TOT) according to system
requirements
–
Design Per-Phase OC and RG resistor in order to have IINFOx = IOC_TH (35μA)
when IOUT is about 10% higher than the IOC_TOT current. It results:
(1.1 ⋅ IOC_TOT) ⋅ DCR
RG = --------------------------------------------------------
N ⋅ IOCTH
where N is the number of phases and DCR the DC resistance of the inductors. RG
should be designed in worst-case conditions.
–
Design the total current OC and RILIM in order to have the ILIM pin voltage to
V
OC_TOT at the desired maximum current IOC_TOT. It results:
VOC_TOT ⋅ RG
RILIM = --------------------------------------
IOC_TOT ⋅ DCR
DCR
ILIM = ------------- ⋅ I
RG
OUT
where VOC_TOT is typically 2.5V and IOC_TOT is the total current OC threshold
desired.
–
–
Adjust the defined values according to bench-test of the application.
An additional capacitor in parallel to RILIM can be considered to add a delay in the
protection intervention.
Note:
What previously listed is the typical design flow. Custom design and specifications may
require different settings and ratios between the Per-Phase OC threshold and the total
current OC threshold. Applications with huge ripple across inductors may be required to set
Per-Phase OC to values different than 110%: design flow should be modified accordingly.
DRP_ADJ command from power manager I2C does not alter the current information used
for Per-Phase OC and total current OC.
8.4.2
IddSpike and IddTDC support
L6717A supports G34 processors and as a consequence, allows dual level OCP supporting
IddSpike and IddTDC (refer to CPU related documents for details about IddSpike and
IddTDC levels).
Proper design of the per-phase and Total Current OC is required to meet these
specifications:
–
–
per-phase OC is used to face with IddSpike: set to 120% (Typ) of IddSpike;
Total current OC is used to face with IddTDC: set to 120% (Typ) of IddTDC and
provide proper filtering.
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G34 design flow is the following:
–
Define the maximum total output current (IOC_TOT) according to system
requirements: IOC_TOT = 120% x IddTDC (Typ)
–
Design Per-Phase OC and RG resistor in order to have IINFOx = IOC_TH (35 μA)
when IOUT is 120% higher than the IddSpike current. It results:
(1.2 ⋅ IddSpike) ⋅ DCR
RG = -------------------------------------------------------------
N ⋅ IOCTH
where N is the number of phases and DCR the DC resistance of the inductors.
RG should be designed in worst-case conditions.
–
Design the total current OC and RILIM in order to have the ILIM pin voltage to
V
OC_TOT at the desired maximum current IOC_TOT. It results:
VOC_TOT ⋅ RG VOC_TOT ⋅ RG
RILIM = -------------------------------------- = ----------------------------------------------------
IOC_TOT ⋅ DCR 1.2 ⋅ IddTDC ⋅ DCR
DCR
ILIM = ------------- ⋅ I
RG
OUT
where VOC_TOT is typically 2.5 V and IOC_TOT = 120% x IddTDC is the Total
Current OC threshold desired.
–
–
Provide filtering capacitor for ILIM pin in order to properly filter IddSpike (1.5 mSec
Typ time-constant).
Adjust the defined values according to bench-test of the application.
8.4.3
NB section
NB Section performs per-phase over current: its maximum information current (IINFO_NB) is
internally limited to IOCTH_NB (35μA typ). If the current information for the NB phase exceeds
the end-of-scale current (i.e. if IINFO_NB > IOCTH_NB), the device will turn-on the Low-Side
MOSFET, also skipping clock cycles, until the threshold is re-crossed (i.e. until IINFO_NB
<
IOCTH_NB). After exiting the OC condition, the low-side MOSFET is turned off and the high-
side is turned on with a duty cycle driven by the PWM comparator.
Design RG_NB resistor in order to have IDROOP_NB = IOCTH_NB (35μA) at the IOC_NBmax
current. It results:
I
⋅ DCR
IOCTH_NB
RG = --O----C---_---N---B---m----a---x-------------------
Note:
DRP_ADJ command from power manager I2C does not alter the current information used
for Per-Phase OC.
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Main oscillator
9
Main oscillator
The controller embeds a dual-oscillator: one section is used for the CORE and it is a
multiphase programmable oscillator managing equal phase-shift among all phases and the
other section is used for the NB section. Phase-shift between the CORE and NB ramps is
automatically adjusted according to the CORE phase # programmed.
The internal oscillator generates the triangular waveform for the PWM charging and
discharging with a constant current an internal capacitor. The switching frequency for each
channel, FSW, is internally fixed at 200 kHz: the resulting switching frequency for the CORE
section at the load side results in being multiplied by N (number of configured phases).
The current delivered to the oscillator is typically 20 μA (corresponding to the free running
frequency FSW=200 kHz) and it may be varied using an external resistor (ROSC) typically
connected between the OSC pin and SGND. Since the OSC pin is fixed at 1.240 V, the
frequency is varied proportionally to the current sunk from the pin considering the internal
gain of 10 kHz/μA (See Figure 15).
Connecting ROSC to SGND the frequency is increased (current is sunk from the pin),
according to the following relationships:
1.240V
FSW = 200kHz + ------------------ ⋅ 10----------
ROSC μA
kHz
Connecting ROSC to a positive voltage the frequency is reduced (current is forced into the
pin), according to the following relationships:
+V – 1.240
FSW = 200kHz – --------------------------- ⋅ 10----------
ROSC μA
kHz
where +V is the positive voltage which the ROSC resistor is connected.
Figure 15. ROSC vs. switching frequency
1200
1000
800
600
400
200
0
1000
100
10
75
100
125
150
175
200
200
300
400
500
600
700
800
900 1000
Fsw [kHz]
Fsw [kHz]
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High current embedded drivers
L6717A
10
High current embedded drivers
L6717A provides high-current driving control for CORE and NB sections. The driver for the
high-side MOSFET use BOOTx pin for supply and PHASEx pin for return. The driver for the
low-side MOSFET use the VCCDR pin for supply and GND pin for return.
The embedded driver embodies an anti-shoot-through and adaptive dead-time control to
minimize low-side body diode conduction time maintaining good efficiency saving the use of
Schottky diodes: when the high-side MOSFET turns off, the voltage on its source begins to
fall; when the voltage reaches about 2 V, the low-side MOSFET gate drive voltage is
suddenly applied. When the low-side MOSFET turns off, the voltage at LGATE pin is
sensed. When it drops below about 1 V, the high-side MOSFET gate drive voltage is
suddenly applied. If the current flowing in the inductor is negative, the source of high-side
MOSFET will never drop. To allow the low-side MOSFET to turn-on even in this case, a
watchdog controller is enabled: if the source of the high-side MOSFET doesn't drop, the
low-side MOSFET is switched on so allowing the negative current of the inductor to
recirculate. This mechanism allows the system to regulate even if the current is negative.
10.1
Boot capacitor design
Bootstrap capacitor needs to be designed in order to show a negligible discharge due to the
high-side MOSFET turn-on. In fact it must give a stable voltage supply to the high-side
driver during the MOSFET turn-on also minimizing the power dissipated by the embedded
boot diode. Figure 16 gives some guidelines on how to select the capacitance value for the
bootstrap according to the desired discharge and depending on the selected MOSFET.
To prevent bootstrap capacitor to extra-charge as a consequence of large negative spikes,
an external series resistance RBOOT (in the range of few ohms) may be required in series to
BOOT pin.
Figure 16. Bootstrap capacitor design
2500
2000
1500
1000
500
2.5
2.0
1.5
1.0
0.5
0.0
Cboot = 47nF
Cboot = 100nF
Cboot = 220nF
Cboot = 330nF
Cboot = 470nF
Qg = 10nC
Qg = 25nC
Qg = 50nC
Qg = 100nC
0
0
10
20
30
40
50
60
70
80
90
100
0.0
0.2
0.4
0.6
0.8
1.0
High-Side MOSFET Gate Charge [nC]
Boot Cap Delta Voltage [V]
48/57
DocID024465 Rev 1
L6717A
High current embedded drivers
10.2
Power dissipation
It is important to consider the power that the device is going to dissipate in driving the
external MOSFETs in order to avoid overcoming the maximum junction operative
temperature.
Two main terms contribute in the device power dissipation: bias power and drivers' power.
•
Device power (PDC) depends on the static consumption of the device through the
supply pins and it is simply quantifiable as follow:
PDC = VCC ⋅ ICC + VVCCDR ⋅ IVCCDR
•
Drivers' power is the power needed by the driver to continuously switch ON and OFF
the external MOSFETs; it is a function of the switching frequency and total gate charge
of the selected MOSFETs. It can be quantified considering that the total power PSW
dissipated to switch the MOSFETs dissipated by three main factors: external gate
resistance (when present), intrinsic MOSFET resistance and intrinsic driver resistance.
This last term is the important one to be determined to calculate the device power
dissipation.
The total power dissipated to switch the MOSFETs for each phase featuring embedded
driver results:
PSWx = FSW ⋅ (QGHSx ⋅ VCCDR + QGLSx ⋅ VBOOTx)
Where QGHSx is the total gate charge of the HS MOSFETs and QGLSx is the total gate
charge of the LS MOSFETs for both CORE and NB sections (only Phase1 and Phase2
for CORE section); VBOOTx is the driving voltage for the HSx MOSFETs.
DocID024465 Rev 1
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System control loop compensation
L6717A
11
System control loop compensation
The device embeds two separate and independent control loops for CORE and NB section.
The control loop for NB section is a simple Voltage-Mode control loop with (optional) voltage
positioning featured when DROOP pin is shorted with FB. The control loop for the CORE
section also features a current-sharing loop to equalize the current carried by each of the
configured phases.
The CORE control system can be modeled with an equivalent single-phase converter
whose only difference is the equivalent inductor L/N (where each phase has an L inductor
and N is the number of the configured phases). See Figure 17.
Figure 17. Equivalent control loop for NB and CORE sections
d V
NB_COMP
L
V
d V
L
/N
V
OUT
NB
OUT_NB
COMP
CORE
PWM
PWM
ESR_NB
ESR
C
C
O
O_NB
Ref
VID_NB
Ref
VID_CORE
NB_FB
NB_COMP
FB
COMP
R
F_NB
C
F_NB
R
F
C
F
Z
(s)
Z
(s)
Z
F
F
R
FB_NB
R
FB
Z
(s)
FB
(s)
FB
This means that the same analysis can be used for both the sections with the only exception
of the different equivalent inductor value (L=LNB for NB Section and L=LCORE/N for the
CORE section) and the current reading gain (DCR/RG_NB for NB Section and DCR/RG for
the CORE section).
The control loop gain results (obtained opening the loop after the COMP pin):
PWM ⋅ ZF(s) ⋅ (RLL + ZP(s))
GLOOP(s) = –-------------------------------------------------------------------------------------------------------------------
ZF(s)
A(s)
1
[ZP(s) + ZL(s)] ⋅ -------------- + 1 + ----------- ⋅ RFB
A(s)
Where:
•
•
RLL is the equivalent output resistance determined by the droop function;
ZP(s) is the impedance resulting by the parallel of the output capacitor (and its ESR)
and the applied load RO;
•
•
•
•
ZF(s) is the compensation network impedance;
ZL(s) is the equivalent inductor impedance;
A(s) is the error amplifier gain;
VIN
3
PWM = -- ⋅ ------------------ is the PWM transfer function.
ΔVOSC
5
The control loop gain for each section is designed in order to obtain a high DC gain to
minimize static error and to cross the 0dB axes with a constant -20dB/Dec. slope with the
desired crossover frequency ωT. Neglecting the effect of ZF(s), the transfer function has one
zero and two poles; both the poles are fixed once the output filter is designed (LC filter
resonance ωLC) and the zero (ωESR) is fixed by ESR and the droop resistance.
50/57
DocID024465 Rev 1
L6717A
System control loop compensation
Figure 18. Control loop bode diagram and fine tuning (not in scale)
dB
dB
C
F
G
(s)
G
(s)
LOOP
LOOP
K
K
Z (s)
F
R [dB]
R [dB]
F
Z (s)
F
F
R
F
ω
=
ω
ω
ω
=
ω
ω
LC
F
ω
LC
F
ω
ω
T
T
ω
ESR
ESR
To obtain the desired shape an RF-CF series network is considered for the ZF(s)
implementation. A zero at ωF=1/RFCF is then introduced together with an integrator. This
integrator minimizes the static error while placing the zero ωF in correspondence with the L-
C resonance assures a simple -20dB/Dec. shape of the gain.
In fact, considering the usual value for the output filter, the LC resonance results to be at
frequency lower than the above reported zero.
Compensation network can be simply designed placing ωF=ωLC and imposing the cross-
over frequency ωT as desired obtaining (always considering that ωT might be not higher than
1/10th of the switching frequency FSW):
RFB ⋅ ΔVOSC
3
5
L
RF = --------------------------------- ⋅ -- ⋅ ωT ⋅ ------------------------------------------
VIN
N ⋅ (RLL + ESR)
CO ⋅ L
CF = -------------------
RF
11.1
Compensation network guidelines
The compensation network design assures to having system response according to the
cross-over frequency selected and to the output filter considered: it is anyway possible to
further fine-tune the compensation network modifying the bandwidth in order to get the best
response of the system as follow (See Figure 18):
–
–
–
Increase RF to increase the system bandwidth accordingly;
Decrease RF to decrease the system bandwidth accordingly;
Increase CF to move ωF to low frequencies increasing as a consequence the
system phase margin.
Having the fastest compensation network gives not the confidence to satisfy the
requirements of the load: the inductor still limits the maximum dI/dt that the system can
afford. In fact, when a load transient is applied, the best that the controller can do is to
“saturate” the duty cycle to its maximum (dMAX) or minimum (0) value. The output voltage
dV/dt is then limited by the inductor charge / discharge time and by the output capacitance.
In particular, the most limiting transition corresponds to the load removal since the inductor
results being discharged only by VOUT (while it is charged by dMAXVIN-VOUT during a load
appliance).
DocID024465 Rev 1
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LTB Technology®
L6717A
12
LTB Technology®
LTB Technology® further enhances the performance of dual-edge asynchronous systems by
reducing the system latencies and immediately turning ON all the phases to provide the
correct amount of energy to the load. By properly designing the LTB network as well as the
LTB gain, the undershoot and the ring-back can be minimized also optimizing the output
capacitors count. LTB Technology® applies only to the CORE Section.
LTB Technology® monitors the output voltage through a dedicated pin detecting load-
transients with selected dV/dt, it cancels the interleaved phase-shift, turning-on
simultaneously all phases. it then implements a parallel, independent loop that reacts to
load-transients bypassing E/A latencies.
LTB Technology® control loop is reported in Figure 19.
Figure 19. LTB Technology® control loop (CORE section)
LTB Ramp
LTB
LT Detect
PWM_BOOST
L/N
VOUT
d VCOMP
ESR
CO
PWM
Ref
VID
Monitor
LT Detect
COMP
FB
VSEN
RLTB
CLTB
ZF(s)
ZFB(s)
The LTB detector is able to detect output load transients by coupling the output voltage
through an RLTB - CLTB network. After detecting a load transient, the LTB Ramp is reset and
then compared with the COMP pin level. The resulting duty-cycle programmed is then OR-
ed with the PWMx signal of each phase by-passing the main control loop. All the phases will
then be turned-on together and the EA latencies results bypassed as well.
Sensitivity of the load transient detector can be programmed in order to control precisely
both the undershoot and the ring-back.
R
LTB - CLTB is designed according to the output voltage deviation dVOUT which is desired
the controller to be sensitive as follow:
dVOUT
RLTB = -----------------
25μA
1
CLTB = -------------------------------------------------
2π ⋅ N ⋅ RLTB ⋅ FSW
LTB technology® design tips.
–
Decrease RLTB to increase the system sensitivity making the system sensitive to
smaller dVOUT
.
–
Increase CLTB to increase the system sensitivity making the system sensitive to
higher dV/dt.
52/57
DocID024465 Rev 1
L6717A
Layout guidelines
13
Layout guidelines
Layout is one of the most important things to consider when designing high current
applications. A good layout solution can generate a benefit in lowering power dissipation on
the power paths, reducing radiation and a proper connection between signal and power
ground can optimize the performance of the control loops.
Two kind of critical components and connections have to be considered when laying-out a
VRM based on L6717A: power components and connections and small signal components
connections.
13.1
Power components and connections
These are the components and connections where switching and high continuous current
flows from the input to the load. The first priority when placing components has to be
reserved to this power section, minimizing the length of each connection and loop as much
as possible. To minimize noise and voltage spikes (EMI and losses) these interconnections
must be a part of a power plane and anyway realized by wide and thick copper traces: loop
must be anyway minimized. The critical components, i.e. the power transistors, must be
close one to the other. The use of multi-layer printed circuit board is recommended.
Traces between the driver section and the MOSFETs should be wide to minimize the
inductance of the trace so minimizing ringing in the driving signals. Moreover, VIAs count
needs to be minimized to reduce the related parasitic effect.
Locate the bypass capacitor (VCC, VCCDR and BOOT capacitors) close to the device with
the shortest possible loop and use wide copper traces to minimize parasitic inductance.
Systems that do not use Schottky diodes in parallel to the low-side MOSFET might show big
negative spikes on the phase pin. This spike can be limited as well as the positive spike but
it causes the bootstrap capacitor to be over-charged. This extra-charge can cause, in the
worst case condition of maximum input voltage and during particular transients, that boot-to-
phase voltage overcomes the abs.max.ratings also causing device failures. It is then
suggested in this cases to limit this extra-charge by adding a small resistor RBOOT in series
to the boot capacitor or the boot diode. The use of RBOOT also contributes in the limitation of
the spike present on the BOOT pin.
Figure 20. Driver turn-on and turn-off paths
VCCDR
C
GD
BOOTx
HGATEx
PHASEx
CGD
RGATE
R
INT
RGATE
RINT
LGATEx
C
GS
CDS
C
GS
CDS
GND (PAD)
LSx DRIVER
LS MOSFET
HSx DRIVER
HS MOSFET
For heat dissipation, place copper area under the IC. This copper area must be connected
with internal copper layers through several VIAs to improve the thermal conductivity. The
DocID024465 Rev 1
53/57
Layout guidelines
L6717A
combination of copper pad, copper plane and VIAs under the controller allows the device to
reach its best thermal performance.
13.2
Small signal components and connections
These are small signal components and connections to critical nodes of the application as
well as bypass capacitors for the device supply. Locate the bypass capacitor close to the
device and refer sensible components such as frequency set-up resistor ROSC, offset
resistor and OVP resistor ROVP to SGND (when applicable). Star grounding is suggested:
use the device exposed PAD as a connection point.
VSEN pin filtered vs. SGND helps in reducing noise injection into device and EN pin filtered
vs. SGND helps in reducing false trip due to coupled noise: take care in routing driving net
for this pin in order to minimize coupled noise.
Remote buffer connection must be routed as parallel nets from the FBG/FBR pins to the
load in order to avoid the pick-up of any common mode noise. Connecting these pins in
points far from the load will cause a non-optimum load regulation, increasing output
tolerance.
Locate current reading components close to the device. The PCB traces connecting the
reading point must use dedicated nets, routed as parallel traces in order to avoid the pick-up
of any common mode noise. It's also important to avoid any offset in the measurement and,
to get a better precision, to connect the traces as close as possible to the sensing elements.
Symmetrical layout is also suggested. Small filtering capacitor can be added, near the
controller, between VOUT and SGND, on the CSxN line when reading across inductor to
allow higher layout flexibility.
54/57
DocID024465 Rev 1
L6717A
VFQFPN48 mechanical data and package dimensions
14
VFQFPN48 mechanical data and package dimensions
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Figure 21. VFQFPN48 mechanical data and package dimensions
mm
mils
OUTLINE AND
MECHANICAL DATA
DIM.
MIN. TYP. MAX. MIN.
0.800 0.900 1.000 31.50
0.200
TYP. MAX.
A
A3
b
39.37
35.43
7.874
0.180 0.250 0.300 7.087 9.843 11.81
6.900 7.000 7.100 271.6 275.6 279.5
5.050 5.150 5.250 198.8 2.02.7 206.7
D
D2
E
6.900 7.000 7.100
5.050 5.150 5.250
0.500
271.6 275.6 279.5
198.8 202.7 206.7
19.68
E2
e
L
0.300 0.400 0.500 11.81
0.080
VFQFPN-48 (7x7x1.0mm)
Very Fine Quad Flat Package No lead
19.68
3.150
15.75
ddd
ddd
DocID024465 Rev 1
55/57
Revision history
L6717A
15
Revision history
Table 22. Document revision history
Revision Changes
Date
22-Apr-2013
1
Initial release.
56/57
DocID024465 Rev 1
L6717A
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right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
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No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
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