L6717TR_技术文档

L6717

High-efficiency hybrid AM2r2 controller

with I²C interface and embedded drivers

Features

■ Hybrid controller for both PVI and SVI CPUs

■ Dual controller with 2 embedded high current

drivers + 2 PWM for external driver for CPU

CORE and 1 embedded high current driver for

CPU NB

VFQFPN48

■ Dynamic phase management (DPM)

VFQFPN48

2

■ I C interface to control offset, switching

frequency and power management options

Description

■ Dual-edge asynchronous architecture with LTB

®

technology

L6717 is a hybrid CPU power supply controller

embedding 2 high-current drivers for the CORE

section and 1 driver for the NB section - requiring

up to 2 external drivers when the CORE section

works at 4 phase to optimize the application over-

all cost.

■ PSI management to increase efficiency in light-

load conditions

■ Dual overcurrent protection: Total and per-

phase

■ Accurate voltage positioning

■ Dual remote sense

2

I C interface allows to manage offset both CORE

and NB sections, switching frequency and

dynamic phase management saving in

component count, space and power consumption.

■ Feedback disconnection protection

■ Programmable OV protection

Dynamic phase management automatically

adjusts phase-count according to CPU load

optimizing the system efficiency under all load

conditions.

■ Oscillator internally fixed at 200 kHz externally

adjustable

■ LSLess startup to manage pre-biased output

■ VFQFPN48 Package

The dual-edge asynchronous architecture is

®

optimized by LTB technology allowing fast load-

Applications

transient response minimizing the output

capacitor and reducing the total BOM cost.

■ Hybrid high-current VRM / VRD for desktop /

Server / Workstation / IPC CPUs supporting

PVI and SVI interface

Fast protection against load over current is

provided for both the sections. Feedback

disconnection protection prevents from damaging

the load in case of disconnections in the system

board.

■ High-density DC / DC converters

L6717 is available in VFQFPN48 package.

Table 1.

Device summary

Order codes

Package

Packing

L6717

Tray

VFQFPN48

L6717TR

Tape and reel

March 2010

Doc ID 17326 Rev 1

1/56

www.st.com

56

Contents

L6717

Contents

1

2

3

Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 4

1.1

1.2

Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 8

2.1

2.2

Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.1

3.2

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4

5

Device description and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Hybrid CPU support and CPU_TYPE detection . . . . . . . . . . . . . . . . . . 19

5.1

5.2

5.3

5.4

PVI - parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

PVI start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

SVI - serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

SVI start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.4.1

5.4.2

5.4.3

5.4.4

5.4.5

Set VID command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

PWROK de-assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

PSI_L and efficiency optimization at light-load . . . . . . . . . . . . . . . . . . . 24

HiZ management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Hardware jumper override - V_FIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6

Power manager I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.1

Power manager commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.1.1

6.1.2

6.1.3

6.1.4

6.1.5

Overspeeding command (OVRSPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Overvoltage threshold adjustment (OV_SET) . . . . . . . . . . . . . . . . . . . . 30

Switching frequency adjustment (FSW_ADJ) . . . . . . . . . . . . . . . . . . . . 30

Droop function adjustment (DRP_ADJ) . . . . . . . . . . . . . . . . . . . . . . . . . 31

Power management flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.2

Dynamic phase management (DPM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

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7

Output voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.1

7.2

7.3

7.4

7.5

7.6

7.7

7.8

CORE section - phase # programming . . . . . . . . . . . . . . . . . . . . . . . . . . 35

CORE section - current reading and current sharing loop . . . . . . . . . . . . 35

CORE section - defining load-line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

CORE section - analog offset (Optional - I2CDIS = 3.3 V) . . . . . . . . . . . . 37

NB section - current reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

NB section - defining load-line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

On-the-fly VID transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.8.1

LS-Less Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8

Output voltage monitoring and protections . . . . . . . . . . . . . . . . . . . . . 41

8.1

8.2

8.3

8.4

Programmable overvoltage (I2DIS = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . 41

Feedback disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

PWRGOOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Overcurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.4.1

8.4.2

CORE section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

NB section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9

Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

10

High current embedded drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

10.1 Boot capacitor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

10.2 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

11

System control loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

11.1 Compensation network guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

12

13

LTB Technology

Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

13.1 Power components and connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

13.2 Small signal components and connections . . . . . . . . . . . . . . . . . . . . . . . 53

14

15

VFQFPN48 mechanical data and package dimensions . . . . . . . . . . . . 54

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Doc ID 17326 Rev 1

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Typical application circuit and block diagram

L6717

1

Typical application circuit and block diagram

1.1

Application circuit

Figure 1.

Typical 4+1 application circuit

CHF

L_IN

V

IN

C_{BULK_IN}

3

2

49

42

3.3V

VCC

48

BOOT

BOOT1

CHF

47

46

45

HS1

LS1

HS3

LS3

UGATE

PHASE

LGATE

GND

EN

PWRGOOD

PWROK

UGATE1

PHASE1

LGATE1

35

1

L1

L3

PWM

VID0 / VFIX

34

33

32

31

30

29

R

VID1 / CORE_TYPE

PVI / SVID Bus

C

VID2 / SVD

VID3 / SVC

15

CS1P

CS1N

VID4 / I2C_DIS

VID5 / ADDRESS

R

G

16

20

CS3N

CS3P

R

19

5V SBY

3.3V

28

OSC / EN / FLT

PWM3

VCC

14

39

R

OSC

BOOT

BOOT2

C

HF

CHF

R

ILIM

40

41

44

Q_EN

ILIM

HS2

LS2

HS4

LS4

UGATE

PHASE

LGATE

GND

EN

UGATE2

PHASE2

LGATE2

EN

13

L2

L4

PWM

C

ILIM

R

C

SCL / OS

26

25

17

Power Manager I2C

CS2P

CS2N

SDA / OVP

R

G

18

22

CS4N

CS4P

R

21

27

PWM4

COMP

4

C

F

36

CP

NB_BOOT

CHF

R

37

38

43

HS_NB

LS_NB

NB_UGATE

NB_PHASE

NB_LGATE

FB

L_NB

PVI / SVID AM2 CPU

5

C_MLCC

C_OUT

C_{OUT_NB}

LTB

R_NB

8

C

I

C

R

LTB

C_NB

C_{MLCC_NB}

RFB

SVI/PVI Interface

23

R

NB_CSP

NB_CSN

LTB

24

12

R

G_NB

VSEN

6

NB_FBG

FBG

7

9

10

11

CF_NB

R

F_NB

RFB_NB

ST L6717 (4+1) Reference Schematic

4/56

Doc ID 17326 Rev 1

L6717

Typical application circuit and block diagram

Figure 2.

Typical 3+1 application circuit

CHF

L_IN

V

IN

C_{BULK_IN}

3

2

49

42

3.3V

VCC

48

BOOT

BOOT1

CHF

L1

R

CHF

47

46

45

HS1

LS1

HS3

LS3

UGATE

PHASE

LGATE

GND

EN

PWRGOOD

PWROK

UGATE1

PHASE1

LGATE1

35

1

L3

PWM

VID0 / VFIX

34

33

32

31

30

29

R

VID1 / CORE_TYPE

PVI / SVID Bus

C

VID2 / SVD

VID3 / SVC

15

CS1P

CS1N

VID4 / I2C_DIS

VID5 / ADDRESS

RG

16

20

CS3N

CS3P

19

5V SBY

28

OSC / EN / FLT

PWM3

14

39

ROSC

RILIM

BOOT2

CHF

L2

R

40

41

44

Q_EN

ILIM

HS2

LS2

UGATE2

PHASE2

LGATE2

EN

13

CILIM

C

SCL / OS

26

25

17

Power Manager I2C

CS2P

CS2N

SDA / OVP

RG

18

22

CS4N

CS4P

21

27

PWM4

COMP

4

CF

36

C

NB_BOOT

CHF

RF

37

38

43

HS_NB

LS_NB

NB_UGATE

NB_PHASE

NB_LGATE

FB

L_NB

R_NB

PVI / SVID AM2 CPU

5

C_MLCC

C_OUT

C_{OUT_NB}

C_{MLCC_NB}

LTB

8

CI

RI

CLTB

C_NB

RFB

SVI/PVI Interface

23

NB_CSP

NB_CSN

RLTB

24

12

RG_NB

VSEN

6

7

NB_FBG

FBG

9

10

11

CF_NB RF_NB

RFB_NB

ST L6717 (3+1) Reference Schematic

Doc ID 17326 Rev 1

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Typical application circuit and block diagram

Figure 3. Typical 2+1 application circuit

L6717

CHF

L_IN

V

IN

C_{BULK_IN}

3

2

49

42

48

BOOT1

C^HF

L1

R

47

46

45

HS1

LS1

PWRGOOD

PWROK

UGATE1

PHASE1

LGATE1

35

1

VID0 / VFIX

34

33

32

31

30

29

VID1 / CORE_TYPE

PVI / SVID Bus

C

VID2 / SVD

VID3 / SVC

15

CS1P

CS1N

VID4 / I2C_DIS

VID5 / ADDRESS

RG

16

20

CS3N

CS3P

19

5V SBY

28

OSC / EN / FLT

PWM3

14

39

ROSC

RILIM

BOOT2

C^HF

L2

R

40

41

44

Q_EN

ILIM

HS2

LS2

UGATE2

PHASE2

LGATE2

EN

13

CILIM

C

SCL / OS

26

25

17

Power Manager I2C

CS2P

CS2N

SDA / OVP

RG

18

22

CS4N

CS4P

21

27

PWM4

COMP

4

CF

36

C

NB_BOOT

C^HF

RF

37

38

43

HS_NB

LS_NB

NB_UGATE

NB_PHASE

NB_LGATE

FB

L_NB

R_NB

PVI / SVID AM2 CPU

5

C_MLCC

C_OUT

C_{OUT_NB}

C_{MLCC_NB}

LTB

8

CI

RI

CLTB

C_NB

RFB

SVI/PVI Interface

23

NB_CSP

NB_CSN

RLTB

24

12

RG_NB

VSEN

6

7

NB_FBG

FBG

9

10

11

CF_NB RF_NB

RFB_NB

ST L6717 (2+1) Reference Schematic

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L6717

Typical application circuit and block diagram

1.2

Block diagram

Figure 4.

Block diagram

VCCDR

EMBEDDED DRIVER

CORE PHASE #2

EMBEDDED DRIVER

CORE PHASE #1

DIFFERENTIAL

CURRENT SENSE

GND_PAD

PWM2

VID0 / V_FIX

VID1 / CORE_TYPE

VID2 / SVD

VID3 / SVC

LTB

COMP

FB

VID4 / I2CDIS

VID5 / ADDR

PWROK

PWRGOOD

OSC / EN

DUAL CHANNEL

OSCILLATOR (4+1)

IDROOP

ILIM

I_LIM

SDA / OVP

SCL / OS

FBG

VSEN

NB_CS+

NB_CS-

NB_PWM

64k

EMBEDDED DRIVER

CORE NB PHASE

REMOTE

BUFFER

ERROR

AMPLIFIER

64k

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Pins description and connection diagrams

L6717

2

Pins description and connection diagrams

Figure 5.

Pins connection (Top view)

36 35 34 33 32 31 30 29 28 27 26 25

24

NB_UGATE

NB_PHASE

BOOT2

37

38

39

40

41

42

43

44

45

46

47

48

NB_CSN

NB_CSP

CS4N

23

22

21

20

19

18

17

16

15

14

13

UGATE2

PHASE2

VCCDRV

NB_LGATE

LGATE2

CS4P

CS3N

CS3P

L6717

PAD (GND)

CS2N

CS2P

LGATE1

CS1N

PHASE1

UGATE1

BOOT1

CS1P

OSC / EN /FLT

ILIM

1

2

3

4

5

6

7

8

9 10 11 12

2.1

Pin descriptions

Table 2.

Pin#

Pin description

Name

Function

System-wide Power Good input (Ignored in PVI mode).

Internally pulled-low by 10μA. When low, the device will decode the two SVI bits SVC

and SVD to determine the Pre-PWROK Metal VID. When high, the device will actively

run the SVI protocol.

1

PWROK

Pre-PWROK Metal VID are latched after EN is asserted and re-used in case of

PWROK de-assertion. Latch is reset by VCC or EN cycle.

Device signal ground.

2

3

SGND

VCC

All the internal references are referred to this pin. Connect to the PCB signal ground.

Device power supply.

Operative voltage is 12 15%. Filter with 1μF MLCC to SGND.

Do not connect VCC to any voltage greater than VCCDR.

CORE error amplifier output.

4

COMP

Connect with an R_F- C_Fto FB.

The CORE section and/or the device cannot be disabled by grounding this pin.

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Pins description and connection diagrams

Function

Table 2.

Pin#

Pin description (continued)

Name

CORE error amplifier inverting input.

5

6

FB

VSEN

FBG

LTB

Connect with a resistor R_FBto VSEN and with an R_F- C_Fto COMP. Droop current for

voltage positioning is sourced from this pin.

CORE output voltage monitor.

It manages OVP and UVP protections and PWRGOOD. Connect to the positive side

of the load for remote sensing. See Section 8 for details.

CORE remote ground sense.

7

Connect to the negative side of the load for remote sensing. See Section 11 for proper

layout of this connection.

LTB Technology^®input pin.

8

Connect through an R_LTB- C_LTBnetwork to the regulated voltage (CORE section) to

detect load transient. See Section 12 for details.

NB error amplifier output.

9

NB_COMP Connect with an R_{F_NB}- C_{F_NB}to NB_FB.

The NB section and/or the device cannot be disabled by grounding this pin.

NB error amplifier inverting input.

10

NB_FB

NB_VSEN

NB_FBG

Connect with a resistor R_{FB_NB}to NB_VSEN and with an R_{F_NB}- C_{F_NB}to NB_COMP.

Droop current for voltage positioning is sourced from this pin.

NB output voltage monitor.

It manages OVP and UVP protections and PWRGOOD. Connect to the positive side

of the NB load to perform remote sensing. See Section 11 for proper layout of this

connection.

11

12

NB remote ground sense.

Connect to the negative side of the load to perform remote sense. See Section 11 for

proper layout of this connection.

CORE over current pin.

A current I_LIM=DCR/R_G*I_OUTproportional to the current delivered by the CORE

Section is sourced from this pin. The OC threshold is programmed by connecting a

resistor R_ILIMto SGND. When the generated voltage crosses the OC_TOT threshold

(V_{OC_TOT}= 2.5V Typ) the device latches with all MOSFETs OFF (to recover, cycle

VCC or the EN pin).

13

ILIM

This pin is monitored for dynamic phase management.

Filter with proper capacitor to provide OC masking time; do not exceed 30μsec. See

Section 8.4.1 for details.

OSC: It allows programming the switching frequency F_SWof both sections. Switching

frequency can be increased according to the resistor R_OSCconnected to SGND with a

gain of 9.1kHz/µA (see Section 9 for details). If floating, the switching frequency is

200kHz per phase.

OSC / EN / EN: Pull-low (tie to GND) to disable the device. When set free, the device immediately

14

FLT

checks for the VID1 status to determine the SVI / PVI protocol to be adopted and

configures itself accordingly.

FLT: The pin is internally forced high (3.3V) in case of an OV / UV fault. To recover

from this condition, cycle VCC or the EN pin.

To enable/disable the IC drive OSC/EN/FAUT pin by an open drain circuit.

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Pins description and connection diagrams

L6717

Table 2.

Pin#

Pin description (continued)

Name

Function

Channel 1 current sense positive input.

15

16

17

18

CS1P

CS1N

CS2P

CS2N

Connect through an R-C filter to the phase-side of the channel 1 inductor. See

Section 11 for proper layout of this connection.

Channel 1 current sense negative input.

Connect through a R_Gresistor to the output-side of the channel inductor. Filter the

Vout-side of R_Gresistor with 100nF to GND.

See Section 11 for proper layout of this connection.

Channel 2 current sense positive input.

Connect through an R-C filter to the phase-side of the channel 2 inductor. See

Section 11 for proper layout of this connection.

Channel 2 current sense negative input.

Connect through a R_Gresistor to the output-side of the channel inductor. Filter the

Vout-side of R_Gresistor with 100nF to GND.

See Section 11 for proper layout of this connection.

Channel 3 current sense positive input.

Connect through an R-C filter to the phase-side of the channel 3 inductor. When

19

20

21

22

CS3P

CS3N

CS4P

CS4N

working at 2 phase, directly connect to V_{out_CORE}

.

See Section 11 for proper layout of this connection.

Channel 3 current sense negative input.

Connect through a R_Gresistor to the output-side of the channel inductor. When

working at 2 phase, connect through R_Gto CS3+. Filter the Vout-side of R_Gresistor

with 100nF to GND.

See Section 11 for proper layout of this connection.

Channel 4 current sense positive input.

Connect through an R-C filter to the phase-side of the channel 4 inductor. When

working at 2 or 3 phase, directly connect to V_{out_CORE}

.

See Section 11 for proper layout of this connection.

Channel 4 current sense negative input.

Connect through a R_Gresistor to the output-side of the channel inductor. When

working at 2 or 3 phase, connect through R_Gto CS4+.Filter the Vout-side of R_G

resistor with 100nF to GND.

See Section 11 for proper layout of this connection.

NB channel current sense positive input.

23

24

NB_CSP

NB_CSN

Connect through an R-C filter to the phase-side of the NB channel inductor. See

Section 11 for proper layout of this connection.

NB channel current sense negative input.

Connect through a R_Gresistor to the output-side of the channel inductor. Filter the

Vout-side of R_Gresistor with 100nF to GND.

See Section 11 for proper layout of this connection.

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Pins description and connection diagrams

Function

Table 2.

Pin#

Pin description (continued)

Name

2

SDA - power manager I C data.

When power manager I C is enabled, this is the data connection.

See Section 6 for details.

OVP - over voltage setting.

When power manager I C is disabled (VID4 / I2CDIS to 3.3V) the pin is used to set

25

SDA / OVP

2

the OVP protection for CORE and NB sections. Define the OVP threshold by

connecting the pin to the center tap of a voltage divider from 3V3 to SGND.

See Section 8.1 for details.

2

SCL - power manager I C clock.

When power manager I C is enabled, this is the clock connection.

See Section 6 for details.

OS - CORE section offset.

When power manager I C is disabled (VID4 / I2CDIS to 3.3V) this pin is internally set

26

SCL / OS

2

to 1.24V(2.0V): connecting a R_OSresistor to GND (3.3V) allows setting a current that

is mirrored into FB pin in order to program a positive (negative) offset according to the

selected R_FB. Short to GND to disable the function. See Section 7.4 for details.

PWM output for external drivers.

Connect to external drivers PWM inputs. The device is able to manage HiZ status by

setting the pins floating.

PWM4,

PWM3

27, 28

By shorting to GND PWM4 or PWM3 and PWM4, it is possible to program the CORE

section to work at 3 or 2 phase respectively.

See Section 5.4.4 for details about HiZ management.

2

Voltage identification pin - I C address pin.

VID5 /

ADDR

Internally pulled-low by 10μA, it programs the output voltage in PVI mode. In SVI

mode, the pin is monitored on the EN pin rising-edge to modify the I C address. See

Section 5 for details.

29

30

2

Voltage identification pin - I C disable pin.

VID4 /

I2CDIS

Internally pulled-low by 10μA, it programs the output voltage in PVI mode. In SVI

2

mode, the pin is monitored on the EN pin rising-edge to enable/disable the I C. See

Section 5 for details.

Voltage IDentification Pin - SVI clock pin.

31

32

VID3 / SVC

VID2 / SVD

Internally pulled-low by 10μA, it programs the output voltage in both SVI and PVI

modes. In SVI mode, the 10μA pull down is disabled. See Section 5 for details.

Voltage identification pins - SVI data pin.

Internally pulled-low by 10μA, it programs the output voltage in both SVI and PVI

modes. In SVI mode, the 10μA pull down is disabled. See Section 5 for details.

Voltage identification pin.

VID1 /

CORETYPE

Internally pulled-low by 10μA, it programs the output voltage in PVI mode. The pin is

monitored on the EN pin rising-edge to define the operative mode of the controller

(SVI or PVI). See Section 5 for details.

33

34

Voltage identification pin.

Internally pulled-low by 10μA, it programs the output voltage in PVI mode. If the pin is

pulled to 3.3V, the device enters V_FIX mode and SVI commands are ignored.

See Section 5 for details.

VID0 / VFIX

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Pins description and connection diagrams

L6717

Table 2.

Pin#

Pin description (continued)

Name

Function

VCORE and NB Power Good.

It is an open-drain output set free after SS as long as both the voltage planes are

within specifications. Pull-up to 3.3V (typ) or lower, if not used it can be left floating.

35

PWRGOOD

NB_BOOT

When in PVI mode, it monitors the CORE section only.

NB section high-side driver supply.

This pin supplies the high-side floating driver. Connect through C_BOOTcapacitor to the

NB_PHASE pin.

36

See Section 10 for guidance in designing the capacitor value.

NB section high-side driver output.

37

38

NB_UGATE

NB_PHASE

Connect to NB section high-side MOSFET gate. A small series resistor may help in

reducing NB_PHASE pin negative spike as well as cooling the device.

NB section high-side driver return path.

Connect to the NB section high-side MOSFET source.

This pin is also monitored for the adaptive dead-time management.

CORE section, phase 2 high-side driver supply.

This pin supplies the High-Side floating driver. Connect through C_BOOTcapacitor to

the PHASE2 pin.

39

BOOT2

See Section 10 for guidance in designing the capacitor value.

High-side driver output.

40

41

42

UGATE2

PHASE2

Connect to Phase2 high-side MOSFET gate. A small series resistor may help in

reducing PHASE2 pin negative spike as well as cooling the device.

CORE section, phase 2 high-side driver return path. Connect to the Phase2 high-side

MOSFET source.

This pin is also monitored for the adaptive dead-time management.

Supply voltage for low-side embedded drivers.

VCCDRV Operative voltage is flexible from 5V 5% to 12 15%. Filter with 1μF MLCC to GND.

Do not connect VCC to any voltage greater than VCCDR.

Low-side driver output.

NB_LGATE,

43 to

45

Connect directly to the low-side MOSFET gate of the related section. A small series

LGATE2,

resistor can be useful to reduce dissipated power especially in high frequency

LGATE1

applications.

CORE section, phase 1 high-side driver return path. Connect to the phase1 high-side

MOSFET source.

46

47

PHASE1

UGATE1

This pin is also monitored for the adaptive dead-time management.

High-side driver output.

Connect to phase1 high-side MOSFET gate. A small series resistor may help in

reducing PHASE1 pin negative spike as well as cooling the device.

CORE section, phase 1 high-side driver supply.

This pin supplies the high-side floating driver. Connect through C_BOOTcapacitor to the

PHASE1 pin.

See Section 10 for guidance in designing the capacitor value.

48

BOOT1

GND

Thermal

PAD

All internal references, logic, and the Silicon substrate are referenced to this pin.

Connect to the PCB GND ground plane by multiple vias to improve heat dissipation.

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L6717

Pins description and connection diagrams

2.2

Thermal data

Table 3.

Symbol

Thermal data

Parameter

Value

Unit

Thermal resistance junction to ambient

(Device soldered on 2s2p PC board)

R_THJA

40

°C/W

R_THJC

T_MAX

T_STG

T_J

Thermal resistance junction to case

Maximum junction temperature

Storage temperature range

1

°C/W

°C

150

-40 to 150

0 to 125

°C

Junction temperature range

°C

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Electrical specifications

L6717

3

Electrical specifications

3.1

Absolute maximum ratings

Table 4.

Symbol

_CC,V_CCDRV

Absolute maximum ratings

Parameter

Value

Unit

V

to GND

-0.3 to 15

V

to GND

41

15

V_BOOTx

V_UGATEx

,

V

to PHASEx

to GND

-8 to 26

30

V_PHASEx

to GND, t < 200nsec.

to GND

-0.3 to VCCDRV + 0.3

-3

V_LGATEx

V

to GND, t < 100nsec.

All other pins to GND

-0.3 to 3.6

Maximum withstanding voltage range test

condition: CDF-AEC-Q100-002- “human body

model” acceptance “normal performance”

1750

V

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Doc ID 17326 Rev 1

L6717

Electrical specifications

3.2

Electrical characteristics

V_CC=12 V 15%, T_J= 0 °C to 70 °C unless otherwise specified.

Table 5.

Electrical characteristics

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

Supply current and power-on

I_CC

VCC supply current

VCCDR supply current

BOOTx supply current

VCC turn-ON

15

4

mA

V

I_CCDR

I_BOOTx

OSC = GND

1.5

VCC rising

VCC falling

4.5

UVLO_VCC

Oscillator

F_SW

VCC turn-OFF

4

V

Main oscillator accuracy

Oscillator adjustability

PWM ramp amplitude

Voltage at pin OSC

180

425

200

500

1.5

220

575

kHz

V

R_OSC= 36kΩ

ΔV_OSC

FAULT

EN

CORE and NB section

OVP, UVP latch active

OSC/EN falling

3

3.6

V

Turn-OFF threshold

0.3

V

PVI / SVI interface

Input high

1.3

V

PWROK

Input low

0.80

Input high

Input low

(SVI mode)

0.95

V

VID2,/SVD

VID3/SVC

0.65

250

V

SVD

Voltage low (ACK)

Input high

Input low

I_SINK= -5mA

mV

V

(PVI mode)

1.3

3

VID0 to

VID5

(PVI mode)

0.80

V

V_FIX

Entering V_FIX mode

VID0/V_FIX rising

V

2

Power manager I C

Input high

1.3

V

SDA, SCL

SDA

Input low

0.8

Voltage low (ACK)

I_SINK= -5mA

250

mV

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Electrical specifications

L6717

Unit

Table 5.

Symbol

Electrical characteristics (continued)

Parameter Test conditions

Min.

Typ.

Max.

Voltage positioning (CORE and NB section)

CORE

NB

VSEN to V_CORE; FBG to GND_CORE

NBVSEN to V_NB; NBFBG to GND_FB

I2DIS=3.3V, I_OS= 0 to 250μA

I2DIS=3.3V

-8

-10

1.190

0

8

10

mV

V

Output voltage accuracy

OFFSET bias voltage

OFFSET current range

1.24

1.290

250

2.25

9

μA

dB

V/μs

OS

I2DIS=3.3V, I_OS= 0μA

-2.25

-9

OFFSET - I_FBaccuracy

DROOP accuracy

I2DIS=3.3V, I_OS= 250μA

I_DROOP= 0 to 25μA, k_DRP= 1/4

-3

3

DROOP

I_{NB_DROOP}= 0 to 6μA, k_NBDRP= 1/4

-1

1

A₀

EA DC gain

Slew rate

100

20

SR

COMP, NB_COMP to SGND = 10pF

PWM outputs (CORE only) and embedded drivers

Output high

Output low

Test current

I = 1mA

I = -1mA

3

3.6

0.2

V

PWM3,

PWM4

I_PWMx

10

μA

High current embedded drivers

R_HIHS

HS source resistance

HS source current

BOOT - PHASE = 12V; 100mA

2.3

2

2.8

Ω

BOOT - PHASE = 12V; ⁽¹⁾

C_UGATEto PHASE = 3.3nF

I_UGATE

A

R_LOHS

R_HILS

I_LGATE

R_LOLS

HS sink resistance

LS source resistance

LS source current

LS sink resistance

BOOT - PHASE = 12V; 100mA

2

1.3

3

2.5

1.8

Ω

A

100mA

C_LGATEto GND = 5.6nF, ⁽¹⁾

100mA

1

1.5

Ω

Protections

2

I C enabled, no commands issued,

wrt VID, CORE & NB section

+200

+250

+300

mV

V

Over voltage protection

SDA/OVP bias current

2

OVP

I C disabled, V_FIX mode;

1.800

VSEN, NB_VSEN rising

I2CDIS = 3.3V

9

11

13

μA

mV

V

UVP

Under voltage protection VSEN, NB_VSEN falling; wrt Ref.

-450

-285

-400

-250

-350

-215

0.4

PGOOD threshold

Voltage low

VSEN, NB_VSEN falling; wrt Ref

_PWRGOOD= -4mA

PWRGOOD

I

V_CSNrising, above VSEN

CORE and NB sections

V_FB-DISC

FB disconnection

600

500

mV

V_{FBG DISC}

FBG disconnection

EA NI input wrt VID

16/56

Doc ID 17326 Rev 1

L6717

Electrical specifications

Table 5.

Electrical characteristics (continued)

Parameter Test conditions

Symbol

V_{OC_TOT}

Min.

Typ.

Max.

Unit

2.425

0

2.500

2.575

4

V

CORE OC

I_LIM= 0μA

μA

kI_ILIM

I_LIM= 100μA

100

1. Parameter(s) guaranteed by designed, not fully tested in production

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Device description and operation

L6717

4

Device description and operation

L6717 is a hybrid CPU power supply controller compatible with both parallel (PVI) and serial

(SVI) protocols for AMD Processors. The device provides complete control logic and

protections for a high-performance step-down DC-DC voltage regulator, optimized for

advanced microprocessor power supply supporting both PVI and SVI communication. It

embeds two independent controllers for CPU CORE and the integrated NB, each one with

its own set of protections. NB phase (when enabled) is automatically phase-shifted with

respect to the CORE phases in order to reduce the total input rms current amount.

2

The device features an additional power manager I C interface to easy the system design

for enthusiastic application where the main parameters of the voltage regulator have to be

modified. L6717 is able to adjust the regulated voltage, the switching frequency and also the

2

OV protection threshold through the power manager I C bus while the application is running

assuring fast and reliable transitions.

Dynamic phase management (DPM) allows the device to automatically adjust the phase

count according to the current delivered to the load. This feature allow the system to keep

alive only the phases really necessary to sustain the load saving in power dissipation so

optimizing the efficiency over the whole current range of the application. DPM can be

2

enabled through the power manager I C bus.

L6717 is able to detect which kind of CPU is connected in order to configure itself to work as

a single-plane PVI controller or dual-plane SVI controller.

The controller performs a single-phase control for the NB section and a programmable 2-to-

4 phase control for the CORE section featuring dual-edge non-latched architecture: this

allows fast load-transient response optimizing the output filter consequently reducing the

total BOM cost. Further reduction in output filter can be achieved by enabling LTB

®

Technology .

PSI_L flag is sent to the VR through the SVI bus. The controller monitors this flag and

selectively modifies the phase number in order to optimize the system efficiency when the

CPU enters low-power states. This causes the over-all efficiency to be maximized at light

loads so reducing losses and system power consumption.

Both sections feature programmable overvoltage protection and adjustable constant

overcurrent protection. Voltage positioning (LL) is possible thanks to an accurate fully-

differential current-sense across the main inductors for both sections.

L6717 features dual remote sensing for the regulated outputs (CORE and NB) in order to

recover from PCB voltage drops also protecting the load from possible feedback network

disconnections.

LSLess start-up function allows the controller to manage pre-biased start-up avoiding

dangerous current return through the main inductors as well as negative undershoot on the

output voltage if the output filter is still charged before start-up.

L6717 supports V_FIX mode for system debugging: in this particular configuration the SVI

bus is used as a static bus configuring 4 operative voltages for both the sections and

ignoring any serial-VID command.

When working in PVI mode, the device features on-the-fly VID management: VID code is

continuously sampled and the reference update according to the variation detected,

L6717 is available in VFQFPN48 package.

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L6717

Hybrid CPU support and CPU_TYPE detection

5

Hybrid CPU support and CPU_TYPE detection

L6717 is able to detect the type of the CPU-core connected and to configure itself

accordingly. At system Start-up, on the rising-edge of the EN signal, the device monitors the

status of VID1 and configures the PVI mode (VID1 = 1) or SVI mode (VID1 = 0).

When in PVI mode, L6717 uses the information available on the VID[0: 5] bus to address the

CORE Section output voltage according to Table 6. NB Section is kept in HiZ mode, both

MOSFETs are kept OFF.

When in SVI mode, L6717 ignores the information available on VID0, VID4 and VID5 and

uses VID2 and VID3 as a SVI bus addressing the CORE and NB Sections according to the

SVI protocol.

Caution:

To avoid any risk of errors in CPU type detection (i.e. detecting SVI CPU when PVI CPU is

installed on the socket and vice versa), it is recommended to carefully control the start-up

sequencing of the system hosting L6717 in order to ensure than on the EN rising-edge,

VID1 is in valid and correct state. Typical connections consider VID1 connected to CPU

CORE_TYPE through a resistor to correctly address the CPU detection.

5.1

PVI - parallel interface

PVI is a 6-bit-wide parallel interface used to address the CORE section reference. According

to the selected code, the device sets the CORE section reference and regulates its output

voltage as reported into Table 6.

NB section is always kept in HiZ; no activity is performed on this section and both the high-

side and low-side of this section are kept OFF. Furthermore, PWROK information is ignored

as well since the signal only applies to the SVI protocol.

5.2

PVI start-up

Once the PVI mode has been detected, the device uses the whole code available on the

VID[0:5] lines to define the reference for the CORE section. NB section is kept in HiZ. Soft-

start to the programmed reference is performed regardless of the state of PWROK.

See Section 7.8 for details about soft-start.

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Hybrid CPU support and CPU_TYPE detection

L6717

Table 6.

Voltage Identifications (VID) codes for PVI mode

Output

voltage

Output

voltage

VID5 VID4 VID3 VID2 VID1 VID0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.5500

1.5250

1.5000

1.4750

1.4500

1.4250

1.4000

1.3750

1.3500

1.3250

1.3000

1.2750

1.2500

1.2250

1.2000

1.1750

1.1500

1.1250

1.1000

1.0750

1.0500

1.0250

1.0000

0.9750

0.9500

0.9250

0.9000

0.8750

0.8500

0.8250

0.8000

0.7750

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.7625

0.7500

0.7375

0.7250

0.7125

0.7000

0.6875

0.6750

0.6625

0.6500

0.6375

0.6250

0.6125

0.6000

0.5875

0.5750

0.5625

0.5500

0.5375

0.5250

0.5125

0.5000

0.4875

0.4750

0.4625

0.4500

0.4375

0.4250

0.4125

0.4000

0.3875

0.3750

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L6717

Hybrid CPU support and CPU_TYPE detection

5.3

SVI - serial interface

SVI is a two wire, clock and data, bus that connects a single master (CPU) to one slave

(L6717). The master initiates and terminates SVI transactions and drives the clock, SVC,

and the data, SVD, during a transaction. The slave receives the SVI transactions and acts

2

accordingly. SVI wire protocol is based on fast-mode I C.

SVI interface also considers two additional signal needed to manage the system start-up.

These signals are EN and PWROK. The device return a PWRGOOD signal if the output

voltages are in regulation.

5.4

SVI start-up

Once the SVI mode has been detected on the EN rising-edge, L6717 checks for the status

of the two serial VID pins, SVC and SVD, and stores this value as the Pre-PWROK Metal

VID. The controller initiate a soft-start phase regulating both CORE and NB voltage planes

to the voltage level prescribed by the Pre-PWROK Metal VID. See Table 7 for details about

Pre-PWROK Metal VID codifications. The stored Pre-PWROK Metal VID value are re-used

in any case of PWROK de-assertion.

After bringing the output rails into regulation, the controller asserts the PWRGOOD signal

and waits for PWROK to be asserted. Until PWROK is asserted, the controller regulates to

the Pre-PWROK Metal VID ignoring any commands coming from the SVI interface.

After PWROK is asserted, the processor has initialized the serial VID interface and L6717

waits for commands from the CPU to move the voltage planes from the Pre-PWROK Metal

VID values to the operative VID values. As long as PWROK remains asserted, the controller

will react to any command issued through the SVI interface according to SVI protocol.

See Section 7.8 for details about Soft-Start.

Table 7.

SVC

V_FIX mode and Pre-PWROK MetalVID

Output voltage [V]

SVD

Pre-PWROK metal VID

V_FIX mode

0

1

0

1

0

1

1.1V

1.0V

0.9V

0.8V

1.4V

1.2V

1.0V

0.8V

5.4.1

Set VID command

The set VID command is defined as the command sequence that the CPU issues on the SVI

bus to modify the voltage level of the CORE section and/or the NB section.

During a set VID command, the processor sends the start (START) sequence followed by

the address of the section which the set VID command applies. The processor then sends

the write (WRITE) bit. After the write bit, the voltage regulator (VR) sends the acknowledge

(ACK) bit. The processor then sends the VID bits code during the data phase. The VR

sends the acknowledge (ACK) bit after the data phase. Finally, the processor sends the stop

(STOP) sequence. After the VR has detected the stop, it performs an on-the-fly VID

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Hybrid CPU support and CPU_TYPE detection

L6717

transition for the addressed section(s) or, more in general, react to the sent command

accordingly. Refer to Figure 6, Table 8 and Table 9 for details about the set VID Command.

L6717 is able to manage individual power OFF for both the sections. The CPU may issue a

serial VID command to power OFF or power ON one Section while the other one remains

powered. In this case, the PWRGOOD signal remains asserted.

Figure 6.

SVI Communications - send byte

ACK

STOP

START

SLAVE ADDRESSING + W

ACK

DATA PHASE

6

5

4

3

0

7

6

0

SVC

SVD

ACK

110b

START

Slave Addressing

(7 Clocks)

WRITE ACK

(1Ck) (1Ck)

Data Phase

(8 Clocks)

ACK

(1Ck)

STOP

BUS DRIVEN BY L6717

BUS DRIVEN BY MASTER (CPU)

Table 8.

bits

SVI send byte - address and data phase description

Description

Address phase

6:4

3

Always 110b.

Not applicable, ignored.

2

CORE section⁽¹⁾

If set then the following data byte contains the VID code for CORE section.

NB section⁽¹⁾

.

1

.

0

If set then the following data byte contains the VID code for NB section.

Data phase

PSI_L flag (Active low).When asserted, the VR is allowed to enter power-saving

mode. See Section 5.4.3.

7

6:0

VID code. See Table 9.

1. Assertion in both bit 1 and 0 will address the VID code to both CORE and NB simultaneously.

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L6717

Hybrid CPU support and CPU_TYPE detection

Table 9.

SVI [6:0]

Data phase - serial VID codes

Output

voltage

Output

voltage

Output

voltage

Output

voltage

SVI [6:0]

000_0000

000_0001

000_0010

000_0011

000_0100

000_0101

000_0110

000_0111

000_1000

000_1001

000_1010

000_1011

000_1100

000_1101

000_1110

000_1111

001_0000

001_0001

001_0010

001_0011

001_0100

001_0101

001_0110

001_0111

001_1000

001_1001

001_1010

001_1011

001_1100

001_1101

001_1110

001_1111

1.5500

1.5375

1.5250

1.5125

1.5000

1.4875

1.4750

1.4625

1.4500

1.4375

1.4250

1.4125

1.4000

1.3875

1.3750

1.3625

1.3500

1.3375

1.3250

1.3125

1.3000

1.2875

1.2750

1.2625

1.2500

1.2375

1.2250

1.2125

1.2000

1.1875

1.1750

1.1625

010_0000

010_0001

010_0010

010_0011

010_0100

010_0101

010_0110

010_0111

010_1000

010_1001

010_1010

010_1011

010_1100

010_1101

010_1110

010_1111

011_0000

011_0001

011_0010

011_0011

011_0100

011_0101

011_0110

011_0111

011_1000

011_1001

011_1010

011_1011

011_1100

011_1101

011_1110

011_1111

1.1500

1.1375

1.1250

1.1125

1.1000

1.0875

1.0750

1.0625

1.0500

1.0375

1.0250

1.0125

1.0000

0.9875

0.9750

0.9625

0.9500

0.9375

0.9250

0.9125

0.9000

0.8875

0.8750

0.8625

0.8500

0.8375

0.8250

0.8125

0.8000

0.7875

0.7750

0.7625

100_0000

100_0001

100_0010

100_0011

100_0100

100_0101

100_0110

100_0111

100_1000

100_1001

100_1010

100_1011

100_1100

100_1101

100_1110

100_1111

101_0000

101_0001

101_0010

101_0011

101_0100

101_0101

101_0110

101_0111

101_1000

101_1001

101_1010

101_1011

101_1100

101_1101

101_1110

101_1111

0.7500

0.7375

0.7250

0.7125

0.7000

0.6875

0.6750

0.6625

0.6500

0.6375

0.6250

0.6125

0.6000

0.5875

0.5750

0.5625

0.5500

0.5375

0.5250

0.5125

0.5000

0.4875

0.4750

0.4625

0.4500

0.4375

0.4250

0.4125

0.4000

0.3875

0.3750

0.3625

110_0000

110_0001

110_0010

110_0011

110_0100

110_0101

110_0110

110_0111

110_1000

110_1001

110_1010

110_1011

110_1100

110_1101

110_1110

110_1111

111_0000

111_0001

111_0010

111_0011

111_0100

111_0101

111_0110

111_0111

111_1000

111_1001

111_1010

111_1011

111_1100

111_1101

111_1110

111_1111

0.3500

0.3375

0.3250

0.3125

0.3000

0.2875

0.2750

0.2625

0.2500

0.2375

0.2250

0.2125

0.2000

0.1875

0.1750

0.1625

0.1500

0.1375

0.1250

0.1125

0.1000

0.0875

0.0750

0.0625

0.0500

0.0375

0.0250

0.0125

OFF

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Hybrid CPU support and CPU_TYPE detection

L6717

5.4.2

PWROK de-assertion

Anytime PWROK de-asserts, while EN is asserted, the controller uses the previously stored

Pre-PWROK Metal VID and sets both CORE and NB planes voltage to the corresponding

level performing an on-the-fly VID transition.

Anytime the PWROK is de-asserted the PWRGOOD is tied low; after being pulled low the

PWRGOOD is treated appropriately and kept de-asserted until the output voltage of both

CORE and NB sections is within the PWRGOOD validity window referred to Pre-PWROK

Metal VID.

5.4.3

PSI_L and efficiency optimization at light-load

PSI_L is an active-low flag (i.e. low logic level when asserted) that can be set by the CPU to

allow the VR to enter power-saving mode to maximize the system efficiency when in light-

load conditions. The status of the flag is communicated to the controller through the SVI

bus.

When the PSI_L flag is asserted by the CPU through the SVI bus, the device adjusts the

phase number according to the programmed strategy. Default PSI_L strategy consists in

working in single phase. PSI_L strategy can be disabled as well as re-configured through

2

specific Power Manager I C commands. See Section 6 for details.

When CPU issues PSI_L flag, L6717 adjusts phase number according to the selected

PSI_L strategy: the device sets HiZ on the related phases and re-configures internal phase-

shift to maintain the correct interleaving among active phases. Furthermore, the internal

current-sharing is adjusted considering the phase number reduction.

When PSI_L is de-asserted, the device will return to the original configuration.

Start-up is performed with all the configured phases enabled.

When PSI_L is active L6717 performs on-the-fly VID transitions with all the programmed

phases.

NB section is not impacted by PSI_L status change.

Figure 7 shows an example of the efficiency improvement that can be achieved by enabling

the PSI management.

Figure 7.

System efficiency enhancement by PSI

4 PHASE

1 PHASE

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L6717

Hybrid CPU support and CPU_TYPE detection

5.4.4

HiZ management

L6717 is able to manage HiZ both for internal driver and for external drivers through the

PWMx signals. When the controller needs to set HiZ state for a phase or section, it sets the

corresponding PWMx pin floating and, at the same time, turn OFF both HS and LS

MOSFETs by proper action of the corresponding embedded driver.

5.4.5

Hardware jumper override - V_FIX

VID0/V_FIX pin allows the device to operate in V_FIX mode.

Anytime L6717 is enabled it checks the pin VID0/V_FIX voltage level: pull up VID0/V_FIX to

3.3V to enter V_FIX mode.

When in V_FIX mode, both NB and CORE Section voltages are governed by the information

shown in Table 7.

Regardless of the state of VID1, the device will work in SVI mode and furthermore PWROK

logic level is ignored.

SVC and SVD are considered as static VID and the output voltage changes according to

their status. Dynamic SVC/SVD-change management is provided in this condition.

V_FIX mode is intended for system debug only.

Protection management differs in this case, see Section 8.1 for details.

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Power manager I2C

L6717

2

6

Power manager I C

2

L6717 features a secondary power manager I C bus to easy the implementation of power

management features as well as over-speeding for “enthusiastic” users. The power

2

manager I C bus is operative after the PWRGOOD signal is driven high at the end of the

soft-start.

2

Power manager I C is a two wire, SCL (Clock) and SDA (Data), bus connecting a single

master to one or more slaves (L6717) separately addressable. The master initiates and

2

terminates I C transactions and drives both the clock, SCL, and the data, SDA, during a

2

transaction. The slave receives the I C transactions and acts accordingly.

2

Power manager I C wire protocol is based on fast-mode I C.

2

Power manager I C address configuration can be programmed through ADDR pin while

I2CDIS pin allows to disable the bus. See Table 10.

2

Power manager I C and SVI bus are two independent buses working in parallel. In case two

commends are issued in the same time on the two buses, L6717 performs them in the same

time.

2

Table 10. Power manager I C configuration

I2CDIS

ADDR

Description

2

Power manager I C disabled.

SDA/OVP now becomes OVP to program the OV threshold for

both CORE and NB sections.

3.3V

n/a

SCL/OS now becomes OS to program Offset for the CORE

section.

2

3.3V

It sets I C address to 1100111.

OPEN

2

OPEN

It sets I C address to 1100110 (default).

6.1

Power manager commands

2

Power manager I C master issues different command sequences to modify several voltage

positioning parameters for CORE and/or NB Sections of L6717.

2

Moreover the power manager I C commands allow to configure DPM and other power-

saving-related features.

During a power manager command:

– The bus master sends the start (START) sequence followed by the address of the

controller which the power manager command applies. The bus master then sends

the write (WRITE) bit. After the write bit, the voltage regulator (VR, L6717) sends the

acknowledge (ACK) bit.

– The bus master sends the command code during the command phase. The VR

(L6717) sends the acknowledge (ACK) bit after the command phase.

– The bus master sends the data stream related to the command phase previously

issued (if applicable). The VR (L6717) sends the acknowledge (ACK) bit after the data

stream. Finally, the bus master sends the stop (STOP) sequence.

– After the VR (L6717) has detected the STOP sequence, it performs operations

according to the command issued by the bus master.

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L6717

Power manager I2C

Refer to Figure 8, Table 11 and Table 12 for details.

2

Figure 8.

Power manager I C communication format

COMMAND

2

Table 11. Power manager I C - address and command phase description

bits

Description

Address phase

1:6

Always 110011b.

Slave address.

7

According to ADDR connection, the device will act if addressed by 0b or 1b.

Default address bit is 0b.

8

WRITE bit.

Command phase

1:3

4:6

Not applicable, ignored.

Command code

7, 8

Not applicable, ignored.

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Power manager I2C

L6717

2

Table 12. Power manager I C command phase and data stream

Command

code [4:6]

Data stream

[1:8]

Description

OVERSPEEDING: Adds a positive/negative offset to the regulation

according to the SIGN bit with 50mV LSB and 5bit resolution.

[3] SIGN: 1b for positive offset, 0b for negative offset.

Negative offset is applicable only to CORE section (NB does not react

to negative OS command)

[4:8] OVRSPD: 5bit code (4:MSB to 8:LSB), defines the offset to add

to the programmed reference (VID).

[1:2] xx

[3] SIGN

1CN

Maximum CORE output voltage reachable is limited to 2.8V.

Maximum NB output voltage reachable is limited by the Maximum NB

Offset: +600mV (over VID)

[4:8] OVRSPD

“CN” bits in command code address CORE section (“C” bit) or NB

section (“N” bit) if set to 1b. Asserting both C and N bits will apply the

command to both CORE and NB section.

See Table 13 for details about OVRSPD codification.

OV_SET: Overvoltage threshold setup for CORE and/or NB sections.

Sets the OV threshold above the programmed VID (including

OVRSPD) in with three 200mV steps from + 250mV up to +850mV

(up to 650mV for NB).

[1:4] xxxx

[1:4]: ignored

000

[5:6] OV_NB [5:6] OV_NB: NorthBridge OVP. 2bit code, defines the OV threshold

for the NB section above the programmed reference (VID).

[7:8] OV_CORE

[7:8] OV_CORE: Core OVP. 2bit code, defines the OV threshold for

the CORE section above the programmed reference (VID).

Default OV threshold is +250mV above reference for both sections.

See Table 14 for details about OV_SET codification.

FSW_ADJ: Switching frequency adjustment. Modifies the switching

frequency programmed through OSC pin according to FSW code by

+/- 10% or +/-20%.

[1:5] xxxxx

[6:8] FSW

[1:5]: ignored

001

[6:8]: FSW: Switching frequency adjustment. 3 bits code to adjust the

switching frequency with respect programmed voltage.

See Table 15 for details about FSW_ADJ codification.

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Power manager I2C

2

Table 12. Power manager I C command phase and data stream

Command

code [4:6]

Data stream

[1:8]

Description

DRP_ADJ: Droop function adjustment. Modifies the slope of the

output voltage implemented through the droop function.

[1:4]: ignored

[1:4] xxxx

[5:6] k_DRPNB

[7:8] k_DRP

[5:6]: k_DRPNB. Defines the k_DRPfactor for NB section.

[7:8]: k_DRP. Defines the k_DRPNBfactor for CORE section.

Default value is k_DRPx= 1/4 for both sections.

010

See Table 16 for details about DRP_ADJ codification and Section 7.3

and Section 7.6 for LoadLine definition.

Power management flags: Set of three flags to define power

management actions of the controller.

[1:3]: ignored

[4:5]: DPM thresholds. Default is 00b.

[6] PSI_A: PSI action. It defines the action to take when PSI_L flag is

asserted by SVI bus. The same action is considered by DPM. Send

0b to work in single phase (default) or 1b to work at two phases.

[1:3] xxx

[4:5] DPMTH

[6] PSI_A

[7] PSI_EN: PSI enable. It enables or disables the PSI management.

Set to 1b (default) to manage PSI_L according to PSI_A or set to 0b

to ignore PSI_L flag sent through SVI bus.

011

[7] PSI_EN

[8] DPM_ON

[8] DPM_ON: Dynamic phase management. It enables or disables

the DPM mode. Set to 1b to enable DPM or set to 0b (default) to

disable it.

When enabled DPM acts automatically cutting phases according to

PSI action flag at light load.

See Section 6.2 for details about DPM.

6.1.1

Overspeeding command (OVRSPD)

This command allows to add a variable positive/negative offset to the CORE and/or NB

reference programmed by the SVI bus in order to overspeed the CPU. L6717 allows adding

up to 1.550 V in 50 mV steps to the reference.

The maximum possible output voltage for CORE section is internally limited to 2.8 V. In case

the SVI programmed reference plus the offset set through the OVRSPD command exceed

this value, the reference for the regulation is clamped to 2.8 V.

The maximum possible output voltage for NB section is internally limited by the maximum

offset achievable for NB section that is +600 mV over the SVI programmed reference.

Once the controller acknowledges the command and recognizes the OVRSPD command,

the reference will step up or down until reaching the target offset performing a on-the-fly VID

transition. In case a new overspeed command is issued while the output voltage is not yet

stabilized (i.e. the reference is still stepping to the target), the target is updated according to

the new offset defined.

The command addresses both sections through two separate bits in the command code

(“CN” bits - See Table 12). By asserting the corresponding bit, the subsequent data stream

will apply to the identified section. Asserting both bits (“CN” = 11b) will address both

sections. CN = 00b will be ignored regardless of the data Stream provided. “CN” = 10b and

“CN” = 01b allow to address only CORE or only NB section respectively.

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Power manager I2C

L6717

See Table 12 and Table 13 for details about the codification of the command and the data

stream.

(1) (2)

Table 13. OVRSPD command - offset codification

Data

stream

[4:8]

Offset to

reference

[V]

Data

stream

[4:8]

Offset to

reference

[V]

Data

stream

[4:8]

Offset to

reference

[V]

Data

stream

[4:8]

Offset to

reference

[V]

00000

00001

00010

00011

00100

00101

00110

00111

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

01000

01001

01010

01011

01100

01101

01110

01111

0.40

0.45

0.50

0.55

0.60

0.65

0.70

0.75

10000

10001

10010

10011

10100

10101

10110

10111

0.80

0.85

0.90

0.95

1.00

1.05

1.10

1.15

11000

11001

11010

11011

11100

11101

11110

11111

1.20

1.25

1.30

1.35

1.40

1.45

1.50

1.55

1. Offset is added with an OTF VID transition above the programmed VID.

2. Maximum regulated output voltage is internally limited to 2.8V maximum: regardless the offset over VID

reference the IC does not allow to reach an higher voltage.

6.1.2

Overvoltage threshold adjustment (OV_SET)

This command allows to adjust the overvoltage threshold independently for CORE and NB

Sections. The default OVP threshold value of +250 mV over the reference is adjustable, in

200 mV steps up to +850 mV above the reference for CORE and +650 mV above the

reference for NB.

See Table 12 and Table 14 for details about the codification of the command and the data

stream.

Table 14. OVP_SET command - threshold codification

Data stream [5:6] and [7:8]

OVP threshold [V]

00

01

10

11

+250mV (Default)

+450mV

+650mV

+850mV CORE / +650mV for NB

6.1.3

Switching frequency adjustment (FSW_ADJ)

This command allows to adjust the switching frequency for the system in +/-10% steps

across the main level defined by the OSC pin. Switching frequency margining may benefit

the system from the thermal and performance point of view.

See Table 12 and Table 15 for details about the codification of the command and the data

stream.

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L6717

Power manager I2C

Fsw adjustment

Table 15. FSW_ADJ command - switching frequency adjustment codification

Data stream

[6:8]

Data stream

[6:8]

Fsw adjustment

Reset to frequency

programmed by OSC

Reset to frequency

programmed by OSC

000

100

001

010

011

-10%

-20%

101

110

111

+10%

+20%

Ignored

6.1.4

Droop function adjustment (DRP_ADJ)

This command allows to adjust the slope for the output voltage load line once the external

components are defined by modifying the k

and k

parameters defined in

DRP

DRPNB

Section 7.3 and Section 7.6.

See Table 12 and Table 16 for details about the codification of the command and the data

stream.

Table 16. DRP_ADJ command - droop function adjustment codification

Data stream [5:6] and [7:8]

DRP adjustment k_DRPNB[5:6] and k_DRP[7:8]

00

01

10

11

1/4

1/2

Ignored

Droop disabled

6.1.5

Power management flags

This command allows to set several flags to configure L6717 power management.

The flags allows to define:

– PSI_A. This flag defines phase shedding strategy adopted when CPU asserts PSI_L

by SVI bus. Set PSI_A = 0b (default) to program the device to work in single phase or

set PSI_A = 1b to program two phase mode.

The selected strategy applies also to DPM mode.

See Section 5.4.3 for details about PSI management and light-load efficiency

optimizations. See Section 6.2 for details about DPM.

– PSI_EN. This flag defines whether to enable or not the PSI_L management. Default is

to manage PSI_L flag assertion through SVI bus (PSI_EN = 1b).

– DPM_ON. This flag defines whether to enable or not the DPM mode. The strategy

adopted by DPM is defined through the PSI_A flag. See Section 6.2 for details about

DPM. DPM is disabled by default (DPM_ON = 0h).

– DPMTH. Allow to program up to 4 different strategies for DPM mode by properly

adjusting the V

threshold. See Section 6.2 for details about DPM.

DPM

See Table 12 and Table 17 for details about the codification of the command and the data

stream.

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Power manager I2C

L6717

Table 17. Power management flags

Data stream bit

Flag

Description

[1:3]

[4:5]

n/a

Ignored.

DPM threshold. Allow to define 4 different values for V_DPM

See Section 6.2 for code/thresholds correspondence.

.

DPMTH

PSI_A

0b (default): IC working in single phase when PSI_L asserted.

1b:IC working in two phase when PSI_L asserted.

[6]

[7]

[8]

0b: PSI_L flag in SVI ignored.

1b (default): PSI_L flag in SVI monitored and phase dropping

enabled according to PSI_A.

PSI_EN

0b (default): DPM disabled.

1b: DPM enabled.

DPM_ON

6.2

Dynamic phase management (DPM)

Dynamic phase management allows to adjust the number of working phases according to

the delivered current still maintaining the benefits of the multiphase regulation.

Phase number is reduced by monitoring the voltage level across ILIM pin: L6717 reduces

the number of working phase according to the strategy defined by the PSI_A flag when the

voltage across ILIM pin is lower than V

. When the load current increases the phase

DPM

number is restored to the original value as soon as the voltage across ILIM pin exceeds

V

.

DPM

V

is selected through the DPMTH command. See Section 6.1.

DPM

The current at which the transition happens (I

V_DPMR_G

) can be estimated as:

DPM

-------------- -------------

I_DPM

=

⋅

R_ILIMDCR

V

thresholds are defined as a percentage of the voltage on ILIM pin corresponding to

DPM

the Thermal Design Current of the application.

1.8V on ILIM pin corresponds to 100% of the load and DPM threshold are defined as a

percentage of 1.8V (see Table 18 for details).

An hysteresis is provided for each threshold in order to avoid multiple DPM actions

triggering in steady load conditions.

Table 18.

V

thresholds

DPM

CODE

V_DPM(I_LIMrising)

V_DPM(I_LIMfalling)

00 (default)

20%

25%

30%

35%

15%

20%

25%

30%

01

10

11

DPM is disabled by default: Soft-start is performed with all the available phases.

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L6717

Power manager I2C

When the soft start is over and once PWRGOOD rise to Logic “1”, L6717 can receive

2

commands on power manager I C bus to enable DPM.

Once DPM is enabled, L6717 starts monitoring the ILIM voltage: the voltage is compared

with the internal V

threshold defining the current level to trigger the number modification.

DPM

DPM is reset in particular conditions:

–

during OTF VID transition issued by the CPU;

®

when LTB Technology detects a load transient.

After being reset, DPM is re-enabled with a proper delay: the phase number is again defined

according to the ILIM pin voltage with respect V

.

DPM

Delay in the intervention of DPM can be adjusted by properly sizing the filer across ILIM pin.

Increasing the capacitance results in increased delay in the DPM intervention.

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Output voltage positioning

L6717

7

Output voltage positioning

Output voltage positioning is performed by selecting the controller operative-mode (SVI, PVI

and V_FIX) and by programming the droop function and offset to the reference of both the

sections (See Figure 9). The controller reads the current delivered by each section by

monitoring the voltage drop across the DCR Inductors. The current (I

/ I

)

DROOP DROOP_NB

sourced from the FB / NB_FB pin, directly proportional to the read current, causes the

related section output voltage to vary according to the external R / R

resistor so

FB

FB_NB

implementing the desired load-line effect.

L6717 embeds a dual remote-sense buffer to sense remotely the regulated voltage of each

Section without any additional external components. In this way, the output voltage

programmed is regulated compensating for board and socket losses. Keeping the sense

traces parallel and guarded by a power plane results in common mode coupling for any

picked-up noise.

Figure 9.

Voltage positioning

Offset from Power Manager I2C

(Active when enabled)

Operative only when Power Manager I2C disabled

from SVI DAC...

Clamp to 2.8V_max

CORE_REFERENCE

1.2V

CORE Protection

Monitor

SCL/OS

FB

COMP

C_F

VSEN

FBG

R

OS

R_F

To VDD_CORE

(Remote Sense)

R_FB

from DAC...

NB_REFERENCE

NB Protection

Monitor

NB_FB

NB_COMP

C_{F_NB}

NB_VSEN

NB_FBG

R_{F_NB}

To VDD_NB

(Remote Sense)

R_{FB_NB}

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Output voltage positioning

7.1

CORE section - phase # programming

CORE section implements a flexible 2 to 4 interleaved-phase converter. To program the

desired number of phase, simply short to GND the PWMx signal that is not required to be

used according to Table 19. For three phase operation, short PWM4 to GND while for two

phase operation, short PWM3 and PWM4 to GND.

Caution:

For the disabled phase(s), the current reading pins need to be properly connected to avoid

errors in current-sharing and voltage-positioning: CSxP needs to be connected to the

regulated output voltage while CSxN needs to be connected to CSxP through the same R

G

resistor used for the active phases. See Figure 2 and Figure 3 for details in 3-phase and 2-

phase connections.

Table 19. CORE section - phase number programming

Phase number

PWM3

PWM4

2

3

4

GND

To driver

7.2

CORE section - current reading and current sharing loop

L6717 embeds a flexible, fully-differential current sense circuitry for the CORE Section that

is able to read across inductor parasitic resistance or across a sense resistor placed in

series to the inductor element. The fully-differential current reading rejects noise and allows

placing sensing element in different locations without affecting the measurement's accuracy.

The trans-conductance ratio is issued by the external resistor R placed outside the chip

G

between CSxN pin toward the reading points. The current sense circuit always tracks the

current information, the pin CSxP is used as a reference keeping the CSxN pin to this volt-

age. To correctly reproduce the inductor current an R-C filtering network must be introduced

in parallel to the sensing element. The current that flows from the CSxN pin is then given by

the following equation (See Figure 10):

DCR 1 + s ⋅ L ⁄ DCR

------------- -------------------------------------

⋅ I

I_CSxN

=

⋅

R_G

1 + s ⋅ R ⋅ C

PHASEx

Considering now to match the time constant between the inductor and the R-C filter applied

(Time constant mismatches cause the introduction of poles into the current reading network

causing instability. In addition, it is also important for the load transient response and to let

the system show resistive equivalent output impedance) it results:

R_L

-------

L

------------- = R ⋅ C

⇒

I_CSxN

=

⋅ I_PHASEx= I_INFOx

R_G

DCR

R resistor is typically designed in order to have an information current I

in the range of

G

INFOx

about 35μA (I

) at the OC Threshold.

OCTH

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Output voltage positioning

Figure 10. Current reading

L6717

I_PHASEx

Lx DCR_x

V_OUT

I_CSxN=I_INFOx

R

C

CSxP

CSxN

R_G

Inductor DCR Current Sense

The current read through the CSxP / CSxN pairs is converted into a current I

propor-

INFOx

tional to the current delivered by each phase and the information about the average current

I

= ΣI / N is internally built into the device (N is the number of working phases). The

AVG

INFOx

error between the read current I

and the reference I

is then converted into a voltage

INFOx

AVG

that with a proper gain is used to adjust the duty cycle whose dominant value is set by the

voltage error amplifier in order to equalize the current carried by each phase.

7.3

CORE section - defining load-line

L6717 introduces a dependence of the output voltage on the load current recovering part of

the drop due to the output capacitor ESR in the load transient. Introducing a dependence of

the output voltage on the load current, a static error, proportional to the output current,

causes the output voltage to vary according to the sensed current.

Figure 10 shows the current sense circuit used to implement the load-line. The current flow-

ing across the inductor(s) is read through the R - C filter across CSxP and CSxN pins. R

G

programs a trans-conductance gain and generates a current I

proportional to the current

CSx

of the phase. The sum of the I

current, with proper gain defined by the DRP_ADJ com-

CSx

mand (k

), is then sourced by the FB pin (k

I

). R gives the final gain to pro-

DRP

DRP DROOP FB

gram the desired load-line slope (Figure 9).

Time constant matching between the inductor (L / DCR) and the current reading filter (RC)

is required to implement a real equivalent output impedance of the system so avoiding over

and/or under shoot of the output voltage as a consequence of a load transient. See

Section 7.2. The output characteristic vs. load current is then given by:

DCR

R_G

-------------

⋅ I_OUT= VID – R_LL⋅ I_OUT

V_CORE= VID – R_FB⋅ k_DRP⋅ I_DROOP= VID – k_DRP⋅ R_FB

⋅

Where R is the resulting load-line resistance implemented by the CORE Section. k

value is determined by the Power Manager I C and its default value is 1/4.

LL

DRP

2

R

resistor can be then designed according to the R specifications and DRP_ADJ setting

LL

FB

as follow:

R_LL

R_G

------------- -------------

R_FB

=

⋅

k_DRPDCR

See Section 6.2 for details about DRP_ADJ command.

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Output voltage positioning

7.4

CORE section - analog offset (Optional - I2CDIS = 3.3 V)

2

When power manager I C is disabled (I2CDIS = 3.3 V), L6717 still provide the way to add

positive/negative offset to the CORE section. In this particular conditions, the pin SCL/OS

becomes a virtual ground and allows programming a positive/negative offset (V_OS) for the

CORE section output voltage by connecting a resistor R_OSto SGND/VCC. The pin is inter-

nally fixed at 1.240 V (2.0 V in case of negative offset, R tied to VCC) so a current is pro-

OS

grammed by connecting the resistor R_OSbetween the pin and SGND/VCC: this current is

mirrored and then properly sunk/sourced from the FB pin as shown in Figure 9. Output volt-

age is then programmed as follow:

V_CORE= VID – R_FB⋅ (k_DRP⋅ I_DROOP– I_OS

)

Offset resistor can be designed by considering the following relationship (R_FBis be fixed by

the droop effect):

1.240V

V_OS

------------------

⋅ R_FB(positive offset)

R_OS

=

VCC – 2.0V

-------------------------------

R_OS

⋅ R_FB(negative offset)

V_OS

Caution:

Offset implementation is optional, in case it is not desired, simply short the pin to GND.

In the above formulas, R has to be considered being the total resistance connected

Note:

FB

between FB pin and the regulated voltage. k

value since power manager I C is disabled.

has to be considered having its default

DRP

2

7.5

NB section - current reading

NB section performs the same differential current reading across DCR as the CORE Sec-

tion. According to Section 7.2, the current that flows from the NB_CSN pin is then given by

the following equation (See Figure 10):

DCR(NB)

R_{G_NB}

------------------------

⋅ I_NB= I_{DROOP_NB}

I_{NB_CSN}

=

R

resistor is typically designed according to the OC threshold. See Section 8.4 for

G_NB

details.

7.6

NB section - defining load-line

This method introduces a dependence of the output voltage on the load current recovering

part of the drop due to the output capacitor ESR in the load transient. Introducing a depen-

dence of the output voltage on the load current, a static error, proportional to the output cur-

rent, causes the output voltage to vary according to the sensed current.

Figure 10 shows the current sense circuit used to implement the load-line. The current flow-

ing across the inductor DCR is read through R

. R

programs a trans-conductance

G_NB

gain and generates a current I

proportional to the current delivered by the NB

DROOP_NB

Section that is then sourced from the NB_FB pin with proper gain defined by the DRP_ADJ

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Output voltage positioning

L6717

gives the final gain to program the desired load-line slope

command (k

). R

FB_NB

DRPNB

(Figure 9).

The output characteristic vs. load current is then given by:

V_{OUT_NB}= VID – R_{FB_NB}⋅ k_DRPNB⋅ I_{DROOP_NB}

DCR(NB)

---------------------------

⋅ I_OUT= VID – R_{LL_NB}⋅ I_{OUT_NB}

VID – R_{FB_NB}⋅ k_DRPNB

⋅

R_{G_NB}

Where R

is the resulting Load-Line resistance implemented by the NB Section.

LL_NB

2

k

value is determined by the Power Manager I C and its default value is 1/4.

DRPNB

R

resistor can be then designed according to the R

specifications and DRP_ADJ

FB_NB

LL_NB

setting as follow:

R_{LL_NB}

R_{G_NB}

-------------------- ---------------------------

R_{FB_NB}

=

⋅

k_DRPNBDCR(NB)

7.7

On-the-fly VID transitions

L6717 manages on-the-fly VID Transitions that allow the output voltage of both sections to

modify during normal device operation for CPU power management purposes. OV, UV and

PWRGOOD signals are masked during every OTF-VID Transition and they are re-activated

with a 16 clock cycle delay to prevent from false triggering.

When changing dynamically the regulated voltage (OTF-VID), the system needs to charge

or discharge the output capacitor accordingly. This means that an extra-current I_OTF-VID

needs to be delivered (especially when increasing the output regulated voltage) and it must

be considered when setting the over current threshold of both the sections. This current

results:

dV

--------^O----^U----^T-

⋅

I_OTF-VID= C_OUT

dT_VID

where dV_OUT/ dT_VIDdepends on the operative mode (3mV/μsec. in SVI or externally driven

in PVI).

Overcoming the OC threshold during the dynamic VID causes the device latch and disable.

Dynamic VID transition is managed in different ways according to the device operative

mode:

●

PVI mode.

L6717 checks for VID code modifications (See Figure 11) on the rising-edge of an

internal additional OTFVID-clock and waits for a confirmation on the following falling

edge. Once the new code is stable, on the next rising edge, the reference starts

stepping up or down in LSB increments every two OTFVID-clock cycle until the new

VID code is reached. During the transition, VID code changes are ignored; the device

re-starts monitoring VID after the transition has finished on the next rising-edge

available. OTFVID-clock frequency (F

) is 500 kHz.

OTFVID

If the new VID code is more than 1 LSB different from the previous, the device will

execute the transition stepping the reference with the OTFVID-clock frequency F

OTFVID

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Output voltage positioning

until the new code has reached. The output voltage rate of change will be of 12.5 mV /

4 μsec. = 3.125 mV/μsec.

Figure 11. PVI mode - on-the-fly VID transitions

OTFVID Clock

t

VID [0:5]

t

Int. Reference

T_OTFVID

T

sw

t

V

out

T_VID

x 4 Step VID Transition

4 x 1 Step VID Transition

Vout Slope Controlled by internal

OTFVID-Clock Oscillator

Vout Slope Controlled by external

driving circuit (T_VID

)

●

SVI mode.

As soon as the controller receives a new valid command to set the VID level for one (or

both) of the two sections, the reference of the involved section steps up or down

according to the target-VID with a 3 mV/μsec. slope (Typ). until the new VID code is

reached.

If a new valid command is issued during the transition, the device updates the target-

VID level and performs the on-the-fly transition up to the new code.

Pre-PWROK Metal-VID OTF-VID are not managed in this case because the Pre-

PWROK Metal VID are stored after EN is asserted.

●

V_FIX mode.

L6717 checks for SVC/SVD modifications and, once the new code is stable, it steps the

reference of both sections up or down according to the target-VID with a 3 mV/μsec.

slope (Typ). until the new VID code is reached.

OV, UV and PWRGOOD are masked during the transition and re-activated with a 16 clock

cycle delay after the end of the transition to prevent from false triggering.

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Output voltage positioning

L6717

7.8

Soft-start

L6717 implements a soft-start to smoothly charge the output filter avoiding high in-rush cur-

rents to be required to the input power supply. In SVI mode, soft-start time is intended as the

time required by the device to set the output voltages to the Pre-PWROK Metal VID. During

this phase, the device increases the reference of the enabled section(s) from zero up to the

programmed reference in closed loop regulation. Soft-start is implemented only when VCC

is above UVLO threshold and the EN pin is set free. See Section 5 for details about the SVI

interface and how SVC/SVD are interpreted in this phase.

At the end of the digital soft-start, PWRGOOD signal is set free.

Protections are active during this phase as follow:

–

Undervoltage is enabled when the reference voltage reaches 0.5 V.

Overvoltage is always enabled according to the programmed threshold (by R

FB disconnection is enabled.

).

OVP

Reference is increased with fixed dV/dt; Soft-start time depends on the programmed voltage

as follow:

T_SS[ms] = Target_VID ⋅ 2.56

Figure 12. System start-up: SVI (left) and PVI (right)

7.8.1

LS-Less Start-up

In order to avoid any kind of negative undershoot on the load side during start-up, L6717

performs a special sequence in enabling the drivers for both sections: during the soft-start

phase, the LS MOSFET is kept OFF (PWMx set to HiZ and ENDRV = 0) until the first PWM

pulse. After the first PWM pulse, the PWMx outputs switches between logic “0” and logic “1”

and ENDRV are set to logic “1”.

This particular sequence avoids the dangerous negative spike on the output voltage that

can happen if starting over a pre-biased output especially when exiting from a CORE-OFF

state.

Low-side MOSFET turn-on is masked only from the control loop point of view: protections

are still allowed to turn-ON the low-side MOSFET in case of over voltage if needed.

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L6717

Output voltage monitoring and protections

8

Output voltage monitoring and protections

L6717 monitors the regulated voltage of both sections through pin VSEN and NB_VSEN in

order to manage OV, UV and PWRGOOD. The device shows different thresholds when in

different operative conditions but the behavior in response to a protection event is still the

same as described below.

Protections are active also during soft-start (See Section 7.8) while they are masked during

OTF-VID transitions with an additional delay to avoid false triggering.

Table 20. L6717 protection at a glance

Section

L6717

CORE

North bridge

2

SVI / PVI: +250mV above reference, programmable by power manager I C bus.

I2CDIS = 3.3V: Programmable through SDA/OVP pin.

V_FIX: Fixed to 1.8V.

Overvoltage

(OV)

Action: IC Latch; LS=ON & PWMx = 0 (if applicable);

Other section (SVI only): HiZ; FLT driven high.

VSEN, NB_VSEN = VID -400mV. Active after Ref > 500mV

Undervoltage

(UV)

Action: IC latch; both sections HiZ; FLT driven high.

PWRGOOD is the logic AND between internal CORE and NB PGOOD in SVI

mode while is the CORE section PGOOD in PVI mode.

PWRGOOD

Each PGOOD is set to zero when the related voltage falls below the

programmed reference -250mV.

Action: Section(s) continue switching, PWRGOOD driven low.

Set when VSEN > CS1N +600mV.

Set when VSEN > NB_CSN +600mV.

VSEN, NB_VSEN

disconnection

Action: UV-Like

Action: UV-Like (SVI only)

Internal comparator across the opamp to recover from GND losses.

FBG, NB_FBG

disconnection

Action: UV-Like

Current monitor across inductor DCR.

Dual protection, per-phase and

average.

Current monitor across inductor DCR.

Constant current.

Over Current

(OC)

Action: UV-Like

Protections masked with the exception of OC with additional 16 clock delay to

prevent from false triggering (both SVI and PVI).

On-the-fly VID

8.1

Programmable overvoltage (I2DIS = 3.3 V)

2

When power manager I C is disabled, L6717 provides the possibility to adjust OV threshold

(common for both sections) through the SDA/OVP pin. Connecting the pin to the center tap

of a voltage divider from 3.3 V to SGND, the OVP threshold becomes the voltage present at

the pin.

The OVP threshold results:

R_OVPL

------------------------------------------

OVP_TH= 3.3 ⋅

R

_OVPH+ R_OVPL

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Output voltage monitoring and protections

Figure 13. Analog OVP threshold

L6717

3V3

R_OVPH

SDA/OVP

R_OVPL

C_OVP

Analog OVP Setting (I2C Disabled)

When the voltage sensed by VSEN and/or NB_VSEN overcomes the OV threshold, the con-

troller:

–

Permanently sets the PWM of the involved section to zero keeping ENDRV of that

section high in order to keep all the low-side MOSFETs on to protect the load of

the section in OV condition.

–

Permanently sets the PWM of the non-involved section to HiZ while keeping

ENDRV of the non-involved section low in order to realize an HiZ condition of the

non-involved section.

–

Drives the OSC/ FLT pin high.

Power supply or EN pin cycling is required to restart operations.

Filter OVP pin with 1nF(typ) to SGND.

8.2

Feedback disconnection

L6717 provides both CORE and NB sections with FB disconnection protection. This feature

acts in order to stop the device from regulating dangerous voltages in case the remote

sense connections are left floating. The protection is available for both the sections and

operates for both the positive and negative sense.

According to Figure 14, the protection works as follow:

●

CORE section:

Positive sense is performed monitoring the CORE output voltage through both VSEN

and CS1N. As soon as CS1N is more than 600 mV higher than VSEN, the device

latches in HiZ. FLT pin is driven high. A 30 μA pull-down current on the VSEN forces

the device to detect this fault condition.

Negative sense is performed monitoring the internal OpAmp used to recover the GND

losses by comparing its output and the internal reference generated by the DAC. As

soon as the difference between the output and the input of this OpAmp is higher than

500 mV, the device latches in HiZ. FLT pin is driven high.

●

NB section (SVI only)

Positive sense is performed monitoring the NB output voltage through both NB_VSEN

and NB_CSN. As soon as NB_CSN is more than 600 mV higher than NB_VSEN, the

device latches in HiZ. FLT pin is driven high. A 30 μA pull-down current on the

NB_VSEN forces the device to detect this fault condition.

Negative sense is performed monitoring the internal OpAmp used to recover the GND

losses by comparing its output and the internal reference generated by the DAC. As

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Output voltage monitoring and protections

soon as the difference between the output and the input of this OpAmp is higher than

500mV, the device latches in HiZ. FLT pin is driven high.

To recover from a latch condition, cycle VCC or EN.

Figure 14. FB disconnection protection

500mV

FBG DISCONNECTED

CORE_REFERENCE

from DAC...

CS1-

600mV

FB

COMP

C_F

VSEN

FBG

R_F

To VDD_CORE

(Remote Sense)

R_FB

CORE and NB SECTION - VSEN AND FBG DISCONNECTION

8.3

8.4

PWRGOOD

It is an open-drain signal set free after the soft-start sequence has finished; it is the logic

AND between the internal CORE and NB PGOOD (or just the CORE PGOOD in PVI mode).

It is pulled low when the output voltage of one of the two sections drops 250 mV below the

programmed voltage. It is masked during on-the-fly VID transitions as well as when the

CORE section is set to OFF (from SVI bus) while the NB section is still operative.

Overcurrent

The overcurrent threshold has to be programmed to a safe value, in order to be sure that

each section doesn't enter OC during normal operation of the device. This value must take

into consideration also the extra current needed during the OTF-VID transition (I

) and

OTF-VID

the process spread and temperature variations of the sensing elements (Inductor DCR).

Moreover, since also the internal threshold spreads, the design has to consider the mini-

mum/maximum values of the threshold. Considering the reading method, the two sections

will show different behaviors in OC.

8.4.1

CORE section

L6717 performs two different OC protections for the CORE section: it monitors both the total

current and the per-phase current and allows to set an OC threshold for both.

–

Per-phase OC.

Maximum information current per-phase (I

end-of-scale current (I

for each phase (I

end-of-scale current (i.e. if I

MOSFET until the threshold is re-crossed (i.e. until I

) is internally limited to 35 μA. This

) is compared with the information current generated

). If the current information for the single phase exceed the

INFOx

OC_TH

INFOx

> I

), the device will turn-on the LS

INFOx

OC_TH

< I

).

INFOx

OC_TH

Total current OC.

ILIM pin allows to define a maximum total output current for the system (I

).

OC_TOT

I

current is sourced from the ILIM pin (not altered by DRP_ADJ command). By

LIM

connecting a resistor R

to SGND, a load indicator with 2.5 V (V

) end-of-

ILIM

OC_TOT

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Output voltage monitoring and protections

L6717

scale can be implemented. When the voltage present at the ILIM pin crosses

V

, the device detects an OC and immediately latches with all the MOSFETs

OC_TOT

of all the sections OFF (HiZ).

Typical design considers the intervention of the total current OC before the per-phase OC,

leaving this last one as an extreme-protection in case of hardware failures in the external

components. Typical design flow is the following:

–

Define the maximum total output current (I ) according to system

OC_TOT

requirements

–

Design per-phase OC and R resistor in order to have I

= I

(35 μA)

OC_TH

G

INFOx

when I

is about 10% higher than the I

current. It results:

OUT

OC_TOT

(1.1 ⋅ I_{OC_TOT}) ⋅ DCR

R_G= --------------------------------------------------------

N ⋅ I_OCTH

where N is the number of phases and DCR the DC resistance of the inductors. R

should be designed in worst-case conditions.

G

–

Design the total current OC and R

in order to have the ILIM pin voltage to

ILIM

V

at the desired maximum current I

. It results:

OC_TOT

V_{OC_TOT}⋅ R_G

R_ILIM= --------------------------------------

I_{OC_TOT}⋅ DCR

DCR

-------------

⋅ I_OUT

⎛

⎝

⎞

I_LIM

=

⎠

R_G

where V

desired.

is typically 2.5V and I

is the total current OC threshold

OC_TOT

–

Adjust the defined values according to bench-test of the application.

An additional capacitor in parallel to R

protection intervention.

can be considered to add a delay in the

ILIM

Note:

What previously listed is the typical design flow. Custom design and specifications may

require different settings and ratios between the per-phase OC threshold and the Total

Current OC threshold. Applications with huge ripple across inductors may be required to set

per-phase OC to values different than 110%: design flow should be modified accordingly.

2

DRP_ADJ command from power manager I C does not alter the current information used

for per-phase OC and total current OC.

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Output voltage monitoring and protections

8.4.2

NB section

NB section performs per-phase over current: its maximum information current (I

) is

INFO_NB

internally limited to I

(35 μA typ). If the current information for the NB phase

OCTH_NB

exceeds the end-of-scale current (i.e. if I

> I

), the device will turn-on the

INFO_NB

OCTH_NB

low-side MOSFET, also skipping clock cycles, until the threshold is re-crossed (i.e. until

< I ).

I

INFO_NB

OCTH_NB

After exiting the OC condition, the low-side MOSFET is turned off and the high-side is

turned on with a duty cycle driven by the PWM comparator.

Design R

current.

resistor in order to have I

= I

(35μA) at the I

OCTH_NB OC_NBmax

G_NB

DROOP_NB

It results:

I_{OC_NBmax}⋅ DCR

R_GNB= -------------------------------------------

I_{OCTH_NB}

2

Note:

DRP_ADJ command from power manager I C does not alter the current information used

for per-phase OC.

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Main oscillator

L6717

9

Main oscillator

The controller embeds a dual-oscillator: one section is used for the CORE and it is a multi-

phase programmable oscillator managing equal phase-shift among all phases and the other

section is used for the NB section. Phase-shift between the CORE and NB ramps is

automatically adjusted according to the CORE phase # programmed.

The internal oscillator generates the triangular waveform for the PWM charging and

discharging with a constant current an internal capacitor. The switching frequency for each

channel, F_SW, is internally fixed at 200 kHz: the resulting switching frequency for the CORE

section at the load side results in being multiplied by N (number of configured phases).

The current delivered to the oscillator is typically 20 μA (corresponding to the free running

frequency F_SW=200 kHz) and it may be varied using an external resistor (R_OSC) typically

connected between the OSC pin and SGND. Since the OSC pin is fixed at 1.240 V, the

frequency is varied proportionally to the current sunk from the pin considering the internal

gain of 9.1 kHz/μA (See Figure 15).

Connecting R_OSCto SGND the frequency is increased (current is sunk by the pin),

according to the following relationships:

1.240V

R_OSC

kHz

μA

------------------

----------

⋅ 9.1

F_SW= 200kHz +

Connecting R_OSCto a positive voltage (recommended 3.3 V rail) the frequency is reduced

(current is injected into the pin), according to the following relationships:

+V – 1.240

R_OSC

kHz

μA

---------------------------

----------

⋅ 9.1

F_SW= 200kHz –

where +V is the positive voltage which the R

resistor is connected.

OSC

Figure 15. R_OSCvs. switching frequency

FSW vs. Rosc

425

375

325

275

225

175

125

75

Rosc+ (to SGND)

Rosc- (to 3V3)

0

50

100

150

200

250

300

350

400

450

Rosc [kOhm]

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High current embedded drivers

10

High current embedded drivers

L6717 provides high-current driving control for CORE and NB sections. The driver for the

high-side MOSFET use BOOTx pin for supply and PHASEx pin for return. The driver for the

low-side MOSFET use the VCCDR pin for supply and GND pin for return.

The embedded driver embodies an anti-shoot-through and adaptive dead-time control to

minimize low-side body diode conduction time maintaining good efficiency saving the use of

Schottky diodes: when the high-side MOSFET turns off, the voltage on its source begins to

fall; when the voltage reaches about 2 V, the low-side MOSFET gate drive voltage is

suddenly applied. When the low-side MOSFET turns off, the voltage at LGATE pin is

sensed. When it drops below about 1 V, the high-side MOSFET gate drive voltage is

suddenly applied. If the current flowing in the inductor is negative, the source of high-side

MOSFET will never drop. To allow the low-side MOSFET to turn-on even in this case, a

watchdog controller is enabled: if the source of the High-Side MOSFET doesn't drop, the

low-side MOSFET is switched on so allowing the negative current of the inductor to

recirculate. This mechanism allows the system to regulate even if the current is negative.

10.1

Boot capacitor design

Bootstrap capacitor needs to be designed in order to show a negligible discharge due to the

high-side MOSFET turn-on. In fact it must give a stable voltage supply to the high-side driver

during the MOSFET turn-on also minimizing the power dissipated by the embedded boot

diode. Figure 16 gives some guidelines on how to select the capacitance value for the

bootstrap according to the desired discharge and depending on the selected MOSFET.

To prevent bootstrap capacitor to extra-charge as a consequence of large negative spikes,

an external series resistance R

BOOT pin.

(in the range of few ohms) may be required in series to

BOOT

Figure 16. Bootstrap capacitor design

2500

2000

1500

1000

500

2.5

Cboot = 47nF

Qg = 10nC

Qg = 25nC

Qg = 50nC

Qg = 100nC

2.0

1.5

1.0

0.5

0.0

Cboot = 100nF

Cboot = 220nF

Cboot = 330nF

Cboot = 470nF

0

10

20

30

40

50

60

70

80

90

100

0.0

0.2

0.4

0.6

0.8

1.0

High-Side MOSFET Gate Charge [nC]

Boot Cap Delta Voltage [V]

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High current embedded drivers

L6717

10.2

Power dissipation

It is important to consider the power that the device is going to dissipate in driving the exter-

nal MOSFETs in order to avoid overcoming the maximum junction operative temperature.

Two main terms contribute in the device power dissipation: bias power and drivers' power.

●

Device power (P ) depends on the static consumption of the device through the

DC

supply pins and it is simply quantifiable as follow:

P_DC= V_CC⋅ I_CC+ V_VCCDR⋅ I_VCCDR

●

Drivers' power is the power needed by the driver to continuously switch ON and OFF

the external MOSFETs; it is a function of the switching frequency and total gate charge

of the selected MOSFETs. It can be quantified considering that the total power P

SW

dissipated to switch the MOSFETs dissipated by three main factors: external gate

resistance (when present), intrinsic MOSFET resistance and intrinsic driver resistance.

This last term is the important one to be determined to calculate the device power

dissipation.

The total power dissipated to switch the MOSFETs for each phase featuring embedded

driver results:

P_SWx= F_SW⋅ (Q_GLSx⋅ VCCDR + Q_GHSx⋅ VBOOTx)

Where Q

is the total gate charge of the HS MOSFETs and Q

is the total gate

GHSx

GLSx

charge of the LS MOSFETs for both CORE and NB sections (only Phase1 and Phase2

for CORE section); VBOOTx is the driving voltage for the HSx MOSFETs.

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System control loop compensation

11

System control loop compensation

The device embeds two separate and independent control loops for CORE and NB section.

The control loop for NB section is a simple voltage-mode control loop with (optional) voltage

positioning featured when DROOP pin is shorted with FB. The control loop for the CORE

section also features a current-sharing loop to equalize the current carried by each of the

configured phases.

The CORE control system can be modeled with an equivalent single-phase converter

whose only difference is the equivalent inductor L/N (where each phase has an L inductor

and N is the number of the configured phases). See Figure 17.

Figure 17. Equivalent control loop for NB and CORE sections

d V

NB_COMP

L

V

d V

COMP

L

/N

CORE

V

OUT

NB

OUT_NB

PWM

ESR_NB

ESR

C

O

O_NB

Ref

VID_NB

Ref

VID_CORE

NB_FB

NB_COMP

FB

COMP

R

F_NB

C

F_NB

R

C

F

Z (s)

F

Z

(s)

Z

F

R

FB_NB

R

FB

Z (s)

FB

(s)

FB

This means that the same analysis can be used for both the sections with the only exception

of the different equivalent inductor value (L=L for NB section and L=L /N for the

NB

CORE

CORE section) and the current reading gain (DCR/R

the CORE section).

for NB Section and DCR/R for

G_NB

G

The control loop gain results (obtained opening the loop after the COMP pin):

PWM ⋅ Z_F(s) ⋅ (R_LL+ Z_P(s))

G_LOOP(s) = –-------------------------------------------------------------------------------------------------------------------

Z_F(s)

1

⎛

⎞

[Z_P(s) + Z_L(s)] ⋅ -------------- + 1 + ----------- ⋅ R_FB

⎝

⎠

A(s)

Where:

●

R_LLis the equivalent output resistance determined by the droop function;

●

Z_P(s) is the impedance resulting by the parallel of the output capacitor (and its ESR)

and the applied load R_O;

●

Z_F(s) is the compensation network impedance;

Z_L(s) is the equivalent inductor impedance;

A(s) is the error amplifier gain;

V_IN

-- ------------------

is the PWM transfer function.

3

PWM =

⋅

5

ΔV_OSC

The control loop gain for each section is designed in order to obtain a high DC gain to

minimize static error and to cross the 0dB axes with a constant -20 dB/Dec. slope with the

desired crossover frequency ω_T. Neglecting the effect of Z_F(s), the transfer function has one

zero and two poles; both the poles are fixed once the output filter is designed (LC filter

resonance ω_LC) and the zero (ω_ESR) is fixed by ESR and the droop resistance.

Doc ID 17326 Rev 1

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System control loop compensation

Figure 18. Control loop bode diagram and fine tuning (not in scale)

L6717

dB

C

F

G

(s)

G

(s)

LOOP

K

Z (s)

F

R [dB]

F

R [dB]

F

Z (s)

F

R

F

ω

=

ω

=

ω

LC

F

ω

LC

F

ω

T

ω

ESR

To obtain the desired shape an R_F-C_Fseries network is considered for the Z_F(s)

implementation. A zero at ω_F=1/R_FC_Fis then introduced together with an integrator. This

integrator minimizes the static error while placing the zero ω_Fin correspondence with the L-

C resonance assures a simple -20 dB/Dec. shape of the gain.

In fact, considering the usual value for the output filter, the LC resonance results to be at

frequency lower than the above reported zero.

Compensation network can be simply designed placing ω_F=ω_LCand imposing the cross-

over frequency ω_Tas desired obtaining (always considering that ω_Tmight be not higher than

1/10th of the switching frequency F_SW):

R_FB⋅ ΔV_OSC

3

5

L

--------------------------------- --

------------------------------------------

R_F

=

⋅

⋅ ω_T⋅

V_IN

N ⋅ (R_LL+ ESR)

C_O⋅ L

C_F= -------------------

R_F

11.1

Compensation network guidelines

The compensation network design assures to having system response according to the

cross-over frequency selected and to the output filter considered: it is anyway possible to

further fine-tune the compensation network modifying the bandwidth in order to get the best

response of the system as follow (See Figure 18):

–

Increase R_Fto increase the system bandwidth accordingly;

Decrease R_Fto decrease the system bandwidth accordingly;

Increase C_Fto move ω_Fto low frequencies increasing as a consequence the

system phase margin.

Having the fastest compensation network gives not the confidence to satisfy the

requirements of the load: the inductor still limits the maximum dI/dt that the system can

afford. In fact, when a load transient is applied, the best that the controller can do is to

“saturate” the duty cycle to its maximum (d_MAX) or minimum (0) value. The output voltage

dV/dt is then limited by the inductor charge / discharge time and by the output capacitance.

In particular, the most limiting transition corresponds to the load removal since the inductor

results being discharged only by V_OUT(while it is charged by d_MAXV_IN-V_OUTduring a load

appliance).

50/56

Doc ID 17326 Rev 1

®

L6717

LTB Technology

®

12

LTB Technology

®

LTB Technology further enhances the performances of dual-edge asynchronous systems

by reducing the system latencies and immediately turning ON all the phases to provide the

correct amount of energy to the load. By properly designing the LTB network as well as the

LTB gain, the undershoot and the ring-back can be minimized also optimizing the output

®

capacitors count. LTB Technology applies only to the CORE section.

®

LTB Technology monitors the output voltage through a dedicated pin detecting Load-

Transients with selected dV/dt, it cancels the interleaved phase-shift, turning-on

simultaneously all phases. it then implements a parallel, independent loop that reacts to

load-transients bypassing E/A latencies.

®

LTB Technology control loop is reported in Figure 19.

®

Figure 19. LTB Technology control loop (CORE section)

LTB Ramp

LTB

LT Detect

PWM_BOOST

L/N

V_OUT

d V_COMP

ESR

C_O

PWM

Ref

VID

Monitor

LT Detect

COMP

FB

VSEN

R_LTB

C_LTB

Z_F(s)

Z_FB(s)

The LTB detector is able to detect output load transients by coupling the output voltage

through an R - C network. After detecting a load transient, the LTB Ramp is reset and

LTB

then compared with the COMP pin level. The resulting duty-cycle programmed is then OR-

ed with the PWMx signal of each phase by-passing the main control loop. All the phases will

then be turned-on together and the EA latencies results bypassed as well.

Sensitivity of the load transient detector can be programmed in order to control precisely

both the undershoot and the ring-back.

R

- C

is designed according to the output voltage deviation dV

which is desired the

LTB

OUT

controller to be sensitive as follow:

dV

1

R_LTB= --------^O----^U----^T-

C_LTB= -------------------------------------------------

25μA

2π ⋅ N ⋅ R_LTB⋅ F_SW

®

LTB Technology design tips.

–

Decrease R

to increase the system sensitivity making the system sensitive to

LTB

smaller dV

.

OUT

–

Increase C

to increase the system sensitivity making the system sensitive to

LTB

higher dV/dt.

Doc ID 17326 Rev 1

51/56

Layout guidelines

L6717

13

Layout guidelines

Layout is one of the most important things to consider when designing high current

applications. A good layout solution can generate a benefit in lowering power dissipation on

the power paths, reducing radiation and a proper connection between signal and power

ground can optimize the performance of the control loops.

Two kind of critical components and connections have to be considered when laying-out a

VRM based on L6717: power components and connections and small signal components

connections.

13.1

Power components and connections

These are the components and connections where switching and high continuous current

flows from the input to the load. The first priority when placing components has to be

reserved to this power section, minimizing the length of each connection and loop as much

as possible. To minimize noise and voltage spikes (EMI and losses) these interconnections

must be a part of a power plane and anyway realized by wide and thick copper traces: loop

must be anyway minimized. The critical components, i.e. the power transistors, must be

close one to the other. The use of multi-layer printed circuit board is recommended.

Traces between the driver section and the MOSFETs should be wide to minimize the

inductance of the trace so minimizing ringing in the driving signals. Moreover, VIAs count

needs to be minimized to reduce the related parasitic effect.

Locate the bypass capacitor (VCC, VCCDR and BOOT capacitors) close to the device with

the shortest possible loop and use wide copper traces to minimize parasitic inductance.

Systems that do not use Schottky diodes in parallel to the low-side MOSFET might show big

negative spikes on the phase pin. This spike can be limited as well as the positive spike but

it causes the bootstrap capacitor to be over-charged. This extra-charge can cause, in the

worst case condition of maximum input voltage and during particular transients, that boot-to-

phase voltage overcomes the abs.max.ratings also causing device failures. It is then

suggested in this cases to limit this extra-charge by adding a small resistor R

in series

BOOT

to the boot capacitor or the boot diode. The use of R

the spike present on the BOOT pin.

also contributes in the limitation of

BOOT

Figure 20. Driver turn-on and turn-off paths

VCCDR

C

GD

BOOTx

HGATEx

PHASEx

CGD

RGATE

R

INT

RGATE

RINT

LGATEx

C

GS

CDS

C

GS

CDS

GND (PAD)

LSx DRIVER

LS MOSFET

HSx DRIVER

HS MOSFET

52/56

Doc ID 17326 Rev 1

L6717

Layout guidelines

For heat dissipation, place copper area under the IC. This copper area must be connected

with internal copper layers through several VIAs to improve the thermal conductivity. The

combination of copper pad, copper plane and VIAs under the controller allows the device to

reach its best thermal performances.

13.2

Small signal components and connections

These are small signal components and connections to critical nodes of the application as

well as bypass capacitors for the device supply. Locate the bypass capacitor close to the

device and refer sensible components such as frequency set-up resistor R_OSC, offset

resistor and OVP resistor R_OVPto SGND (when applicable). Star grounding is suggested:

use the device exposed PAD as a connection point.

VSEN pin filtered vs. SGND helps in reducing noise injection into device and EN pin filtered

vs. SGND helps in reducing false trip due to coupled noise: take care in routing driving net

for this pin in order to minimize coupled noise.

Remote buffer connection must be routed as parallel nets from the FBG/FBR pins to the

load in order to avoid the pick-up of any common mode noise. Connecting these pins in

points far from the load will cause a non-optimum load regulation, increasing output

tolerance.

Locate current reading components close to the device. The PCB traces connecting the

reading point must use dedicated nets, routed as parallel traces in order to avoid the pick-up

of any common mode noise. It's also important to avoid any offset in the measurement and,

to get a better precision, to connect the traces as close as possible to the sensing elements.

Symmetrical layout is also suggested. Small filtering capacitor can be added, near the

controller, between V_OUTand SGND, on the CSxN line when reading across inductor to

allow higher layout flexibility.

Doc ID 17326 Rev 1

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VFQFPN48 mechanical data and package dimensions

L6717

14

VFQFPN48 mechanical data and package dimensions

In order to meet environmental requirements, ST offers these devices in different grades of

®

ECOPACK packages, depending on their level of environmental compliance. ECOPACK

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK is an ST trademark.

Figure 21. VFQFPN48 mechanical data and package dimensions

mm

mils

OUTLINE AND

MECHANICAL DATA

DIM.

MIN. TYP. MAX. MIN.

0.800 0.900 1.000 31.50

0.200

TYP. MAX.

A

A3

b

39.37

35.43

7.874

0.180 0.250 0.300 7.087 9.843 11.81

6.900 7.000 7.100 271.6 275.6 279.5

5.050 5.150 5.250 198.8 2.02.7 206.7

D

D2

E

6.900 7.000 7.100

5.050 5.150 5.250

0.500

271.6 275.6 279.5

198.8 202.7 206.7

19.68

E2

e

L

0.300 0.400 0.500 11.81

0.080

VFQFPN-48 (7x7x1.0mm)

Very Fine Quad Flat Package No lead

19.68

3.150

15.75

ddd

54/56

Doc ID 17326 Rev 1

L6717

Revision history

15

Revision history

Table 21. Document revision history

Date

Revision

Changes

29-Mar-2010

1

Initial release.

Doc ID 17326 Rev 1

55/56

L6717

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56/56

Doc ID 17326 Rev 1


型号：	L6717TR
厂家：	ST
描述：	High-Efficiency Hybrid AM2r2 Controller with I<sup>2</sup>C Interface and Embedded Drivers 开关
文件：	总56页 (文件大小：1056K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

L6717TR [STMICROELECTRONICS]

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