L6917_技术文档

L6917B

5 BIT PROGRAMMABLE DUAL-PHASE CONTROLLER

■

2 PHASE OPERATION WITH

SYNCRHONOUS RECTIFIER CONTROL

ULTRA FAST LOAD TRANSIENT RESPONSE

INTEGRATED HIGH CURRENT GATE

DRIVERS: UP TO 2A GATE CURRENT

TTL-COMPATIBLE 5 BIT PROGRAMMABLE

OUTPUT COMPLIANT WITH VRM 9.0

0.8% INTERNAL REFERENCE ACCURACY

10% ACTIVE CURRENT SHARING

ACCURACY

■

SO-28

■

ORDERING NUMBERS:L6917BD

L6917BDTR (Tape & Reel)

■

DESCRIPTION

■

DIGITAL 2048 STEP SOFT-START

OVERVOLTAGE PROTECTION

The device is a power supply controller specifically

designed to provide a high performance DC/DC con-

version for high current microprocessors.

The device implements a dual-phase step-down con-

troller with a 180° phase-shift between each phase.

A precise 5-bit digital to analog converter (DAC) al-

lows adjusting the output voltage from 1.100V to

1.850V with 25mV binary steps.

The high precision internal reference assures the se-

lected output voltage to be within ±0.8%. The high

peak current gate drive affords to have fast switching

to the external power mos providing low switching

losses.

The device assures a fast protection against load

over current and load over/under voltage. An internal

crowbar is provided turning on the low side mosfet if

an over-voltage is detected. In case of over-current,

the system works in Constant Current mode.

OVERCURRENT PROTECTION REALIZED

USING THE LOWER MOSFET'S R

SENSE RESISTOR

OR A

dsON

■

300 kHz INTERNAL OSCILLATOR

OSCILLATOR EXTERNALLY ADJUSTABLE

UP TO 600kHz

POWER GOOD OUTPUT AND INHIBIT

FUNCTION

REMOTE SENSE BUFFER

PACKAGE: SO-28

■

APPLICATIONS

■

POWER SUPPLY FOR SERVERS AND

WORKSTATIONS

■

POWER SUPPLY FOR HIGH CURRENT

MICROPROCESSORS

DISTRIBUTED DC-DC CONVERTERS

BLOCK DIAGRAM

ROSC / INH

SGND

VCCDR

BOOT1

PGOOD

UGATE1

PHASE1

HS

2

PHASE

OSCILLATOR

PWM1

-

+

CH 1 OVER

CURRENT

LGATE1

ISEN1

LS

DIGITAL

SOFT START

VCC

VCCDR

CURRENT

READING

LOGIC

AND

PROTECTIONS

PGNDS1

PGND

TOTAL

CURRENT

+

VID4

VID3

AVG

CURRENT

PGNDS2

CURRENT

READING

VID2

VID1

VID0

< >

DAC

CH2 OVER

CURRENT

ISEN2

CH1 OVER

CURRENT

LGATE2

CH

CURRENT

2 OVER

LS

10k

+

-

10k

IFB

FBG

FBR

PHASE2

UGATE2

BOOT2

PWM2

ERROR

AMPLIFIER

REMOTE

BUFFER

HS

10k

Vcc

VSEN

COMP

Vcc

FB

September 2002

1/33

L6917B

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Value

15

Unit

V

Vcc, V

to PGND

CCDR

V

-V

Boot Voltage

15

V

BOOT PHASE

V

-V

15

V

UGATE1 PHASE1

-V

UGATE2 PHASE2

LGATE1, PHASE1, LGATE2, PHASE2 to PGND

All other pins to PGND

-0.3 to Vcc+0.3

-0.3 to 7

26

V

Sustainable Peak Voltage t < 20ns @ 600kHz

phase

THERMAL DATA

Symbol

Parameter

Value

60

Unit

°C/W

°C

R

Thermal Resistance Junction to Ambient

Maximum junction temperature

Storage temperature range

th j-amb

T

150

max

T

-40 to 150

-25 to 125

2

°C

storage

T

j

Junction Temperature Range

°C

P

Max power dissipation at T

= 25°C

W

MAX

amb

PIN CONNECTION

LGATE1

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

PGND

LGATE2

PHASE2

UGATE2

BOOT2

PGOOD

VID4

VCCDR

PHASE1

UGATE1

BOOT1

VCC

2

3

4

5

6

GND

7

COMP

FB

8

VID3

9

VID2

VSEN

FBR

10

11

12

13

14

VID1

VID0

FBG

OSC / INH / FAULT

ISEN2

ISEN1

PGNDS1

PGNDS2

SO28

2/33

L6917B

ELECTRICAL CHARACTERISTICS

= 12V 10%, T = 0 to 70°C unless otherwise specified

V

±

CC

J

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

Vcc SUPPLY CURRENT

Vcc supply current

I

HGATEx and LGATEx open

=V =12V

7.5

10

12.5

mA

CC

V

CCDR

BOOT

I

V

supply current

LGATEx open; V =12V

CCDR

2

3

1

4

mA

CCDR

I

Boot supply current

HGATEx open; PHASEx to PGND

0.5

1.5

BOOTx

V

=V

=12V

CC

BOOT

POWER-ON

Turn-On V threshold

V

Rising; V

Falling; V

=5V

7.8

6.5

4.2

9

10.2

8.5

V

CC

CCDR

Turn-Off V threshold

=5V

7.5

4.4

CC

CCDR

Turn-On V

Threshold

V

Rising

4.6

CCDR

=12V

CC

Turn-Off V

Threshold

V

Falling

=12V

4.0

4.2

4.4

V

CCDR

CC

OSCILLATOR/INHIBIT/FAULT

f

Initial Accuracy

OSC = OPEN

OSC = OPEN; Tj=0°C to 125°C

278

270

300

322

330

kHz

OSC

f

Total Accuracy

R to GND=74kΩ

450

0.8

70

500

0.85

75

550

0.9

kHz

V

OSC,Rosc

INH

T

Inhibit threshold

Maximum duty cycle

Ramp Amplitude

I

=5mA

SINK

d

MAX

OSC = OPEN

%

V

∆Vosc

1.8

4.75

2

2.2

FAULT Voltage at pin OSC

OVP or UVP Active

5.0

5.25

V

REFERENCE AND DAC

Output Voltage

Accuracy

VID0, VID1, VID2, VID3, VID4

see Table1;

-0.8

-

0.8

%

FBR = V ; FBG = GND

OUT

I

VID pull-up Current

VID pull-up Voltage

VIDx = GND

4

5

-

6

µA

DAC

VIDx = OPEN

3.1

3.4

V

ERROR AMPLIFIER

DC Gain

80

15

dB

SR

Slew-Rate

COMP=10pF

V/µs

DIFFERENTIAL AMPLIFIER (REMOTE BUFFER)

DC Gain

1

V/V

dB

CMRR Common Mode Rejection Ratio

40

3/33

L6917B

ELECTRICAL CHARACTERISTICS (continued)

V

= 12V

±

10%, T = 0 to 70°C unless otherwise specified

CC

J

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

Input Offset

FBR=1.100V to1.850V;

FBG=GND

-12

12

mV

SR

Slew Rate

VSEN=10pF

15

50

V/µs

µA

DIFFERENTIAL CURRENT SENSING

I

,

Bias Current

Iload=0

45

55

ISEN1

I

ISEN2

I

Bias Current

45

80

50

85

55

90

µA

PGNDSx

I

,

Bias Current at

ISEN1

Over Current Threshold

I

ISEN2

I

Active Droop Current

Iload<0%

Iload=100%

0

50

1

52.5

µA

FB

47.5

GATE DRIVERS

t

High Side

Rise Time

V

C

-V =10V;

BOOTx PHASEx

15

2

30

ns

A

RISE

HGATE

to PHASEx=3.3nF

HGATEx

I

High Side

Source Current

V

-V =10V

BOOTx PHASEx

HGATEx

R

High Side

Sink Resistance

-V =12V;

BOOTx PHASEx

1.5

2

2.5

55

Ω

HGATEx

t

Low Side

Rise Time

V

C

=10V;

30

ns

RISE

CCDR

LGATE

to PGNDx=5.6nF

LGATEx

I

Low Side

Source Current

V

=10V

1.8

1.1

A

LGATEx

CCDR

R

Low Side

=12V

0.7

1.5

Ω

LGATEx

Sink Resistance

P GOOD and OVP/UVP PROTECTIONS

PGOOD Upper Threshold

V

Rising

Falling

Rising

Falling

108

84

112

88

116

92

%

V

SEN

(V

SEN

/DACOUT)

PGOOD Lower Threshold

(V /DACOUT)

SEN

OVP

Over Voltage Threshold

(V

2.0

56

2.25

64

)

SEN

UVP

Under Voltage Trip

(V /DACOUT)

60

%

V

SEN

V

PGOOD Voltage Low

I

= -4mA

PGOOD

0.3

0.4

0.5

PGOOD

4/33

L6917B

Table 1. VID Settings

VID4

1

0

VID3

VID2

1

0

1

0

1

0

1

0

VID1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

VID0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Output Voltage (V)

1

0

1

0

OUTPUT OFF

1.100

1.125

1.150

1.175

1.200

1.225

1.250

1.275

1.300

1.325

1.350

1.375

1.400

1.425

1.450

1.475

1.500

1.525

1.550

1.575

1.600

1.625

1.650

1.675

1.700

1.725

1.750

1.775

1.800

1.825

1.850

5/33

L6917B

PIN FUNCTION

N

1

2

3

Name

LGATE1 Channel 1 low side gate driver output.

Description

VCCDR Mosfet driver supply. It can be varied from 5V to 12V.

PHASE1 This pin is connected to the source of the upper mosfet and provides the return path for the high

side driver of channel 1.

4

5

UGATE1 Channel 1 high side gate driver output.

BOOT1 Channel 1 bootstrap capacitor pin. Through this pin is supplied the high side driver and the upper

mosfet. Connect through a capacitor to the PHASE1 pin and through a diode to Vcc (cathode vs.

boot).

6

7

8

VCC

GND

Device supply voltage. The operative supply voltage is 12V.

All the internal references are referred to this pin. Connect it to the PCB signal ground.

COMP This pin is connected to the error amplifier output and is used to compensate the control

feedback loop.

9

FB

This pin is connected to the error amplifier inverting input and is used to compensate the voltage

control feedback loop.

A current proportional to the sum of the current sensed in both channel is sourced from this pin

(50µA at full load, 70µA at the Over Current threshold). Connecting a resistor between this pin

and VSEN pin allows programming the droop effect.

10

11

VSEN

Connected to the output voltage it is able to manage Over & Under-voltage conditions and the

PGOOD signal. It is internally connected with the output of the Remote Sense Buffer for Remote

Sense of the regulated voltage.

If no Remote Sense is implemented, connect it directly to the regulated voltage in order to

manage OVP, UVP and PGOOD.

FBR

FBG

Remote sense buffer non-inverting input. It has to be connected to the positive side of the load to

perform a remote sense.

If no remote sense is implemented, connect directly to the output voltage (in this case connect

also the VSEN pin directly to the output regulated voltage).

12

13

Remote sense buffer inverting input. It has to be connected to the negative side of the load to

perform a remote sense.

Pull-down to ground if no remote sense is implemented.

ISEN1 Channel 1 current sense pin. The output current may be sensed across a sense resistor or

across the low-side mosfet Rds This pin has to be connected to the low-side mosfet drain or

ON.

to the sense resistor through a resistor Rg in order to program the positive current limit at 140%

as follow:

35µA R_g

I_MAX= --------------------------

R_sense

Where 35µA is the current offset information relative to the Over Current condition (offset at OC

threshold minus offset at zero load).

The net connecting the pin to the sense point must be routed as close as possible to the

PGNDS1 net in order to couple in common mode any picked-up noise.

14

15

PGNDS1 Channel 1 Power Ground sense pin. The net connecting the pin to the sense point (*) must be

routed as close as possible to the ISEN1 net in order to couple in common mode any picked-up

noise.

PGNDS2 Channel 2 Power Ground sense pin. The net connecting the pin to the sense point (*) must be

routed as close as possible to the ISEN2 net in order to couple in common mode any picked-up

noise.

(*) Through a resistor Rg.

6/33

L6917B

PIN FUNCTION (continued)

N

Name

Description

16

ISEN2 Channel 2 current sense pin. The output current may be sensed across a sense resistor or

across the low-side mosfet Rds This pin has to be connected to the low-side mosfet drain or

ON.

to the sense resistor through a resistor Rg in order to program the positive current limit at 140%

as follow:

35µA R_g

I_MAX= --------------------------

R_sense

Where 35µA is the current offset information relative to the Over Current condition (offset at OC

threshold minus offset at zero load).

The net connecting the pin to the sense point must be routed as close as possible to the

PGNDS2 net in order to couple in common mode any picked-up noise.

17

OSC/

INH/

Oscillator switching frequency pin. Connecting an external resistor from this pin to GND, the

external frequency is increased according to the equation:

FAULT

14.82 10⁶

f _S= 300KHz + -----------------------------

R

_OSC(KΩ)

Connecting a resistor from this pin to Vcc (12V), the switching frequency is reduced according to

the equation:

12.91 10⁷

f _S= 300KHz – -----------------------------

R

_OSC(KΩ)

If the pin is not connected, the switching frequency is 300KHz.

Forcing the pin to a voltage lower than 0.8V, the device stop operation and enter the inhibit state.

The pin is forced high when an over or under voltage is detected. This condition is latched; to

recover it is necessary turn off and on VCC.

18-22

23

VID4-0 Voltage IDentification pins. These input are internally pulled-up and TTL compatible. They are

used to program the output voltage as specified in Table 1 and to set the power good thresholds.

Connect to GND to program a ‘0’ while leave floating to program a ‘1’.

PGOOD This pin is an open collector output and is pulled low if the output voltage is not within the above

specified thresholds.

If not used may be left floating.

24

BOOT2 Channel 2 bootstrap capacitor pin. Through this pin is supplied the high side driver and the upper

mosfet. Connect through a capacitor to the PHASE2 pin and through a diode to Vcc (cathode vs.

boot).

25

26

UGATE2 Channel 2 high side gate driver output.

PHASE2 This pin is connected to the source of the upper mosfet and provides the return path for the high

side driver of channel 2.

27

28

LGATE2 Channel 2 low side gate driver output.

PGND Power ground pin. This pin is common to both sections and it must be connected through the

closest path to the low side mosfets source pins in order to reduce the noise injection into the

device.

7/33

L6917B

Device Description

The device is an integrated circuit realized in BCD technology. It provides complete control logic and protections

for a high performance dual-phase step-down DC-DC converter optimized for microprocessor power supply. It

is designed to drive N Channel MOSFETs in a dual-phase synchronous-rectified buck topology. A 180 deg

phase shift is provided between the two phases allowing reduction in the input capacitor current ripple, reducing

also the size and the losses. The output voltage of the converter can be precisely regulated, programming the

VID pins, from 1.100V to 1.850V with 25mV binary steps, with a maximum tolerance of ±0.8% over temperature

and line voltage variations. The device provides an average current-mode control with fast transient response.

It includes a 300kHz free-running oscillator adjustable up to 600kHz. The error amplifier features a 15V/

rate that permits high converter bandwidth for fast transient performances. Current information is read across

the lower mosfets r or across a sense resistor in fully differential mode. The current information corrects

µ

s slew

DSON

the PWM output in order to equalize the average current carried by each phase. Current sharing between the

two phases is then limited at ±10% over static and dynamic conditions. The device protects against over-cur-

rent, with an OC threshold for each phase, entering in constant current mode. Since the current is read across

the low side mosfets, the constant current keeps constant the bottom of the inductors current triangular wave-

form. When an under voltage is detected the device latches and the FAULT pin is driven high. The device per-

forms also over voltage protection that disable immediately the device turning ON the lower driver and driving

high the FAULT pin.

Oscillator

The device has been designed in order to operate an each phase at the same switching frequency of the internal

oscillator. So, input and output resulting frequency is doubled.

The switching frequency is internally fixed to 300kHz. The internal oscillator generates the triangular waveform

for the PWM charging and discharging with a constant current an internal capacitor. The current delivered to the

µ

oscillator is typically 25 A and may be varied using an external resistor (R

) connected between OSC pin

OSC

and GND or Vcc. Since the OSC pin is maintained at fixed voltage (typ). 1.235V, the frequency is varied pro-

µ

portionally to the current sunk (forced) from (into) the pin considering the internal gain of 12KHz/ A.

In particular connecting it to GND the frequency is increased (current is sunk from the pin), while connecting ROSC

to Vcc=12V the frequency is reduced (current is forced into the pin), according to the following relationships:

6

1.237

+ -----------------------------

kHz

---------- =

14.82 10

=

S

+ -----------------------------

R

vs. GND: f

300kHz

12

300kHz

OSC

( Ω)

µ

A

R

K

( Ω)

R

K

OSC

7

–

12 1.237

kHz

----------

12

12.918 10

-----------------------------

=

–

=

– -------------------------------

( Ω)

R

vs. 12V: f

300kHz

S

( Ω)

µ

A

R

K

R

K

OSC

µ

Note that forcing a 25 A current into this pin, the device stops switching because no current is delivered to the

oscillator.

Figure 1. R

vs. Switching Frequency

OSC

7000

1000

900

800

700

600

500

400

300

200

100

0

6000

5000

4000

3000

2000

1000

0

100

200

300

300 400 500 600 700 800 900 1000

Frequency (KHz)

8/33

L6917B

Digital to Analog Converter

The built-in digital to analog converter allows the adjustment of the output voltage from 1.100V to 1.850V with

25mV as shown in the previous table 1. The internal reference is trimmed to ensure the precision of 0.8% and

a zero temperature coefficient around 70°C. The internal reference voltage for the regulation is programmed by

the voltage identification (VID) pins. These are TTL compatible inputs of an internal DAC that is realized by

means of a series of resistors providing a partition of the internal voltage reference. The VID code drives a mul-

tiplexer that selects a voltage on a precise point of the divider. The DAC output is delivered to an amplifier ob-

taining the VPROG voltage reference (i.e. the set-point of the error amplifier). Internal pull-ups are provided

µ

(realized with a 5 A current generator up to 3.3V max); in this way, to program a logic "1" it is enough to leave

the pin floating, while to program a logic "0" it is enough to short the pin to GND. VID code “11111” programs

the NOCPU state: all mosfets are turned OFF and the condition is latched.

The voltage identification (VID) pin configuration also sets the power-good thresholds (PGOOD) and the over-

voltage protection (OVP) thresholds.

Soft Start and INHIBIT

At start-up a ramp is generated increasing the loop reference from 0V to the final value programmed by VID in

2048 clock periods as shown in figure 2.

Before soft start, the lower power MOS are turned ON after that V

reaches 2V (independently by Vcc value)

CCDR

to discharge the output capacitor and to protect the load from high side mosfet failures. Once soft start begins,

the reference is increased; when it reaches the bottom of the oscillator triangular waveform (1V typ) also the

upper MOS begins to switch and the output voltage starts to increase with closed loop regulation.. At the end of

the digital soft start, the Power Good comparator is enabled and the PGOOD signal is then driven high (See fig.

2). The Under Voltage comparator enabled when the reference voltage reaches 0.8V.

The Soft-Start will not take place, if both V and VCCDR pins are not above their own turn-on thresholds. Dur-

CC

ing normal operation, if any under-voltage is detected on one of the two supplies the device shuts down.

Forcing the OSC/INH/FAULT pin to a voltage lower than 0.8V the device enter in INHIBIT mode: all the power

mosfets are turned off until this condition is removed. When this pin is freed, the OSC/INH/FAULT pin reaches

the band-gap voltage and the soft start begins.

Figure 2. Soft Start

V_IN=V_CCDR

Turn ON threshold

2V

V_LGATEx

t

V_OUT

PGOOD

2048 Clock Cycles

Timing Diagram

Acquisition:

CH1 = PGOOD; CH2 = V ; CH4 = LGATEx

OUT

9/33

L6917B

Driver Section

The integrated high-current drivers allow using different types of power MOS (also multiple MOS to reduce the

RDSON), maintaining fast switching transition.

The drivers for the high-side mosfets use BOOTx pins for supply and PHASEx pins for return. The drivers for

the low-side mosfets use VCCDRV pin for supply and PGND pin for return. A minimum voltage of 4.6V at VC-

CDRV pin is required to start operations of the device.

The controller embodies a sophisticated anti-shoot-through system to minimize low side body diode conduction

time maintaining good efficiency saving the use of Schottky diodes. The dead time is reduced to few nanosec-

onds assuring that high-side and low-side mosfets are never switched on simultaneously: when the high-side

mosfet turns off, the voltage on its source begins to fall; when the voltage reaches 2V, the low-side mosfet gate

drive is applied with 30ns delay. When the low-side mosfet turns off, the voltage at LGATEx pin is sensed. When

it drops below 1V, the high-side mosfet gate drive is applied with a delay of 30ns. If the current flowing in the

inductor is negative, the source of high-side mosfet will never drop. To allow the turning on of the low-side mos-

fet even in this case, a watchdog controller is enabled: if the source of the high-side mosfet don't drop for more

than 240ns, the low side mosfet is switched on so allowing the negative current of the inductor to recirculate.

This mechanism allows the system to regulate even if the current is negative.

The BOOTx and VCCDR pins are separated from IC's power supply (VCC pin) as well as signal ground (SGND

pin) and power ground (PGND pin) in order to maximize the switching noise immunity. The separated supply

for the different drivers gives high flexibility in mosfet choice, allowing the use of logic-level mosfet. Several com-

bination of supply can be chosen to optimize performance and efficiency of the application. Power conversion

is also flexible, 5V or 12V bus can be chosen freely.

The peak current is shown for both the upper and the lower driver of the two phases in figure 3. A 10nF capac-

itive load has been used. For the upper drivers, the source current is 1.9A while the sink current is 1.5A with

V

-V

= 12V; similarly, for the lower drivers, the source current is 2.4A while the sink current is 2A with

BOOT PHASE

VCCDR = 12V.

Figure 3. Drivers peak current: High Side (left) and Low Side (right)

CH3 = HGATE1; CH4 = HGATE2

CH3 = LGATE1; CH4 = LGATE2

Current Reading and Over Current

The current flowing trough each phase is read using the voltage drop across the low side mosfets r

or

DSON

across a sense resistor (R ) and internally converted into a current. The transconductance ratio is issued

SENSE

by the external resistor Rg placed outside the chip between ISENx and PGNDSx pins toward the reading points.

The full differential current reading rejects noise and allows to place sensing element in different locations with-

out affecting the measurement's accuracy. The current reading circuitry reads the current during the time in

10/33

L6917B

which the low-side mosfet is on (OFF Time). During this time, the reaction keeps the pin ISENx and PGNDSx

at the same voltage while during the time in which the reading circuitry is off, an internal clamp keeps these two

pins at the same voltage sinking from the ISENx pin the necessary current.

The proprietary current reading circuit allows a very precise and high bandwidth reading for both positive and

negative current. This circuit reproduces the current flowing through the sensing element using a high speed

Track & Hold transconductance amplifier. In particular, it reads the current during the second half of the OFF

time reducing noise injection into the device due to the mosfet turn-on (See fig. 4). Track time must be at least

200ns to make proper reading of the delivered current.

Figure 4. Current Reading Timing (Left) and Circuit (Right)

I_LS1

LGATEX

Rg

I_LS2

ISENX

I_ISENx

Total current

information

Rg

PGNDSX

50µA

Track & Hold

µ

This circuit sources a constant 50 A current from the PGNDSx pin and keeps the pins ISENx and PGNDSx at

the same voltage. Referring to figure 4, the current that flows in the ISENx pin is then given by the following

equation:

R

I

SENSE PHASE

=

µ

+ ---------------------------------------------- =

µ

+

50 A I

INFOx

I

50 A

ISENx

R

g

Where R

is an external sense resistor or the rds,on of the low side mosfet and Rg is the transconductance

SENSE

resistor used between ISENx and PGNDSx pins toward the reading points; I

is the current carried by each

PHASE

phase and, in particular, the current measured in the middle of the oscillator period

The current information reproduced internally is represented by the second term of the previous equation as

follow:

R

I

SENSE PHASE

= ----------------------------------------------

I

INFOx

R

g

Since the current is read in differential mode, also negative current information is kept; this allow the device to

check for dangerous returning current between the two phases assuring the complete equalization between the

phase's currents.

From the current information of each phase, information about the total current delivered (I = I

+ I

)

FB

INFO1

INFO2

and the average current for each phase (I

= (I

+ I

)/2 ) is taken. I

INFO2

is then compared to I

INFOX AVG

AVG

INFO1

to give the correction to the PWM output in order to equalize the current carried by the two phases.

µ

The transconductance resistor Rg has to be designed in order to have current information of 25 A per phase

µ

at full nominal load; the over current intervention threshold is set at 140% of the nominal (IINFOx = 35 A).

According to the above relationship, the limiting current (I ) for each phase, which has to be placed at one half

LIM

of the total delivered maximum current, results:

I

R

SENSE

µ

35 A Rg

R

LIM

= ---------------------------

= -------------------------------------

Rg

I

LIM

µ

35 A

SENSE

An over current is detected when the current flowing into the sense element is greater than 140% of the nominal

11/33

L6917B

µ

>35 A): the device enters in Quasi-Constant-Current operation. The low-side mosfets stays ON

INFOx

current (I

µ

becomes lower than 35 A skipping clock cycles. The high side mosfets can be turned ON with a T

ON

until I

INFO

imposed by the control loop at the next available clock cycle and the device works in the usual way until another

OCP event is detected.

The device limits the bottom of the inductor current triangular waveform. So the average current delivered can

slightly increase also in Over Current condition since the current ripple increases. In fact, the ON time increases

due to the OFF time rise because of the current has to reach the 140% bottom. The worst-case condition is

when the duty cycle reaches its maximum value (d=75% internally limited). When this happens, the device

works in Constant Current and the output voltage decrease as the load increase. Crossing the UVP threshold

causes the device to latch (FAULT pin is driven high).

Figure 5 shows this working condition

Figure 5. Constant Current operation

Ipeak

Vout

Droop

effect

I_MAX

140%

UVP

TonMAX

Iout

MAX

OCP

I

Inom

I

It can be observed that the peak current (Ipeak) is greater than the 140% but it can be determined as follow:

–

V

Vout

MIN

IN

--------------------------------------

+

=

Ipeak

1.4 I

Ton

MAX

NOM

L

Where I

is the nominal current and Vout

is the minimum output voltage (VID-40% as explained below).

MIN

NOM

The device works in Constant-Current, and the output voltage decreases as the load increase, until the output

voltage reaches the under-voltage threshold (Vout ). When this threshold is crossed, all mosfets are turned

MIN

off, the FAULT pin is driven high and the device stops working. Cycle the power supply to restart operation.

The maximum average current during the Constant-Current behavior results:

–

Ipeak 1.4 I

NOM

------------------------------------------------

=

+

2

I

1.4 I

MAX

NOM

2

In this particular situation, the switching frequency results reduced. The ON time is the maximum allowed (Ton-

MAX) while the OFF time depends on the application:

–

Ipeak 1.4 I

NOM

1

------------------------------------------------

=

= ------------------------------------------

f

T

L

OFF

Vout

+

T

Ton

MAX

OFF

µ

reaches 35 A. The full load value is only a convention to work with con-

Over current is set anyway when I

INFOx

venient values for I . Since the OCP intervention threshold is fixed, to modify the percentage with respect to

FB

the load value, it can be simply considered that, for example, to have on OCP threshold of 170%, this will cor-

µ

µ µ

= 20.5 A (I = 41 A).

INFOx FB

respond to I

= 35 A (I = 70 A). The full load current will then correspond to I

INFOx

FB

12/33

L6917B

Integrated Droop Function

The device uses a droop function to satisfy the requirements of high performance microprocessors, reducing

the size and the cost of the output capacitor.

This method "recovers" part of the drop due to the output capacitor ESR in the load transient, introducing a de-

pendence of the output voltage on the load current

As shown in figure 6, the ESR drop is present in any case, but using the droop function the total deviation of the

output voltage is minimized. In practice the droop function introduces a static error (Vdroop in figure 6) propor-

tional to the output current. Since the device has an average current mode regulation, the information about the

total current delivered is used to implement the Droop Function. This current (equal to the sum of both I

)

INFOx

is sourced from the FB pin. Connecting a resistor between this pin and Vout, the total current information flows

only in this resistor because the compensation network between FB and COMP has always a capacitor in series

(See fig. 7). The voltage regulated is then equal to:

V

= V - R · I

ID FB FB

OUT

Since I depends on the current information about the two phases, the output characteristic vs. load current is

FB

given by:

R

SENSE

=

–

---------------------

V

VID

R

I

OUT

FB

Rg

Figure 6. Output transient response without (a) and with (b) the droop function

ESR DROP

V^MAX

V^DROOP

V^NOM

V^MIN

(a)

(b)

Figure 7. Active Droop Function Circuit

R_FB

To VOUT

COMP

FB

I_FB

V_PROG

µ

) and 70 A at the OC threshold,

INFO2

The feedback current is equal to 50 A at nominal full load (I = I

+ I

FB

INFO1

so the maximum output voltage deviation is equal to:

∆

V

µ

∆

µ

V = +R · 70 A

POSITIVE_OC_THRESHOLD FB

= +R · 50 A

FULL_POSITIVE_LOAD

FB

Droop function is provided only for positive load; if negative load is applied, and then I

sunk from the FB pin. The device regulates at the voltage programmed by the VID.

< 0, no current is

INFOx

13/33

L6917B

Output Voltage Protection and Power Good

The output voltage is monitored by pin VSEN. If it is not within +12/-10% (typ.) of the programmed value, the

powergood output is forced low. Power good is an open drain output and it is enabled only after the soft start is

finished (2048 clock cycles after start-up).

The device provides over voltage protection; when the voltage sensed by the V

pin reaches 2.1V (typ.), the

SEN

controller permanently switches on both the low-side mosfets and switches off both the high-side mosfets in or-

der to protect the CPU. The OSC/INH/FAULT pin is driven high (5V) and power supply (Vcc) turn off and on is

required to restart operations. The over Voltage percentage is set by the ratio between the OVP threshold (set

at 2.1V) and the reference programmed by VID.

2.1V

= ----------------------------------------------------------------------------

OVP[%]

100

(

)

Reference Voltage VID

Under voltage protection is also provided. If the output voltage drops below the 60% of the reference voltage for

more than one clock period the device turns off and the FAULT pin is driven high.

Both Over Voltage and Under Voltage are active also during soft start (Under Voltage after than Vout reaches

0.8V). During soft-start the reference voltage used to determine the OV and UV thresholds is the increasing volt-

age driven by the 2048 soft start digital counter.

Remote Voltage Sense

A remote sense buffer is integrated into the device to allow output voltage remote sense implementation without

any additional external components. In this way, the output voltage programmed is regulated between the re-

mote buffer inputs compensating motherboard trace losses or connector losses if the device is used for a VRM

module. The very low offset amplifier senses the output voltage remotely through the pins FBR and FBG (FBR

is for the regulated voltage sense while FBG is for the ground sense) and reports this voltage internally at VSEN

pin with unity gain eliminating the errors.

If remote sense is not required, the output voltage is sensed by the VSEN pin connecting it directly to the output

voltage. In this case the FBG and FBR pins must be connected anyway to the regulated voltage.

Input Capacitor

The input capacitor is designed considering mainly the input rms current that depends on the duty cycle as re-

ported in figure 8. Considering the dual-phase topology, the input rms current is highly reduced comparing with

a single phase operation.

Figure 8. Input rms Current vs. Duty Cycle (D) and Driving Relationships

Single Phase

0.50

I

OUT

2D (1 − 2D)

if D < 0.5

2

I

=

rms

Dual Phase

I

OUT

2

0.25

(2D - 1) (2 − 2D) if D > 0.5

0.25

0.50

0.75

Duty Cycle (V_OUT/V_IN)

It can be observed that the input rms value is one half of the single-phase equivalent input current in the worst

case condition that happens for D = 0.25 and D = 0.75.

14/33

L6917B

The power dissipated by the input capacitance is then equal to:

2

=

(

I

)

RMS

P

ESR

RMS

Input capacitor is designed in order to sustain the ripple relative to the maximum load duty cycle. To reach the

high rms value needed by the CPU power supply application and also to minimize components cost, the input

capacitance is realized by more than one physical capacitor. The equivalent rms current is simply the sum of

the single capacitor's rms current.

Input bulk capacitor must be equally divided between high-side drain mosfets and placed as close as possible

to reduce switching noise above all during load transient. Ceramic capacitor can also introduce benefits in high

frequency noise decoupling, noise generated by parasitic components along power path.

Output Capacitor

Since the microprocessors require a current variation beyond 50A doing load transients, with a slope in the

µ

range of tenth A/ s, the output capacitor is a basic component for the fast response of the power supply.

Dual phase topology reduces the amount of output capacitance needed because of faster load transient re-

sponse (switching frequency is doubled at the load connections). Current ripple cancellation due to the 180°

phase shift between the two phases also reduces requirements on the output ESR to sustain a specified voltage

ripple.

When a load transient is applied to the converter's output, for first few microseconds the current to the load is

supplied by the output capacitors. The controller recognizes immediately the load transient and increases the

duty cycle, but the current slope is limited by the inductor value.

The output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the

ESL):

∆

V

∆

I

OUT

=

· ESR

OUT

A minimum capacitor value is required to sustain the current during the load transient without discharge it. The

voltage drop due to the output capacitor discharge is given by the following equation:

2

∆

I

L

OUT

∆

V

= ---------------------------------------------------------------------------------------------

OUT

(

–

V

)

OUT

2 C

V

D

OUT

INMIN

MAX

Where D

is the maximum duty cycle value. The lower is the ESR, the lower is the output drop during load

MAX

transient and the lower is the output voltage static ripple.

Inductor design

The inductance value is defined by a compromise between the transient response time, the efficiency, the cost

and the size. The inductor has to be calculated to sustain the output and the input voltage variation to maintain

∆

the ripple current IL between 20% and 30% of the maximum output current. The inductance value can be cal-

culated with this relationship:

–

V

OUT OUT

IN

= ------------------------------ --------------

L

∆

fs

is the switching frequency, V is the input voltage and V is the output voltage.

OUT

I

V

L

IN

Where f

SW

IN

Increasing the value of the inductance reduces the ripple current but, at the same time, reduces the converter

response time to a load transient. The response time is the time required by the inductor to change its current

from initial to final value. Since the inductor has not finished its charging time, the output current is supplied by

the output capacitors. Minimizing the response time can minimize the output capacitance required.

The response time to a load transient is different for the application or the removal of the load: if during the ap-

plication of the load the inductor is charged by a voltage equal to the difference between the input and the output

15/33

L6917B

voltage, during the removal it is discharged only by the output voltage. The following expressions give approx-

∆

imate response time for I load transient in case of enough fast compensation network response:

∆

I

L

I

L

V

= ------------------------------

= --------------

t

removal

application

–

V

IN

OUT

The worst condition depends on the input voltage available and the output voltage selected. Anyway the worst

case is the response time after removal of the load with the minimum output voltage programmed and the max-

imum input voltage available.

Figure 9. Inductor ripple current vs V

out

9

L=1.5µH, Vin=12V

8

L=2µH,

Vin=12V

7

6

L=3µH,

5

Vin=12V

L=1.5µH,

Vin=5V

4

3

L=2µH,

Vin=5V

2

L=3µH, Vin=5V

1

0

0.5

1.5

2.5

3.5

Output Voltage [V]

MAIN CONTROL LOOP

The L6917B control loop is composed by the Current Sharing control loop and the Average Current Mode con-

trol loop. Each loop gives, with a proper gain, the correction to the PWM in order to minimize the error in its

regulation: the Current Sharing control loop equalize the currents in the inductors while the Average Current

Mode control loop fixes the output voltage equal to the reference programmed by VID. Figure 10 reports the

block diagram of the main control loop.

Figure 10. Main Control Loop Diagram

L

1

+

PWM1

1/5

I_INFO2

CURRENT

SHARING

DUTY CYCLE

CORRECTION

I_INFO1

1/5

L

2

PWM2

ERROR

AMPLIFIER

C_O

R_O

REFERENCE

PROGRAMMED

BY VID

+

-

4/5

COMP

FB

Z_F(S)

Z_FB

D02IN1392

16/33

L6917B

■ Current Sharing (CS) Control Loop

Active current sharing is implemented using the information from Tran conductance differential amplifier in an

average current mode control scheme. A current reference equal to the average of the read current (I ) is

AVG

internally built; the error between the read current and this reference is converted to a voltage with a proper gain

and it is used to adjust the duty cycle whose dominant value is set by the error amplifier at COMP pin (See fig.

11).

The current sharing control is a high bandwidth control loop allowing current sharing even during load transients.

The current sharing error is affected by the choice of external components; choose precise Rg resistor (±1% is

necessary) to sense the current. The current sharing error is internally dominated by the voltage offset of Tran

conductance differential amplifier; considering a voltage offset equal to 2mV across the sense resistor, the cur-

rent reading error is given by the following equation:

∆

I

2mV

------------------- = ---------------------------------------

READ

I

R

I

SENSE MAX

MAX

∆

Where

I

is the difference between one phase current and the ideal current (I

/2).

MAX

READ

Ω

For Rsense = 4m and Imax = 40A the current sharing error is equal to 2.5%, neglecting errors due to Rg and

Rsense mismatches.

Figure 11. Current Sharing Control Loop

L

1

+

PWM1

I_INFO2

CURRENT

SHARING

DUTY CYCLE

CORRECTION

1/5

I_INFO1

+

PWM2

L

2

V_OUT

COMP

D02IN1393

■ Average Current Mode (ACM) Control Loop

The average current mode control loop is reported in figure 12. The current information IFB sourced by the FB

pin flows into RFB implementing the dependence of the output voltage from the read current.

The ACM control loop gain results (obtained opening the loop after the COMP pin):

( ) (

+

( ))

Z s

P

PWM Z

s

R

F

DROOP

( ) = --------------------------------------------------------------------------------------------------------------------

G

s

LOOP

( )

s

Z

1

F

(

( ) + ( )) -------------- +

+ -----------

1

Z

s

Z

s

R

FB

P

L

( )

A s

( )

A s

Where:

– R

R

sense

= ------------------

R

is the equivalent output resistance determined by the droop function;

FB

DROOP

R

g

– Z (s) is the impedance resulting by the parallel of the output capacitor (and its ESR) and the applied

P

load Ro;

17/33

L6917B

– Z (s) is the compensation network impedance;

F

– Z (s) is the parallel of the two inductor impedance;

L

– A(s) is the error amplifier gain;

∆

V

4

5

IN

-- ------------------

=

– PWM

· is the ACM PWM transfer function where DVosc is the oscillator ramp amplitude

∆

V

OSC

and has a typical value of 2V

Removing the dependence from the Error Amplifier gain, so assuming this gain high enough, the control loop

gain results:

( )

s

V

Z

s

Z

4

5

IN

F

Rs

Rg

P

( ) = –-- ------------------ ------------------------------------ ------- + --------------

G

s

LOOP

∆

( ) + ( )

V

Z

s

Z

s

R

FB

OSC

P

L

With further simplifications, it results:

( )

+

(

R

DROOP

+

)

V

Z

s

Ro

R

1

s Co

//Ro ESR

4

IN

F

DROOP

-- ------------------ -------------- ------------------------------------- ----------------------------------------------------------------------------------------------------------------------------------

( ) = –

G

s

LOOP

∆

V

5

R

L

R

L

2

L

OSC

FB

+ ------

------

+

Ro

-- +

2

--------------- +

2 Ro

+

s

Co

s

Co ESR Co

1

2

Considering now that in the application of interest it can be assumed that Ro>>R ; ESR<<Ro and

L

R <<Ro, it results:

DROOP

( )

+

( +

R

DROOP

)

ESR

V

Z

s

1

s Co

4

5

IN

F

-- ------------------ -------------- ----------------------------------------------------------------------------------------------------------------------------------

( ) = –

s

G

LOOP

∆

V

R

L

2

OSC

FB

L

2

L

-- +

--------------- +

+

------ +

s

Co

s

Co ESR Co 1

2

2 Ro

The ACM control loop gain is designed to obtain a high DC gain to minimize static error and cross the 0dB axes

ω

with a constant -20dB/dec slope with the desired crossover frequency

transfer function has one zero and two poles. Both the poles are fixed once the output filter is designed and the

zero is fixed by ESR and the Droop resistance. To obtain the desired shape an R -C series network is consid-

. Neglecting the effect of Z (s), the

T

F

ω

ered for the Z (s) implementation. A zero at

=1/R C is then introduced together with an integrator. This in-

F

F F

tegrator minimizes the static error while placing the zero in correspondence with the L-C resonance a simple -

20dB/dec shape of the gain is assured (See Figure 12). In fact, considering the usual value for the output filter,

the LC resonance results to be at frequency lower than the above reported zero.

Figure 12. ACM Control Loop Gain Block Diagram (left) and Bode Diagram (right)

dB

IFB

Z^F

C_F

R_F

G_LOOP

RFB

VCOMP

K

REF

Z_F(s)

L/2

VOUT

PWM

•

d V_IN

ω

Cout

ESR

ω_LC

ω_Z

ω_T

Rout

V_IN

K = -- --------------- ----------

∆V_oscR _FB

4

5

1

dB

ω

and imposing the cross-over frequency as

T

Compensation network can be simply designed placing

desired obtaining:

=

Z

LC

18/33

L6917B

L

--

2

Co

∆

R

V

OSC

L

5

FB

----------------------------------

------------------------------------------------------- --

=

ω

= -------------------

R

C

F

T

(

+

)

ESR 4

V

2

R

IN

DROOP

F

LAYOUT GUIDELINES

Since the device manages control functions and high-current drivers, layout is one of the most important things

to consider when designing such high current applications.

A good layout solution can generate a benefit in lowering power dissipation on the power paths, reducing radi-

ation and a proper connection between signal and power ground can optimise the performance of the control

loops.

Integrated power drivers reduce components count and interconnections between control functions and drivers,

reducing the board space.

Here below are listed the main points to focus on when starting a new layout and rules are suggested for a cor-

rect implementation.

■ Power Connections.

These are the connections where switching and continuous current flows from the input supply towards the load.

The first priority when placing components has to be reserved to this power section, minimizing the length of

each connection as much as possible.

To minimize noise and voltage spikes (EMI and losses) these interconnections must be a part of a power plane

and anyway realized by wide and thick copper traces. The critical components, i.e. the power transistors, must

be located as close as possible, together and to the controller. Considering that the "electrical" components re-

ported in fig. 13 are composed by more than one "physical" component, a ground plane or "star" grounding con-

nection is suggested to minimize effects due to multiple connections.

Figure 13. Power connections and related connections layout guidelines (same for both phases)

V_IN

BOOTx

PHASEx

VCC

C_BOOTx

HS

LS

HS

LS

R_gate

HGATEx

PHASEx

L

+V_CC

C_OUT

D

R_gate

LOAD

C_IN

LOAD

C_IN

LGATEx

PGNDx

SGND

C_VCC

a. PCB power and ground planes areas

b. PCB small signal components placement

Fig. 13a shows the details of the power connections involved and the current loops. The input capacitance

(CIN), or at least a portion of the total capacitance needed, has to be placed close to the power section in order

to eliminate the stray inductance generated by the copper traces. Low ESR and ESL capacitors (electrolytic or

Ceramic or both) are required.

■ Power Connections Related.

Fig.13b shows some small signal components placement, and how and where to mix signal and power ground

planes.

The distance from drivers and mosfet gates should be reduced as much as possible. Propagation delay times

19/33

L6917B

as well as for the voltage spikes generated by the distributed inductance along the copper traces are so mini-

mized.

In fact, the further the mosfet is from the device, the longer is the interconnecting gate trace and as a conse-

quence, the higher are the voltage spikes corresponding to the gate pwm rising and falling signals. Even if these

spikes are clamped by inherent internal diodes, propagation delays, noise and potential causes of instabilities

are introduced jeopardizing good system behavior. One important consequence is that the switching losses for

the high side mosfet are significantly increased.

For this reason, it is suggested to have the device oriented with the driver side towards the mosfets and the

GATEx and PHASEx traces walking together toward the high side mosfet in order to minimize distance (see fig

14). In addition, since the PHASEx pin is the return path for the high side driver, this pin must be connected

directly to the High Side mosfet Source pin to have a proper driving for this mosfet. For the LS mosfets, the re-

turn path is the PGND pin: it can be connected directly to the power ground plane (if implemented) or in the

same way to the LS mosfets Source pin. GATEx and PHASEx connections (and also PGND when no power

ground plane is implemented) must also be designed to handle current peaks in excess of 2A (30 mils wide is

suggested).

Gate resistors of few ohms help in reducing the power dissipated by the IC without compromising the system

efficiency.

Figure 14. Device orientation (left) and sense nets routing (right)

To LS mosfet

(or sense resistor)

Towards HS mosfet

(30 mils wide)

Towards LS mosfet

(30 mils wide)

To LS mosfet

Towards HS mosfet

(or sense resistor)

(30 mils wide)

To regulated output

The placement of other components is also important:

– The bootstrap capacitor must be placed as close as possible to the BOOTx and PHASEx pins to mini-

mize the loop that is created.

– Decoupling capacitor from Vcc and SGND placed as close as possible to the involved pins.

– Decoupling capacitor from VCCDR and PGND placed as close as possible to those pins. This capacitor

sustains the peak currents requested by the low-side mosfet drivers.

– Refer to SGND all the sensible components such as frequency set-up resistor (when present) and also

the optional resistor from FB to GND used to give the positive droop effect.

– Connect SGND to PGND on the load side (output capacitor) to avoid undesirable load regulation effect

and to ensure the right precision to the regulation when the remote sense buffer is not used.

– An additional 100nF ceramic capacitor is suggested to place near HS mosfet drain. This helps in reduc-

ing noise.

– PHASE pin spikes. Since the HS mosfet switches in hard mode, heavy voltage spikes can be observed

on the PHASE pins. If these voltage spikes overcome the max breakdown voltage of the pin, the device

can absorb energy and it can cause damages. The voltage spikes must be limited by proper layout, the

use of gate resistors, Schottky diodes in parallel to the low side mosfets and/or snubber network on the

low side mosfets, to a value lower than 26V, for 20nSec, at Fosc of 600kHz max.

■ Current Sense Connections.

Remote Buffer: The input connections for this component must be routed as parallel nets from the FBG/FBR

20/33

L6917B

pins to the load in order to compensate losses along the output power traces and also to avoid the pick-up of

any common mode noise. Connecting these pins in points far from the load will cause a non-optimum load reg-

ulation, increasing output tolerance.

Current Reading: The Rg resistor has to be placed as close as possible to the ISENx and PGNDSx pins in

order to limit the noise injection into the device. The PCB traces connecting these resistors to the reading point

must be routed as parallel traces in order to avoid the pick-up of any common mode noise. It's also important

to avoid any offset in the measurement and to get a better precision, to connect the traces as close as possible

to the sensing elements, dedicated current sense resistor or low side mosfet Rdson.

Moreover, when using the low side mosfet RdsON as current sense element, the ISENx pin is practically con-

nected to the PHASEx pin. DO NOT CONNECT THE PINS TOGETHER AND THEN TO THE HS SOURCE!

The device won't work properly because of the noise generated by the return of the high side driver. In this case

route two separate nets: connect the PHASEx pin to the HS Source (route together with HGATEx) with a wide

net (30 mils) and the ISENx pin to the LS Drain (route together with PGNDSx). Moreover, the PGNDSx pin is

always connected, through the Rg resistor, to the PGND: DO NOT CONNECT DIRECTLY TO THE PGND! In

this case, the device won't work properly. Route anyway to the LS mosfet source (together with ISENx net).

Right and wrong connections are reported in Figure 15.

Symmetrical layout is also suggested to avoid any unbalance between the two phases of the converter.

Figure 15. PCB layout connections for sense nets

CORRECT

NOT CORRECT

To LS Drain

and Source

VIA to GND plane

To HS Gate

and Source

To PHASE

connection

Wrong (left) and correct (right) connections for the current reading sensing nets.

APPLICATION EXAMPLES

The dual-pahse topology can be applied to several different applications ranging from CPU power supply (for

which the device has been designed) to standard high current DC-DC power supply. The application benefits

of all the advantages due to the dual-phase topology ranging from output ripple reduction to dynamic perfor-

mance increase. After a general demo board overview, the following application examples will be illustrated:

– CPU Power Supply: 5 to 12 V ; 1.7V

; 45A

IN

OUT

– CPU Power Supply: 12V ; VRM 9.0 Output; 50A

IN

– High Current DC-DC: 12V ; 3.3 to 5V

T; 35A

OUT

IN

Demo Board Description

The demo board shows the operation of the device in a dual phase application. This evaluation board allows

output voltage adjustability (1.100V - 1.850V) through the switches S0-S4 and high output current capability.

2

The board has been laid out with the possibility to use up to two D PACK mosfets for the low side switch in order

to give maximum flexibility in the mosfet's choice.

µ

The four layers demo board's copper thickness is of 70 m in order to minimize conduction losses considering

the high current that the circuit is able to deliver.

Demo board schematic circuit is reported in Figure 16.

21/33

L6917B

Figure 16. Demo Board Schematic

Vin

JP6

DZ1

JP1

GNDin

C9,C10 C11..C13

JP2

C8

R10

R16

VCCDR

VCC

Vcc

2

6

C5

L1

D4

C7

D3

C6

L2

GNDcc

BOOT1

BOOT2

5

4

24

25

UGATE1

UGATE2

C4

Q2

Q4

C3

R14

R15

PHASE1

LGATE1

ISEN1

PHASE2

LGATE2

ISEN2

3

26

27

16

VoutCORE

GNDCORE

R18

R13

R17

R12

R19

C14,

Q1

1

Q3

C23

D2

D1

R20

Q1a

13

Q3a

R3

R6

R5

U1

L6917B

PGNDS1

PGNDS2

PGND

14

15

28

R1

R4

VID4

VID3

S4

S3

S2

S1

S0

PGOOD

VSEN

22

21

20

19

18

17

23

10

PGOOD

VID2

VID1

JP3

R7

VID0

FB

9

OSC / INH

JP4

JP5

R8

C2

R2

C1

R9

SGND

7

COMP

8

11

12

FBR

FBG

FBR

Several jumpers allow setting different configurations for the device: JP3, JP4 and JP5 allow configuring the

remote buffer as desired. Simply shorting JP4 and JP5 the remote buffer is enabled and it senses the output

voltage on-board; to implement a real remote sense, leave these jumpers open and connect the FBG and FBR

connectors on the demo board to the remote load. To avoid using the remote buffer, simply short all the jumpers

JP3, JP4 and JP5. Local sense through the R7 is used for the regulation.

The input can be configured in different ways using the jumpers JP1, JP2 and JP6; these jumpers control also

the mosfet driver supply voltage. Anyway, power conversion starts from VIN and the device is supplied from

V

CC

(See Figure 17).

Figure 17. Power supply configuration

To Vcc pin

To HS Drains (Power Input)

To BOOTx (HS Driver Supply)

Vin

JP6

DZ1

GNDin

JP2

JP1

To VCCDR pin (LS Driver Supply)

Vcc

GNDcc

Two main configurations can be distinguished: Single Supply (V = V = 12V) and Double Supply (V = 12V

CC

IN

CC

V

IN

= 5V or different).

22/33

L6917B

– Single Supply: In this case JP6 has to be completely shorted. The device is supplied with the same rail

that is used for the conversion. With an additional zener diode DZ1 a lower voltage can be derived to

supply the mosfets driver if Logic level mosfet are used. In this case JP1 must be left open so that the

HS driver is supplied with V -V

through BOOTx and JP2 must be shorted to the left to use V or to

IN DZ1

IN

the right to use V -V

to supply the LS driver through VCCDR pin. Otherwise, JP1 must be shorted

IN DZ1

and JP2 can be freely shorted in one of the two positions.

– Double Supply: In this case V supply directly the controller (12V) while V supplies the HS drains for

CC

IN

the power conversion. This last one can start indifferently from the 5V bus (Typ.) or from other buses

allowing maximum flexibility in the power conversion. Supply for the mosfet driver can be programmed

through the jumpers JP1, JP2 and JP6 as previously illustrated. JP6 selects now V or V depending

CC

IN

on the requirements.

Some examples are reported in the following Figures 18 and 19.

Figure 18. Jumpers configuration: Double Supply

Vcc = 12V

Vin = 5V

GNDin

HS Drains = 5V

HS Supply = 12V

Vin = 5V

GNDin

HS Drains = 5V

HS Supply = 5V

JP6

DZ1

JP1

JP6

DZ1

JP2

JP1

VCCDR (LS Supply) = 12V

VCCDR (LS Supply) = 5V

Vcc = 12V

GNDcc

Vcc = 12V

GNDcc

(a) V = 12V; V

= VCCDR = V = 5V

(b) V = V

_BOOTx= VCCDR =12V; V = 5V

CC

BOOTx

IN

CC

IN

Figure 19. Jumpers configuration: Single Supply

Vcc = 12V

Vin = 12V

HS Drains = 12V

HS Supply = 12V

HS Drains = 12V

HS Supply = 5.2V

Vin = 12V

GNDin

JP6

DZ1

JP2

GNDin

JP6

DZ1 6.8V

JP1

JP2

JP1

Vcc = Open

GNDcc

VCCDR (LS Supply) = 12V

Vcc = Open

GNDcc

VCCDR (LS Supply) = 12V

(a) V = V = VCCDR = 12V; V

= 5.2V

(b) V = V = V

= VCCDR = 12V

CC

IN

BOOTx

CC

IN

BOOTx

23/33

L6917B

PCB and Components Layouts

Figure 20. PCB and Components Layouts

Component Side

Internal PGND Plane

Figure 21. PCB and Components Layouts

Internal SGND Plane

Solder Side

24/33

L6917B

CPU Power Supply: 5 to 12V_IN; 1.7V_OUT; 45A

Considering the high slope for the load transient, a high switching frequency has to be used. In addition to fast

reaction, this helps in reducing output and input capacitor. Inductance value is also reduced.

A switching frequency of 200kHz for each phase is then considered allowing large bandwidth for the compen-

sation network. It can be considered to use the 5V rail for the power conversion in order to allow compatibility

with standard ATX power supply.

– Current Reading Network and Over Current:

Since the maximum output current is I

= 45A, the over current threshold has been set to 46A (23A

MAX

per phase) in the worst case (max mosfet temperature). This because the device limits the valley of the

triangular ripple across the inductors. Considering to sense the output current across the low-side mos-

Ω

fet RdsON, STB90NF03L has 6.5m max at 25°C that becomes 9.1m considering the temperature

variation (+40%); the resulting Tran conductance resistor Rg has to be:

I

RdsON

46 9.1m

----- -------------

MAX

------------ --------------------

=

Ω

5.9k

Rg

(R3 to R6)

µ

35

2

35

2

– Droop function Design:

Considering a voltage drop of 100mv at full load, the feedback resistor RFB has to be:

100mV

= ------------------- =

Ω

R

1.43k

(R7)

FB

µ

70 A

– Inductor design:

Each phase has to deliver up to 22.5A; considering a current ripple of 5A (<25%), the resulting induc-

tance value is:

–

∆

–

5

1

Vin Vout

d

Fsw

12 1.7 1.7

---------------------------- -----------

-------------------- ------- -------------------

=

µ

1 H

L

(L1, L2)

l

12 300000

– Output Capacitor:

µ

Ω

Five Rubycon MBZ (2200 F / 6.3V / 12m max ESR) has been used implementing a resulting ESR of 2.4m

Ω

resulting in an ESR voltage drop of 45A*2.4m = 108mV after a 45A load transient.

– Compensation Network:

A voltage loop bandwidth of 20kHz is considered to let the device fast react after load transient.

The R C network results:

F

R_FB∆V_OSC

5

4

L

1.43k 2 5

1µ

R_F= --------------------------------- -- ω _T------------------------------------------------------- = ---------------------- -- 20k 2π ------------------------------------------------------------------ = 6200Ω

(R8)

V_IN

2

(R_DROOP+ ESR)

12

4

9.1m

2

------------- 1.43k + 2.4m

5.9k

µ

1

2

L

2

--

------

µ

6 2200

Co

= ------------------- = ---------------------------------------- =

C

15nF

(C2)

F

R

6.2k

F

25/33

L6917B

Part List

R1

10k

SMD 0805

SMD 1206

Radial 23x10.5

R2, R20

R3, R4, R5, R6

R7

Not Mounted

5.1k

1%

1.43k

R8

6.2k

R10

82Ω

R12 to R16, R19

R17, R18

C2

2.2Ω

0Ω

15n

C3, C4

100n

C5, C6, C7

C8, C9, C10

C11, C12, C13

C19 to C24

L1, L2

1µ

Ceramic

10µ

Ceramic

1800µ / 16V

2200µ / 6.3V

1µ

Rubycon MBZ

TO50 – 52B – 6 Turns

STMicroelectronics

U1

L6917B

STB90NF03L

SO28

2

Q1, Q3

D PACK

2

Q2, Q4

STB70NF03L

STMicroelectronics

D PACK

D1, D2

D3, D4

STPS340U

1N4148

STMicroelectronics

SMB

SOT23

System Efficiency

Figure 22 shows the demo board measured efficiency versus load current for different values of input voltage.

Mosfet temperature is always lower than 115 °C, at T = 25°C.

amb

Figure 22. Efficiency (f

= 200kHz; Vout = 1.7V)

osc

95

90

85

80

75

70

65

60

55

50

45

Vin= 12V

Vin=5V

0

5

10

15

20

25

30

35

40

Output Current [A]

26/33

L6917B

CPU Power Supply: 12V_IN- VRM 9.0 - 50A thermal

Figure 23 shows the device in a high current CPU core power supply solution.

The output voltage can be adjusted with binary step from 1.100V to 1.850V following VRM 9.0 specifications.

The demo board assembled with the following part list is capable to deliver up to 50A in open air without any

kind of airflow. Peak current can reach 60A without any limitations. For higher DC current, to avoid mosfet

change, airflow or heat sink are required.

Figure 23. CPU Power Supply Schematic

Vin

JP6

DZ1

GNDin

JP2

C8

C9,C10 C11..C13

R10

JP1

C5

R16

VCCDR

VCC

Vcc

2

6

D4

C7

D3

C6

L2

GNDcc

BOOT1

BOOT2

5

4

24

25

UGATE1

UGATE2

C4

Q2

Q4

C3

R14

R15

PHASE1

LGATE1

ISEN1

PHASE2

LGATE2

ISEN2

L1

3

26

27

16

VoutCORE

GNDCORE

R18

R13

R17

R12

R19

C14,

Q1

1

Q3

C23

R20

D2

D1

Q1a

13

Q3a

R3

R6

R5

U1

L6917B

PGNDS1

PGNDS2

PGND

14

15

28

R1

R4

VID4

VID3

VID2

VID1

VID0

S4

S3

S2

S1

S0

PGOOD

VSEN

22

21

20

19

18

17

23

10

PGOOD

Ra

JP3

R7

FB

Ca

9

OSC / INH

JP5

JP4

R8

C2

To Vcc

Rosc

R2

C1

R9

SGND

7

COMP

8

11

12

FBR

FBG

FBR

Part List

R1

10k

SMD 0805

R2, R9

Not Mounted

R3, R4, R5, R6

3.3k

1%

R7

3.6k

R8

3.3k

R10

82

R12 to R15

2.2

R16, R17, R18

0

Ra

1k

Rosc

C1

1.3M

1%

Not Mounted

27/33

L6917B

Part List (continued)

C2

47n

SMD 0805

C3, C4

100n

Ceramic

SMD 0805

C5, C6, C7, C8

C9, C10

1µ

Ceramic

SMD 1206

10µ

Ceramic

SMD 1206

C11 to C13

C14 to C23

Ca

1800µ/ 16V

2200µ/ 6.3V

68n

Rubycon MBZ

Radial 10x10.5

SMD 0805

L1, L2

0.5µ

77121 Core – 3 Turns

STMicroelectronics

Vishay - Siliconix

U1

L6917B

SUB85N03-04P

SO28

2

Q1,Q1a, Q3,Q3a

D PACK

2

Q2, Q4

SUB70N03-09BP

Vishay - Siliconix

D PACK

D1, D2

D3, D4

STPS340U

1N4148

STMicroelectronics

SMB

SOT23

Efficiency

Figure 24 showes the system efficiency for output current ranging form 5A up to 50A.

Figure 24. Efficiency (f

= 200kHz; Vout = 1.7V)

osc

89

87

85

83

81

79

77

75

0

5

10 15 20 25 30 35 40 45 50 55

Output Current [A]

28/33

L6917B

Current Sharing

Figure 25 shows the current balancing between the two phases for different values of output current.

Figure 25.

Load Transient Response

Figure 26 shows the system response from 0 to 50A load transient. To obtain such a response, 5 additional

capacitors have been added to the output filter to reproduce the motherboard output filter. Noise can be further

reduced by adding ceramic decoupling capacitors.

Figure 26. 1.7V Output Voltage Ripple During 0 to 50A Load Transient

29/33

L6917B

High Current DC-DC: 12V_IN- 3.3 (or 5V) OUT - 35A

Figure 27 shows the device in a high current server power supply application.

Adding an external resistor divider after the remote sense buffer gives the possibility to increase the regulated

voltage. Considering for example a divider by two (two equal resistors) the DAC range is doubled from 2.200V

to 3.700V with 50mV binary steps. The external resistor divider must be designed in order to give negligible ef-

fects to the remote buffer gain, this means that the resistors value must be much lower than the remote buffer

Ω

input resistance (20k ). In this way, it is possible to regulate the 3.3V and 2.5V rails from the 12V available from

the AC/DC converter. The 5V rail can be obtained with further modifications to the external divider. The regulator

assures all the advantages of the dual phase conversion especially in the 5V conversion where the duty cycle

is near the 50% and practically no ripple is present in the input capacitors.

The board is able to deliver up to 35A "thermal" at T

25°C without airflow. Higher currents can be reached

amb

for reasonable times considering the overall dynamic thermal capacitance.

Figure 27. Server power supply schematic

Vin

JP6

DZ1

GNDin

C9,C10 C11..C13

JP2

C8

R10

JP1

C5

R16

VCCDR

VCC

Vcc

2

6

D4

C7

D3

C6

L2

GNDcc

BOOT1

BOOT2

5

4

24

25

UGATE1

UGATE2

C4

Q2

Q4

C3

R14

R15

PHASE1

LGATE1

ISEN1

PHASE2

LGATE2

ISEN2

L1

3

26

27

16

VoutCORE

GNDCORE

R18

R13

R17

R12

R19

C14,

Q1

1

Q3

C23

R20

D2

D1

Q1a

13

Q3a

R3

R6

R5

U1

L6917B

PGNDS1

PGNDS2

PGND

14

15

28

R1

R4

VID4

VID3

S4

S3

S2

S1

S0

PGOOD

VSEN

22

21

20

19

18

17

23

10

PGOOD

VID2

VID1

VID0

JP3

R7

FB

9

OSC / INH

JP5

JP4

R8

C2

To Vcc

Rosc

R2

C1

R9

SGND

7

COMP

8

11

12

FBR

FBG

FBR

The following part list refers to the following application:

– Input Voltage: 12V;

– Output voltage: 3.3V;

– Oscilator frequency: 200kHz;

– Output voltage tolerance (over static and dynamic conditions): ±2.5%.

30/33

L6917B

Part List

R1

10k

SMD 0805

SMD 1206

Radial 10x10.5

Radial 10x23

R2, R9

R3, R6

R4, R5

R7

Not Mounted

1.3k

1%

390

75

R8

750

R10

82

R12 to R15

R16, R17, R18

R19

2.2

0

300

1%

R20

390

R

1.3M

Not Mounted

220n

100n

1µ

OSC

C1

C2

C3, C4

Ceramic

C5, C6, C7, C8

C9, C10

Ceramic

10µ

Ceramic

C11 to C13

C14,C16,C18,C20,C22

L1, L2

100µ/ 20V

2200µ/16V

OSCON 20SA100M

SANYO

µ

77121 Core – 9 Turns

STMicroelectronics

2.8

U1

L6917B

SO28

2

Q1,Q1a,Q2, Q3,Q3a,Q4

STB90NF03L

D PACK

D1, D2

D3, D4

DZ1

STPS340U

1N4148

STMicroelectronics

SMB

SOT23

Minimelf

Not Mounted

Figure 28. System Efficiency for a 12V/3.3V

Figure 29. Load Transient Response: 0A to 35A

Application (f

= 200kHz)

@ 1A/µs

osc

93

92

91

90

89

88

0

5

10

15

20

25

30

35

40

Output Current [A]

31/33

L6917B

mm

inch

DIM.

OUTLINE AND

MECHANICAL DATA

MIN. TYP. MAX. MIN. TYP. MAX.

A

a1

b

2.65

0.3

0.104

0.012

0.019

0.013

0.1

0.004

0.35

0.23

0.49 0.014

0.32 0.009

b1

C

0.5

0.020

c1

D

45° (typ.)

17.7

10

18.1 0.697

10.65 0.394

0.713

0.419

E

e

1.27

0.050

0.65

e3

F

16.51

7.4

0.4

7.6

0.291

0.299

0.050

L

1.27 0.016

SO28

S

8 ° (max.)

32/33

L6917B

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

STMicroelectronics GROUP OF COMPANIES

Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain

- Sweden - Switzerland - United Kingdom - U.S.A.

http://www.st.com

33/33


型号：	L6917
厂家：	ST
描述：	5 BIT PROGRAMMABLE DUAL-PHASE CONTROLLER 5位可编程双相控制器控制器
文件：	总33页 (文件大小：593K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

L6917 [STMICROELECTRONICS]

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