L9352B-TR-LF_技术文档

L9352B

Intelligent quad (2 x 5A / 2 x 2.5A) low-side switch

Features

■ Quad low-side switch

■ 2 x 5 A designed as conventional switch

■ 2 x 2.5 A designed as switched current-

regulator

■ Low ON-resistance 4 x 0.2  (typ.)

■ PowerSO-36 - package with integrated cooling

PowerSO-36

area

■ Integrated free-wheeling and clamping Z-

diodes

■ status push-pull stages

■ Output slope control

■ Electrostatic discharge (ESD) protection

■ Short circuit protection

■ Selective overtemperature shutdown

■ Open load detection

Description

The L9352B is an integrated quad low-side power

switch to drive inductive loads like valves used in

ABS systems. Two of the four channels are

current regulators with current range from 0 mA to

2.25 A.

■ Ground and supply loss detection

■ External clock control

■ Recirculation control

■ Regulator drift detection

■ Regulator error control

■ Status monitoring

All channels are protected against fail functions.

They are monitored by a status output.

Table 1.

Device summary

Order code

Package⁽¹⁾

Packing

L9352B-LF

PowerSO-36

Tray

L9352B-TR-LF

Tape and reel

1. ECOPACK® package (see Section 6: Package information).

September 2013

Rev 7

1/27

www.st.com

1

Contents

L9352B

Contents

1

2

3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.1

3.2

3.3

3.4

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Input circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Output stages (not regulated) channel 1 and 2 . . . . . . . . . . . . . . . . . . . . 13

Current-regulator-stages channel 3 and 4 . . . . . . . . . . . . . . . . . . . . . . . . 13

Protective circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Drift detection (regulated channels only) . . . . . . . . . . . . . . . . . . . . . . . . . 17

Other test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5

Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.1

5.2

Non regulated channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Regulated channels (timing diagrams of diagnostic with 2kHz

PWM input signal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6

7

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2/27

L9352B

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Special test mode functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Diagnostic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3/27

List of figures

L9352B

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pins connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Input PWM to output current range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Current accuracy according to the input and clock frequency ratio . . . . . . . . . . . . . . . . . . 14

Output slope, resistive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Overload switch-off delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Normal condition, resistive load, pulsed input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Current overload. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Diagnostic status output at different open load current conditions . . . . . . . . . . . . . . . . . . . 21

Figure 10. Pulsed open load conditions (regulated and non-regulated channels). . . . . . . . . . . . . . . . 22

Figure 11. Normal condition, inductive load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 12. Current overload. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 13. Recirculation error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 14. Current regulation error (e.g. as a result of voltage reduction) . . . . . . . . . . . . . . . . . . . . . . 24

Figure 15. Over temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 16. Test mode 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 17. PowerSO-36 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4/27

L9352B

Block diagram

1

Block diagram

Figure 1.

Block diagram

VS

VCC

VDD

Internal Supply

EN

CLK

IN1

Overtemperature

Channel 4

Overtemperature

Channel 1

Open Load

Overload

Q1

LOGIC

ST1

IPD

GND-det.

Open Load

D4

Q4

IN4

Overload

GND-det.

LOGIC

&

DA

ST4

IPD

Overtemperature

Channel 3

Overtemperature

Channel 2

Open Load

Overload

IN2

Q2

LOGIC

ST2

IPD

GND-det.

Open Load

D3

Q3

Overload

GND-det.

IN3

LOGIC

&

DA

ST3

IPD

drift-det.

TEST

GND

99AT0059

5/27

Pins description

L9352B

2

Pins description

Figure 2.

Pins connection (top view)

CLK

GND

PGND3

Q3

1

2

3

4

5

6

7

8

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

ST3

IN1

IN3

ST1

Q3

D3

Q1

PGND1

VS

PGND2

TEST

EN

ST2

IN4

Q1

9

10

11

12

13

14

15

16

17

18

Q2

D4

Q4

PGND4

IN2

ST4

VDD

VCC

N.C.

99AT0060

Table 2.

N°

Pins description

Description

1

2, 3

4, 5

6, 7

8, 9

10, 11

12, 13

14, 15

16, 17

18

GND

PGND3

Q3

Logic ground

Power ground - Channel 3

Power output - Channel 3

D3

Free-wheeling diode - Channel 3

Power output - Channel 1

Power output - Channel 2

Free-wheeling diode - Channel 4

Power output - Channel 4

Power ground - Channel 4

Not Connected

Q1

Q2

D4

Q4

PGND4

NC

19

VCC

VDD

ST4

IN2

5 V supply

20

5 V supply

21

Status output - Channel 4

Control input - Channel 2

Control input - Channel 4

Status output - Channel 2

Enable input for all four channels

22

23

IN4

24

ST2

EN

25

6/27

L9352B

Pins description

Table 2.

N°

Pins description (continued)

Description

26

TEST

PGND2

VS

Enable input for drift detection

27, 28

Power ground - Channel 2

Supply voltage

29

30, 31

32

PGND1

ST1

Power ground - Channel 1

Status output - Channel 1

Control input - Channel 3

Control input - Channel 1

Status output - Channel 3

Clock input

33

IN3

34

IN1

35

ST3

36

CLK

7/27

Electrical specifications

L9352B

3

Electrical specifications

3.1

Absolute maximum ratings

The absolute maximum ratings are the limiting values for this device.

Warning: Damage may occur if this device is subjected to conditions

which are beyond these values.

Table 3.

Absolute maximum ratings

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

E_Q

Voltages

V_S

Switch off energy for inductive loads

50

mJ

Supply voltage

-0.3

40

6

V

V_CC, V_DDSupply voltage

V_Q

Output voltage static

40

60

6

Output voltage during clamping

Input voltage IN1 to IN4, EN

Input voltage CLK

t < 1ms

I_I< |10|mA

V_IN, V_EN

V_CLK

V_ST

-1.5

-0.3

6

Output voltage status

6

V_D

Recirculation circuits D3, D4

40

Max. reverse breakdown voltage of free

wheeling diodes D3, D4

V_DRmax

Currents

I_Q1/2

55

V

internal

limited

Output current for Q1 and Q2

Output current for Q3 and Q4

>5

>3

-4

A

internal

limited

I_Q3/4

I_Q1/2

,

Output current at reversal supply for Q1

and Q2

I_PGND1/2

I_Q3/4

I_PGND3/4

,

Output current at reversal supply for

Q3 and Q4

-2

-5

A

I_ST

Output current status pin

5

mA

ESD protection

Electrostatical discharging

ESD

MIL883C

2

kV

GND, PGND, Qx, Dx, CLK, ST, IN,

TEST, EN

8/27

L9352B

Table 3.

Electrical specifications

Absolute maximum ratings (continued)

Parameter Test conditions

Symbol

Min

Typ

Max

Unit

VS,

VCC,VDD

Supply pins

vs. GND and PGND

1

kV

vs. Common GND

(PGND1-4 + GND)

ESD

Output pins (Qx, Dx)

4

kV

3.2

Thermal data

Table 4.

Symbol

Thermal data

Parameter

Junction temperature

Test conditions

Min

Typ

Max

Unit

T_j

-40

150

°C

Junction temperature during clamping t = 30min

175

190

T_jc

°C

(life time)

t = 15min

T_stg

T_th

Storage temperature

T_stg

-55

150

200

°C

(1)

Over temperature shutdown threshold

Over temperature shutdown hysteresis

Thermal resistance junction to case

175

(1)

T_hy

10

°C

R_{th j-case}

2

K/W

1. This parameter will not be tested but assured by design.

3.3

Operating range

Table 5.

Symbol

Operating range

Parameter

Test conditions

Min.

Typ.

Max.

Unit

V_S

Supply voltage

4.8

4.5

-1

18

5.5

1

V

V_CC, V_DDSupply voltage

dV_S/dt

V_Q

Supply voltage transient time

V/s

V

Output voltage static

-0.3

40

Voltage will be

limited by internal

Z-diode clamping

Output voltage induced by inductive

switching

V_Q

60

V

V_ST

I_ST

T_j

Output voltage status

Output current status

Junction temperature

-0.3

-1

6

1

V

mA

°C

-40

150

 = 30min

 = 15min

175

190

T_jc

Junction temperature during clamping

°C

9/27

Electrical specifications

L9352B

3.4

Electrical characteristics

Table 6.

Electrical characteristics

(V = 4.8 to 18V; T = -40 to 150°C unless otherwise specified)

S

j

Symbol

Parameter

Test condition

Min.

Typ. Max.

Unit

Power supply

V_S 18V

I_SON

Supply current

5

mA

(outputs ON)

V_S 18V

I_SOFF

Quiescent current

(outputs OFF)

I_cc

I_dd

Supply current VCC (analog supply) V_CC= 5V

5

mA

A

Supply current VDD (digital supply)

V_DD= 5V f_CLK=0Hz

V_DD= 5V f_CLK=250kHz

mA

General diagnostic functions

V_S 6.5V

V_QU

Open load voltage

0.3

0.33

2.5

0.36

x V_Q

(outputs OFF)

V_thGND

V_thPGL

f_CLK,min

Signal-GND-loss threshold

Power-GND-loss threshold

Clock frequency error

V_CC= 5V

0.1

1.5

10

1

V

3.5

100

45

kHz

%

DC_{CLKe_low}Clock duty cycle error detection low

f_CLK= 250 kHz

33,3

66,6

DC_{CLKe_high}Clock duty cycle error detection high f_CLK= 250 kHz

VS_lossSupply detection V_CC= V_DD= 5V

55

2

%

4.5

V

Additional diagnostic functions channel 1 and channel 2 (non regulated channels)

I_QU1,2

I_QO1,2

Open-load current channel 1, 2

Over-load current channel 1, 2

V_S 6.5V

50

5

300

9

mA

A

7.5

Additional diagnostic functions channel 3 and channel 4 (regulated channels)

DC_OUT

I_QO3,4

Output duty cycle error

filtered with 10ms

90

100

8

%

A

Overload current

channel 3,4

V_S 6.5V

2.5

5

Recirculation error shutdown

threshold (open D3/D4)

V_rerr

Iout > 50mA

45

50

60

V

V_IN3= V_IN4= PWM_IN

V_TEST= H

Output PWM ratio during drift

comparison

PWM_dOUT

-14.3

+14.3

%

Digital inputs (IN1 to IN4, ENA, CLK, TEST). The valid PWM-Ratio for IN3/IN4 is 10% to 90%

V_IL

V_IH

Input low voltage

-0.3

2

1

6

V

Input high voltage

V_IHy

Input voltage hysteresis⁽¹⁾

20

500

mV

10/27

L9352B

Table 6.

Electrical specifications

Electrical characteristics (continued)

(V = 4.8 to 18V; T = -40 to 150°C unless otherwise specified)

S

j

Symbol

Parameter

Test condition

Min.

Typ. Max.

Unit

I_I

Input pull down current

V_IN= 5V, V_S 6.5V

8

20

40

A

Digital outputs (ST1 to ST4)

V_STL

Status output voltage in low state ⁽²⁾⁾I_ST 40A

0

0.4

3.45

1.5

V

I_ST - 40A

I_ST -120A

2.5

2

V_STH

Status output voltage in high state ⁽²⁾⁾

V

R_DIAGL

R_DIAGH

R_OUT+ R_DSONin low state

R_OUT+ R_DSONin high state

0.3

1.5

0.64

3.2

k

7.0

Power outputs (Q1 to Q4)

R_DSON

Static drain-source ON-resistance

I_Q= 1A; V_S 9.5V

0.2

0.4

1.5

W

V

Forward voltage of free wheeling path

D3, D4 @250mA

V_{F_250mA}

I_D3/4= -250mA

0.5

2.0

Forward voltage of free wheeling path

D3, D4 @2.25A

V_{F_2.25A}

R_sens

I

_D3/4= -2.25A

4.5

V

Sense resistor = (V_{F_2.25A-}

V_{F_250mA})/2A

1

W

V_Z

I_PD

I_Qlk

Z-diode clamping voltage

Output pull down current

Output leakage current

I_Q 100mA

45

10

60

150

5

V

V_EN= H, V_IN= L

V_EN= L; V_Q= 20V

A

Timing

t_ON

t_OFF

t_IN3/4min

t_OFFREG

t_r

Output ON delay time

I_Q= 1A

0

5

10

2

20

30

s

ms

s

Output OFF delay time channel

Minimum Input Register ON time

Output OFF delay time regulator

Output rise time

I_Q= 1A

(3)

528

1.5

I_Q= 1A

0.5

4

8

t_f

Output fall time

I_Q= 1A

t_sf

Short error detection filter time

Long error detection filter time

Short circuit switch-OFF delay time

Status delay time

f_CLK= 250kHz DC = 50% ⁽³⁾

8

t_lf

f_CLK= 250kHz DC = 50% ⁽³⁾

16

4

32

30

1024

(3)

t_SCP

t_D

(3)

896

t_RE

Regulation error status delay time

Output off status delay time

⁽³⁾(reg. channels only)

⁽³⁾(reg. channels only

10

t_Dreg

528

Reg. current accuracy (reg. channels only)

I_Q3/Q4Maximum current

DC = 90%

2

2.25

2.5

A

11/27

Electrical specifications

L9352B

Unit

Table 6.

Symbol

Electrical characteristics (continued)

(V = 4.8 to 18V; T = -40 to 150°C unless otherwise specified)

S

j

Parameter

Test condition

Min.

Typ. Max.

25

10

6

mA

%

0.00A  I_Q3/Q40.25A

0.25A  I_Q3/Q4 0.40A

0.40A  I_Q3/Q4 0.80A

0.80A  I_Q3/Q4 2.25A

Current Resolution Input Duty Cycle

0.4% - 99% f_clk= 2KHz@

I_Q3/Q4

%

-8

6

%

I_Q3/Q4

Min. quant. step

5

mA

Frequencies

CLK frequency

crystal-controlled

250

2

kHz

Input PWM frequency

(reg. channels only)

1. This parameter will not be tested but assured by design.

2. Short circuit between two digital outputs (one in high the other in low state) will lead to the defined result "LOW".

3. Digital filtered with external clock, only functional test.

12/27

L9352B

Functional description

4

Functional description

4.1

Overview

The L9352B is designed to drive inductive loads (relays, electromagnetic valves) in low side

configuration. Integrated active Zener-clamp (for channel1 and 2) or free wheeling diodes

(for channel 3 and 4) allow the recirculation of the inductive loads. All four channels are

monitored with a status output. All wiring to the loads and supply pins of the device are

controlled. The device is self-protected against short circuit at the outputs and over

temperature. For each channel one independent push-pull status output is used for a

parallel diagnostic function.

Channel 3 and 4 work as current regulator. A PWM signal on the input defines the target

output current. The output current is controlled through the output PWM of the power stage.

The regulator limit of 90% is detected and monitored with the status signal. The current is

measured during recirculation phase of the load.

A test mode compares the differences between the two regulators. This “drift” test compares

the output PWM of the regulators. By this feature a drift of the load during lifetime can be

detected.

4.2

4.3

Input circuits

The INput, CLK, TEST and ENable inputs, are active high, consist of Schmidt triggers with

hysteresis. All inputs are connected to pull-down current sources.

Output stages (not regulated) channel 1 and 2

The two power outputs (5A) consist of DMOS-power transistors with open drain output. The

output stages are protected against short circuit. Via integrated Zener-clamp-diodes the

overvoltage of the inductive loads due to recirculation are clamped to typ. 52V for fast shut

off of the valves. Parallel to the DMOS transistors there are internal pull-down current

sources. They are provided to assure an open load condition in the OFF-state. With EN=low

this current source is switched off, but the open load comparator is still active.

4.4

Current-regulator-stages channel 3 and 4

The current-regulator channels are designed to drive inductive loads. The target value of the

current is given by the duty cycle (DC) of the 2 kHz PWM input signal. The following figure

shows the relation between the input PWM and the output current and the specified

accuracy

.

13/27

Functional description

Figure 3.

L9352B

Input PWM to output current range

2250

IO

(mA)

800

400

250

25

6%

-8% to +6%

10%

mA

10 16

32

INPUT PWM(%)

90

D03AT513A

The ON period of the input signal is measured with a 1MHz clock, synchronized with the

external 250kHz clock. For requested precision of the output current the ratio between the

frequencies of the input signal and the external 250kHz clock has to be fixed according to

the graph shown in Figure 4.

Figure 4.

Current accuracy according to the input and clock frequency ratio

5.6%

Regulator

112.5

125

132

f_CLK/ f_IN

0%

switched off

-10%

The theoretical error is zero for f

/ f = 125.

CLK IN

If the period of the input signal is longer than 132 times the period of the clock the regulator

is switched off. For a clock frequency lower than 100kHz the clock control will also disable

the regulator. For high precision applications the clock frequency and the input frequency

have to be correlated.

The output current is measured during the recirculation of the load. The current sense

resistor is in series to the free wheeling diode. If this recirculation path is interrupted the

regulator stops immediately and the status output remains low for the rest of the input cycle.

The output period is 64 times the clock period. With a clock frequency of 250kHz the output

PWM frequency is 3.9kHz. The output PWM is synchronized with the first negative edge of

the input signal. After that the output and the input are asynchronous. The first period is

14/27

L9352B

Functional description

used to measure the current. This means the first turn-on of the power is 256s after the first

negative edge of the input signal.

As regulator a digital PI-regulator with the Transfer function for:

0.126

KI: --------------

z – 1

and KP: 0.96

for a sampling time of 256µs is realized.

To speed up the current settling time the regulator output is locked to 90% output PWM until

the target current value is reached. This happens also when the target current value

changes and the output PWM reaches 90% during the regulation. The status output gets

low if the target current value is not reached within the regulation error delay time of

t_RE=10ms.

4.5

4.6

Protective circuits

The outputs are protected against current overload, over temperature, and power-GND-loss.

The external clock is monitored by a clock watchdog. This clock watchdog detects a minimal

frequency f_CLK,minand wrong clock duty cycles. The allowed clock duty cycle range is 45% to

55%. The current-regulator stages are protected against recirculation errors, when D3 or D4

is not connected. All these error conditions shut off the power stage and invert the status

output information.

Error detection

The status outputs indicate the switching state under normal conditions (status LOW = OFF;

status HIGH = ON). If an error occurs, the logic level of the status output is inverted, as listed

in the diagnostic table below. All external errors, for example open load, are filtered

internally. The following table shows the detected errors, the filter times and the detection

mode (on/off).

Table 7.

Error detection

ON State

OFF State

Filter time

Reset done by

EN & IN = “LOW”

EN &IN = HIGH EN &IN = LOW

Short circuit of the load

X

t_sf

for T_Dor T_Dreg

Open load

X

t_lf

timer T_D

(under voltage detection)

Open load

X

t_sf

timer T_D

(under current detection)

EN & IN = “LOW”

for T_Dor T_Dreg

Overtemperature

t_sf

in on: EN & IN = “LOW”

for T_Dor T_Dreg

Power-GND-loss

Signal-GND-loss

X

t_lf

in off: timer T_D

timer T_D

15/27

Functional description

L9352B

Table 7.

Error detection (continued)

ON State

EN &IN = HIGH EN &IN = LOW

OFF State

Filter time

Reset done by

timer T_D

Supply-VS-loss

X

t_lf

in on: EN & IN = “LOW”

for T_Dor T_Dreg

Clock control

X

no

in off: timer T_D

in on: EN & IN = “LOW”

for T_Dor T_Dreg

Output voltage clamp active

(regulated

channels)

in off: timer T_D

EN&IN = low means that at least one between enable and input is low. For the inputs IN=low

means also no input PWM. For the regulator input period longer than T and for the

Dreg

standard channel input period longer than T .

D

A detected error is stored in an error register. The reset of this register is made with a timer

T . With this approach all errors are present at the status output at least for the time T .

D

All protection functions like short circuit of the output, over temperature, clock failure or

power-GND-loss in ON condition are stored into an internal “fail” register. The output is then

shut off. The register must be reset with a low signal at the input. A “low signal” means that

the input is low for a time longer than T or T

for the related channel, otherwise it is

D

DReg

interpreted as a PWM input signal and the register is left in set mode.

Signal-GND-loss and VS-loss are detected in the active on mode, but they do not set the fail

register. This type of error is only delayed with the standard timer t_lffunction.

Open load is detected for all four channels in on- and off-state.

Open load in off condition detects the voltage on the output pin. If this voltage is below 0.33

* VS the error register is set and delayed with T . A sink current stage pull the output down

D

to ground, with EN high. With EN low the output is floating in case of openload and the

detection is not assured. In the ON state the load current is monitored by the non-regulated

channels. If it drops below the specified threshold value I an open load is detected and

QU

the error register is set and delayed with T . A regulated channel detects the open load in

D

the on state with the current regulator error detection. If the output PWM reaches 90% for a

time longer than t than an error occurs. This could happen when no load is connected, the

RE

resistivity of the load is too high or the supply voltage too low.

A clock failure (clock loss) is detected when the frequency becomes lower than f_CLK,min. All

status outputs are set on error and all power outputs are shut off. The status signals remain

in their state until the clock signal is present again. A clock failure during power on of V is

CC

detected only on the regulated channels. The status outputs of the channel 1 and 2 are low

in this case.

16/27

L9352B

Functional description

4.7

Drift detection (regulated channels only)

The drift detection is used to compare the two regulated channels during regulation. This

“Drift” test compares the output PWM of the regulators. The resistivity of the load influences

the output PWM. The approximated formula for the output current below shows the

dependency of the load resistor to the output PWM. In this formula the energy reduction

during the recirculation is not taken into account. The real output PWM is higher. The

testmode is enabled with IN, EN and TEST high. With an identical 2kHz PWM-Signal

connected to the IN-inputs the output PWM must be in a range of 14.3%. If the difference

between the two on-times is more than 14.3% of the expected value an error is detected

and monitored by the status outputs, in the same way as described above, but a drift error

will not be registered and also not delayed with T as other errors.

D

VBAT

IOUT = ---------------------------  PWM

RL + RON

Drift Definition:

Drift = PWM(1+E) - PWM (1-E) = 2PWM E

Drift * 4 < PWM (1+E)

with E >14.3% a drift is detected

E.. not correlated Error of the channels

%PWM ... Corresponding ideal output PWM to a given input PWM

A 7bit output-PWM-register is used for the comparison. The register with the lower value is

subtracted from the higher one. This result is multiplied by four and compared with the

higher value.

4.8

Other test modes

The test pin is also used to test the regulated channels in the production. With a special

sequence on this pin the power stages of the regulated channels can be controlled direct

from the input. No status feedback of the regulated channels is given. The status output is

clocked by the regulator logic. The output sequence is a indication of a proper logic

functionality. The following table shows the functionality of this special test mode.

Table 8.

EN

Special test mode functionality

IN

TEST

OUT

STATUS

Note

1

0

X

1

X

1

X

disable test mode

Drift mode

on

off

on

1

X

0

test pattern

test condition one

test condition two

test condition three

test condition four

1

For more details about the test condition four see timing diagram.

17/27

Functional description

L9352B

4.9

Diagnostic

The status follows the input signal in normal operating conditions.

If any error is detected the status is inverted.

Table 9.

Diagnostic

Test

input

TEST

Enable

input

ENA

Status

Power

output/current

reg. Q

Control input

non-reg./reg. IN

Operating condition

output

ST

L

OFF

ON

L

H/PWM

L

Normal function

H

L

H/PWM

H

L

OFF

ON

X

H

L

H/PWM

L

Open load or short to ground

H

H/PWM

L

H

H/PWM

X

OFF

L

Overload or short to supply

Latched overload

Reset latch

H –> L

H

Reset latch

H/PWM –> L

L

H

H/PWM

X

OFF

L

Overtemperature

Latched overtemperature

Reset latch

H –> L

H

Reset latch

H/PWM –> L

Recirculation error (reg.chn.)

Latched error

L

H

PWM

OFF

L

Reset latch

H –> L

H

X

Reset latch

PWM –> L

L

OFF

H

L

H/PWM

L

Clock failure (clock loss)⁽¹⁾

Drift⁽²⁾

H

H/PWM

H

L

OFF

ON

X

L

H/PWM

Failure

No failure

H

ON

H

1. during power on sequence only detected on channel 3 and 4 (see description).

2. This input combination is also used for an internal chip-test and must not be used.

18/27

L9352B

Timing diagrams

5

Timing diagrams

5.1

Non regulated channels

Figure 5.

Output slope, resistive load

V_I

V_IH

V_IL

t

t_OFF

t_r

t_ON

t_f

V_Q

V_S

85% V _S

15% V _S

t

99AT0061

Figure 6.

Overload switch-off delay

I_Q

I_QO

I_QU

t

t_D

t_SCP

V_ST

t_sf

t

00RS0001

19/27

Timing diagrams

Figure 7.

L9352B

Normal condition, resistive load, pulsed input signal

V_IN

V_Q

I_Q

I_QU

t_D

V_ST

99AT0063

Figure 8.

Current overload

t_D

Reset Fail

register

V_IN

V_Q

I_Q

Set Fail

register

I_QO

t_D

V_ST

99AT0064

20/27

L9352B

Timing diagrams

Diagnostic status output at different open load current conditions

Figure 9.

Under current condition followed by normal operation

t_D

V_IN

V_Q

I_Q

I_QU

t_D

V_ST

99AT0065

Open load condition in the case of pulsed input signal followed by normal operation

t_D

V_IN

V_Q

I_QU

I_Q

t_D

V_ST

99AT0066

21/27

Timing diagrams

L9352B

Figure 10. Pulsed open load conditions (regulated and non-regulated channels)

V_IN

V_Q

I_Q

0.33 x V_S

t_D

t_lf

V_ST

99AT0067

5.2

Regulated channels (timing diagrams of diagnostic with

2kHz PWM input signal)

Figure 11. Normal condition, inductive load

t_DREG

500μs

V_IN

V_Q

I_Q

Target Current

256μs

V_ST

99AT0068

22/27

L9352B

Timing diagrams

Figure 12. Current overload

t_DREG

Reset Fail

register

500μs

V_IN

V_Q

I_Q

Set fail

registor

I_QO

t_sf

V_ST

99AT0069

Figure 13. Recirculation error

t_DREG

Reset Fail

register

500μs

V_IN

V_Q

Set Fail

register

target current

I_Q

V_ST

99AT0070

23/27

Timing diagrams

Figure 14. Current regulation error (e.g. as a result of voltage reduction)

L9352B

500μs

V_IN

V_Q

I_Q

PWM_ratio= 90%

target current

t_RE

V_ST

99AT0071

Figure 15. Over temperature

Overtemperature

Condition

t_DREG

Reset Fail

register

500μs

V_IN

V_Q

Set Fail

register

target current

I_Q

V_ST

99AT0072

Figure 16. Test mode 4

Test mode 4

VEN low

V_TEST

V_IN3/4

V_Q3/4

99AT0073

24/27

L9352B

Package information

6

Package information

®

In order to meet environmental requirements, ST (also) offers these devices in ECOPACK

®

packages. ECOPACK packages are lead-free. The category of second Level Interconnect

is marked on the package and on the inner box label, in compliance with JEDEC Standard

JESD97. The maximum ratings related to soldering conditions are also marked on the inner

box label.

ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

Figure 17. PowerSO-36 mechanical data and package dimensions

mm

inch

DIM.

MIN.

TYP. MAX. MIN.

3.60

TYP. MAX.

0.1417

0.0118

0.1299

0.0039

0.0150

0.0126

0.6299

0.3858

0.5709

0.4370

0.1142

0.2441

0.0256

0.4350

0.0039

0.6260

0.0433

OUTLINE AND

MECHANICAL DATA

A

a1

a2

a3

b

0.10

0.30 0.0039

3.30

0

0.10

0.22

0.23

15.80

9.40

13.90

10.90

0.38 0.0087

0.32 0.0091

16.00 0.6220

9.80 0.3701

14.5 0.5472

11.10 0.4291

2.90

c

D

D1

E

E1

E2

E3

e

5.80

6.20 0.2283

0.65

e3

G

11.05

0

0.10

H

15.50

15.90 0.6102

1.10

h

L

0.8

1.10 0.0315

10˚ (max)

8˚ (max)

N

s

PowerSO-36

Note: “D and E1” do not include mold flash or protusions.

- Mold flash or protusions shall not exceed 0.15mm (0.006”)

- Critical dimensions are "a3", "E" and "G".

0096119 C

25/27

Revision history

L9352B

7

Revision history

Table 10. Document revision history

Date

Revision

Changes

20-Feb-2004

5

Initial release.

Document reformatted.

05-Sep-2008

17-Sep-2013

6

7

Updated the order codes in Table 1: Device summary.

Updated Disclaimer

26/27

L9352B

Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the

right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any

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Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no

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No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this

document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products

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UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED

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Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void

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27/27


型号：	L9352B-TR-LF
厂家：	ST
描述：	Intelligent quad (2 x 5A / 2 x 2.5A) low-side switch 驱动光电二极管接口集成电路驱动器
文件：	总27页 (文件大小：334K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

L9352B-TR-LF [STMICROELECTRONICS]

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