L9352PD [STMICROELECTRONICS]
4 CHANNEL, BUF OR INV BASED PRPHL DRVR, PDSO36, POWER, SO-36;
| 型号： | L9352PD |
| 厂家： | 
ST |
| 描述： | 4 CHANNEL, BUF OR INV BASED PRPHL DRVR, PDSO36, POWER, SO-36 外围驱动器 驱动程序和接口 开关 接口集成电路 光电二极管 |
| 文件： | 总21页 (文件大小：330K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L9352
INTELLIGENT QUAD (2X5A/2X2.5A) LOW-SIDE SWITCH
■
■
■
■
■
Quad low-side switch
2 x 5A designed as conventional switch
2 x 2.5A designed as switched current-regulator
Ω
Low ON-resistance 4 x 0.2 (typ.)
Power SO-36 - package with integrated
cooling area
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Integrated free-wheeling and clamping Z-diodes
Output slope control
PowerSO-36
BARE DIE
Short circuit protection
ORDERING NUMBERS:
L9352
Selective overtemperature shutdown
Open load detection
L9352-DIE1
Ground and supply loss detection
External clock control
DESCRIPTION
Recirculation control
The L9352 is an integrated quad low-side power
switch to drive inductive loads like valves used in
ABS systems. Two of the four channels are current
regulators with current range from 250mA to 2.25A
and an accuracy of 10%.
Regulator drift detection
Regulator error control
Regulator resolution 5mA
Status monitoring
All channels are protected against fail functions.
They are monitored by a status output.
Status push-pull stages
Electrostatic discharge (ESD) protection
Figure 1. Pin Connection
CLK
GND
PGND3
PGND3
Q3
1
2
3
4
5
6
7
8
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
ST3
IN1
IN3
ST1
Q3
D3
D3
Q1
PGND1
PGND1
VS
PGND2
PGND2
TEST
EN
ST2
IN4
Q1
9
10
11
12
13
14
15
16
17
18
Q2
Q2
D4
D4
Q4
Q4
PGND4
PGND4
IN2
ST4
VDD
VCC
N.C.
99AT0060
June 2002
1/21
L9352
Figure 2. Block Diagram
VS
VCC
VDD
Internal Supply
EN
CLK
IN1
Overtemperature
Channel 4
Overtemperature
Channel 1
Open Load
Overload
Q1
LOGIC
ST1
IPD
GND-det.
Open Load
D4
Q4
IN4
Overload
GND-det.
LOGIC
&
DA
ST4
IPD
Overtemperature
Channel 3
Overtemperature
Channel 2
Open Load
Overload
IN2
Q2
LOGIC
ST2
IPD
GND-det.
Open Load
D3
Q3
Overload
GND-det.
IN3
LOGIC
&
DA
ST3
IPD
drift-det.
TEST
GND
99AT0059
2/21
L9352
PIN DESCRIPTION
N°
Pin
GND
PGND 3
Q 3
Function
1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
16, 17
18
Logic Ground
Power Ground Channel 3
Power Output Channel 3
Free-Wheeling Diode Channel 3
Power Output Channel 1
Power Output Channel 2
Free-Wheeling Diode Channel 4
Power Output Channel 4
Power Ground Channel 4
Not Connected
D 3
Q 1
Q 2
D 4
Q 4
PGND 4
NC
19
VCC
VDD
ST 4
IN 2
5V Supply
20
5V Supply
21
Status Output Channel 4
Control Input Channel 2
Control Input Channel 4
Status Output Channel 2
Enable Input for all four Channels
Enable Input for Drift detection
Power Ground Channel 2
Supply Voltage
22
23
IN 4
24
ST 2
EN
25
26
TEST
PGND 2
VS
27, 28
29
30, 31
32
PGND 1
ST 1
IN 3
Power Ground Channel 1
Status Output Channel 1
Control Input Channel 3
Control Input Channel 1
Status Output Channel 3
Clock Input
33
34
IN 1
35
ST 3
CLK
36
3/21
L9352
ABSOLUTE MAXIMUM RATINGS
The absolute maximum ratings are the limiting values for this device. Damage may occur if this device is sub-
jected to conditions which are beyond these values.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
E
Q
Switch off energy for inductive loads
50
mJ
Voltages
V
Supply voltage
-0.3
-0.3
40
6
V
V
V
V
V
V
V
V
V
S
V
, V
CC DD
Supply voltage
V
Q
V
Q
Output voltage static
Output voltage during clamping
Input voltage IN1 to IN4, EN
Input Voltage CLK
40
60
6
t < 1ms
V , V
IN
I < |10|mA
I
-1.5
-1.5
-0.3
EN
V
CLK
6
V
Output voltage status
Recirculation circuits D3, D4
6
ST
V
D
40
55
V
max. reverse breakdown voltage of free
wheeling diodes D3, D4
DRmax
Currents
I
Output current for Q1 and Q2
Output current for Q3 and Q4
>5
>3
-4
internal
limited
A
A
A
Q1/2
I
internal
limited
Q3/4
I
,
Output current at reversal supply for Q1
and Q2
Q1/2
I
I
PGND1/2
I
,
Output current at reversal supply for
Q3 and Q4
-2
-5
A
Q3/4
PGND3/4
I
ST
Output current status pin
5
mA
ESD Protection
ESD
Electrostatical Discharging
MIL883C
±2
kV
GND, PGND, Qx, Dx, CLK, ST, IN,
TEST, EN
VS,
VCC,VDD
Supply pins
vs. GND and PGND
±1
kV
kV
ESD
Output Pins (Qx, Dx)
vs. Common GND
(PGND1-4 + GND)
±4
THERMAL DATA
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
°C
T
Junction temperature
T
-40
150
j
j
T
Junction temperature during clamping
(life time)
175
190
°C
Σt = 30min
Σt = 15min
jc
T
Storage temperature
T
-55
150
200
°C
°C
stg
stg
(1)
T
Overtemperature shutdown threshold
175
th
(1)
T
Overtemperature shutdown hysteresis
Thermal resistance junction to case
10
°C
hy
R
R
thJC
2
K/W
thJC
(1) This parameter will not be tested but assured by design
4/21
L9352
OPERATING RANGE
Symbol
Parameter
Test Conditions
Min.
4.8
4.5
-1
Typ.
Max.
18
Unit
V
V
Supply voltage
Supply voltage
S
V
, V
CC
5.5
1
V
DD
dV /dt
Supply voltage transient time
Output voltage static
V/µs
V
S
V
V
-0.3
40
Q
Q
Output voltage induced by inductive switching Voltage will be
60
V
limited by internal
Z-diode clamping
V
Output voltage status
Output current status
Junction temperature
-0.3
-1
6
1
V
ST
I
mA
°C
°C
ST
T
-40
150
j
T
Junction temperature during clamping
175
190
Σ = 30min
Σ = 15min
jc
.
ELECTRICAL CHARACTERISTCS
:
(Vs = 4.8 to 18V; T = -40 to 150°C unless otherwise specified)
j
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Power Supply
I
Supply current
5
5
mA
mA
V ≤ 18V
(outputs ON)
SON
S
I
Quiescent current
V ≤ 18V
S
SOFF
(outputs OFF)
I
Supply current VCC (analog supply)
Supply current VDD (digital supply)
Supply current VDD (digital supply)
VCC =5V
5
5
5
mA
uA
cc
dd
dd
I
I
VDD =5V f
VDD =5V f
=0Hz
CLK
=250kHz
CLK
mA
General Diagnostic Functions
V
Open load voltage
0.3
0.33
2.5
0.36
x V
V ≥ 6.5V
(outputs OFF)
QU
Q
S
V
Signal-GND-loss threshold
Power-GND-loss threshold
Clock frequency error
VCC= 5V
0.1
1.5
10
1
V
V
thGND
V
thPGL
VCC= 5V
3.5
100
45
f
kHz
%
CLK,min
DC
Clock duty cycle error detection low
f
f
= 250 kHz
= 250 kHz
33,3
66,6
CLKe_l
ow
CLK
DC
Clock duty cycle error detection high
55
2
%
V
CLKe_
CLK
high
VS
Supply detection
VCC = VDD = 5V
4.5
loss
Additional Diagnostic Functions channel 1 and channel 2 (non regulated channels)
I
I
Open-load current channel 1, 2
Over-load current channel 1, 2
50
5
300
9
mA
A
V ≥ 6.5V
QU1,2
S
7.5
V ≥ 6.5V
S
QO1,2
5/21
L9352
ELECTRICAL CHARACTERISTCS
: (continued)
(Vs = 4.8 to 18V; T = -40 to 150°C unless otherwise specified)
j
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Additional Diagnostic Functions channel 3 and channel 4 (regulated channels)
DC
I
Output duty cycle range
filtered with 10ms
10
90
8
%
A
OUT
Overload current
channel 3,4
2.5
5
V ≥ 6.5V
S
QO3,4
V
Recirculation error shutdown
threshold (open D3/D4)
Iout > 50mA
45
50
60
V
rerr
PWM
Output PWM ratio during drift
comparison
V
V
= V
= PWM
IN
-14.3
+14.3
%
dOU
IN3
IN4
T
= H
TEST
Digital Inputs (IN1 to IN4, ENA, CLK, TEST). The valid PWM-Ratio for IN3/IN4 is 10% to 90%
V
Input low voltage
Input high voltage
-0.3
2
1
6
V
V
IL
V
IH
(1)
V
20
500
mV
IHy
Input voltage hysteresis
Input pull down current
I
I
8
20
40
V
IN
= 5V, V ≥ 6.5V
µA
S
Digital Outputs (ST1 to ST4)
(2))
(2)
V
0
0.4
V
I
ST ≤ 40µA
STL
Status output voltage in low state
V
2.5
2
3.45
3.45
1.5
V
V
IST ≥ -40µA
STH
Status output voltage in high state
I
ST ≥ -120µA
R
R
R
R
+ R
+ R
in low state
in high state
0.3
1.5
0.64
3.2
kΩ
kΩ
DIAGL
OUT
OUT
DSON
7.0
DIAGH
DSON
Power Outputs (Q1 to Q4)
Static drain-source ON-resistance
R
DSON
0.2
0.4
1.5
Ω
I
I
= 1A; V ≥ 9.5V
S
Q
V
Forward voltage of free wheeling path
D3, D4 @250mA
= -250mA
0.5
2.0
V
F_250mA
D3/4
V
Forward voltage of free wheeling path
D3, D4 @2.25A
I
= -2.25A
4.5
V
F_2.25A
D3/4
R
Sense resistor = (V
2A
V )/
F_2.25A- F_250mA
1
Ω
sens
V
Z-diode clamping voltage
Output pull down current
Output leakage current
45
10
60
150
5
V
I
Q ≥ 100mA
Z
I
PD
V
V
= H, V = L
µA
µA
EN
EN
IN
I
= L; V = 20V
Qlk
Q
Timing
t
Output ON delay time
0
0
5
20
30
µs
µs
ON
I
I
= 1A
Q
Q
t
Output OFF delay time channel
10
OFF
= 1A
(3)
t
Output OFF delay time regulator
Output rise time
528
1.5
µs
µs
OFFREG
t
0.5
8
r
I
= 1A
Q
6/21
L9352
ELECTRICAL CHARACTERISTCS
: (continued)
(Vs = 4.8 to 18V; T = -40 to 150°C unless otherwise specified)
j
Symbol
Parameter
Output fall time
Test Condition
= 1A
Min.
Typ.
Max.
Unit
t
f
0.5
1.5
8
µs
I
f
f
Q
(3)
(3)
t
Short error detection filter time
4
16
4
8
32
µs
µs
sf
= 250kHz DC = 50%
= 250kHz DC = 50%
CLK
CLK
t
lf
Long error detection filter time
(3)
t
Short circuit switch-OFF delay time
30
µs
us
SCP
(3)
(3)
t
Status delay time
896
1024
D
t
Regulation error status delay time
10
ms
RE
(reg. channels only)
(3)
t
Output off status delay time
528
µs
Dreg
(reg. channels only
Reg. Current Accuracy (reg. channels only)
I
Minimum current
Maximum current
DC = 10%
DC = 90%
200
2
250
300
2.5
mA
A
Q3/Q4
Q3/Q4
I
2.25
I
Max. regulation deviation @
DC 10% - 90%
250mA < I
400mA ≤ I
800mA < I
< 400mA
≤ 800mA
< 2.25A
±10
±6
±10
%
%
%
REG
Q3/Q4
Q3/Q4
Q3/Q4
Min. quant. step
5
mA
∆I
Q3/Q4
Frequencies
CLK frequency
crystal-controlled
250
2
kHz
kHz
Input PWM frequency
(reg. channels only)
(1) This parameter will not be tested but assured by design.
(2) Short circuit between two digital outputs (one in high the other in low state) will lead to the defined result "LOW"
(3) Digital filtered with external clock, only functional test
7/21
L9352
1.0
1.1
Functional Description
Overview
The L9352 is designed to drive inductive loads (relays, electromagnetic valves) in low side configuration. Inte-
grated active Zener-clamp (for channel1 and 2) or free wheeling diodes (for channel 3 and 4) allow the recircu-
lation of the inductive loads. All four channels are monitored with a status output. All wiring to the loads and
supply pins of the device are controlled. The device is self-protected against short circuit at the outputs and over-
temperature. For each channel one independent push-pull status output is used for a parallel diagnostic func-
tion.
Channel 3 and 4 work as current regulator. A PWM signal on the input defines the target output current. The
output current is controlled through the output PWM of the power stage. The regulator limits of 10% or 90% are
detected and monitored with the status signal. The current is measured during recirculation phase of the load.
A test mode compares the differences between the two regulators. This “drift” test compares the output PWM
of the regulators. By this feature a drift of the load during lifetime can be detected.
1.2
Input Circuits
The INput, CLK, TEST and ENable inputs, are active high, consist of Schmidt triggers with hysteresis. All inputs
are connected to pull-down current sources.
1.3
Output Stages (not regulated) Channel 1 and 2
The two power outputs (5A) consist of DMOS-power transistors with open drain output. The output stages are
protected against short circuit. Via integrated Zener-clamp-diodes the overvoltage of the inductive loads due to
recirculation are clamped to typ. 52V for fast shut off of the valves. Parallel to the DMOS transistors there are
internal pull-down current sources. They are provided to assure an open load condition in the OFF-state. With
EN=low this current source is switched off, but the open load comparator is still active.
1.4 Current-Regulator-Stages Channel 3 and 4
The current-regulator channels are designed to drive inductive loads. The target value of the current is given by
the duty cycle (DC) of the 2kHz PWM input signal. The following figure shows the relation between the input
PWM and the output current and the specified accuracy
.
Figure 3. Input PWM to output current range
2250
+-10%
800
+- 6%
400
±10%
250
INPUT PWM[%]
90
10
8/21
L9352
The ON period of the input signal is measured with a 1MHz clock, synchronized with the external 250kHz clock.
For requested precision of the output current the ratio between the frequencies of the input signal and the ex-
ternal 250kHz clock has to be fixed according to the graph shown in Fig.
Figure 4. Current accuracy according to the input and clock frequency ratio
5.6%
Regulator
112.5
125
132
fCLK / fIN
0%
switched off
-10%
The theoretical error is zero for f
/ f = 125.
CLK IN
If the period of the input signal is longer than 132 times the period of the clock the regulator is switched off. For
a clock frequency lower than 100kHz the clock control will also disable the regulator. For high precision appli-
cations the clock frequency and the input frequency have to be correlated.
The output current is measured during the recirculation of the load. The current sense resistor is in series to the
free wheeling diode. If this recirculation path is interrupted the regulator stops immediately and the status output
remains low for the rest of the input cycle.
The output period is 64 times the clock period. With a clock frequency of 250kHz the output PWM frequency is
3.9kHz. The output PWM is synchronized with the first negative edge of the input signal. After that the output
and the input are asynchronous. The first period is used to measure the current. This means the first turn-on of
µ
the power is 256 s after the first negative edge of the input signal.
As regulator a digital PI-regulator with the Transfer function for:
KI:
and KP: 0.96
0.126
--------------
z – 1
for a sampling time of 256us is realised.
To speed up the current settling time the regulator output is locked to 90% output PWM untill the target current
value is reached. This happens alsowhen the target current value changes and the output PWM reaches 90%
during the regulation. The status output gets low if the target current value is not reached within the regulation
t
error delay time of RE=10ms. The output PWM is than out of the regulation range from 10% to 90%.
1.5
Protective Circuits
The outputs are protected against current overload, overtemperature, and power-GND-loss. The external clock
f
is monitored by a clock watchdog. This clock watchdog detects a minimal frequency CLK,min and wrong clock
duty cycles. The allowed clock duty cycle range is 45% to 55%. The current-regulator stages are protected
9/21
L9352
against recirculation errors, when D3 or D4 is not connected. All these error conditions shut off the power stage
and invert the status output information.
1.6
Error Detection
The status outputs indicate the switching state under normal conditions (status LOW = OFF; status HIGH = ON).
If an error occurs, the logic level of the status output is inverted, as listed in the diagnostic table below. All ex-
ternal errors, for example open load, are filtered internally. The following table shows the detected errors, the
filter times and the detection mode (on/off).
ON State
OFF State
Filter time
Reset done by
EN &IN = HIGH EN &IN = LOW
Short circuit of the load
X
t
EN & IN = “LOW”
sf
for
or
T
Dreg
T
D
Open load
(under voltage detection)
X
t
lf
timer
T
D
Open load
(under current detection)
X
X
t
t
timer
T
sf
sf
D
Overtemperature
Power-GND-loss
EN & IN = “LOW”
for or
T
T
D
Dreg
in on: EN & IN = “LOW”
for or
X
X
t
lf
T
T
D
Dreg
in off: timer
T
D
Signal-GND-loss
Supply-VS-loss
Clock control
X
X
X
X
X
X
t
timer
timer
T
T
lf
lf
D
D
t
no
in on: EN & IN = “LOW”
for or
T
T
D
Dreg
in off: timer
T
D
Output voltage clamp active
X
no
in on: EN & IN = “LOW”
for or
(regulated
channels)
T
T
D
Dreg
in off: timer
T
D
EN&IN=low means that at least one between enable and input is low. For the inputs IN=low means also no input
PWM. For the regulator input period longer than T and for the standard channel input period longer thanT .
Dreg
D
A detected error is stored in an error register. The reset of this register is made with a timer T . With this ap-
D
proach all errors are present at the status output at least for the time T .
D
All protection functions like short circuit of the output, overtemperature, clock failure or power-GND-loss in ON
condition are stored into an internal “fail” register. The output is then shut off. The register must be reset with a
low signal at the input. A “low signal” means that the input is low for a time longer than T or T
for the re-
DReg
D
ulated channel, otherwise it is interpreted as a PWM input signal and the register is left in set mode.
Signal-GND-loss and VS-loss are detected in the active on mode, but they do not set the fail register. This type
t
of error is only delayed with the standard timer lf function.
Open load is detected for all four channels in on- and off-state.
Open load in off condition detects the voltage on the output pin. If this voltage is below 0.33 * VS the error reg-
ister is set and delayed with T . A sink current stage pull the output down to ground, with EN high. With EN low
D
the output is floating in case of openload and the detection is not assured. In the ON state the load current is
monitored by the non-regulated channels. If it drops below the specified threshold value I
an open load is
QU
detected and the error register is set and delayed with T . A regulated channel detects the open load in the on
D
state with the current regulator error detection. If the output PWM reaches 90% for a time longer than t
than
RE
an error occurs. This could happen when no load is connected, the resistivity of the load is too high or the supply
voltage too low. The same error is shown if the regulator is not able to reduce the current in the load in the time
t
, so the output PWM falls below 10%.
RE
f
A clock failure (clock loss) is detected when the frequency becomes lower than CLK,min. All status outputs are
10/21
L9352
set on error and all power outputs are shut off. The status signals remain in their state until the clock signal is
present again. A clock failure during power on of VCC is detected only on the regulated channels. The status
outputs of the channel 1 and 2 are low in this case.
1.7
Drift Detection (regulated channels only)
The drift detection is used to compare the two regulated channels during regulation. This “Drift” test compares
the output PWM of the regulators. The resistivity of the load influences the output PWM. The approximated for-
mula for the output current below shows the dependency of the load resistor to the output PWM. In this formula
the energy reduction during the recirculation is not taken into account. The real output PWM is higher. The test-
mode is enabled with IN,EN and TEST high. With an identical 2kHz PWM-Signal connected to the IN-inputs the
output PWM must be in a range of +-14.3%. If the difference between the two on-times is more than ±14.3% of
the expected value an error is detected and monitored by the status outputs, in the same way as described
above, but a drift error will not be registered and also not delayed with T as other errors
D
VBAT
RL + RON
----------------------------
IOUT =
PWM
Drift Definition:
Drift = PWM(1+E) - PWM (1-E) = 2PWM E
Drift * 4 < PWM (1+E)
with E >14.3% a drift is detected
E.. not correlated Error of the channels
%PWM ... Corresponding ideal output PWM to a given input PWM
A 7bit output-PWM-register is used for the comparison. The register with the lower value is subtracted from the
higher one. This result is multiplied by four and compared with the higher value.
1.8
Other Test modes
The test pin is also used to test the regulated channels in the production. With a special sequence on this pin
the power stages of the regulated channels can be controlled direct from the input. No status feedback of the
regulated channels is given. The status output is clocked by the regulator logic. The output sequence is a indi-
cation of a proper logic functionality. The following table shows the functionality of this special test mode
EN
1
IN
X
1
TEST
OUT
X
STATUS
Note
disable test mode
Drift mode
X
1
X
1
1
on
0
X
off
test pattern
test condition one
0
0
0
0
X
X
0
1
off
off
off
on
test pattern
test pattern
test pattern
test pattern
test condition two
test condition three
test condition four
test condition four
For more details about the test condition four see timing diagram.
11/21
L9352
Diagnostic Table
The status follows the input signal in normal operating conditions.
If any error is detected the status is inverted.
Operating Condition
Test
Input
TEST
Enable
Input
ENA
Control Input Power Output/
non-reg./reg. Current reg.
Status
Output
ST
IN
Q
Normal function
L
L
L
L
L
L
H
L
OFF
OFF
OFF
ON
L
L
L
H/PWM
L
H/PWM
H
H
Open load or short to ground
L
L
L
L
L
L
H
H
L
OFF
OFF
OFF
ON
X
X
H
L
H/PWM
L
H/PWM
Overload or short to supply
Latched overload
Reset latch
L
L
L
L
H
H
H/PWM
H/PWM
X
OFF
OFF
OFF
OFF
L
L
L
L
H –> L
H
Reset latch
H/PWM –> L
Overtemperature
Latched overtemperature
Reset latch
L
L
L
L
H
H
H/PWM
H/PWM
X
OFF
OFF
OFF
OFF
L
L
L
L
H –> L
H
Reset latch
H/PWM –> L
Recirculation error (reg.chn.)
Latched error
L
L
L
L
H
H
PWM
PWM
X
OFF
OFF
OFF
OFF
L
L
L
L
Reset latch
Reset latch
H –> L
H
PWM –> L
(1)
L
L
L
L
L
L
H
H
L
OFF
OFF
OFF
OFF
H
H
H
L
Clock failure (clock loss)
H/PWM
L
H/PWM
(2)
H
H
H
H
L
L
H
H
L
OFF
OFF
ON
X
X
L
Drift
H/PWM
H/PWM
H/PWM
Failure
No failure
ON
H
(1) during power on sequence only detected on channel 3 and 4 (see description).
(2) This input combination is also used for an internal chip-test and must not be used.
12/21
L9352
2.0
Timing Diagrams
2.1 Non Regulated Channels
Figure 5. Output Slope, Resistive Load
VI
VIH
VIL
t
tOFF
tr
tON
tf
VQ
VS
85% V S
15% V S
t
99AT0061
Figure 6. Overload Switch-OFF Delay
IQ
IQO
IQU
t
tD
tSCP
VST
tsf
t
00RS0001
13/21
L9352
Figure 7. Normal Condition, Resistive Load, Pulsed Input Signal
VIN
VQ
IQ
IQU
tD
tD
VST
99AT0063
Figure 8. Current Overload
tD
Reset Fail
register
VIN
VQ
Set Fail
register
IQO
IQ
tD
VST
99AT0064
14/21
L9352
Figure 9. Diagnostic Status Output at Different OPEN Load Current Conditions
Under current condition followed by normal operation
tD
VIN
VQ
IQ
IQU
tD
VST
99AT0065
Open load condition in the case of pulsed input signal followed by normal operation
tD
VIN
VQ
IQU
IQ
tD
VST
99AT0066
15/21
L9352
Figure 10. Pulsed Open Load Conditions (regulated and non-regulated channels)
VIN
VQ
0.33 x VS
IQ
tD
tlf
tlf
VST
99AT0067
2.2 Regulated Channels (timing diagrams of diagnostic with 2kHz PWM input signal)
Figure 11. Normal Condition, Inductive Load
tDREG
500µs
VIN
VQ
IQ
Target Current
256µs
256µs
VST
99AT0068
16/21
L9352
Figure 12. Current Overload
tDREG
Reset Fail
register
500µs
VIN
VQ
IQ
Set fail
registor
IQO
tsf
VST
99AT0069
Figure 13. Recirculation Error
tDREG
Reset Fail
register
500µs
VIN
VQ
Set Fail
register
target current
IQ
VST
99AT0070
17/21
L9352
Figure 14. Current Regulation Error (e.g. as a result of voltage reduction)
500µs
VIN
VQ
IQ
PWMratio = 90%
target current
tRE
VST
99AT0071
Figure 15. Overtemperature
Overtemperature
Condition
tDREG
Reset Fail
register
500µs
VIN
VQ
Set Fail
register
target current
IQ
VST
99AT0072
18/21
L9352
Figure 16.
Test mode 4
VEN low
VTEST
VIN3/4
VQ3/4
99AT0073
19/21
L9352
mm
inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
OUTLINE AND
MECHANICAL DATA
A
a1
a2
a3
b
3.60
0.141
0.012
0.130
0.004
0.015
0.012
0.630
0.385
0.570
0.10
0.30 0.004
3.30
0
0.10
0
0.22
0.23
0.38 0.008
0.32 0.009
16.00 0.622
9.80 0.370
14.50 0.547
c
D (1) 15.80
D1
E
9.40
13.90
e
0.65
0.0256
0.435
e3
11.05
E1 (1) 10.90
E2
11.10 0.429
2.90
0.437
0.114
0.244
0.126
0.004
0.626
0.043
0.043
E3
E4
G
H
5.80
2.90
0
6.20 0.228
3.20 0.114
0.10
0
15.50
15.90 0.610
1.10
h
L
0.80
1.10 0.031
10°(max.)
8 °(max.)
N
S
PowerSO36
(1): "D" and "E1" do not include mold flash or protrusions
- Mold flash or protrusions shall not exceed 0.15mm (0.006 inch)
- Critical dimensions are "a3", "E" and "G".
N
N
a2
A
c
a1
e
A
DETAIL B
lead
E
DETAIL A
e3
H
DETAIL A
D
slug
a3
BOTTOM VIEW
36
19
E3
B
E1
E2
D1
DETAIL B
0.35
Gage Plane
- C -
SEATING PLANE
1
1
8
S
L
G
C
M
b
0.12
A B
PSO36MEC
h x 45˚
(COPLANARITY)
20/21
L9352
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21/21
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