L9374XP [STMICROELECTRONICS]

Four channel valve driver; 四通道阀驱动器


型号：	L9374XP
厂家：	ST
描述：	Four channel valve driver 四通道阀驱动器驱动器
文件：	总10页 (文件大小：219K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

L9374

Four channel valve driver

Data Brief

Features

■ Four low-side output drivers with protection

diagnostic

– 2 PWM controlled channels (0.2Ω typ)

– 2 current controlled channels with 6%

accuracy (0.3Ω typ)

PowerSO-36

PowerSSO-36

■ All outputs with 35V Zener clamp

■ Programmable channel timer

■ Clock monitor

are stored in the PWM and in the Counter

Configuration Register respectively.

The PWM Controller translates the programmed

digital duty cycle value in a PWM signal which

controls the output.

■ Integrated recirculation diodes

■ Serial Peripheral Interface with 16bits, up to

5MHz with diagnosis

■ Battery compatible supply voltage

For the current controlled channels the target

current value is programmed. It is also possible to

program two different target currents. The target

current is compared with the real load current.

The output duty cycle is then calculated with an

Arithmetic Logic Unit. As base for the calculation

a load model is used respecting the resistivity of

the load, the supply voltage as well as the

internal recirculation path. To check the

■ Detailed Load diagnosis

– Over load protection

– Open Load

– Under-current

– Under Voltage

– Temperature Warning and Shutdown

– Power or Signal GND loss

– Freewheeling diode loss

– Silent valve driver test

plausibility of the current controller all measured

and calculated values are available and

accessible via SPI.

Description

The L9374 is a four channel low side driver with

integrated recirculation diodes. The switching of

the channels is programmable via a SPI (Serial

Peripheral Interface). The main time base is given

by an external clock via CLKin. The Clock Unit

monitors this external clock and provides the

system clock for all timings.

A Synchronization Unit is used to monitor the SPI

communication and provides a sync signal for the

channel activation.

All channels are equipped with a load Diagnostic.

This allows to detect an open load in off condition

as well as an under current in on condition. The

power stage is protected against over current and

over temperature. A weak connection in power

ground or in the recirculation path is monitored.

All monitored functions can be read out in a serial

diagnostic protocol dedicated for each channel

via SPI..

Table 1.

Device summary

Package

The Output Duty Cycle for each channel can be

programmed individually and will be activated by

the Set Point Unit. Is possible to program two

output Duty Cycles per channel with a block of 16

SPI commands as well as an individual Duration

Time for each channel actuation. Both information

Order code

Packing

L9374

PowerSO-36 (slug down)

PowerSSO-36 (exp. pad)

Tube

L9374XP

July 2007

Rev 2

1/10

For further information contact your local STMicroelectronics sales office.

www.st.com

Block diagram

L9374

Block diagram

Figure 1.

Block diagram

e l v a v d l l e o r t n c o M W P

e v l a v d t e a g u l r e r r u e n C t

e l v a v d l l e o r t n c o M W P

e v l a v d t e a g u l r e r r u e n C t

n o i t c e t e

i / S o t a d M - t s T I e / S / P C

e t r s i g R e e s a g D n o i

E r r o r

d r d n a

K L / S C Y N

e t r g i s R e o i t n u r i a g

C M o n W f P

e t r s g i n i R o e a t u r i g n f C o C o u n t

e t r s g i

u g r i e R e C o n n f i o a c t u n i m m C o

2/10

L9374

Pins description

Figure 2.

PowerSSO36 pins connection (top view)

PGND3

D1/D3

SGND

PGND1

PGND12

PGND2

SPICS

MISO

MOSI

SPICLK

CLKIN

D4/D2

PGND4

D06AT546A

Figure 3.

PowerSO36 pins connection (top view)

PGND

PGND3

D1/D3

SGND

PGND1

PGND12

PGND2

SPICS

MISO

MOSI

SPICLK

CLKIN

D4/D2

PGND

PGND4

AC00419

3/10

Pins description

L9374

Table 2.

Pins description

PwSSO36

Pin No.

PwSO36

Description

N.C.

PGND

Not connected/Power ground

Output.

D1/D3

Free wheeling diode.

Output.

PGND1

PGND12

PGND2

PGND1

PGND12

PGND2

Power ground of the output driver 1& 2.

Output.

N.C.

Not connected.

D4/D2

Free wheeling diode.

Output.

N.C.

PGND

PGND4

N.C.

Not connected/Power ground

Power ground of the output driver 4.

Not connected.

PGND4

N.C.

Not connected.

N.C.

Not connected.

N.C.

Not connected.

Supply pin

CLKIN

SPICLK

MOSI

MISO

SPICS

CLKIN

SPICLK

MOSI

MISO

SPICS

Input for precise clock.

SPI communication CLocK.

Master Out Slave In for SPI communication.

Master In Slave Out for SPI communication.

SPI Chip Select.

Enable

SGND

N.C.

SGND

N.C.

Signal ground.

Not connected.

N.C.

Not connected.

N.C.

Not connected.

N.C.

Not connected.

PGND3

Power ground of the output driver 3.

4/10

L9374

Absolute maximum ratings

Table 3.

Symbol

Absolute maximum ratings

Parameter

Min

Max

Unit

V_s

Supply voltage

-0.3

V_Dx

V_Qx

V_EN

Freewheeling diode voltage

Output voltage

Enable voltage

V_SPICLKSPI clock voltage

V_SPICSSPI chip select voltage

V_MOSISPI MOSI voltage

V_MISOSPI MISO voltage

V_CLKINSPI clock input voltage

-0.3

I_{Q1; 2}

-4

-2

Output current at reversal voltage

I_{Q3; 4}

I_{EN_CL}

I_{SPICLK_}

I_{SPICS_C}Input clamping currents (static)

- 3

+ 3

Input clamping currents (dynamic)

-10

+10

I_{MOSI_CL}

I_{CLKIN_C}

Definition: Current from outside into the L9374-> " + "

Current from L9374 towards external components -> " - "

Warning: Transients beyond this limit will cause currents into ESD

structures which must be limited externally to 10 mA

(maximum energy to be dissipated: 2 mJ).

5/10

ESD susceptibility

L9374

ESD susceptibility

4.1

HBM

ESD susceptibility HBM according to EIA/JESD 22-A 114B otherwise defined.

Table 4.

HBM

Condition

Min

Max

Unit

All Pins

PGND12, PGND3, PGND4, LGND

and GND are connected together.

Output pins D_X; Q_X;

4.2

ESD susceptibility according to EIA/JESD22-A115-A

Table 5.

Parameter

Condition

Min

Max

Unit

Machine Model (MM)

All pins

250

6/10

L9374

Package informations

In order to meet environmental requirements, ST offers this device in ECOPACK package.

This package has a Lead-free second level interconnect. The category of second level

Interconnect is marked on the package and on the inner box label, in compliance with

JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also

marked on the inner box label. ECOPACK is an ST trademark.

ECOPACK specifications are available at: www.st.com.

Figure 4.

PowerSO-36 (slug down) mechanical data and package dimensions

inch

DIM.

MIN.

TYP. MAX. MIN.

3.60

TYP. MAX.

0.1417

0.0118

0.1299

0.0039

0.0150

0.0126

0.6299

0.3858

0.5709

0.4370

0.1142

0.2441

0.0256

0.4350

0.0039

0.6260

0.0433

OUTLINE AND

MECHANICAL DATA

0.10

0.30 0.0039

3.30

0.10

0.22

0.23

15.80

9.40

13.90

10.90

0.38 0.0087

0.32 0.0091

16.00 0.6220

9.80 0.3701

14.5 0.5472

11.10 0.4291

2.90

5.80

6.20 0.2283

0.65

11.05

0.10

15.50

15.90 0.6102

1.10

0.8

1.10 0.0315

10˚ (max)

8˚ (max)

PowerSO-36

Note: “D and E1” do not include mold flash or protusions.

- Mold flash or protusions shall not exceed 0.15mm (0.006”)

- Critical dimensions are "a3", "E" and "G".

0096119 C

7/10

Package informations

Figure 5.

L9374

PowerSSO-36 (exposed pad) mechanical data and package dimensions

inch

TYP. MAX.

0.097

DIM.

MIN.

2.15

0.18

0.23

10.10

TYP. MAX. MIN.

2.47 0.084

2.40 0.084

OUTLINE AND

MECHANICAL DATA

0.094

0.003

0.014

0.012

0.075

0.36 0.007

0.32 0.009

10.50 0.398

(1)

0.413

(1)

7.4

7.6

0.291

0.299

0.50

8.50

2.3

0.020

0.035

0.090

0.004

0.002

0.413

0.016

0.033

0.169

0.10

0.06

10.50 0.398

0.40

10.10

0.55

0.85 0.022

4.3

10˚ (max)

1.2

0.8

2.9

3.65

1.0

0.047

0.031

0.114

0.144

0.039

0.185

0.279

4.10

6.50

4.70 0.161

7.10 0.256

PowerSSO-36

(exposed pad)

(1) “D and E” do not include mold flash or protusions.

Mold flash or protusions shall not exceed 0.15mm (0.006”)

(2) No intrusion allowed inwards the leads.

(3) Flash or bleeds on exposed die pad shall not exceed 0.4 mm

per side

7587131 A

8/10

L9374

Revision history

Table 6.

Date

Document revision history

Revision

Changes

4-Jun-2007

31-Jul-2007

Initial release.

Updated Section 1: Block diagram , Section 2: Pins description and

Section 4: ESD susceptibility.

9/10

L9374

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10/10

L9374XP [STMICROELECTRONICS]

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