L9733 [STMICROELECTRONICS]
Octal self configuring Low/High side driver; 八路自我配置低/高侧驱动器
| 型号： | L9733 |
| 厂家： | 
ST |
| 描述： | Octal self configuring Low/High side driver |
| 文件： | 总33页 (文件大小：560K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L9733
Octal self configuring Low/High side driver
Preliminary Data
Features
■ Eight independently self configuring low/high
drivers
■ Supply voltage from 4.5V to 5.5V
■ RON(max)=0.7Ω @ T = 25°C,
j
SO-28
PowerSSO-28
R
ON(max)=1.2Ω @T = 125°C
j
■ Minimum current limit of each output 1A
■ Output voltage clamping min. 40V in low side
Outputs 1-8 are self-configuring as high or low
side drives. Self-configuration allows a user to
connect a high or low side load to any of these
outputs and the L9733 will drive them correctly as
well as provide proper fault mode operation with
no other needed inputs. In additon, Outputs 6, 7 and
8 can be PWM controlled via a external pins (IN6-8).
configuration
■ Output voltage clamping max. -14V in high side
configuration
■ SPI interface for outputs control and for
diagnosis data communication
■ Additional PWM inputs for 3 outputs
This device is capable of switching variable load
currents over the ambient range of -40°C to
+125°C. The outputs are MOSFET drivers to
minimize Vdd current requirements. For low side
configured outputs an internal zener clamp from
the drain to gate with a breakdown of 50V
minimum will provide fast turn off of inductive
loads. When a high side configured output is
commanded OFF after having been commanded
ON, the source voltage will go to (VGND - 15V).
■ Independent thermal shutdown for all outputs
Open load, Short to GND, short to Vb,
Overcurrent diagnostics in latched or unlatched
mode for each channel
■ Internal charge pump without need of external
capacitor
■ Controlled SR for reduced EMC
Description
An 16 bit SPI input is used to command the 8
output drivers either "On" or "Off", reducing the
I/O port requirement of the microcontroller.
Multiple L9733 can be daisy-chained. In addition
the SPI output indicates latched fault conditions
that may have occurred.
The L9733 IC is a highly flexible monolithic,
medium current, output driver that incorporates 8
outputs that can be used as either internal low or
high side drives in any combination.
Order codes
Part number
Package
SO-28
PowerSSO-28 (Exposed pad)
Packing
L9733
Tube
Tube
L9733XP
August 2006
Rev 3
1/33
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
www.st.com
1
Contents
L9733
Contents
1
2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
2.2
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute maximun ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
4
Electrical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
3.2
3.3
DC Characteristics: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
AC Characteristics: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SPI Characteristics and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1
Configurations for Outputs 1-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1.1
4.1.2
Low Side Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
High Side Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2
4.3
4.4
4.5
Outputs 1-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Outputs 6-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Drn1-8 Susceptibility To Negative Voltage Transients . . . . . . . . . . . . . . . 18
Supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.5.1
4.5.2
4.5.3
Main Power Input (Vdd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Battery supply (Vbat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Discrete Inputs Voltage Supply (VDO) . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.6
Discrete inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.6.1
4.6.2
Output 6-8 Enable Input (In6, ln7, ln8) . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Reset Input (RES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1
5.2
5.3
5.4
5.5
5.6
Serial Data Output (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Serial Data Input (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Chip Select (CS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Serial Clock (SCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Initial Input Command Register & Fault Register SPI Cycle . . . . . . . . . . . 21
Input Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/33
L9733
Contents
6
Other L9733 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1
6.2
6.3
6.4
Charge Pump Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Waveshaping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
POR Register Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7
Fault Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.1
7.2
Low Side Configured Output Fault Operation . . . . . . . . . . . . . . . . . . . . . . 24
7.1.1
7.1.2
No latch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Latch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
High Side Configured Output Fault Operation . . . . . . . . . . . . . . . . . . . . . 26
7.2.1
7.2.2
No latch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Latch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8
9
Package informations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3/33
List of tables
L9733
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute maximun ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SPI Characteristics and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Bit Command Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Command Register Logic Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Fault Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Fault Logic Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4/33
L9733
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Pin Connection (Top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Output Turn On/Off Delays and Slew Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DO Loading for Disable Time Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SPI Input/Output Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SPI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
L9733 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
L9733 HVAC applicative examplesL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
L9733 Powertrain applicative examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SO28 Mechanical Data & Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 10. PowerSSO28 Mechanical Data & Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5/33
Pin description
L9733
1
Pin description
Figure 1.
Pin Connection (Top view)
VDD
SCLK
CS
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDO
D0
2
3
D1
SRC1
DRN1
DRN2
SRC2
SRC3
DRN3
DRN4
SRC4
IN6
4
SRC8
DRN8
DRN7
SRC7
SRC6
DRN6
DRN5
SRC5
RES
5
6
7
8
9
10
11
12
13
14
IN7
IN8
Vbat
GND
D06AT544
Table 1.
N°
Pin Description
Pin
Function
1
2
VDD 5 Volt Supply Input
SCLK SPI Serial Clock Input
3
CS
SPI Chip Select (Active Low)
4
SRC1 Source Pin of Configurable Driver #1 (0.7 Ω Rdson @+25°)
DRN1 Drain Pin of Configurable Driver #1(0.7 Ω Rdson @+25°)
DRN2 Drain Pin of Configurable Driver #2 (0.7 Ω Rdson @+25°)
SRC2 Source Pin of Configurable Driver #2 (0.7 Ω Rdson @+25°)
SRC3 Source Pin of Configurable Driver #3 (0.7 Ω Rdson @+25°)
DRN3 Drain Pin of Configurable Driver #3 (0.7 Ω Rdson @+25°)
DRN4 Drain Pin of Configurable Driver #4 (0.7 Ω Rdson @+25°)
SRC4 Source Pin of Configurable Driver #4 (0.7 Ω Rdson @+25°)
5
6
7
8
9
10
11
12
13
14
15
16
17
18
IN6
IN7
Discrete Input used to PWM Output Driver #6
Discrete Input used to PWM Output Driver #7
Vbat Battery Supply Voltage
GND Analog Ground
IN8
Discrete Input used to PWM Output Driver #8
RES Reset Input (Active Low)
SRC5 Source Pin of Configurable Driver #5 (0.7 Ω Rdson @+25°)
6/33
L9733
Pin description
Table 1.
N°
Pin Description (continued)
Pin
Function
19
20
21
22
23
24
25
26
27
28
DRN5 Drain Pin of Configurable Driver #5 (0.7 Ω Rdson @+25°)
DRN6 Drain Pin of Configurable Driver #6 (0.7 Ω Rdson @+25°)
SRC6 Source Pin of Configurable Driver #6 (0.7 Ω Rdson @+25°)
SRC7 Source Pin of Configurable Driver #7 (0.7 Ω Rdson @+25°)
DRN7 Drain Pin of Low Side Driver #7 (0.7 Ω Rdson @+25°)
DRN8 Drain Pin of Low Side Driver #8 (0.7 Ω Rdson @+25°)
SRC8 Source Pin of Configurable Driver #8 (0.7 Ω Rdson @+25°)
DI
SPI Data In
DO
SPI Data Out
VDO Microcontroller Logic Interface Voltage
7/33
Operating conditions
L9733
2
Operating conditions
2.1
Maximum ratings
This part may not operate if taken outside the maximum ratings. Once the condition is
returned to within the specified maximum rating or the power is recycled, the part will
recover with no damage or degradation.
Table 2.
Symbol
Maximum ratings
Parameter
Value
Unit
Vdd
Vbat
Tj
Supply Voltage
4.5 to 5.5
4.5 to 18
-40 to 150
min 50
V
V
Battery Supply Voltage
Thermal Junction Temperature Range
Snubbing Volatage of DRN1-8
Output Current 1-8
°C
VDC
mA
IO
max 800
2.2
Absolute maximun ratings
This part may be irreparably damaged if taken outside the specified Absolute Maximum
Ratings. Operation outside the Absolute Maximum Ratings may also cause a decrease in
reliability.
Table 3.
Symbol
Absolute maximun ratings
Parameter
Value
Unit
VDD
Vbat
Supply Voltage
-0.3 to 7
-0.3 to 40
-0.3 to 7.0
-24 to 40
-0.3 to 60
2.5
V
V
Supply Voltage
CS,DI,DO,SCLK,EN,IN6,IN7,IN8,VDO
SRC 1-8
V
VDC
VDC
A
DRN1-8
IOL
IOP
Current Limit of Output 1-8 ( -40°C)
OverCurrent protection at Output 1-8 ( -40°C)
Maximum Clamping Energy
Human Body Model
3
A
20
mj
ESD
2 vs. GND
kV
Table 4.
Symbol
Thermal Data
Parameter
Min
Typ
Max
Unit
Tamb
Tstg
Tj
Operating Ambient Temperature
StorageTemperature
-40
-50
125
150
150
200
°C
°C
°C
°C
Maximum Operating Junction Temperature
Thermal Shut-down Temperature
Rth
151
175
8/33
L9733
Operating conditions
Table 4.
Symbol
Thermal Data
Parameter
Thermal Shut-down Temperature Hysteresis
Thermal resistance junction to ambient
for SO28 (1)
for PowerSSO28 (2)
Min
Typ
Max
Unit
Rth-hys
7
10
25
°C
55
24
°C/W
°C/W
RTh j-amb
RTh j-case Thermal resistance junction to case (PowerSSO28)
RTh j-pins Thermal resistance junction to pins (SO28)
3
°C/W
°C/W
20
1. With 6cm2 on board heat sink area.
2. With 2s2p PCB thermally enhanced.
9/33
Electrical performance characteristics
L9733
3
Electrical performance characteristics
These are the electrical capabilities this part was designed to meet. It is required that every
part meet these characteristics.
3.1
DC Characteristics:
Tamb = -40 to 125°C, Vdd = 4.5 to 5.5 Vdc, Vbat = 4.5 to 18Vdc (high side configuration),
unless otherwise specified.
Table 5.
DC Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Units
IN6vih
IN6vil
IIN6il
0.7vdo
V
V
IN6 Input Voltage
0.3vdo
10
In6 = 0 VDC
|10|
100
µA
µA
V
IN6 Input Current
IN7 Input Voltage Voltage
IN7 Input Current
IN8 Input Voltage
IN8 Input Current
CS Input Voltage
CS Input Current
SCLK Input Voltage
SCLK Input Current
DI Input Voltage
IIN6ih
IN7vih
IN7vil
IIN7il
In6 = VDO
0.7vdo
0.3vdo
10
V
In7 = 0 VDC
In7 = VDO
|10|
100
µA
µA
V
IIN7ih
IN8vih
IN8vil
IIN8il
0.7vdo
0.3vdo
10
V
In8 = 0 VDC
In8 = VDO
|10|
100
µA
µA
V
IIN8ih
CSih
0.7vdo
CSil
0.3vdo
10
V
ICSih
CS = VDO
|10|
100
µA
µA
V
ICSil
CS = 0 VDC
SCLKih
SCLKil
ISCLKih
ISCLKil
DIih
0.7vdo
0.3vdo
10
V
SCLK = VDO
|10|
100
µA
µA
V
SCLK = 0 VDC
0.7vdo
DIil
0.3vdo
10
V
IDIih
DI = VDO
|10|
100
0.4
µA
µA
V
DI Input Current
IDIil
DI = 0 VDC
IDO = 2.5 mA
IDO = -2.5 mA
DOol
DOoh
DO Output Voltages
vdo-0.6
V
10/33
L9733
Electrical performance characteristics
Table 5.
DC Characteristics (continued)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Symbol
IDOzol
IDOzoh
RESih
RESil
IRESil
Parameter
Conditions
DO = 0 VDC
Min
Typ
Max
|10|
Units
µA
µA
V
DO Tri-State Currents
DO = VDO
|10|
0.7vdo
RES Input Voltage
RES Input Current
0.3vdo
10
V
RES = 0 VDC
100
|10|
µA
µA
IRESih
RES = VDO
VDD = SRC1-8 = 0VDC
DRN1-DRN8=18VDC , Vb. Sum
currents(Tamb > 0°C)
Islp
Vbat Sleep Current
Vbat current
10
3
µA
µA
(Tamb @ -40°C)
VDD=5V
Ivbat
15
mA
All Outputs Commanded On
IVDD
IVDD
Max VDD Current
Min VDD Current
All Outputs Commanded On
All Outputs Commanded Off
8.5
mA
mA
0.5
DRN1 - DRN8
Leakage Currents
(Low Side)
VDD = 0 VDC : SRC1-8 = 0 VDC
DRN1- DRN8 = 16 VDC
IDRN1lk
IDRN8lk
-
5
µA
µA
DRN1- DRN8 = 40 VDC
10
VDD = 0 VDC : SRC1-8 = 0 VDC
DRN1- 8 = 16 V
SRC1 – SRC8
ISRC1lk
ISRC8lk.
-
-5
µA
µA
Leakage Currents (High
Side)
DRN1- 8 = 40 VDC
-10
SRC1-8 = GND DI = AC00h
Rload ≤ 11KΩ
Rload ≤ 200KΩ
DRN1 – DRN8 Sink
Current (Low Side)
IDrn1-8sink
10
100
280
µA
µA
120
Open Load Detection
Resistance
RDRN1-8
VBAT>=9V
11
200
KΩ
µA
IDrn1-8source Source Current
Isrc1-8sink
Isrc1-8source
DRN1-DRN8 = GND
-10
-100
DRN1- 8 = Vb, DI = AC00h
SCR1- 8 = Vb
SRC1 – SRC8 Sink/Source
10
100
µA
µA
Current High Side)
SCR1- 8 = GND
-18
-100
SRC1- 8 = GND, DI = AC00h
DRN1- DRN8 = Open
Vdd=4.9 to 5.1 Vdc
2.7
3.1
V
DRN1 – DRN8 Open Load
Voltage (Low Side)
VDrn1-8open
SRC1- 8 = GND, DI = AC00h
DRN1- DRN8 = Open
2.5
2.0
3.5
2.8
V
V
SRC1 – SRC8 Open Load
Vsrc1-8open Voltage (High Side) DRN1 -
DRN8
DRN1-8 = Vb, DI = AC00h
SCR1-8 = open
11/33
Electrical performance characteristics
L9733
Units
Table 5.
Symbol
DC Characteristics (continued)
Parameter
Conditions
Min
Typ
Max
DI = ACFFh, DI = AAFFh
SRC1 – SRC8 = 0 VDC
DRN1 - DRN8
IDRN1limit
IDRN8limit
-
DRN1 - DRN8 = 4.5 - 16 VDC
(Tamb > 0°C)
Current Limits (Low Side)
1
1
2.2
2.5
A
A
(Tamb @ -40°C )
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DI = AC00h, DI = AA00h SRC1 –
SRC8 = 0 VDC
IDRN1OVC
-
DRN1 - DRN8 Overcurrent
threshold (Low Side)
DRN1 - DRN8 = 4.5 - 16 VDC
(Tamb > 0°C)
IDRN8OVC
1
1
2.7
3
A
A
(Tamb - 40°C)
DI = ACFFh, DI = AAFFh
DRN1 - DRN8 = Vb
ISRC1limit
ISRC8limit
-
SRC1 – SRC8 Current
Limits (High Side)
SRC1 – SRC8 = GND
(Tamb > 0°C)
1
1
2.2
2.5
A
A
(Tamb - 40°C)
SRC1 – SRC8
DI = AC00h, DI = AA00h
DRN1 - DRN8 = Vbat
Overcurrent threshold
(High Side)
SRC1 – SRC8 = GND
(Tamb > 0°C)
ISRC1OVC
ISRC8OVC
-
1
1
2.7
3
A
A
(Tamb - 40°C)
DRN1 - DRN8
DRN1 - DRN8
DI = AC00h
DRN1Cl+
DRN8Cl+
-
50
60
V
V
Clamp Voltages (Low Side) SRC1-8 = GND, IDRN1-8 = 350 mA
SRC1 – SRC8 DI = AC00h
Clamp Voltages (High Side) DRN1-8 = Vbat, ISRC1-8 = -350 mA
SRC1Cl+
SRC8Cl+
-
-24
-14
DRN1 - DRN8
DI = AC00h
VDrn1-8open
SRC1 – SRC8 = GND:
Short to GND threshold
distance from open load
voltage (Low side)
0.3
0.3
0.7
0.7
V
V
- DRN1-
8VthGND
Decrease Drn1 - Drn8 until Faults
are ”Set”
DRN1 - DRN8
DI = AC00h
DRN1-
Short to Vbat threshold
distance from open load
voltage (Low Side)
SRC1 – SRC8 = GND : Increase
Drn1 - Drn8 until Faults are ”Not
Set”
8VthVbat
VDrn1-8open
-
SRC1 - SRC8
VDrn1-8open
DI = AC00h
Short to GND threshold
distance from open load
voltage (High Side)
0.2
0.2
0.6
0.6
V
V
- SRC1-
8VthGND
Drn1 – Drn8 = Vb: Decrease SRC1
- SRC8 until Faults are ”Not Set”
SRC1 – SRC8
DI = AC00h
SRC1-
8VthVbat
VDrn1-8open
Short to Vbat threshold
distance from open load
voltage (High Side)
Drn1 – Drn8 = Vbat: Increase
SCR1 - SCR8 until Faults are ”
Set”
-
12/33
L9733
Electrical performance characteristics
Table 5.
DC Characteristics (continued)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
@ +125°C @ IDRN = 350mA
@ +25o C @ IDRN = 350mA
@ -40°C @ IDRN = 350mA
1.2
0.7
0.5
W
W
W
On Resistance
(Drn to SRC1-8)
RdsonDrn1-8
DI = ACFFh, IDrn1-8 = 1 mA,
Thermal Shutdown
Temperature
SRC1 – SRC8 = GND, Increase
temperature until Drn1 - Drn8 > 2
VDC, Verify DO Bits 0-15 are ”Set”
(1)
Drn1-8ther
151
5
200
15
°C
°C
(1)
Drn1-8hyst
Hysteresis
Drn1 - Drn8 < 2 VDC
1. Design Information, Not Tested.
3.2
AC Characteristics:
Tamb= -40 to 125°C, Vdd = 4.5 to 5.5 Vdc, Vbat = 4.5 to 18Vdc, unless otherwise specified
Table 6.
AC Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRN1 - DRN8
Open load & short to
GND filter time (Low
Side)
DI = AC00h, DI = A3FFh
SRC1 – SRC8 = GND
TfiltDRN1-8
300
900
µs
(Latch mode)
SRC1 - SRC8
Open load & short to
Vbatfilter time (High
Side)
DI = AC00h, DI = A3FFh
DRN1 – DRN8 = Vb
TfiltSRC1-8
300
10
900
60
µs
µs
(Latch mode)
DRN1 - DRN8
Overcurrent Switch Off
Delay
DI = ACFFh, DI = AA00h
SRC1 – SRC8 = GND
TdelDRN1-8
(Low Side)
SRC1 - SRC8
Overcurrent Switch Off
Delay
DI = ACFFh, DI = AA00h
DRN1 – DRN8 = Vb
TdelSRC1-8
10
60
µs
(High Side)
Restart time after
overcurrent switch off
Time (Int)
Tres
DI = ACFFh, DI = AA00h
120
450
ms
Slew Rate
Turn On
Outputs loaded per Figure 5
See Figure 2
Drn1-8htol
Drn1-8ltoh
0.65
0.5
1.95
1.5
V/µs
V/µs
Turn Off (Low Side)
See Figure 2
13/33
Electrical performance characteristics
L9733
Units
Table 6.
Symbol
AC Characteristics (continued)
Parameter
Conditions
Min
Typ
Max
Slew Rate
Turn On
Outputs loaded per Figure 5
See Figure 2
SRC1-8htol
0.65
0.5
1.95
1.5
V/µs
V/µs
SRC1-8ltoh Turn Off (High Side)
See Figure 2
Outputs loaded per Figure 5
See Figure 2
Delay time
Drn1-8tondly
Turn On
2
20
µs
µs
Drn1-8toffdly Turn Off (Low Side)
10
100
See Figure 2
Delay time
SRC1-8tondly
Outputs loaded per Figure 5
See Figure 2
Figure 2
2
Turn On
20
µs
µs
SRC1-8toffdly Turn Off (High Side)
10
100
See Figure 2
Drn1-8offon Delay Delta
SRC1-8offon Delay Delta
Drn1-8toffdly - Drn1-8tondly
SRC1-8toffdly - SRC1-8tondly
10
10
60
60
µs
µs
Figure 2.
Output Turn On/Off Delays and Slew Rates
6-8
IN
IN 6-8
-
90%
20%
90%
20%
DRN1-8
LSD
HSD
DRN1-8
DRN1-8ltoh
DRN1-8htol
DRN1-8toffdly
DRN1-8tondly
80%
10%
80%
10%
SRC1-8
SRC1-8
SRC1-8htol
SRC1-8toffdly
SRC1-8ltoh
SRC1-8tondly
IN1- 5 are available on wafer only
14/33
L9733
Electrical performance characteristics
3.3
SPI Characteristics and timings
Tamb= -40 to 125°C, Vdd = 4.5 to 5.5 Vdc, Vbat = 4.5 to 18Vdc, unless otherwise specified
Table 7.
SPI Characteristics and timings
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DINCin
20
20
pF
pF
Input Capacitance
SCLKCin
50 pF from DO to Ground
Output Data (DO)
Rise Time
DOrise
DOfall
70
ns
ns
See Figure 4
Output Data (DO)
Fall Time
Figure
5
See Figure 4
70
DOa
DOsum
DOhm
Access Time
Set Up Time
Hold Time
See Figure 5
See Figure 5
See Figure 5
350
ns
ns
ns
20
10
Output Data (DO)
Disable Time
DOdis
No Capacitor on DO, See Figure 4
400
20
ns
tthFilt
Filter Time
All Fault bits are “Set”
5
µs
ns
ns
ns
ns
ns
SCLKwid
SCLKlm
SCLKhm
SCLKrise
SCLKfall
SCLK Width
See Figure 4, @ fSCLK = 5.4MHz(1)
See Figure 4, @ fSCLK = 5.4MHz(1)
See Figure 4, @ fSCLK = 5.4MHz(1)
See Figure 4, @ fSCLK = 5.4MHz(1)
See Figure 4, @ fSCLK = 5.4MHz(1)
185
58
SCLK Low Time
SCLK High Time
SCLK Rise Time
SCLK Fall Time
58
21
21
Channel Select (CS)
Rise Time
CSrise
CSfall
CSlead
CSlag
DIrise
DIfall
See Figure 4(1)
See Figure 4(1)
100
100
ns
ns
Channel Select (CS)
Fall Time
Channel Select (CS)
Lead Time
(1)
See Figure 5
165
50
Channel Select (CS)
Lag Time
(1)
See Figure 5
Input Data (DI)
Rise Time
See Figure 4, @ fSCLK = 5.4MHz(1)
30
30
ns
ns
Input Data (DI)
Fall Time
See Figure 4, 5,
@ fSCLK = 5.4MHz(1)
Input Data (DI)
Set-up Time
DIsus
DIhs
See Figure 5, @ fSCLK = 5.4MHz(1)
See Figure 5, @ fSCLK = 5.4MHz(1)
15
10
Input Data (DI)
Hold Time
1. Guaranteed by design
15/33
Electrical performance characteristics
Figure 3. DO Loading for Disable Time Measurement
L9733
+5 V
Vcc
4.0 V
DOdis
DO
1 k
1 k
Ω
Ω
1.0 V
DO
0 V
CS
Figure 4.
SPI Input/Output Slew Rate
SCLKwid
SCLKlm
SCLKhm
90%
10%
SCLKrise
SCLK
CLKfall
S
90%
90%
CS
DI
CSrise
CSfall
90%
DIrise
DIfall
10%
10%
DO
DOrise
DOfall
10%
Figure 5.
SPI Timing Diagram
CS
CSlead
CSlag
SCLK
DOa
DOhm
DOsum
DOdis
DO
FAULT LSB
FAULT MSB
DI
DI
DI LSB
DIsus
DI MSB
DIhs
16/33
L9733
Functional description
4
Functional description
L9733 integrates 8 self-configuring outputs (OUT1-8) which are able to drive either
incandescent lamps, inductive loads (non-pwm'd, in pwm is necessary an external diode to
reduce flyback power dissipation), or resistive loads biased to Vbat ( low side configuration)
or to GND (high side configuration). These outputs can be enabled and disabled via the SPI
bus. Each of these outputs has a short circuit protection (with 0.8-2.4 Amps threshold)
selectable via SPI bus between a filtered switching OFF overcurrent protection or a linear
current limitation (default condition after power ON is switching OFF protection enabled).
An over-temperature protection as described in Section 2.1 is available for each outputs.
When a high side configured output is commanded OFF after having been commanded ON,
the source voltage will go to (VGND - 15V). This is due to the design of the circuitry and the
transconductance of the MOSFET. When a low side configured output is commanded OFF
after having been commanded ON, the output voltage will rise to the internal zener clamp
voltage (50 VDC minimum) due to the flyback of the inductive load.
Outputs 1-8 are able to drive any combination of inductive loads or lamps at one time.
Inductive loads for the L9733 can range from 35mH to a maximum of 325mH. The
recommended worst-case solenoid loads (at -40°C) are calculated using a minimum
resistance of 40Ω for each output. The maximum single pulse inductive load energy the
L9733 outputs is able to be safely handle is 20mJ at -40°C to 125°C (Worst-case load of
325mH & 40Ω).
4.1
Configurations for Outputs 1-8
The drain and source pins for each Output must be connected in one of the two following
configurations (see Figure 6).
4.1.1
Low Side Drivers
When any combination of Outputs 1-8 are connected in a low side drive configuration the
source of the applicable Output (Src1-8) shall be connected to ground. The drain of the
applicable Output (Drn1-8) shall be connected to the low side of the load.
4.1.2
High Side Drivers
When any combination of Outputs 1-8 are connected in a high side drive configuration the
Drain of the applicable Output (Drn1-8) shall be connected to Vbat. The source of the
applicable Output (Src1-8) shall be connected to the high side of the load.
4.2
Outputs 1-5
These five outputs can be used as either high or low side drives. The room temperature
Rdson of these outputs is 0.7Ω. A current limited (100µA max) voltage generator is
connected to Src 1-5 for open load and short to GND detection when a low side configured
output is commanded OFF. Another current limited (100µA max if VDrn 1-5 > 60%Vbat,
280µA max if VDrn 1-5 < 60%Vbat) voltage generator is connected to Drn 1-5 for open load
and short to Vbat detection when a high side configured output is commanded OFF.
Drain pins of Outputs 1-5 (Drn1-5) are connected to the drains of the N channel MOSFET
17/33
Functional description
L9733
transistors. Source pins of Outputs 1-5 (Src1-5) are connected to the sources of the N
channel MOSFET transistors.
4.3
Outputs 6-8
These three self-configuring outputs can be used to drive either high or low side loads. In
addition to being controlled by the SPI BUS these outputs can also be enabled and disabled
via the IN6 & IN7& IN8 inputs. The IN6, IN7 and IN8 inputs are logically or'd with the SPI
commands to allow either the IN6 & IN7 & IN8 inputs or the SPI commands to activate these
outputs. The use of the IN6 & IN7 & IN8 pins for PWM control on these outputs should only
be done with non-inductive loads if an external flyback diode is not present. The room
temperature Rdson of these four outputs is 0.7Ω. A current limited (100µA max) voltage
generator is connected to Src 6-8 for open load and short to GND detection when a low side
configured output is commanded OFF. Another current limited (100µA max if VDrn 6-8 >
60%Vbat, 280µA max if VDrn 6-8 < 60%Vbat) voltage generator is connected to Drn 6-8 for
open load and short to Vbat detection when a high side configured output is commanded
OFF.
Drain pins of Outputs 6-8 (Drn6-8) are connected to the drains of the N channel MOSFET
transistors. Source pins of Outputs 6-8 (Src6-8) are connected to the sources of the N
channel MOSFET transistors.
4.4
Drn1-8 Susceptibility To Negative Voltage Transients
All outputs connected in the low side configuration must have a ceramic chip capacitor of
0.01µF to 0.1µF connected from drain to ground. This is needed to prevent potential
problems with the device operation due to the presence of fast negative transient(s) on the
drain(s) of the device. Adequate de-coupling capacitors from the Drain (VBAT) to ground
shall be provided for high side configured outputs.
4.5
Supply pins
4.5.1
Main Power Input (Vdd)
An external +5.0 0.5 VDC supply provided from an external source is the primary power
source to the L9733. This supply is used as the power source for all of its internal logic
circuitry and other miscellaneous functions.
4.5.2
4.5.3
Battery supply (Vbat)
This input is the supply for the on board charge pump. This input shall be connected directly
to battery. If this input is not connected to the same supply, without additional voltage drops,
of the drains of any high side connected outputs, then the Rdson of that given output will be
higher than the specified maximum.
Discrete Inputs Voltage Supply (VDO)
This pin is used to supply the discrete input stages of L9733 and must be connected to the
same voltage used to supply the peripherals of the processor interfaced to L9733.
18/33
L9733
Functional description
4.6
Discrete inputs
4.6.1
Output 6-8 Enable Input (In6, ln7, ln8)
This input allows Output 6 (or Output 7, or Output 8) to be enabled via this external pin
without the use of the SPI. The SPI command and the In6-7 input are logically or'd together.
A logic "1" on this input (In6, ln7 or ln8) will enable this output no matter what the status of
the SPI command register. A logic "0" on this input will disable this output if the SPI
command register is not commanding this output on. This pins (In6, ln7 or ln8) can be left
"open" if the internal output device is being controlled only via the SPI. This input has a
nominal 100kΩ resistor connected from this pin to ground, which will pull this pin to ground if
an open circuit condition occur. This input is ideally suited for non-inductive loads that are
pulse width modulated (PWM'd). This allows PWM control without the use of the SPI inputs.
4.6.2
Reset Input (RES)
When this input goes low it resets all the internal registers and switches off all the output
stages. This input has a nominal 100 kΩ resistor connected from this pin to VDD, which will
pull this pin to VDD if an open circuit condition occur.
19/33
Serial Peripheral Interface (SPI)
L9733
5
Serial Peripheral Interface (SPI)
The L9733 has a serial peripheral interface consisting of Serial Clock (SCLK), Data Out
(DO), Data In (DI), and Chip Select (CS). All outputs will be controlled via the SPI. The input
pins CS, SCLK, and DI, thanks to VDO pin, have level input voltages allowing proper
operation from microcontrollers that are using 5.0 or 3.3 volts for their Vdd supply. The
design of the L9733 allows a "daisy-chaining" of multiple L9733's to further reduce the need
for controller pins.
5.1
Serial Data Output (DO)
This output pin is in a tri-state condition when CS is a logic '1'. When CS is a logic '0', this
pin transmits 16 bits of data from the fault register to the digital controller. After the first 16
bits of DO fault data are transmitted (after a CS transition from a logic '1' to a logic '0'), then
the DO output sequentially transmits the digital data that was just received (16 SCLK cycles
earlier) on the DI pin. The DO output continues to transmit the 16 SCLK delayed bit data
from the DI input until CS eventually transitions from a logic '0' to a logic '1'. DO data
changes state 10 nsec or later, after the falling edge of SCLK. The LSB is the first bit of the
byte transmitted on DO and the MSB is the last bit of the byte transmitted on DO, once CS
transitions from a logic '1' to a logic '0'.
5.2
Serial Data Input (DI)
This input takes data from the digital controller while CS is low. The L9733 accepts an 16 bit
byte to command the outputs on or off. The L9733 also serially wraps around the DI input
bits to the DO output after the DO output transmits its 16 fault flag bits. The LSB is the first
bit of each byte received on DI and the MSB is the last bit of each byte received on DI, once
CS transitions from a logic '1' to a logic '0'. The last 4 bits (b15-b12) of the first 16 bit byte
are used as key-word. The 4 bits (b11-b8) of the first 16 bits byte are used to select writing
mode between OUT8-1 status and diagnosis operating mode . The DI input has a nominal
100 kΩ resistor connected from this pin to the VDO pin, which pulls this pin to VDO if an
open circuit condition occurs.
5.3
Chip Select (CS)
This is the chip select input pin. On the falling edge of CS, the DO pin is released from tri-
state mode. While CS is low, register data are shifted in and shifted out the DI pin and DO
pin, respectively, on each subsequent SCLK. On the rising edge of CS, the DO pin is tri-
stated and the fault register is "Cleared" if a valid DI byte has been received. A valid DI byte
is defined as such:
–
–
1 A multiple of 16 bits was received.
2 A valid key-word was received
The fault data is not cleared unless all of the 2 previous conditions have been met. The CS
input has a nominal 100kΩ resistor connected from this pin to the VDO pin, which pulls this
pin to VDO if an open circuit condition occurs.
20/33
L9733
Serial Peripheral Interface (SPI)
5.4
Serial Clock (SCLK)
This is the clock signal input for synchronization of serial data transfer. DI data is shifted into
the DI input on the rising edge of SCLK and DO data changes on the falling edge of SCLK.
The SCLK input has a nominal 100kΩ resistor connected from this pin to the VDO pin,
which pulls this pin to VDO if an open circuit condition occurs.
5.5
Initial Input Command Register & Fault Register SPI Cycle
After initial application of Vdd to the L9733, the input command register and the fault register
are "Cleared" by the POR circuitry and that means that the default condition for the output
status is Off , the default diagnostic mode is No Latch and the switching OFF overcurrent
protection is enable. During the initial SPI cycle, and all subsequent cycles, valid fault data
will be clocked out of DO (fault bits).
5.6
Input Command Register
An input byte (16 bits) is routed to the Command Register. The content of this Command
Register is given in table 9. Additional DI data will continue to be wrapped around to the DO
pin. If CS should happen to go high before complete reception of the current byte, this just
transmitted byte shall be ignored (invalid).
Table 8.
Bit Command Register Definition
Key Word
Writing Mode: Output
Output Status
MSB
LSB
OUT 8 OUT 7 OUT 6 OUT 5 OUT 4 OUT 3 OUT 2 OUT 1
1
0
1
0
1
1
0
0
b15 b14 b13
b12
b11 b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Key Word
MSB
Writing Mode: Diag
Driver Diag Mode
LSB
1
0
1
0
0
0
1
1
Diag 8 Diag 7 Diag 6 Diag 5 Diag 4 Diag 3 Diag 2 Diag 1
b15 b14 b13
b12
b11 b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Key Word
MSB
Writing Mode: Protect
Driver Overcurrent Protection
LSB
1
0
1
0
1
0
1
0
Ilim 8 Ilim 7 Ilim 6 Ilim 5 Ilim 4 Ilim 3 Ilim 2 Ilim 1
b15 b14 b13
b12
b11 b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
21/33
Serial Peripheral Interface (SPI)
L9733
Table 9.
BIT
Command Register Logic Definition
STATE
STATUS
Writing Mode
b0-b7
b0-b7
b0-b7
b0-b7
b0-b7
b0-b7
0
1
0
1
0
1
OUT1 - OUT8 are Commanded Off
Output
Output
OUT1 - OUT8 are Commanded On
OUT1 - OUT8 Diagnostic is No Latch Mode
OUT1 - OUT8 Diagnostic is Latch Mode
OUT1 - OUT8 Switching OFF Overcurrent Protection
OUT1 - OUT8 Linear Overcurrent Protection
Diag
Diag
Protection
Protection
22/33
L9733
Other L9733 Features
6
Other L9733 Features
6.1
Charge Pump Usage
In order to provide low Rdson values when connected in a high side configuration, a charge
pump to drive the internal gate voltage(s) above Vbat is implemented. The charge pump
used on the L9733 doesn't need external capacitor. The L9733 uses a common charge
pump and oscillator for all the 8 configurable output channels. The charge pump uses the
Vbat supply connected directly to the Vb pin. The normal range of the Vbat voltage is 10 to
18V18V. However, the L9733 is functional with Vbat voltages as low as 4.5V DC with
eventually a degradation of Rdson.
The frequency range of this charge pump is from 3.6 to to 7.6 MHz. The frequency is above
1.8MHz in order to be above the AM radio band and below 8.0MHz so that harmonics do not
get within the FM radio band.
6.2
6.3
Waveshaping
Both the turn on and the turn off slew rates on all outputs (OUT1-8) are limited to between
10µs and 100µs for both rise and fall times (10 to 90%, and vice versa), to reduce conducted
EMC energy in the vehicle's wiring harness. The characteristics of the turn-on and turn-off
voltage is linear, with no discontinuities, during the output driver state transition.
POR Register Initialization
When the L9733 wakes up, the Vdd supply to the L9733 is allowed from 0 to 5 VDC in 0.3 to
3ms. The L9733 has a POR circuit, which monitors the Vdd voltage. When the Vdd voltage
reaches an internal threshold, and remains above this trip level for at least 5 to 20µs, the
Command and Fault registers are "cleared". Before Vdd reaches this trip level, none of the
eight outputs are allowed to momentarily glitch on.
6.4
Thermal Shutdown
Each of the eight outputs has independent thermal protection circuitry that disables each
output driver once the local N-Channel MOSFET's device temperature reaches between
+151 and +200°C. A filter is present to validate the thermal fault (5µs to 20µs). There is a 5
to 15°C hysteresis between the enable and disable temperature levels. The faulted channel
will periodically turn off and on until the fault condition is cleared, the ambient temperature is
decreased sufficiently or the output is commanded off. If a thermal shutdown, of one or
more output drivers, is active during the falling edge of the chip select (CS) signal all the bits
of the Fault Register are "setted" to "1" (thermal shutdown is not latched and could be read
only in the moment it is present). The thermal fault is cleared on the rising edge of Chip
Select if a valid DI byte was received.
Note:
Due to the design of the L9733 each output's thermal limit "may not" be truly independent to
the extent that if one output is shorted, it may impact the operation of other outputs (due to
lateral heating in the die).
23/33
Fault Operation
L9733
7
Fault Operation
The fault diagnostic capability consists of one internal 16 bits shift register and 2 bits are
used for each output. The diagnostic information are: no fault present, overcurrent, open
load and short circuit.
All of the faults will be cleared on the rising edge of Chip Select if a valid DI byte was
received
Table 10. Fault Register Definition
OUT 8 OUT 7 OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
LSB
MSB
D1
D0
D1
D0
D1
D0
D1
b9
D0
b8
D1
D0
b6
D1
b5
D0
b4
D1
b3
D0
b2
D1
b1
D0
b0
b15
b14
b13 b12 b11 b10
b7
Table 11. Fault Logic Definition
D1
D0
FAULT STATUS
0
0
1
1
0
1
0
1
No fault is present
Open load
Short circuit to GND (low side) or Short circuit to Vbat(high side)
Overcurrent
If all the bits b0-b15 of the fault register have value '1' it means that a thermal fault, at least
on one of the eight independent Outputs, occurred.
7.1
Low Side Configured Output Fault Operation
The diagnostic circuitry verifies for the low side configured output the following condition:
Normal operation, open load, short circuit to GND and overcurrent (only if the switching OFF
protection, selectable for each channel via SPI bus, is active).
The diagnostic circuitry operates in two different modes, selected for each channel by SPI:
no latch mode and latch mode. The fault priority is overcurrent and then open load or short
circuit to GND, this means that if an overcurrent occurs the fault register is always
overwritten and following open load or short to GND faults that happen before that the
register is cleared will be ignored.
7.1.1
No latch mode
This diagnostic operating mode doesn't latch open load and short to GND faults.
1. Open load
The diagnostic of open load is detected only in OFF condition sensing the Drn1-8
output voltage. This fault is detected on the falling edge of the CS input if the power
drain voltage is inside the voltage range limited by the two thresholds Vth_Vbat and
24/33
L9733
Fault Operation
Vth_GND. An internal current limited voltage regulator fixes the drain voltage inside
the described range when no load is connected.
2. Short Circuit to GND
The diagnostic of short circuit to GND is detected only in OFF condition sensing the
Drn1-8 output voltage. This fault is detected on the falling edge of the CS input if the
power drain voltage is lower than the Vth_GND threshold.
3. Overcurrent
The diagnostic of overcurrent is detected only in ON condition, if the switching OFF
protection of the channel is enabled (default), sensing the current level of the output
power transistor. If the output current has been above the short threshold Iovc for the
filtering time Tdel the output power is switched off and at the same time an overcurrent
fault is written in the fault register.
There are three possibilities to restart one output after the fault has occourred:
–
–
Automatically after a time Tres
On the rising edge of CS if two valid DI byte has been received and first the Output
Status in the command register is written with logic '0' and then with a logic “1” in
the following SPI cycle
–
–
On the rising edge (low to high transition) at the corresponding parallel input pin
(only for Outputs 6-8).
If the switching OFF protection is not active the On phase overcurrent protection is
a linear current limitation and no diagnosis is available.
The use of the IN6-8 pins for PWM control on the outputs 6-8 could generates bad
diagnostic behavior when the falling edge of CS happens a short time after the falling edge
of IN6-8 during the power MOS transient. Software filtering may be needed to ignore fault
signals during Drn6-8 transient after falling edge of IN6-8.
7.1.2
Latch mode
This diagnostic operating mode latches all faults when they happen.
1. Open load
The diagnostic of open load is detected only in OFF condition sensing the Drn1-8
output voltage. This fault is detected if the power drain voltage is inside the voltage
range limited by the two thresholds Vth_Vbat and Vth_GND for the filtering time Tfilt.
An internal current limited voltage regulator fixes the drain voltage inside the described
range when no load is connected.
2. Short Circuit to GND
The diagnostic of short circuit to GND is detected only in OFF condition sensing the
Drn1-8 output voltage. This fault is detected if the power drain voltage is lower than the
Vth_GND threshold for the filtering time Tfilt.
3. Overcurrent
The diagnostic of overcurrent is detected only in ON condition, if the switching OFF
protection of the channel is enabled (default), sensing the current level of the output
power transistor. If the output current has been above the short threshold Iovc for the
filtering time Tdel the output power is switched off and at the same time an overcurrent
fault is written in the fault register. If the switching OFF protection is not active the On
25/33
Fault Operation
L9733
phase overcurrent protection is a linear current limitation and no diagnosis is available.
There are three possibilities to restart one output after the fault has occourred:
–
–
Automatically after a time Tres
On the rising edge of CS if two valid DI byte has been received and first the Output
Status in the command register is written with logic '0' and then with a logic “1” in
the following SPI cycle
–
On the rising edge (low to high transition) at the corresponding parallel input pin
(only for Outputs 6-8).
If the power MOS transient, after a switching-off command, is longer than Tdel
filtering time, a bad diagnostic behavior happens and software filtering may be
needed.
7.2
High Side Configured Output Fault Operation
The diagnostic circuitry verifies for the high side configured output the following condition:
Normal operation, open load, short circuit to Vbat and overcurrent (only if the switching OFF
protection, selectable for each channel via SPI bus, is active).
The diagnostic circuitry operates in two different modes, selected for each channel by SPI:
no latch mode and latch mode. The fault priority is overcurrent and then open load or short
circuit to Vb, this means that if an overcurrent occurs the fault register is always overwritten
and following open load or short to Vbat faults that happen before that the register is cleared
will be ignored.
7.2.1
No latch mode
This diagnostic operating mode doesn't latch open load and short to Vbat faults.
1. Open load
The diagnostic of open load is detected only in OFF condition sensing the Src1-8
output voltage. This fault is detected on the falling edge of the CS input if the power
drain voltage is inside the voltage range limited by the two thresholds Vth_Vbat and
Vth_GND. An internal current limited voltage regulator fixes the drain voltage inside the
described range when no load is connected.
2. Short Circuit to Vb
The diagnostic of short circuit to Vbat is detected only in OFF condition sensing the
Src1-8 output voltage. This fault is detected on the falling edge of the CS input if the
power drain voltage is higher than the Vth_Vbat threshold.
3. Overcurrent
The diagnostic of overcurrent is detected only in ON condition, if the switching OFF
protection of the channel is enabled (default),sensing the current level of the output
power transistor. If the output current has been above the short threshold Iovc for the
filtering time Tdel the output power is switched off and at the same time an overcurrent
26/33
L9733
Fault Operation
fault is written in the fault register.
There are three possibilities to restart one output after the fault has occourred:
–
–
Automatically after a time Tres
On the rising edge of CS if two valid DI byte has been received and first the Output
Status in the command register is written with logic '0' and then with a logic “1” in
the following SPI cycle
–
–
On the rising edge (low to high transition) at the corresponding parallel input pin
(only for Outputs 6-8).
If the switching OFF protection is not active the On phase overcurrent protection is
a linear current limitation and no diagnosis is available.
The use of the IN6-8 pins for PWM control on the outputs 6-8 could generates bad
diagnostic behavior when the falling edge of CS happens a short time after the
falling edge of IN6-8 during the power MOS transient. Software filtering may be
needed to ignore fault signals during Drn6-8 transient after falling edge of IN6-8.
7.2.2
Latch mode
This diagnostic operating mode latches all faults when they happen.
1. Open load
The diagnostic of open load is detected only in OFF condition sensing the Src1-8
output voltage. This fault is detected if the power drain voltage is inside the voltage
range limited by the two thresholds Vth_Vbat and Vth_GND for the filtering time Tfilt.
An internal current limited voltage regulator fixes the drain voltage inside the described
range when no load is connected.
2. Short Circuit to Vb
The diagnostic of short circuit to Vbat is detected only in OFF condition sensing the
Src1-8 output voltage. This fault is detected if the power drain voltage is higher than the
Vth_Vbat threshold for the filtering time Tfilt.
3. Overcurrent
The diagnostic of overcurrent is detected only in ON condition, if the switching OFF
protection of the channel is enabled (default), sensing the current level of the output
power transistor. If the output current has been above the short threshold Iovc for the
filtering time Tdel the output power is switched off and at the same time an overcurrent
fault is written in the fault register.
There are three possibilities to restart one output after the fault has occourred:
–
–
Automatically after a time Tres
On the rising edge of CS if two valid DI byte has been received and first the Output
Status in the command register is written with logic '0' and then with a logic “1” in
the following SPI cycle
–
On the rising edge (low to high transition) at the corresponding parallel input pin
(only for Outputs 6-8).
If the switching OFF protection is not active the On phase overcurrent protection is
a linear current limitation and no diagnosis is available.
If the power MOS transient, after a switching-off command, is longer than Tdel filtering time,
a bad diagnostic behavior happens and software filtering may be needed.
27/33
Fault Operation
L9733
Figure 6.
L9733 Application schematic
VDD
RES
8 HIGH/LOW SIDE DRIVER
VBAT
SCLK
DI
DRN[x]
DO
High Side Driver
Configuration
CS
SRC[x]
DRN[x]
SRC[x]
VDO
IN6
IN7
IN8
Low Side Driver
Configuration
To driver 6
To driver 7
To driver 8
GND
Figure 7.
L9733 HVAC applicative examples
Vbatt
Vbatt
M
SM
SM
SM
SM
M
M
L9733
L9733
Stall sense
4 channels configured to low- and 4 channels
configured to high side build a quad half bridge.
This allows to drive 3 DC-motors in sequential ly.
Four flap motors become sequentially driven. Unipolar stepper motor are
selected by 4 high-side configured switches. If the decoupling diodes are inside
the motor housing, only 8 wires are needed to drive this arrangement.
28/33
L9733
Fault Operation
Figure 8.
L9733 Powertrain applicative examples
Vbatt
Vbatt
Tach-Out
(PWM)
Starter Relay
Key-On Relay
A/C Fan Relay
Power Latch Relay
A/C Compressor Relay
Canister Purge Relay
(opt PWM)
Air Pump Relay
MIL Lamp
Water Lamp
SM
Idle Speed Control
Fuel Pump Relay
(opt PWM)
L9733
L9733
Coolant Fan Relay
Main Relays and Lamps Driving
Idle speed stepper motor driving and auxiliary loads
29/33
Package informations
L9733
8
Package informations
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 9.
SO28 Mechanical Data & Package Dimensions
mm
inch
DIM.
OUTLINE AND
MECHANICAL DATA
MIN. TYP. MAX. MIN. TYP. MAX.
A
a1
b
2.65
0.3
0.104
0.012
0.019
0.013
0.1
0.004
0.35
0.23
0.49 0.014
0.32 0.009
b1
C
0.5
0.020
c1
D
45° (typ.)
17.7
10
18.1 0.697
10.65 0.394
0.713
0.419
E
e
1.27
0.050
0.65
e3
F
16.51
7.4
0.4
7.6
0.291
0.299
0.050
L
1.27 0.016
SO-28
S
8 ° (max.)
30/33
L9733
Package informations
Figure 10. PowerSSO28 Mechanical Data & Package Dimensions
mm
inch
TYP. MAX.
0.097
DIM.
MIN.
2.15
2.15
0
0.18
0.23
10.10
TYP. MAX. MIN.
2.47 0.084
2.40 0.084
OUTLINE AND
MECHANICAL DATA
A
A2
a1
b
0.094
0.003
0.014
0.012
0.075
0
0.36 0.007
0.32 0.009
10.50 0.398
c
(1)
0.413
D
(1)
E
7.4
7.6
0.291
0.299
e
e3
F
G
G1
H
h
0.65
8.45
2.3
0.025
0.033
0.090
0.004
0.002
0.413
0.016
5˚
0.033
0.169
10˚
0.047
0.031
0.114
0.144
0.039
0.190
0.283
0.10
0.06
10.50 0.398
0.40
10.10
0.55
k
L
5˚
0.85 0.022
10˚
M
N
O
Q
S
T
U
X
4.3
1.2
0.8
2.9
3.65
1.0
PowerSSO-28
(exposed-pad)
4.2
6.6
4.8
7.2
0.165
0.260
Y
(1) "D" and "E" do not include mold flash or protrusions Mold flash
or protrusions shall not exceed 0.15 mm per side(0.006")
h x 45û
C
LEAD COMPLANARITY
G
A
D
e
Y
Q
BOTTOM VIEW
B
M
M
0.1
A B
b
e3
7633868 A
31/33
Revision history
L9733
9
Revision history
Table 12. Document revision history
Date
Revision
Changes
13-Apr-2005
15-Jun-2006
08-Aug-06
1
2
3
Initial release.
Changed only look and fill.
Modified Table 8: Bit Command Register Definition on page 21
32/33
L9733
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