LNBP21PD-TR [STMICROELECTRONICS]

LNBP SUPPLY AND CONTROL IC WITH STEP-UP CONVERTER AND I2C INTERFACE; LNBP电源和控制IC与升压转换器和I2C接口


型号：	LNBP21PD-TR
厂家：	ST
描述：	LNBP SUPPLY AND CONTROL IC WITH STEP-UP CONVERTER AND I2C INTERFACE LNBP电源和控制IC与升压转换器和I2C接口转换器稳压器开关式稳压器或控制器电源电路开关式控制器光电二极管升压转换器
文件：	总20页 (文件大小：695K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LNBP21

LNBP SUPPLY AND CONTROL IC WITH

STEP-UP CONVERTER AND I C INTERFACE

■

COMPLETE INTERFACE BETWEEN LNB

AND I2CTM BUS

BUILT-IN DC/DC CONTROLLER FOR

SINGLE 12V SUPPLY OPERATION

ACCURATE BUILT-IN 22KHz TONE

OSCILLATOR

■

SUITS WIDELY ACCEPTED STANDARDS

PowerSO-20

SO-20

FAST OSCILLATOR START-UP FACILITATES

DiSEqCTM ENCODING

■

BUILT-IN 22KHz TONE DETECTOR

SUPPORTS BI-DIRECTIONAL DiSEqCTM

LOOP-THROUGH FUNCTION FOR SLAVE

OPERATION

LNB SHORT CIRCUIT PROTECTION AND

DIAGNOSTIC

DESCRIPTION

Intended for analog and digital satellite STB

receivers/SatTV, sets/PC cards, the LNBP21 is a

monolithic voltage regulator and interface IC,

assembled in SO-20 and PowerSO-20,

specifically designed to provide the power and the

13/18V, 22KHz tone signalling to the LNB

■

CABLE LENGTH DIGITAL COMPENSATION

INTERNAL OVER TEMPERATURE

PROTECTION

■

ESD RATING 4KV ON POWER

INPUT-OUTPUT PINS

SCHEMATIC DIAGRAM

LNBP21

Gate

LT1

LT2

OUT

Sense

Feedback

Step-up

Controller

Vup

Vcc

Preregul.+

U.V.lockout

+P.ON res.

Enable

Linear Post-reg

+Modulator

I Select

Byp

+Protections

V Select

EXTM

SDA

SCL

Diagnostics

I²C

interf.

DETIN

Tone

Detector

22KHz

Oscill.

ADDR

DSQIN

DSQOUT

October 2002

1/20

LNBP21

downconverter in the antenna or to the multiswitch

box. In this application field, it offers a complete

solution with extremely low component count, low

power dissipation together with simple design and

capaci-tor must be used to couple the modulating

signal source to the EXTM pin. When external

modulation is not used, the relevant pin can be left

open.

I CTM standard interfac-ing.

The current limitation block has two thresholds

that can be selected by the I

bit of the SR; the

This IC has a built in DC/DC step-up controller

that, from a single supply source ranging from 8 to

15V, generates the voltages that let the linear

post-regulator to work at a minimum dissipated

power. An UnderVoltage Lockout circuit will

SEL

lower threshold is between 400 and 550mA

(I =HIGH), while the higher threshold is

SEL

between 500 and 650mA (I

=LOW).

SEL

The current protection block is SOA type. This

limits the short circuit current (Isc) typically at

disable the whole circuit when the supplied V

drops below a fixed threshold (6.7V typically). The

internal 22KHz tone generator is factory trimmed

in accordance to the standards, and can be

200mA with I

=HIGH and at 300mA with

SEL

=LOW when the output port is connected to

SEL

ground.

controlled either by the I C

interface or by a

It is possible to set the Short Circuit Current

protection either statically (simple current clamp)

or dy-namically by the PCL bit of the SR; when

the PCL (Pulsed Current Limiting) bit is set to

LOW, the overcurrent protection circuit works

dynamically: as soon as an overload is detected,

the output is shut-down for a time t , typically

900ms. Simultaneously the OLF bit of the System

dedicated pin (DSQIN) that allows immediate

DiSEqC

data encoding (*). All the functions of

this IC are controlled via I C

bus by writing 6

bits on the System Register (SR, 8 bits) . The

same register can be read back, and two bits will

report the diagnostic status. When the IC is put in

Stand-by (EN bit LOW), the power blocks are

disabled and the loop-through switch between

LT1 and LT2 pins is closed, thus leaving all LNB

powering and control functions to the Master

Receiver (**). When the regulator blocks are

active (EN bit HIGH), the output can be logic

controlled to be 13 or 18 V (typ.) by mean of the

VSEL bit (Voltage SELect) for remote controlling

of non-DiSEqC LNBs. Additionally, it is possible

to increment by 1V (typ.) the selected voltage

value to compensate for the excess voltage drop

along the coaxial cable (LLC bit HIGH). In order to

minimise the power dissipation, the output voltage

of the internal step-up converter is adjusted to

allow the linear regulator to work at minimum

dropout. Another bit of the SR is addressed to the

remote control of non-DiSEqC LNBs: the TEN

(Tone ENable) bit. When it is set to HIGH, a

continuous 22KHz tone is generated regardless

of the DSQIN pin logic status. The TEN bit must

off

elapsed, the output is resumed for a time t =1/

10t (typ.). At the end of t , if the overload is still

off

detected, the protection circuit will cycle again

through Toff and Ton. At the end of a full Ton in

which no overload is detected, normal operation is

resumed and the OLF bit is reset to LOW. Typical

Ton+Toff time is 990ms and it is determined by an

internal timer. This dynamic operation can greatly

reduce the power dissipation in short circuit

condition, still ensuring excellent power-on start

up in most conditions (**) .

However, there could be some cases in which an

highly capacitive load on the output may cause a

difficult start-up when the dynamic protection is

chosen. This can be solved by initiating any power

start-up in static mode (PCL=HIGH) and then

switching to the dynamic mode (PCL=LOW) after

a chosen amount of time. When in static mode,

the OLF bit goes HIGH when the current clamp

limit is reached and returns LOW when the

overload condition is cleared.

be set LOW when the DSQIN pin is used for

DiSEqC

encoding. The fully bi-directional

interfacing is completed by the built-in

22KHz tone detector. Its input pin (DETIN) must

This IC is also protected against overheating:

when the junction temperature exceeds 150°C

(typ.), the step-up converter and the linear

regulator are shut off, the loop-trough switch is

opened, and the OTF bit of the SR is set to HIGH.

Normal operation is resumed and the OTF bit is

reset to LOW when the junction is cooled down to

140°C (typ.).

be AC coupled to the DiSEqC

bus, and the

extracted PWK data are available on the

DSQOUT pin (*).

In order to improve design flexibility and to allow

implementation of newcoming LNB remote control

standards, an analogic modulation input pin is

available (EXTM). An appropriate DC blocking

(*): External components are needed to comply to bi-directional DiSEqC bus hardware require-ments. Full compliance of the whole appli-

cation to DiSEqC specifications is not implied by the use of this IC.

(**): The current limitation circuit has no effect on the loop-through switch. When EN bit is LOW, the current flowing from LT1 to LT2 must

be externally limited.

2/20

LNBP21

ORDERING CODES

SO-20

(Tube)

SO-20

(Tape & Reel)

PowerSO-20

(Tube)

PowerSO-20

(Tape & Reel)

TYPE

LNBP21

LNBP21D2

LNBP21D2-TR

LNBP21PD

LNBP21PD-TR

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Value

Unit

DC Input Voltage

Output Current

, V

LT2

LT1

Internally Limited

-0.3 to 22

-0.3 to 7

DC Output Pin Voltage

Logic Input Voltage (SDA, SCL, DSQIN)

Detector Input Signal Amplitude

Logic High Output Voltage (DSQOUT)

Bypass Switch ON Current

Bypass Switch OFF Voltage

Gate Current

DETIN

900

±20

±400

GATE

Current Sense Voltage

-0.3 to 1

-0.3 to 7

-40 to +150

-40 to +125

SENSE

Address Pin Voltage

ADDRESS

Storage Temperature Range

Operating Junction Temperature Range

°C

stg

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is

not implied.

THERMAL DATA

Symbol

Parameter

Thermal Resistance Junction-case

SO-20

PowerSO-20 Unit

°C/W

thj-case

PIN CONFIGUARATION (top view)

SO-20

PowerSO-20

3/20

LNBP21

TABLE A: PIN CONFIGURATIONS

PIN NUMBER

vs PACKAGE

SYMBOL

NAME

FUNCTION

SO-20

PowerSO-20

Supply Input

8V to 15V supply. A 220µF bypass capacitor to

GND with a 470nF (ceramic) in parallel is

recommended

GATE Exrernal Switch Gate

SENSE Current Sense Input

External MOS switch Gate connection of the

step-up converter

Current Sense comparator input. Connected to

current sensing resistor

Step-up Voltage

Input of the linear post-regulator. The voltage on this

pin is monitored by internal step-ut controller to

keep a minimum dropout across the linear pass

transistor

OUT

Output Port

Output of the linear post regulator modulator to the

LNB. See truth table for voltage selections.

SDA

SCL

Serial Data

Serial Clock

Bidirectional data from/to I C bus.

Clock from I C bus.

DSQIN DiSEqC Input

When the TEN bit of the System Register is LOW,

this pin will accept the DiSEqC code from the main

µcontroller. The LNBP21 will use this code to

modulate the internally generated 22kHz carrier. Set

to GND thi pin if not used.

DETIN Detector In

22kHz Tone Detector Input. Must be AC coupled to

the DiSEcQ bus.

DSQOUT DiSEqC Output

Open collector output of the tone Detector to the

main µcontroller for DiSEcQ data decoding. It is

LOW when tone is detected.

EXTM Extrernal Modulator

External Modulation Input. Need DC decoupling to

the AC source. If not used, can be left open.

GND

Ground

Circuit Ground. It is internally connected to the die

frame for heat dissipation.

5, 6, 15, 16 1, 10, 11, 20

BYP

LT1

Bypass Capacitor

Needed for internal preregulator filtering

Loop Through Switch

In standby mode the power switch between LT1

and LT2 is closed. Max allowed current is 900mA.

this pin can be left open if loopthrough function is

not needed.

LT2

Loop Through Switch

Same as above

ADDR Address Setting

Four I C bus addresses available by setting the

Address Pin level voltage

4/20

LNBP21

TYPICAL APPLICATION CIRCUIT

D1 1N4001

IC1

Master STB

LT1

Vup

470nF

Ceramic

220µF

10nF

LT2

IC2

STS4DNFS30L

(Note 3)

270µH

to LNB

Gate

BAT43

10nF

15 ohm

LNBP21

see Note 2

Sense

Vcc

DETIN

(Note 1)

L1=22µH

10nF

0.1

Ω

(Note 4)

Byp

470nF

220µF

470nF

Ceramic

Vin

12V

EXTM

ADDRESS

DSQOUT

DSQIN(Note 1)

SCL

0<Vaddr<V

Byp

SDA

GND

(*) Set to GND if not used

(**) filter to be used according to EUTELSAT reccomendation to implement the DiSEqC 2.x, not needed if bidirectional DiSEqC 2.x is

not implemented (see DiSEqC implementation note)

(***) IC2 is a ST Fettky, STS4DNFS30L, that includes both the schottky diode and the N-Channel Mos-Fet, needed for the DC/DC converter,

in a So-8 package. It can be replaced by a schottky diode (STPS2L3A or similar) and a N-Channel Mos-Fet (STN4NF03L or similar)

I C BUS INTERFACE

Data transmission from main µP to the LNBP21

and viceversa takes place through the 2 wires I2C

bus interface, consisting of the two lines SDA and

SCL (pull-up resistors to positive supply voltage

must be externally connected).

ACKNOWLEDGE

The master (µP) puts a resistive HIGH level on the

SDA line during the acknowledge clock pulse (see

fig. 3). The peripheral (LNBP21) that

acknowledges has to pull-down (LOW) the SDA

line during the acknowledge clock pulse, so that

the SDA line is stable LOW during this clock pulse.

The peripheral which has been addressed has to

generate an acknowledge after the reception of

each byte, other-wise the SDA line remains at the

HIGH level during the ninth clock pulse time. In

this case the master transmitter can generate the

STOP information in order to abort the transfer.

The LNBP21 won't gen-erate the acknowledge if

the Vcc supply is below the Undervoltage Lockout

threshold (6.7V typ.).

DATA VALIDITY

As shown in fig. 1, the data on the SDA line must

be stable during the high period of the clock. The

HIGH and LOW state of the data line can only

change when the clock signal on the SCL line is

LOW.

START AND STOP CONDITIONS

As shown in fig.2 a start condition is a HIGH to

LOW transition of the SDA line while SCL is HIGH.

The stop condition is a LOW to HIGH transition of

the SDA line while SCL is HIGH. A STOP

condi-tions must be sent before each START

condition.

TRANSMISSION WITHOUT ACKNOWLEDGE

Avoiding to detect the acknowledge of the

LNBP21, the µP can use a simpler transmission:

simply it waits one clock without checking the

slave acknowledging, and sends the new data.

BYTE FORMAT

Every byte transferred to the SDA line must

contain 8 bits. Each byte must be followed by an

ac-knowledge bit. The MSB is transferred first.

This approach of course is less protected from

misworking and decreases the noise immunity.

5/20

LNBP21

Figure 1 : DATA VALIDITY ON THE I C BUS

Figure 2 : TIMING DIAGRAM ON I C BUS

Figure 3 : ACKNOWLEDGE ON I C BUS

6/20

LNBP21

LNBP1 SOFTWARE DESCRIPTION

INTERFACE PROTOCOL

The interface protocol comprises:

- A start condition (S)

- A chip address byte = hex 10 / 11 (the LSB bit

determines read(=1)/write(=0) transmission)

- A sequence of data (1 byte + acknowledge)

- A stop condition (P)

CHIP ADDRESS

DATA

MSB

LSB

MSB

LSB

R/W ACK

ACK

ACK= Acknowledge

S= Start

P= Stop

R/W= Read/Write

SYSTEM REGISTER (SR, 1 BYTE)

MSB

LSB

R, W

PCL

R, W

ISEL

R, W

TEN

R, W

LLC

R, W

VSEL

OTF

OLF

R,W= read and write bit

R= Read-only bit

All bits reset to 0 at Power-On

TRANSMITTED DATA (I C BUS WRITE MODE)

When the R/W bit in the chip address is set to 0,

the main µP can write on the System Register

the 8 available can be written by the µP, since the

re-maining 2 are left to the diagnostic flags, and

are read-only.

(SR) of the LNBP21 via I C bus. Only 6 bits out of

PCL ISEL TEN LLC VSEL EN

OTF OLF

Function

=13V, V =16V Loopthrough switch open

OUT

=18V, V =21V Loopthrough switch open

OUT

=14V, V =17V Loopthrough switch open

=19V, V =22V Loopthrough switch open

22KHz tone is controlled by DSQIN pin

22KHz tone is ON, DSQIN pin disabled

=500mA, I

=400mA, I

=650mA I =300mA

OUT(min)

OUT(max)

=550mA I =300mA

OUT(max)

Pulsed (dynamic) current limiting is selected

Static current limiting is selected

Power blocks disabled, Loopthrough switch closed

X= don't care.

Values are typical unless otherwise specified

RECEIVED DATA (I C bus READ MODE)

LNBP21 issues a byte on the SDA data bus line

(MSB transmitted first).

At the ninth clock bit the MCU master can:

- acknowledge the reception, starting in this way

the transmission of another byte from the

LNBP21;

The LNBP21 can provide to the Master a copy of

the SYSTEM REGISTER information via I2C bus

in read mode. The read mode is Master activated

by sending the chip address with R/W bit set to 1.

At the following master generated clocks bits, the

7/20

LNBP21

- no acknowledge, stopping the read mode

communication.

While the whole register is read back by the µP,

only the two read-only bits OLF and OTF convey

di-agnostic informations about the LNBP21.

PCL ISEL TEN LLC VSEL EN

OTF OLF

Function

T <140°C, normal operation

T >150°C, power block disabled, Loothrough switch open

These bits are read exactly the same as

they were left after last write operation

, normal operation

OUT OMAX

, overload protection triggered

OUT OMAX

Values are typical unless otherwise specified

POWER-ON I2C INTERFACE RESET

PWK data in accordance to the DiSEqC pro-tocol.

Full compliance of the system to the specification

is thus not implied by the bare use of the LNBP21.

The I2C interface built in the LNBP21 is

automatically reset at power-on. As long as the

Vcc stays be-low the UnderVoltage Lockout

threshold (6.7V typ.), the interface will not respond

to any I2C com-mand and the System Register

(SR) is initialised to all zeroes, thus keeping the

power blocks disabled. Once the Vcc rises above

7.3V, the I2C interface becomes operative and the

SR can be configured by the main µP. This is due

to About 500mV of hysteresis provided in the UVL

threshold to avoid false retriggering of the

Power-On reset circuit.

The system designer should also take in

consideration the bus hardware requirements,

that include the source impedance of the Master

Transmitter measured at 22KHz. To limit the

attenuation at car-rier frequency, this impedance

has to be 15ohm at 22KHz, dropping to zero ohm

at DC to allow the power flow towards the

peripherals. This can be simply accomplished by

the LR termination put on the OUT pin of the

LNBP, as shown in the Typical Application Circuit

on page 5.

DiSEqCTM IMPLEMENTATION

Unidirectional (1.x) DiSEqC and non-DiSEqC

systems normally don't need this termination, and

the OUT pin can be directly connected to the LNB

supply port of the Tuner. There is also no need of

Tone Decoding, thus, it is recommended to

connect the DETIN and DSQOUT pins to ground

to avoid EMI.

The LNBP21 helps the system designer to

implement the bi-directional (2.x) DiSEqC protocol

by al-lowing an easy PWK modulation/

demodulation of the 22KHz carrier. The PWK data

are exchanged between the LNBP21 and the

main µP using logic levels that are compatible with

both 3.3 and 5V mi-crocontrollers. This data

exchange is made through two dedicated pins,

DSQIN and DSQOUT, in or-der to maintain the

timing relationships between the PWK data and

the PWK modulation as accurate as possible.

These two pins should be directly connected to

two I/O pins of the µP, thus leaving to the resident

firmware the task of encoding and decoding the

ADDRESS PIN

Connecting this pin to GND the Chip I2C interface

address is 0001000, but, it is possible to choice

among 4 different addresses simply setting this

pin at 4 fixed voltage levels (see table on page

10).

ELECTRICAL CHARACTERISTICS FOR LNBP SERIES (T = 0 to 85°C, EN=1, LLC=0, TEN=0, ISEL=0,

PCL=0, DSQIN=0, V =12V, I

for I C access to the system register)

=50mA, unless otherwise specified. See software description section

OUT

Symbol

Parameter

Supply Voltage

Test Conditions

Min.

Typ.

Max.

Unit

= 500 mA TEN=VSEL=LLC=1

LT1 Input Voltage

Supply Current

LT1

= 0mA TEN=VSEL=LLC=1 EN=1

EN=0

2.5

Output Voltage

= 500 mA VSEL=1

LLC=0

LLC=1

17.3

18.7

8/20

LNBP21

Symbol

Parameter

Output Voltage

Test Conditions

= 500 mA VSEL=0

Min.

Typ.

Max.

Unit

LLC=0

12.5

13.5

LLC=1

∆V

Line Regulation

=15 to 18V

VSEL=0

VSEL=1

IN1

∆V

Load Regulation

VSEL=0 or 1 I

= 50 to 500mA

200

OUT

Output Current Limiting

ISEL=1

ISEL=0

ISEL=1

ISEL=0

400

500

550

650

MAX

Output Short Circuit Current

200

300

900

Dynamic Overload

protection OFF Time

PCL=0

Output Shorted

OFF

Dynamic Overload

protection ON Time

/10

OFF

Tone Frequency

TEN=1

0.55

0.9

KHz

Vpp

TONE

Tone Amplitude

0.72

TONE

Tone Duty Cycle

TONE

t , t

Tone Rise and Fall Time

External Modulation Gain

µs

∆V

/∆V ,

EXTM

f = 10Hz to 40KHz

EXTM

OUT

External Modulation Input

Voltage

AC Coupling

400

0.6

mVpp

Ω

External Modulation

Impedance

f = 10Hz to 50KHz

260

0.35

220

EXTM

Loopthrough Switch Voltage EN=0,

Drop (lt1 to LT2)

=300mA,

V =12 or 19V

DC/DC Converter Switch

Frequency

kHz

Vpp

kΩ

Tone Detector Frequency

Capture Range

0.4Vpp sinewave

=22kHz sinewave

DETIN

Tone Detector Input

Amplitude

0.2

1.5

DETIN

Tone Detector Input

Impedance

150

0.3

Overload Flag Pin Logic

LOW

Tone present

Tone absent

=2mA

0.5

Overload Flag Pin OFF

State Leakage Current

= 6V

µA

DSQIN Input Pin Logic

LOW

0.8

DSQIN Input Pin Logic

HIGH

DSQIN Pins Input Current

Output Backward Current

= 5V

-4

µA

°C

EN=0

= 18V

OBK

-10

OBK

Temperature Shutdown

Threshold

150

SHDN

∆T

Temperature Shutdown

Hysteresis

°C

SHDN

9/20

LNBP21

GATE AND SENSE ELECTRICAL CHARACTERISTICS (T = 0 to 85°C, V =12V)

Symbol

Parameter

Test Conditions

Min.

Typ.

4.5

Max.

Unit

Ω

Gate LOW R

=-100mA

DSON-L

DSON

GATE

Gate LOW R

=100mA

4.5

Ω

DSON-H

GATE

Current Limit Sense Voltage

200

SENSE

I C ELECTRICAL CHARACTERISTICS (T = 0 to 85°C, V =12V)

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

LOW Level Input Voltage

SDA, SCL

0.8

HIGH Level Input Voltage SDA, SCL

Input Current

SDA, SCL, V = 0.4 to 4.5v

-10

µA

DSQIN Input Pin Logic

LOW

SDA (open drain), I = 6mA

0.6

Maximum Clock Frequency SCL

500

KHz

MAX

ADDRESS PIN CHARACTERISTICS (T = 0 to 85°C, V =12V)

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

0.7

1.7

2.7

Unit

"0001000" Addr Pin Voltage

"0001001" Addr Pin Voltage

"0001010" Addr Pin Voltage

"0001011" Addr Pin Voltage

ADDR-1

1.3

2.3

3.3

ADDR-2

ADDR-3

ADDR-4

TEST CIRCUIT

1N4001

ILT

V_MI,V_OBK

Vup

LT1

10nF

STPS2L30A

470nF

STN4NF03L

220µF

Scope Probe

Load

Gate

LT2

, IOBK

L1=22µH

Sense

Rsc

0.1

Ω

OUT

IIN

Vin

LNBP21

Vcc

VOUT

20µF

220µF

470nF

EXTM

SDA

SCL

SDA

SCL

From I C

VEXTM, VDETIN

10nF

{

Master

DETIN

DSQIN

BYP

470nF

DSQOUT

Pulse Gen.

/ I

IOZ / IOL

ADDRESS

10/20

LNBP21

TYPICAL CHARACTERISTICS (unless otherwise specified T = 25°C)

Figure 4 : Output Voltage vs Temperature

Figure 5 : Output Voltage vs Temperature

Figure 6 : Line Regulation vs Temperature

Figure 7 : Line Regulation vs Temperature

Figure 8 : Load Regulation vs Temperature

Figure 9 : Load Regulation vs Temperature

11/20

LNBP21

Figure 10 : Supply Current vs Temperature

Figure 13 : Dynamic Overload Protection OFF

Time vs Temperature

Figure 11 : Supply Current vs Temperature

Figure 14 : Output Current Limiting vs

Temperature

Figure 12 : Dynamic Overload Protection ON

Figure 15 : Output Current Limiting vs

Time vs Temperature

Temperature

12/20

LNBP21

Figure 16 : Tone Frequency vs Temperature

Figure 17 : Tone Amplitude vs Temperature

Figure 18 : Tone Duty Cicle vs Temperature

Figure 19 : Tone Rise Time vs Temperature

Figure 20 : Tone Fall Time vs Temperature

Figure 21 : Loopthrought Switch Drop Voltage vs

Temperature

13/20

LNBP21

Figure 22 : Loopthrought Switch Drop Voltage vs

Figure 25 : DSQOUT Pin Logic Low vs

Temperature

Figure 23 : Loopthrought Switch Drop Voltage vs

Figure 26 : Undervoltage Lockout Threshold vs

Loopthrought Current

Temperature

Figure 24 : Loopthrought Switch Drop Voltage vs

Figure 27 : Output Backward Current vs

Loopthrought Current

Temperature

14/20

LNBP21

Figure 28 : DC/DC Converter Efficiency vs

Temperature

Figure 31 : DSQIN Tone Enable Transient

Response

=12V, I =50mA, EN=1, TEN=0

Figure 29 : Current Limit Sense vs Temperature

Figure 32 : DSQIN Tone Enable Transient

Response

=12V, I =50mA, EN=1, TEN=0

Figure 30 : 22kHz Tone

Figure 33 : DSQIN Tone Disable Transient

Response

=12V, I =50mA, EN=TEN=1

V =12V, I =50mA, EN=1, TEN=0

CC O

15/20

LNBP21

Figure 34 : Output Voltage Transient Response

Figure 35 : Output Voltage Transient Response

from 13V to 18V

=12V, I =50mA, VSEL=from 0 to 1, EN=1

=12V, I =50mA, VSEL=from 1 to 0, EN=1

CC O

TERMAL DESIGN NOTES

During normal operation, this device dissipates

some power. At maximum rated output current

(500mA), the voltage drop on the linear regulator

lead to a total dissipated power that is of about

1.7W. The heat generated requires a suitable

heatsink to keep the junction temperature below

body. This area can be the inner GND layer of a

multi-layer PCB, or, in a dual layer PCB, an

unbroken GND area even on the opposite side

where the IC is placed. In both cases, the thermal

path between the IC GND pins and the dissipating

copper area must exhibit a low thermal resistance.

the

Assuming

overtemperature

protection

threshold.

In figure 4 , it is shown a suggested layout for the

SO-20 package with a dual layer PCB, where the

IC Ground pins and the square dissipating area

are thermally connected through 32 vias holes,

40°C temperature inside the

Set-Top-Box case, the total Rthj-amb has to be

less than 50°C/W.

filled by solder.

L=50mm, achieves an Rthc-a of about 25°C/W.

This arrangement, when

While this can be easily achieved using a

through-hole power package that can be attached

to a small heatsink or to the metallic frame of the

receiver, a surface mount power package must

rely on PCB solutions whose thermal efficiency is

often limited. The simplest solution is to use a

large, con-tinuous copper area of the GND layer to

dissipate the heat coming from the IC body.

Different layouts are possible, too. Basic

principles, however, suggest to keep the IC and its

ground pins approximately in the middle of the

dissipating area; to provide as many vias as

possible; to de-sign a dissipating area having a

shape as square as possible and not interrupted

by other copper traces.

The SO-20 package of this IC has 4 GND pins that

are not just intended for electrical GND

connec-tion, but also to provide a low thermal

resistance path between the silicon chip and the

PCB heatsink. Given an Rthj-c equal to 15°C/W,

a maximum of 35°C/W are left to the PCB

heatsink. This figure is achieved if a minimum of

25cm2 copper area is placed just below the IC

Due to presence of an exposed pad connected to

GND below the IC body, the PowerSO-20

package has a Rthj-c much lower than the SO-20,

only 2°C/W. As a result, much lower copper area

must be provided to dissipate the same power and

minimum of 12cm2 copper area is enough, see

figure 5.

16/20

LNBP21

Figure 36 : SO-20 SUGGESTED PCB HEATSINK LAYOUT

Figure 37 : PowerSO-20 SUGGESTED PCB HEATSINK LAYOUT

17/20

LNBP21

SO-20 MECHANICAL DATA

mm.

inch

TYP.

DIM.

MIN.

TYP

MAX.

2.65

0.2

MIN.

MAX.

0.104

0.008

0.096

0.019

0.012

0.1

0.004

2.45

0.49

0.32

0.35

0.23

0.014

0.009

0.5

0.020

45˚ (typ.)

12.60

10.00

13.00

10.65

0.496

0.393

0.512

0.419

1.27

0.050

0.450

11.43

7.40

0.50

7.60

1.27

0.75

0.291

0.020

0.300

0.050

0.029

˚ (max.)

PO13L

18/20

LNBP21

PowerSO-20 MECHANICAL DATA

mm.

inch

TYP.

DIM.

MIN.

TYP

MAX.

3.60

0.30

3.30

0.10

0.53

0.32

16.00

MIN.

MAX.

0.1417

0.0118

0.1299

0.0039

0.0209

0.0013

0.630

0.10

0.0039

0.40

0.23

15.80

13.90

0.0157

0.0090

0.6220

0.5472

D (1)

14.50

0.5710

1.27

0.0500

0.4500

E1 (1)

11.43

10.90

11.10

2.90

0.10

1.10

0.4291

0.0000

0.0314

0˚

0.4370

0.1141

0.0039

0.0433

10˚

0.80

0˚

8˚

10.0

0.3937

(1) “D and E1” do not include mold flash or protusions - Mold flash or protusions shall not exceed 0.15mm (0.006”)

DETAILB

DETAILA

leda

slug

DETAILB

0.35

GagePlaen

-C-

SEATING PLANE

(COPLANARITY)

PSO20MEC

hx45˚

0056635

19/20

LNBP21

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the

consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from

its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications

mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information

previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or

systems without express written approval of STMicroelectronics.

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Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.

20/20

LNBP21PD-TR [STMICROELECTRONICS]

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