LSM303DLM_技术文档

LSM303DLM

Sensor module:

3-axis accelerometer and 3-axis magnetometer

Preliminary data

Features

■ Analog supply voltage: 2.16 V to 3.6 V

■ Digital supply voltage IOs: 1.8 V

■ Power-down mode

■ 3 magnetic field channels and 3 acceleration

channels

LGA-28L (5x5x1.0 mm)

■ ±1.3 to ±8.1 gauss magnetic field full-scale

The various sensing elements are manufactured

by using specialized micromachining processes,

while the IC interfaces are realized using a CMOS

technology that allows the design of a dedicated

circuit which is trimmed to better match the

sensing element characteristics. The

LSM303DLM has a linear acceleration full-scale

of ±2 g / ±± g / ±8 g and a magnetic field full-scale

of ±1.3 / ±1.9 / ±2.5 / ±±.0 / ±±.7 / ±5.6 / ±8.1

gauss, both fully selectable by the user.

■ ±2 g/±± g/±8 g dynamically selectable full-

scale

■ High performance g-sensor

2

■ I C serial interface

■ 2 independent programmable interrupt

generators for free-fall and motion detection

■ Accelerometer sleep-to-wakeup function

■ 6D orientation detection

2

®

The LSM303DLM includes an I C serial bus

■ ECOPACK , RoHS, and “Green” compliant

interface that supports standard mode (100 kHz)

and fast mode (±00 kHz). The system can be

configured to generate an interrupt signal by

inertial wakeup/free-fall events, as well as by the

position of the device itself. Thresholds and timing

of interrupt generators are programmable on the

fly by the end user.

Applications

■ Compensated compass

■ Map rotation

■ Position detection

■ Motion-activated functions

■ Free-fall detection

Magnetic and accelerometer parts can be

enabled or put into power-down mode separately.

The LSM303DLM is available in a plastic land grid

array package (LGA), and is guaranteed to

operate over an extended temperature range from

-±0 to +85 °C.

■ Intelligent power-saving for handheld devices

■ Display orientation

■ Gaming and virtual reality input devices

■ Impact recognition and logging

■ Vibration monitoring and compensation

Table 1.

Device summary

Temp.

Part number

range

[°C]

Package Packing

Description

The LSM303DLM is a system-in-package

featuring a 3D digital linear acceleration sensor

and a 3D digital magnetic sensor.

LSM303DLM

LSM303DLMTR

Tray

-±0 to +85 LGA-28

Tape and

reel

April 2011

Doc ID 018725 Rev 1

1/38

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to

change without notice.

www.st.com

38

Contents

LSM303DLM

Contents

1

Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1

1.2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2

Module specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1

2.2

2.3

Sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 10

2

2.3.1

Sensor I C - inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3

4

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

±.1

±.2

±.3

Linear acceleration sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Sleep-to-wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5

6

Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.1

Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.1

6.2

6.3

External capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1±

Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

High current wiring effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7

Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.1

I²C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2

7.1.1

7.1.2

7.1.3

I C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Linear acceleration digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Magnetic field digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

8

9

Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2/38

Doc ID 018725 Rev 1

LSM303DLM

Contents

9.1

Linear acceleration register description . . . . . . . . . . . . . . . . . . . . . . . . . . 22

9.1.1

9.1.2

9.1.3

9.1.±

9.1.5

9.1.6

9.1.7

9.1.8

9.1.9

CTRL_REG1_A (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

CTRL_REG2_A (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

CTRL_REG3_A (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2±

CTRL_REG±_A (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

CTRL_REG5_A (2±h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ) 26

HP_FILTER_RESET_A (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

REFERENCE_A (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

STATUS_REG_A(27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

OUT_X_L_A (28h), OUT_X_H_A (29h) . . . . . . . . . . . . . . . . . . . . . . . . . 27

9.1.10 OUT_Y_L_A (2Ah), OUT_Y_H_A (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . 27

9.1.11 OUT_Z_L_A (2Ch), OUT_Z_H_A (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . 27

9.1.12 INT1_CFG_A (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

9.1.13 INT1_SRC_A (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

9.1.1± INT1_THS_A (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

9.1.15 INT1_DURATION_A (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

9.1.16 INT2_CFG_A (3±h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

9.1.17 INT2_SRC_A (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

9.1.18 INT2_THS_A (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

9.1.19 INT2_DURATION_A (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

9.2

Magnetic field sensing register description . . . . . . . . . . . . . . . . . . . . . . . 32

9.2.1

9.2.2

9.2.3

9.2.±

9.2.5

9.2.6

9.2.7

9.2.8

9.2.9

CRA_REG_M (00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

CRB_REG_M (01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

MR_REG_M (02h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

OUT_X_H_M (03), OUT_X_LH_M (0±h) . . . . . . . . . . . . . . . . . . . . . . . . 33

OUT_Z_H_M (05), OUT_Z_L_M (06h) . . . . . . . . . . . . . . . . . . . . . . . . . 3±

OUT_Y_H_M (07), OUT_Y_L_M (08h) . . . . . . . . . . . . . . . . . . . . . . . . . 3±

SR_REG_M (09h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±

IR_REG_M (0Ah/0Bh/0Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±

WHO_AM_I _M (0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±

10

11

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Doc ID 018725 Rev 1

3/38

List of tables

LSM303DLM

List of tables

Table 1.

Table 2.

Table 3.

Table ±.

Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2

Table 5.

I C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 6.

Table 7.

Table 8.

Table 9.

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 16

SAD and read/write patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 17

SAD and read/write patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

CTRL_REG1_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

CTRL_REG1_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Power mode and low-power output data rate configurations . . . . . . . . . . . . . . . . . . . . . . . 21

Normal-mode output data rate configurations and low-pass cut-off frequencies . . . . . . . . 22

CTRL_REG2_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

CTRL_REG2_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

High-pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

High-pass filter cut-off frequency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

CTRL_REG3_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

CTRL_REG3_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Data signal on INT 1 and INT 2 pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2±

CTRL_REG±_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2±

CTRL_REG±_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2±

CTRL_REG5_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

CTRL_REG5_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Sleep-to-wakeup configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

REFERENCE_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

REFERENCE_A description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

STATUS_REG_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

STATUS_REG_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

INT1_CFG_A register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

INT1_CFG_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Interrupt 1 source configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

INT1_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

INT1_SRC_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

INT1_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

INT1_THS description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

INT1_DURATION_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

INT2_DURATION_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

INT2_CFG_A register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

INT2_CFG_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Interrupt mode configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

INT2_SRC_A register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 10.

Table 11.

Table 12.

Table 13.

Table 1±.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 2±.

Table 25.

Table 26.

Table 27.

Table 28.

Table 29.

Table 30.

Table 31.

Table 32.

Table 33.

Table 3±.

Table 35.

Table 36.

Table 37.

Table 38.

Table 39.

Table ±0.

Table ±1.

Table ±2.

Table ±3.

Table ±±.

Table ±5.

Table ±6.

Table ±7.

Table ±8.

±/38

Doc ID 018725 Rev 1

LSM303DLM

List of tables

Table ±9.

Table 50.

Table 51.

Table 52.

Table 53.

Table 5±.

Table 55.

Table 56.

Table 57.

Table 58.

Table 59.

Table 60.

Table 61.

Table 62.

Table 63.

Table 6±.

Table 65.

Table 66.

Table 67.

Table 68.

INT2_SRC_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

INT2_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

INT2_THS description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

INT2_DURATION_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

INT2_DURATION_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

CRA_REG_M register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

CRA_REG_M description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Data rate configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

CRA_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Gain setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

MR_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

MR_REG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Magnetic sensor operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

SR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

SR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

IRA_REG_M. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

IRB_REG_M. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

IRC_REG_M. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

WHO_AM_I_M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Doc ID 018725 Rev 1

5/38

Block diagram and pin description

LSM303DLM

1

Block diagram and pin description

1.1

Block diagram

Figure 1.

Block diagram

A/D

converter

Control

Logic

Sensing Block

Sensing Interface

X+

Y+

Z+

CHARGE

AMPLIFIER

SDA_A

SCL_A

I (a)

+

MUX

-

SDA_M

SCL_M

Z-

Y-

X-

INT1

INT2

X+

CHARGE

AMPLIFIER

Y+

Z+

I (M)

+

MUX

-

Z-

Y-

X-

TRIMMING

CIRCUITS

INTERRUPT GEN.

CLOCK

REFERENCE

BUILT-IN

SET/RESET

OFFSET

CIRCUITS

AM09239V1

6/38

Doc ID 018725 Rev 1

LSM303DLM

Block diagram and pin description

1.2

Pin description

Figure 2.

Pin connection

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Table 2.

Pin description

Name

Pin#

Function

1

2

3

Reserved

GND

Connect to GND

0 V supply

Reserved

Connect to GND

Linear acceleration signal I²C less significant bit of the device

address (SA0)

±

SA0_A

5

NC

Internally not connected

Power supply

6

Vdd

7

Reserved

SET2

Connect to Vdd

8

Leave unconnected

9

Leave unconnected

10

11

12

13

1±

15

16

17

18

19

Leave unconnected

S/R capacitor connection (C2)

Leave unconnected

Reserved

C1

Leave unconnected

Reserved capacitor connection (C1)

S/R capacitor connection (C2)

Connect to GND

SET1

Reserved

DRDY_M

SDA_M

Magnetic signal interface data ready

Magnetic signal interface I²C serial data (SDA)

Doc ID 018725 Rev 1

7/38

Block diagram and pin description

LSM303DLM

Table 2.

Pin#

Pin description (continued)

Name

Function

20

21

22

23

2±

25

26

27

28

SCL_M

NC

Magnetic signal interface I²C serial clock (SCL)

Internally not connected

Vdd_IO

Reserved

SCL_A

SDA_A

INT1

Signal interface power supply for I/O pins

Connect to Vdd_IO

Linear acceleration signal interface I²C serial clock (SCL)

Linear acceleration signal interface I²C serial data (SDA)

Inertial Interrupt 1

INT2

Inertial Interrupt 2

Reserved

Connect to GND

8/38

Doc ID 018725 Rev 1

LSM303DLM

Module specifications

2

Module specifications

2.1

Sensor characteristics

(a)

@ Vdd = 2.5 V, T = 25 °C unless otherwise noted

.

Table 3.

Symbol

Sensor characteristics

Parameter

Test conditions

FS bit set to 00

Min.

Typ.⁽¹⁾

Max.

Unit

±2.0

±±.0

±8.0

±1.3

±1.9

±2.5

±±.0

±±.7

±5.6

±8.1

Linear acceleration

LA_FS

M_FS

FS bit set to 01

g

measurement range⁽²⁾

FS bit set to 11

GN bits set to 001

GN bits set to 010

GN bits set to 011

Magnetic measurement range GN bits set to 100

GN bits set to 101

gauss

GN bits set to 110

GN bits set to 111

FS bit set to 00

12-bit representation

1

2

FS bit set to 01

Linear acceleration sensitivity

LA_So

mg/digit

12-bit representation

FS bit set to 11

12-bit representation

3.9

GN bits set to 001 (X,Y)

GN bits set to 001 (Z)

GN bits set to 010 (X,Y)

GN bits set to 010 (Z)

GN bits set to 011 (X,Y)

GN bits set to 011 (Z)

GN bits set to 100 (X,Y)

GN bits set to 100 (Z)

GN bits set to 101 (X,Y)

GN bits set to 101 (Z)

GN bits set to 110 (X,Y)

GN bits set to 110 (Z)

1100

980

855

760

670

600

±50

±00

355

330

295

230

205

LSB/

M_GN

Magnetic gain setting

gauss

GN bits set to 111⁽²⁾(X,Y)

GN bits set to 111⁽²⁾(Z)

a. The product is factory calibrated at 2.5 V. The operational power supply range is from 2.16 V to 3.6 V.

Doc ID 018725 Rev 1

9/38

Module specifications

LSM303DLM

Table 3.

Symbol

Sensor characteristics (continued)

Parameter

Test conditions

Min.

Typ.⁽¹⁾

Max.

Unit

Linear acceleration sensitivity

change vs. temperature

LA_TCSo

FS bit set to 00

±0.01

%/°C

Linear acceleration typical

LA_TyOff Zero-g level offset

FS bit set to 00

±60

mg

accuracy^(3),(±)

Linear acceleration Zero-g level

change vs. temperature

LA_TCOff

Max. delta from 25 °C

±0.5

±1

mg/°C

Cross field = 0.5 gauss

H applied = ±3 gauss

%FS/

gauss

M_CAS Magnetic cross-axis sensitivity

No permitting effect on

zero reading

M_EF

M_R

Maximum exposed field

Magnetic resolution

10000

gauss

5

mgauss

Sensitivity starts to

M_DF

Disturbing field

degrade. Use S/R pulse to

restore sensitivity

20

gauss

°C

Top

Operating temperature range

-±0

+85

1. Typical specifications are not guaranteed.

2. Verified by wafer level test and measurement of initial offset and sensitivity.

3. Typical Zero-g level offset value after MSL3 preconditioning.

±. Offset can be eliminated by enabling the built-in high-pass filter.

2.2

Electrical characteristics

@ Vdd = 2.5 V, T = 25 °C unless otherwise noted.

Table 4.

Symbol

Electrical characteristics

Test

Parameter

Min.

Typ.⁽¹⁾

Max.

Unit

conditions

Vdd

Supply voltage

2.16

1.71

3.6

V

Vdd_IO

Module power supply for I/O

1.8

Vdd+0.1

Current consumption in normal

Idd

360

µA

mode⁽²⁾

-

Current consumption in power-

down mode

IddPdn

Top

2

µA

°C

Operating temperature range

-±0

+85

1. Typical specifications are not guaranteed.

2. Magnetic sensor setting ODR = 7.5 Hz. Accelerometer sensor ODR = 50 Hz.

10/38

Doc ID 018725 Rev 1

LSM303DLM

Module specifications

2.3

Communication interface characteristics

2

2.3.1

Sensor I C - inter IC control interface

Subject to general operating conditions for Vdd and top.

2

Table 5.

Symbol

I C slave timing values

I²C standard mode ⁽¹⁾

I²C fast mode ⁽¹⁾

Parameter

Unit

KHz

µs

Min.

0

Max.

Min.

0

Max.

f_(SCL)

t_w(SCLL)

t_w(SCLH)

t_su(SDA)

t_h(SDA)

SCL clock frequency

SCL clock low time

SCL clock high time

SDA setup time

100

±00

±.7

±.0

250

0.01

1.3

0.6

100

0.01

ns

µs

SDA data hold time

SDA and SCL rise time

3.±5

1000

300

0.9

300

(2)

t

_r(SDA)t_r(SCL)

t_{f(SDA) f(SCL)}

t_h(ST)

t_su(SR)

20 + 0.1C_b

ns

t

SDA and SCL fall time

20 + 0.1C_b

0.6

START condition hold time

±

Repeated START condition

setup time

±.7

±

0.6

1.3

µs

t_su(SP)

STOP condition setup time

Bus free time between STOP

and START condition

t_w(SP:SR)

±.7

1. Data based on standard I²C protocol requirement, not tested in production.

2. Cb = total capacitance of one bus line, in pF.

2

(b)

Figure 3.

I C slave timing diagram

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b. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.

Doc ID 018725 Rev 1

11/38

Absolute maximum ratings

LSM303DLM

3

Absolute maximum ratings

Stresses above those listed as “absolute maximum ratings” may cause permanent damage

to the device. This is a stress rating only and functional operation of the device under these

conditions is not implied. Exposure to maximum rating conditions for extended periods may

affect device reliability.

Table 6.

Symbol

Absolute maximum ratings

Ratings

Maximum value

Unit

Vdd

Vdd_IO

Vin

Supply voltage

-0.3 to ±.8

V

I/O pins supply voltage

Input voltage on any control pin (SCL, SDA)

-0.3 to Vdd_IO +0.3

3,000 for 0.5 ms

10,000 for 0.1 ms

3,000 for 0.5 ms

10,000 for 0.1 ms

-±0 to +85

V

g

A_POW

Acceleration (any axis, powered, Vdd = 2.5 V)

Acceleration (any axis, unpowered)

g

A_UNP

g

T_OP

Operating temperature range

Storage temperature range

°C

T_STG

-±0 to +125

This is a mechanical shock sensitive device, improper handling can cause permanent

damage to the part.

This is an ESD sensitive device, improper handling can cause permanent damage to

the part.

12/38

Doc ID 018725 Rev 1

LSM303DLM

Terminology

4

Terminology

4.1

Linear acceleration sensitivity

Linear acceleration sensitivity describes the gain of the accelerometer sensor and can be

determined by applying 1 g acceleration to it. As the sensor can measure DC accelerations,

this can be done easily by pointing the selected axis towards the ground, noting the output

value, rotating the sensor 180 degrees (pointing to the sky) and noting the output value

again. By doing so, a ±1 g acceleration is applied to the sensor. Subtracting the larger

output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity

of the sensor. This value changes very little over temperature and over time. The sensitivity

tolerance describes the range of sensitivities of a large number of sensors.

4.2

Zero-g level

Zero-g level Offset (LA_TyOff) describes the deviation of an actual output signal from the

ideal output signal if no linear acceleration is present. A sensor in steady-state on a

horizontal surface measures 0 g on both the X and Y axes, whereas the Z axis measures 1

g. Ideally, the output is in the middle of the dynamic range of the sensor (content of OUT

registers 00h, data expressed as 2’s complement number). A deviation from the ideal value

in this case is called Zero-g offset. Offset is, to some extent, a result of stress to the MEMS

sensor and therefore the offset can slightly change after mounting the sensor onto a printed

circuit board or exposing it to extensive mechanical stress. Offset changes little over

temperature, see “Linear acceleration Zero-g level change vs. temperature” (LA_TCOff) in

Table 3. The Zero-g level tolerance (TyOff) describes the standard deviation of the range of

Zero-g levels of a group of sensors.

4.3

Sleep-to-wakeup

The “sleep-to-wakeup” function, in conjunction with low-power mode, allows further

reduction of system power consumption and the development of new smart applications.

The LSM303DLM may be set to a low-power operating mode, characterized by lower data

rate refreshing. In this way, the device, even if sleeping, continues sensing acceleration and

generating interrupt requests.

When the sleep-to-wakeup function is activated, the LSM303DLM is able to automatically

wake up as soon as the interrupt event has been detected, increasing the output data rate

and bandwidth. With this feature the system may be efficiently switched from low-power

mode to full-performance depending on user-selectable positioning and acceleration events,

therefore ensuring power-saving and flexibility.

Doc ID 018725 Rev 1

13/38

Functionality

LSM303DLM

5

Functionality

The LSM303DLM is a system-in-package featuring a 3D digital linear acceleration and 3D

digital magnetic field detection sensor.

The system includes specific sensing elements and an IC interface capable of measuring

both the linear acceleration and the magnetic field applied on it and to provide a signal to the

2

external world through an I C serial interface with separated digital output.

The sensing system is manufactured using specialized micromachining processes, while

the IC interfaces are realized using a CMOS technology that allows the design of a

dedicated circuit which is trimmed to better match the sensing element characteristics.

The LSM303DLM features two data-ready signals (RDY) which indicate when a new set of

measured acceleration data and magnetic data are available, therefore simplifying data

synchronization in the digital system that uses the device.

The LSM303DLM may also be configured to generate an inertial wakeup and free-fall

interrupt signal according to a programmed acceleration event along the enabled axes. Both

free-fall and wakeup can be used simultaneously on two different accelerometer interrupts.

5.1

Factory calibration

The IC interface is factory calibrated for linear acceleration sensitivity (LA_So), and linear

acceleration Zero-g level (LA_TyOff).

The trimming values are stored inside the device in non-volatile memory. When the device is

turned on, the trimming parameters are downloaded into the registers to be used during

normal operation. This allows the use of the device without further calibration.

1±/38

Doc ID 018725 Rev 1

LSM303DLM

Application hints

6

Application hints

2

Figure 4.

LSM303DLM electrical connection - recommended for I C fast mode

Vdd_IO

Electrical connection

Rpu

Rpu=10kOhm

Z

Vdd

1

Y

C3 = 10uF

X

DIRECTIONS OF

DETECTABLE

MAGNETIC FIELDS

C± = 100uF

Vdd_IO

28

22

Z

Rpu

Rpu=10kOhm

RES

1

21 NC

SCL_M

Y

GND

SDA_M

GND

X

SA0

DRDY_M

LSM303DLM

(TOP VIEW)

RES

DIRECTIONS OF

DETECTABLE

ACCELERATIONS

NC

SET1

VDD

C1=±.7uF

RES

C1

7

15

8

1±

C2=0.22uF

GND

AM092±0V1

6.1

External capacitors

The C1 and C2 external capacitors should have a low SR value ceramic type construction.

Reservoir capacitor C1 is nominally ±.7 µF in capacitance, with the set/reset capacitor C2

nominally 0.22 µF in capacitance.

The device core is supplied through the Vdd line. Power supply decoupling capacitors

(C±=100 nF ceramic, C3=10 µF Al) should be placed as near as possible to the supply pin

of the device (common design practice). All the voltage and ground supplies must be

present at the same time to obtain proper behavior of the IC (refer to Figure 4).

The functionality of the device and the measured acceleration/magnetic field data is

2

selectable and accessible through the I C interface.

The functions, the threshold, and the timing of the two interrupt pins (INT 1 and INT 2) can

2

be completely programmed by the user through the I C interface.

Doc ID 018725 Rev 1

15/38

Application hints

LSM303DLM

6.2

Soldering information

®

The LGA package is compliant with the ECOPACK , RoHS and “Green” standard.

It is qualified for soldering heat resistance according to JEDEC J-STD-020.

Leave “pin 1 indicator” unconnected during soldering.

Land pattern and soldering recommendations are available at www.st.com.

6.3

High current wiring effects

High current in the wiring and printed circuit traces can be the cause of errors in magnetic

field measurements for compassing.

Conductor-generated magnetic fields add to the Earth’s magnetic field, creating errors in

compass heading computation.

Keep currents that are higher than 10 mA a few millimeters further away from the sensor IC.

16/38

Doc ID 018725 Rev 1

LSM303DLM

Digital interfaces

7

Digital interfaces

2

The registers embedded inside the LSM303DLM are accessible through two separate I C

serial interfaces; one for the accelerometer core and the other for the magnetometer core.

The two interfaces can be connected together on the PCB.

Table 7.

Pin name

SCL_A

Serial interface pin description

Pin description

I²C serial clock (SCL) for accelerometer

I²C serial data (SDA) for accelerometer

I²C serial clock (SCL) for magnetometer

I²C serial data (SDA) for magnetometer

SDA_A

SCL_M

SDA_M

7.1

I²C serial interface

2

The LSM303DLM I C is a bus slave. The I C is employed to write the data into the registers

whose content can also be read back.

2

The relevant I C terminology is given in the table below.

Table 8.

Term

Serial interface pin description

Description

Transmitter

Receiver

The device which sends data to the bus

The device which receives data from the bus

The device which initiates a transfer, generates clock signals, and terminates a

transfer

Master

Slave

The device addressed by the master

2

There are two signals associated with the I C bus; the serial clock line (SCL) and the serial

data line (SDA). The latter is a bidirectional line used for sending and receiving the data

to/from the interface.

Doc ID 018725 Rev 1

17/38

Digital interfaces

2

LSM303DLM

7.1.1

I C operation

The transaction on the bus is started through a START (ST) signal. A START condition is

defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After

this has been transmitted by the master, the bus is considered busy. The next byte of data

transmitted after the start condition contains the address of the slave in the first 7 bits and

th

the 8 bit tells whether the master is receiving data from the slave or transmitting data to the

slave. When an address is sent, each device in the system compares the first seven bits

after a start condition with its address. If they match, the device considers itself addressed

by the master.

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line

during the acknowledge pulse. The receiver must then pull the data line LOW so that it

remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which

has been addressed is obliged to generate an acknowledge after each byte of data

received.

2

The I C embedded inside the LSM303DLM behaves like a slave device and the following

protocol must be adhered to. After the start condition (ST) a slave address is sent. Once a

slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted; the

7 LSBs represent the actual register address while the MSB enables address auto-

increment. If the MSb of the SUB field is ‘1’, the SUB (register address) is automatically

increased to allow multiple data read/write.

Table 9.

Transfer when master is writing one byte to slave

ST SAD + W SUB

Master

DATA

SP

Slave

SAK

Table 10. Transfer when master is writing multiple bytes to slave

Master

Slave

ST

SAD + W

SUB

DATA

SP

SAK

Table 11. Transfer when master is receiving (reading) one byte of data from slave

Master ST SAD + W

SUB

SR SAD + R

NMAK SP

Slave

SAK

DATA

Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number

of bytes transferred per transfer is unlimited. Data is transferred with the most significant bit

(MSb) first. If a receiver cannot receive another complete byte of data until it has performed

some other function, it can hold the clock line SCL LOW to force the transmitter into a wait

state. Data transfer only continues when the receiver is ready for another byte and releases

the data line. If a slave receiver does not acknowledge the slave address (i.e. it is not able to

receive because it is performing a real-time function) the data line must be left HIGH by the

slave. The master can then abort the transfer. A LOW to HIGH transition on the SDA line

while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be

terminated by the generation of a STOP (SP) condition.

18/38

Doc ID 018725 Rev 1

LSM303DLM

Digital interfaces

7.1.2

Linear acceleration digital interface

For linear acceleration, the default (factory) 7-bit slave address is 001100xb. The SDO/SA0

pad can be used to modify the least significant bit of the device address. If the SA0 pad is

connected to voltage supply, the LSB is ‘1’ (address 0011001b) otherwise, if the SA0 pad is

connected to ground, the LSB value is ‘0’ (address 0011000b). This solution permits

2

connecting and addressing two different accelerometers to the same I C lines.

The slave address is completed with a read/write bit. If the bit is ‘1’ (read), a repeated

START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (write),

the master transmits to the slave with the direction unchanged. Table 12 explains how the

SAD+read/write bit pattern is composed, listing all the possible configurations.

Table 12. SAD and read/write patterns

Command

SAD[6:1]

SAD[0] = SA0

R/W

SAD+R/W

Read

Write

Read

Write

001100

0

1

0

1

0

00110001 (31h)

00110000 (30h)

00110011 (33h)

00110010 (32h)

In order to read multiple bytes, it is necessary to assert the most significant bit of the sub-

address field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the

address of the first register to be read.

In the presented communication format, MAK is master acknowledge and NMAK is no

master acknowledge.

Table 13. Transfer when master is receiving (reading) multiple bytes of data from slave

Master ST SAD+W

Slave

SUB

SR SAD+R

MAK

NMAK SP

SAK

SAK DATA

DATA

7.1.3

Magnetic field digital interface

For magnetic sensors the default (factory) 7-bit slave address is 0011110xb.

The slave address is completed with a read/write bit. If the bit is ‘1’ (read), a repeated

START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (write),

the master transmits to the slave with the direction unchanged. Table 14 explains how the

SAD is composed.

Table 14. SAD and read/write patterns

Command

SAD[6:0]

R/W

SAD+R/W

Read

Write

0011110

1

0

00111101 (3Dh)

00111100 (3Ch)

Doc ID 018725 Rev 1

19/38

Digital interfaces

LSM303DLM

Magnetic signal interface reading/writing

The interface uses an address pointer to indicate which register location is to be read from

or written to. These pointer locations are sent from the master to this slave device and

succeed the 7-bit address plus 1 bit read/write identifier.

To minimize communication between the master and magnetic digital interface of

LSM303DLM, the address pointer updates automatically without master intervention.

This automatic address pointer update has two additional features. First, when address 12

or higher is accessed, the pointer updates to address 00, and secondly, when address 08 is

reached, the pointer rolls back to address 03. Logically, the address pointer operation

functions as shown below.

If (address pointer = 08) then the address pointer = 03

Or else, if (address pointer >= 12) then the address pointer = 0

Or else, (address pointer) = (address pointer) + 1

2

The address pointer value itself cannot be read via the I C bus.

Any attempt to read an invalid address location returns 0, and any write to an invalid

address location, or an undefined bit within a valid address location, is ignored by this

device.

20/38

Doc ID 018725 Rev 1

LSM303DLM

Register mapping

8

Register mapping

Table 15 provides a listing of the 8-bit registers embedded in the device and the related

addresses:

Table 15. Register address map

Register address

Hex Binary

Slave

address

Name

Type

Default

Comment

Reserved (do not modify)

CTRL_REG1_A

CTRL_REG2_A

CTRL_REG3_A

CTRL_REG±_A

CTRL_REG5_A

HP_FILTER_RESET_A

REFERENCE_A

STATUS_REG_A

OUT_X_L_A

Table 12

Table 14

--

rw

r

00 - 1F

20

--

Reserved

010 0000

010 0001

010 0010

010 0011

010 0100

010 0101

010 0110

010 0111

010 1000

010 1001

010 1010

010 1011

010 1100

010 1101

--

00000111

00000000

--

21

22

23

2±

25

Dummy register

rw

r

26

00000000

output

27

r

28

OUT_X_H_A

r

29

output

OUT_Y_L_A

r

2A

output

OUT_Y_H_A

r

2B

output

OUT_Z_L_A

r

2C

2D

2E - 2F

30

output

OUT_Z_H_A

r

output

Reserved (do not modify)

INT1_CFG_A

--

Reserved

rw

r

011 0000

011 0001

011 0010

011 0011

011 0100

011 0101

011 0110

011 0111

--

00000000

--

INT1_SOURCE_A

INT1_THS_A

31

rw

r

32

INT1_DURATION_A

INT2_CFG_A

33

3±

INT2_SOURCE_A

INT2_THS_A

35

rw

--

36

INT2_DURATION_A

Reserved (do not modify)

CRA_REG_M

37

38 - 3F

00

Reserved

rw

00000000

00000001

00000010

00010000

00100000

00000011

CRB_REG_M

01

MR_REG_M

02

Doc ID 018725 Rev 1

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Register mapping

LSM303DLM

Comment

Table 15. Register address map (continued)

Slave

Register address

Hex Binary

Name

Type

Default

address

OUT_X_H_M

OUT_X_L_M

Table 14

r

03

0±

00000011

00000100

00000101

00000110

00000111

00001000

00001001

00001010

00001011

00001100

--

output

OUT_Y_H_M

r

07

output

OUT_Y_L_M

r

08

output

OUT_Z_H_M

r

05

output

OUT_Z_L_M

r

06

output

SR_REG_Mg

r

09

00000000

01001000

00110100

00110011

--

IRA_REG_M

r

0A

IRB_REG_M

r

0B

IRC_REG_M

r

0C

Reserved (do not modify)

WHO_AM_I_M

Reserved (do not modify)

--

r

0D - 0E

0F

Reserved

Who am I ID

Reserved

00001111

--

00111100

--

10 - 3A

Registers marked as “reserved” must not be changed. Writing to these registers may cause

permanent damage to the device.

The content of the registers that are loaded at boot should not be changed. They contain the

factory calibrated values. Their content is automatically restored when the device is powered

up.

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Register description

9

Register description

The device contains a set of registers which are used to control its behavior and to retrieve

acceleration data. The register address, made up of 7 bits, is used to identify them and to

write the data through the serial interface.

9.1

Linear acceleration register description

CTRL_REG1_A (20h)

9.1.1

Table 16. CTRL_REG1_A register

PM2

PM1

PM0

DR1

DR0

Zen

Yen

Xen

Table 17. CTRL_REG1_A description

Power mode selection. Default value: 000

PM2 - PM0

DR1, DR0

Zen

(000: power-down; others: refer to Table 18)

Data rate selection. Default value: 00

(00:50 Hz; others: refer to Table 19)

Z axis enable. Default value: 1

(0: Z axis disabled; 1: Z axis enabled)

Y axis enable. Default value: 1

Yen

(0: Y axis disabled; 1: Y axis enabled)

X axis enable. Default value: 1

Xen

(0: X axis disabled; 1: X axis enabled)

PM bits allow selection between power-down and two operating active modes. The device is

in power-down mode when the PD bits are set to “000” (default value after boot). Table 18

shows all the possible power mode configurations and respective output data rates. Output

data in the low-power modes are computed with a low-pass filter cut-off frequency defined

by DR1 and DR0 bits.

DR bits, in normal-mode operation, select the data rate at which acceleration samples are

produced. In low-power mode they define the output data resolution. Table 19 shows all the

possible configurations for the DR1 and DR0 bits.

Table 18. Power mode and low-power output data rate configurations

Output data rate [Hz]

PM2

PM1

PM0

Power mode selection

ODR_LP

0

1

0

1

0

Power-down

Normal mode

Low-power

--

ODR

0.5

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Register description

LSM303DLM

Table 18. Power mode and low-power output data rate configurations (continued)

Output data rate [Hz]

PM2

PM1

PM0

Power mode selection

ODR_LP

0

1

0

1

0

1

0

Low-power

1

2

5

10

Table 19. Normal-mode output data rate configurations and low-pass cut-off

frequencies

Output data rate [Hz]

ODR

Low-pass filter cut-off

frequency [Hz]

DR1

DR0

0

1

0

1

0

1

50

100

±00

1000

37

7±

292

780

9.1.2

CTRL_REG2_A (21h)

Table 20. CTRL_REG2_A register

BOOT HPM1 HPM0 FDS

HPen2

HPen1

HPCF1

HPCF0

Table 21. CTRL_REG2_A description

Reboot memory content. Default value: 0

BOOT

(0: normal mode; 1: reboot memory content)

High-pass filter mode selection. Default value: 00

HPM1, HPM0

FDS

(00: normal mode; others: refer to Table 22)

Filtered data selection. Default value: 0

(0: internal filter bypassed; 1: data from internal filter sent to output register)

High-pass filter enabled for Interrupt 2 source. Default value: 0

(0: filter bypassed; 1: filter enabled)

HPen2

High-pass filter enabled for Interrupt 1 source. Default value: 0

(0: filter bypassed; 1: filter enabled)

HPen1

High-pass filter cut-off frequency configuration. Default value: 00

(00: HPc=8; 01: HPc=16; 10: HPc=32; 11: HPc=6±)

HPCF1,

HPCF0

The BOOT bit is used to refresh the content of internal registers stored in the Flash memory

block. At device power-up, the content of the Flash memory block is transferred to the

internal registers related to trimming functions to permit good device behavior. If, for any

2±/38

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LSM303DLM

Register description

reason, the content of the trimming registers has changed, it is sufficient to use this bit to

restore the correct values. When the BOOT bit is set to ‘1’ the content of the internal Flash is

copied to the corresponding internal registers and is used to calibrate the device. These

values are factory-trimmed and are different for every accelerometer. They permit good

device behavior and normally do not have to be modified. At the end of the boot process, the

BOOT bit is again set to ‘0’.

Table 22. High-pass filter mode configuration

HPM1

HPM0

High-pass filter mode

0

1

0

1

0

Normal mode (reset reading HP_RESET_FILTER)

Reference signal for filtering

Normal mode (reset reading HP_RESET_FILTER)

HPCF[1:0]. These bits are used to configure the high-pass filter cut-off frequency (f , which

t)

is given by:

f_s

1

HPc

⎛

⎞

------

f_t= ln 1 – ----------- ⋅

⎝

⎠

2π

The equation can be simplified to the following approximated equation:

f_s

f_t= ----------------------

6 ⋅ HPc

Table 23. High-pass filter cut-off frequency configuration

f_t[Hz]

HPcoeff2,1

Data rate = 50 Hz Data rate = 100 Hz Data rate = 400 Hz Data rate = 1000 Hz

00

01

10

11

1

2

1

8

±

2

1

20

10

5

0.5

0.25

0.125

0.5

0.25

2.5

9.1.3

CTRL_REG3_A (22h)

Table 24. CTRL_REG3_A register

IHL

PP_OD

LIR2

I2_CFG1

I2_CFG0

LIR1

I1_CFG1

I1_CFG0

Table 25. CTRL_REG3_A description

Interrupt active high, low. Default value: 0

(0: active high; 1: active low)

IHL

Push-pull/open drain selection on interrupt pad. Default value 0.

(0: push-pull; 1: open drain)

PP_OD

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Register description

LSM303DLM

Table 25. CTRL_REG3_A description (continued)

Latch interrupt request on INT2_SRC register, with INT2_SRC register cleared by

reading INT2_SRC itself. Default value: 0.

LIR2

(0: interrupt request not latched; 1: interrupt request latched)

Data signal on INT 2 pad control bits. Default value: 00.

I2_CFG1,

I2_CFG0

(see Table 26)

Latch interrupt request on INT1_SRC register, with INT1_SRC register cleared by

reading INT1_SRC register. Default value: 0.

LIR1

(0: interrupt request not latched; 1: interrupt request latched)

Data signal on INT 1 pad control bits. Default value: 00.

I1_CFG1,

I1_CFG0

(see Table 26)

Table 26. Data signal on INT 1 and INT 2 pad

I1(2)_CFG1

I1(2)_CFG0

INT 1(2) Pad

0

1

0

1

0

1

Interrupt 1 (2) source

Interrupt 1 source OR Interrupt 2 source

Data ready

Boot running

9.1.4

CTRL_REG4_A (23h)

Table 27. CTRL_REG4_A register

BDU BLE FS1

FS0

0

0⁽¹⁾

---

1. This bit must be set to ‘0’ for correct working of the device.

Table 28. CTRL_REG4_A description

Block data update. Default value: 0

BDU

(0: continuos update; 1: output registers not updated between MSB and LSB reading)

Big/little endian data selection. Default value 0.

BLE

(0: data LSB @ lower address; 1: data MSB @ lower address)

Full-scale selection. Default value: 00.

FS1, FS0

(00: ±2 g; 01: ±± g; 11: ±8 g)

The BDU bit is used to inhibit output register updates between the reading of the upper and

lower register parts. In default mode (BDU = ‘0’), the lower and upper register parts are

updated continuously. If it is not certain whether to read faster than the output data rate, it is

recommended to set BDU bit to ‘1’. In this way, after the reading of the lower (upper) register

part, the content of that output register is not updated until the upper (lower) part is read

also. This feature avoids reading LSB and MSB related to different samples.

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Register description

9.1.5

CTRL_REG5_A (24h)

Table 29. CTRL_REG5_A register

0

TurnOn1

TurnOn0

Table 30. CTRL_REG5_A description

TurnOn1,

TurnOn0

Turn-on mode selection for sleep-to-wakeup function. Default value: 00.

TurnOn bits are used for turning on the sleep-to-wakeup function.

Table 31. Sleep-to-wakeup configuration

TurnOn1

TurnOn0

Sleep-to-wakeup status

Sleep-to-wakeup function is disabled

0

Turned on: the device is in low-power mode

(ODR is defined in CTRL_REG1_A)

1

By setting the TurnOn [1:0] bits to 11, the “sleep-to-wakeup” function is enabled. When an

interrupt event occurs, the device goes into normal mode, increasing the ODR to the value

defined in CTRL_REG1_A. Although the device is in normal mode, CTRL_REG1_A content

is not automatically changed to “normal mode” configuration.

9.1.6

9.1.7

HP_FILTER_RESET_A (25h)

Dummy register. Reading at this address instantaneously zeroes the content of the internal

high-pass filter. If the high-pass filter is enabled, all three axes are instantaneously set to 0

g. This makes it possible to surmount the settling time of the high-pass filter.

REFERENCE_A (26h)

Table 32. REFERENCE_A register

Ref7

Ref6

Ref5

Ref±

Ref3

Ref2

Ref1

Ref0

Table 33. REFERENCE_A description

Ref7 - Ref0 Reference value for high-pass filter. Default value: 00h.

This register sets the acceleration value taken as a reference for the high-pass filter output.

When the filter is turned on (at least one FDS, HPen2, or HPen1 bit is equal to ‘1’) and HPM

bits are set to “01”, filter out is generated taking this value as a reference.

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Register description

LSM303DLM

9.1.8

STATUS_REG_A(27h)

Table 34. STATUS_REG_A register

ZYXOR ZOR YOR XOR

ZYXDA

ZDA

YDA

XDA

Table 35. STATUS_REG_A description

X, Y, and Z axis data overrun. Default value: 0

ZYXOR

(0: no overrun has occurred, 1: new data has overwritten the previous one)

Z axis data overrun. Default value: 0

ZOR

(0: no overrun has occurred, 1: new data for the Z-axis has overwritten the previous

one)

Y axis data overrun. Default value: 0

YOR

(0: no overrun has occurred, 1: new data for the Y-axis has overwritten the previous

one)

X axis data overrun. Default value: 0

XOR

ZYXDA

ZDA

(0: no overrun has occurred, 1: new data for the X-axis has overwritten the previous

one)

X, Y, and Z axis new data available. Default value: 0

(0: a new set of data is not yet available, 1: a new set of data is available)

Z axis new data available. Default value: 0

(0: new data for the Z-axis is not yet available, 1: new data for the Z-axis is available)

YDA

Y axis new data available. Default value: 0

(0: new data for the Y-axis is not yet available, 1: new data for the Y-axis is available)

XDA

X axis new data available. Default value: 0

(0: new data for the X-axis is not yet available, 1: new data for the X-axis is available)

9.1.9

OUT_X_L_A (28h), OUT_X_H_A (29h)

X-axis acceleration data. The value is expressed as 2’s complement.

9.1.10

9.1.11

9.1.12

OUT_Y_L_A (2Ah), OUT_Y_H_A (2Bh)

Y-axis acceleration data. The value is expressed as 2’s complement.

OUT_Z_L_A (2Ch), OUT_Z_H_A (2Dh)

Z-axis acceleration data. The value is expressed as 2’s complement.

INT1_CFG_A (30h)

Table 36. INT1_CFG_A register

AOI

6D

ZHIE

ZLIE

YHIE

YLIE

XHIE

XLIE

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Register description

Table 37. INT1_CFG_A description

AND/OR combination of interrupt events. Default value: 0

AOI

6D

(see Table 38).

6-direction detection function enable. Default value: 0

(see Table 38).

Enable interrupt generation on Z high event. Default value: 0

(0: disable interrupt request,

ZHIE

1: enable interrupt request on measured accel. value higher than preset threshold)

Enable interrupt generation on Z low event. Default value: 0

(0: disable interrupt request,

ZLIE

YHIE

YLIE

XHIE

XLIE

1: enable interrupt request on measured accel. value lower than preset threshold)

Enable interrupt generation on Y high event. Default value: 0

(0: disable interrupt request,

1: enable interrupt request on measured accel. value higher than preset threshold)

Enable interrupt generation on Y low event. Default value: 0

(0: disable interrupt request,

1: enable interrupt request on measured accel. value lower than preset threshold)

Enable interrupt generation on X high event. Default value: 0

(0: disable interrupt request,

1: enable interrupt request on measured accel. value higher than preset threshold)

Enable interrupt generation on X low event. Default value: 0

(0: disable interrupt request,

1: enable interrupt request on measured accel. value lower than preset threshold)

Configuration register for Interrupt 1 source.

Table 38. Interrupt 1 source configurations

AOI

6D

Interrupt mode

0

1

0

1

0

1

OR combination of interrupt events

6-direction movement recognition

AND combination of interrupt events

6-direction position recognition

9.1.13

INT1_SRC_A (31h)

Table 39. INT1_SRC register

IA ZH

0

ZL

YH

YL

XH

XL

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Register description

LSM303DLM

Table 40. INT1_SRC_A description

Interrupt active. Default value: 0

IA

(0: no interrupt has been generated, 1: one or more interrupts have been generated)

Z high. Default value: 0

ZH

ZL

YH

YL

XH

XL

(0: no interrupt, 1: Z high event has occurred)

Z low. Default value: 0

(0: no interrupt, 1: Z low event has occurred)

Y high. Default value: 0

(0: no interrupt, 1: Y high event has occurred)

Y low. Default value: 0

(0: no interrupt, 1: Y low event has occurred)

X high. Default value: 0

(0: no interrupt, 1: X high event has occurred)

X low. Default value: 0

(0: no interrupt, 1: X low event has occurred)

Interrupt 1 source register. Read-only register.

Reading at this address clears the INT1_SRC_A IA bit (and the interrupt signal on the INT 1

pin) and allows the refreshing of data in the INT1_SRC_A register if the latched option was

chosen.

9.1.14

INT1_THS_A (32h)

Table 41. INT1_THS register

0

THS6

THS5

THS±

THS3

THS2

THS1

THS0

Table 42. INT1_THS description

THS6 - THS0 Interrupt 1 threshold. Default value: 000 0000

9.1.15

INT1_DURATION_A (33h)

Table 43. INT1_DURATION_A register

0

D6

D5

D±

D3

D2

D1

D0

Table 44. INT2_DURATION_A description

D6 - D0 Duration value. Default value: 000 0000

The D6 - D0 bits set the minimum duration of the Interrupt 2 event to be recognized.

Duration steps and maximum values depend on the ODR chosen.

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Register description

9.1.16

INT2_CFG_A (34h)

Table 45. INT2_CFG_A register

AOI

6D

ZHIE

ZLIE

YHIE

YLIE

XHIE

XLIE

Table 46. INT2_CFG_A description

AND/OR combination of interrupt events. Default value: 0

AOI

6D

(see Table 47).

6-direction detection function enable. Default value: 0

(see Table 47).

Enable interrupt generation on Z high event. Default value: 0

(0: disable interrupt request,

ZHIE

1: enable interrupt request on measured accel. value higher than preset threshold)

Enable interrupt generation on Z low event. Default value: 0

(0: disable interrupt request,

ZLIE

YHIE

YLIE

XHIE

XLIE

1: enable interrupt request on measured accel. value lower than preset threshold)

Enable interrupt generation on Y high event. Default value: 0

(0: disable interrupt request,

1: enable interrupt request on measured accel. value higher than preset threshold)

Enable interrupt generation on Y low event. Default value: 0

(0: disable interrupt request,

1: enable interrupt request on measured accel. value lower than preset threshold)

Enable interrupt generation on X high event. Default value: 0

(0: disable interrupt request,

1: enable interrupt request on measured accel. value higher than preset threshold)

Enable interrupt generation on X low event. Default value: 0

(0: disable interrupt request,

1: enable interrupt request on measured accel. value lower than preset threshold)

Configuration register for Interrupt 2 source.

Table 47. Interrupt mode configuration

AOI

6D

Interrupt mode

0

1

0

1

0

1

OR combination of interrupt events

6-direction movement recognition

AND combination of interrupt events

6-direction position recognition

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Register description

LSM303DLM

9.1.17

INT2_SRC_A (35h)

Table 48. INT2_SRC_A register

IA ZH

0

ZL

YH

YL

XH

XL

Table 49. INT2_SRC_A description

Interrupt active. Default value: 0

IA

(0: no interrupt has been generated; 1: one or more interrupts have been generated)

Z high. Default value: 0

ZH

ZL

(0: no interrupt, 1: Z high event has occurred)

Z low. Default value: 0

(0: no interrupt; 1: Z low event has occurred)

Y high. Default value: 0

YH

YL

XH

XL

(0: no interrupt, 1: Y high event has occurred)

Y low. Default value: 0

(0: no interrupt, 1: Y low event has occurred)

X high. Default value: 0

(0: no interrupt, 1: X high event has occurred)

X Low. Default value: 0

(0: no interrupt, 1: X low event has occurred)

Interrupt 2 source register. Read-only register.

Reading at this address clears the INT2_SRC_A IA bit (and the interrupt signal on the INT 2

pin) and allows the refreshing of data in the INT2_SRC_A register if the latched option was

chosen.

9.1.18

INT2_THS_A (36h)

Table 50. INT2_THS register

0

THS6

THS5

THS±

THS3

THS2

THS1

THS0

Table 51. INT2_THS description

THS6 - THS0 Interrupt 1 threshold. Default value: 000 0000

9.1.19

INT2_DURATION_A (37h)

Table 52. INT2_DURATION_A register

0

D6

D5

D±

D3

D2

D1

D0

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Register description

Table 53. INT2_DURATION_A description

D6 - D0 Duration value. Default value: 000 0000

The D6 - D0 bits set the minimum duration of the Interrupt 2 event to be recognized.

Duration time steps and maximum values depend on the ODR chosen.

9.2

Magnetic field sensing register description

9.2.1

CRA_REG_M (00h)

Table 54. CRA_REG_M register

0⁽¹⁾

DO2

DO1

DO0

0⁽¹⁾

1. This bit must be set to ‘0’ for correct working of the device.

Table 55. CRA_REG_M description

Data output rate bits. These bits set the rate at which data is written to all three data

output registers (refer to Table 56). Default value: 100

DO2 to DO0

Table 56. Data rate configurations

DO2

DO1

DO0

Minimum data output rate (Hz)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.75

1.5

3.0

7.5

15

30

75

220

9.2.2

CRB_REG_M (01h)

Table 57. CRA_REG register

GN2 GN1 GN0

0⁽¹⁾

1. This bit must be set to ‘0’ for correct working of the device.

CRA_REG description

Gain configuration bits. The gain configuration is common for all channels (refer to

Table 58)

GN1-0

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Register description

LSM303DLM

Table 58. Gain setting

Gain X/Y and

Z

Sensor input

field range

[Gauss]

Gain Z

GN2

GN1

GN0

Output range

[LSB/Gauss]

0

1

0

1

0

1

0

1

0

1

0

1

±1.3

±1.9

±2.5

±±.0

±±.7

±5.6

±8.1

1100

855

670

±50

±00

330

230

980

760

600

±00

355

295

205

0xF800–0x07FF

(-20±8–20±7)

9.2.3

MR_REG_M (02h)

Table 59. MR_REG

0⁽¹⁾

MD1

MD0

1. This bit must be set to ‘0’ for correct working of the device

Table 60. MR_REG description

Mode select bits. These bits select the operation mode of this device (refer to

Table 61)

MD1-0

Table 61. Magnetic sensor operating mode

MD1

MD0

Mode

0

1

0

1

0

1

Continuous-conversion mode

Single-conversion mode

Sleep-mode. Device is placed in sleep-mode

9.2.4

9.2.5

9.2.6

OUT_X_H_M (03), OUT_X_LH_M (04h)

X-axis magnetic field data. The value is expressed as 2’s complement.

OUT_Z_H_M (05), OUT_Z_L_M (06h)

Z-axis magnetic field data. The value is expressed as 2’s complement.

OUT_Y_H_M (07), OUT_Y_L_M (08h)

Y-axis magnetic field data. The value is expressed as 2’s complement.

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Register description

9.2.7

SR_REG_M (09h)

Table 62. SR register

--

LOCK

DRDY

Table 63. SR register description

Data output register lock. Once a new set of measurements is available, this bit

is set when the first magnetic field data register has been read.

LOCK

DRDY

Data ready bit. This bit is when a new set of measurements is available.

9.2.8

IR_REG_M (0Ah/0Bh/0Ch)

Table 64. IRA_REG_M

0

1

0

1

0

1

0

1

0

1

0

1

Table 65. IRB_REG_M

0

Table 66. IRC_REG_M

0

9.2.9

WHO_AM_I _M (0F)

Table 67. WHO_AM_I_M

0

1

0

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35/38

Package information

LSM303DLM

10

Package information

In order to meet environmental requirements, ST offers these devices in different grades of

®

ECOPACK packages, depending on their level of environmental compliance. ECOPACK

specifications, grade definitions, and product status are available at: www.st.com.

ECOPACK is an ST trademark.

Figure 5.

LGA-28: mechanical data and package dimensions

Dimensions

Outline and

mechanical data

mm

Ref.

Min.

Typ.

Max.

A1

A2

A3

D1

E1

L1

L2

N1

M

1

0.785

0.200

5.000

1.650

3.300

0.550

0.100

0.300

0.±00

0.200

0.050

0.100

±.850

5.150

0.0±0

0.260

0.360

0.160

0.3±0

0.±±0

T1

T2

d

LGA-28 (5x5x1)

Land Grid Array Packages

k

h

8192208_B

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Doc ID 018725 Rev 1

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Revision history

11

Revision history

Table 68. Document revision history

Date

Revision

Changes

11-Apr-2011

1

Initial release.

Doc ID 018725 Rev 1

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LSM303DLM

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Doc ID 018725 Rev 1


型号：	LSM303DLM
厂家：	ST
描述：	Sensor module:3-axis accelerometer and 3-axis magnetometer 传感器模块： 3轴加速计和3轴磁强计传感器
文件：	总38页 (文件大小：511K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LSM303DLM [STMICROELECTRONICS]

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