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M24128-BWCS3P/A [STMICROELECTRONICS]

16KX8 I2C/2-WIRE SERIAL EEPROM, PBGA8, 0.50 MM PITCH, ROHS COMPLIANT, WLCSP-8;
M24128-BWCS3P/A
型号： M24128-BWCS3P/A
厂家： ST    ST
描述：

16KX8 I2C/2-WIRE SERIAL EEPROM, PBGA8, 0.50 MM PITCH, ROHS COMPLIANT, WLCSP-8

可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器
文件： 总38页 (文件大小：356K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
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M24128-BW  
M24128-BR M24128-BF  
128 Kbit serial I²C bus EEPROM  
Features  
2
■ Supports the I C bus modes:  
– 400 kHz Fast-mode  
– 100 kHz Standard-mode  
■ Single supply voltages:  
SO8 (MN)  
150 mil width  
– 2.5 V to 5.5 V (M24128-BW)  
– 1.8 V to 5.5 V (M24128-BR)  
– 1.7 V to 5.5 V (M24128-BF)  
■ Write Control input  
■ Byte and Page Write  
■ Random and Sequential Read modes  
■ Self-timed programming cycle  
■ Automatic address incrementing  
■ Enhanced ESD/latch-up protection  
■ More than 1 Million write cycles  
■ More than 40-year data retention  
■ Packages  
TSSOP8 (DW)  
169 mil width  
WLCSP (CS)  
®
– ECOPACK2 (RoHS-compliant and  
Halogen-free)  
UFDFPN8  
(MB, MC)  
November 2011  
Doc ID 16892 Rev 20  
1/38  
www.st.com  
1
 
 
Contents  
M24128-BW, M24128-BR, M24128-BF  
Contents  
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
2.1  
2.2  
2.3  
2.4  
2.5  
2.6  
Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
2.6.1  
2.6.2  
2.6.3  
2.6.4  
Operating supply voltage V  
CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9  
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
3
4
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
4.1  
4.2  
4.3  
4.4  
4.5  
4.6  
4.7  
4.8  
4.9  
Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
ECC (error correction code) and write cycling . . . . . . . . . . . . . . . . . . . . . 17  
4.10 Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 18  
4.11 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
4.12 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
4.13 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
4.14 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
4.15 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
2/38  
Doc ID 16892 Rev 20  
M24128-BW, M24128-BR, M24128-BF  
Contents  
5
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34  
6
7
8
9
10  
Doc ID 16892 Rev 20  
3/38  
List of tables  
M24128-BW, M24128-BR, M24128-BF  
List of tables  
Table 1.  
Table 2.  
Table 3.  
Table 4.  
Table 5.  
Table 6.  
Table 7.  
Table 8.  
Table 9.  
Table 10.  
Table 11.  
Table 12.  
Table 13.  
Table 14.  
Table 15.  
Table 16.  
Table 17.  
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Address most significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Address least significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Operating conditions (M24xxx-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Operating conditions (M24xxx-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Operating conditions (M24xxx-F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
AC test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
DC characteristics (M24xxx-W, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
DC characteristics (M24xxx-W, device grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
DC characteristics (M24xxx-R - device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
DC characteristics (M24xxx-F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
SO8 narrow – 8 lead plastic small outline, 150 mils body width,  
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
TSSOP8 – 8 lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 30  
UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead  
Table 18.  
Table 19.  
2 x 3 mm, mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
WLCSP, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34  
Table 20.  
Table 21.  
Table 22.  
4/38  
Doc ID 16892 Rev 20  
M24128-BW, M24128-BR, M24128-BF  
List of figures  
List of figures  
Figure 1.  
Figure 2.  
Figure 3.  
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
8-pin package connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
WLCSP connections (top view, marking side, with balls on the  
underside) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Figure 4.  
Figure 5.  
Figure 6.  
Figure 7.  
Figure 8.  
Figure 9.  
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
2
Maximum R value versus bus parasitic capacitance (C) for an I C bus. . . . . . . . . . . . . . 10  
P
2
I C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Figure 10. Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Figure 11. Read mode sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Figure 12. AC test measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Figure 13. AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
Figure 14. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . 28  
Figure 15. TSSOP8 – 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 30  
Figure 16. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead  
2 × 3mm, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
Figure 17. WLCSP, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
Doc ID 16892 Rev 20  
5/38  
Description  
M24128-BW, M24128-BR, M24128-BF  
1
Description  
2
The M24128-BW, M24128-BR and M24128-BF devices are I C-compatible electrically  
erasable programmable memories (EEPROM). They are organized as 16384 × 8 bits.  
Figure 1.  
Logic diagram  
6
##  
ꢄ
%ꢀꢅ%ꢆ  
3$!  
-ꢆꢃXXX  
3#,  
7#  
6
!)ꢀꢁꢂꢃꢃF  
33  
2
I C uses a two-wire serial interface, comprising a bidirectional data line and a clock line. The  
2
devices carry a built-in 4-bit device type identifier code (1010) in accordance with the I C  
bus definition.  
2
The device behaves as a slave in the I C protocol, with all memory operations synchronized  
by the serial clock. Read and Write operations are initiated by a Start condition, generated  
by the bus master. The Start condition is followed by a device select code and Read/Write  
bit (RW) (as described in Table 2), terminated by an acknowledge bit.  
th  
When writing data to the memory, the device inserts an acknowledge bit during the 9 bit  
time, following the bus master’s 8-bit transmission. When data is read by the bus master, the  
bus master acknowledges the receipt of the data byte in the same way. Data transfers are  
terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.  
6/38  
Doc ID 16892 Rev 20  
M24128-BW, M24128-BR, M24128-BF  
Description  
Table 1.  
Signal names  
Signal name  
Function  
Chip Enable  
Direction  
E0, E1, E2  
SDA  
Input  
I/O  
Serial Data  
Serial Clock  
Write Control  
Supply voltage  
Ground  
SCL  
Input  
Input  
WC  
VCC  
VSS  
Figure 2.  
8-pin package connections  
%ꢀ  
%ꢁ  
%ꢆ  
ꢁ
ꢂ
ꢈ
ꢉ
ꢇ
6
##  
7#  
ꢆ
ꢄ
ꢃ
3#,  
3$!  
6
33  
!)ꢀꢁꢂꢃꢇF  
1. See Package mechanical data section for package dimensions, and how to identify pin-1.  
Figure 3.  
WLCSP connections (top view, marking side, with balls on the  
underside)  
VCC  
E1  
E0  
E2  
WC  
SDA  
SCL  
VSS  
ai14799  
Doc ID 16892 Rev 20  
7/38  
 
Signal description  
M24128-BW, M24128-BR, M24128-BF  
2
Signal description  
2.1  
Serial Clock (SCL)  
This input signal is used to strobe all data in and out of the device. In applications where this  
signal is used by slave devices to synchronize the bus to a slower clock, the bus master  
must have an open drain output, and a pull-up resistor must be connected from Serial Clock  
(SCL) to V . (Figure 5 indicates how the value of the pull-up resistor can be calculated). In  
CC  
most applications, though, this method of synchronization is not employed, and so the pull-  
up resistor is not necessary, provided that the bus master has a push-pull (rather than open  
drain) output.  
2.2  
2.3  
Serial Data (SDA)  
This bidirectional signal is used to transfer data in or out of the device. It is an open drain  
output that may be wire-OR’ed with other open drain or open collector signals on the bus. A  
pull up resistor must be connected from Serial Data (SDA) to V . (Figure 5 indicates how  
CC  
the value of the pull-up resistor can be calculated).  
Chip Enable (E0, E1, E2)  
These input signals are used to set the value that is to be looked for on the three least  
significant bits (b3, b2, b1) of the 7-bit device select code. These inputs must be tied to V  
CC  
or V , to establish the device select code as shown in Figure 4. When not connected (left  
SS  
floating), these inputs are read as low (0,0,0).  
Figure 4.  
Device select code  
V
V
CC  
CC  
M24xxx  
M24xxx  
E
E
i
i
V
V
SS  
SS  
Ai12806  
2.4  
Write Control (WC)  
This input signal is useful for protecting the entire contents of the memory from inadvertent  
write operations. Write operations are disabled to the entire memory array when Write  
Control (WC) is driven high. When unconnected, the signal is internally read as V , and  
IL  
Write operations are allowed.  
When Write Control (WC) is driven high, device select and Address bytes are  
acknowledged, Data bytes are not acknowledged.  
8/38  
Doc ID 16892 Rev 20  
 
 
 
M24128-BW, M24128-BR, M24128-BF  
Signal description  
2.5  
VSS ground  
V
is the reference for the V supply voltage.  
CC  
SS  
2.6  
Supply voltage (VCC)  
2.6.1  
Operating supply voltage V  
CC  
Prior to selecting the memory and issuing instructions to it, a valid and stable V voltage  
CC  
within the specified [V (min), V (max)] range must be applied (see Table 7, Table 8 and  
CC  
CC  
Table 9). In order to secure a stable DC supply voltage, it is recommended to decouple the  
V
V
line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the  
CC  
/V package pins.  
CC SS  
This voltage must remain stable and valid until the end of the transmission of the instruction  
and, for a Write instruction, until the completion of the internal write cycle (t ).  
W
2.6.2  
2.6.3  
Power-up conditions  
The V voltage has to rise continuously from 0 V up to the minimum V operating voltage  
CC  
CC  
defined in Table 7, Table 8 and Table 9. The rise time must not vary faster than 1 V/µs.  
Device reset  
In order to prevent inadvertent Write operations during power-up, a power on reset (POR)  
circuit is included. At power-up (continuous rise of V ), the device does not respond to any  
CC  
instruction until V has reached the power on reset threshold voltage (this threshold is  
CC  
lower than the minimum V operating voltage defined in Table 8 and Table 9). Until V  
CC  
CC  
passes over the POR threshold, the device is reset and in Standby Power mode.  
In a similar way, during power-down (continuous decay of V ), as soon as V drops below  
CC  
CC  
the POR threshold voltage, the device is reset and stops responding to any instruction sent  
to it.  
2.6.4  
Power-down conditions  
During power-down (continuous decay of V ), the device must be in Standby Power mode  
CC  
(mode reached after decoding a Stop condition, assuming that there is no internal Write  
cycle in progress).  
Doc ID 16892 Rev 20  
9/38  
 
 
 
 
 
Signal description  
Figure 5.  
M24128-BW, M24128-BR, M24128-BF  
2
Maximum R value versus bus parasitic capacitance (C) for an I C bus  
P
100  
When t  
LOW  
= 1.3 µs (min value for  
× C  
f
= 400 kHz), the R  
C
bus  
bus  
V
CC  
time constant must be below the  
400 ns time constant line  
represented on the left.  
10  
R
bus  
Here R  
bus  
× C = 120 ns  
bus  
4 kΩ  
SCL  
SDA  
I²C bus  
master  
M24xxx  
1
30 pF  
C
bus  
10  
100  
Bus line capacitor (pF)  
1000  
ai14796b  
2
Figure 6.  
I C bus protocol  
SCL  
SDA  
SDA  
Input  
SDA  
Change  
Start  
Condition  
Stop  
Condition  
1
2
3
7
8
9
SCL  
SDA  
ACK  
MSB  
Start  
Condition  
1
2
3
7
8
9
SCL  
SDA  
MSB  
ACK  
Stop  
Condition  
AI00792B  
10/38  
Doc ID 16892 Rev 20  
 
 
M24128-BW, M24128-BR, M24128-BF  
Signal description  
Table 2.  
Device select code  
Device type identifier(1)  
Chip Enable address(2)  
RW  
b7  
b6  
b5  
b4  
b3  
b2  
b1  
b0  
Device select code  
1
0
1
0
E2  
E1  
E0  
RW  
1. The most significant bit, b7, is sent first.  
2. E0, E1 and E2 are compared against the respective external pins on the memory device.  
Table 3.  
Address most significant byte  
b14 b13 b12  
b15  
b11  
b3  
b10  
b2  
b9  
b1  
b8  
b0  
Table 4.  
Address least significant byte  
b6 b5 b4  
b7  
Doc ID 16892 Rev 20  
11/38  
 
 
 
Memory organization  
M24128-BW, M24128-BR, M24128-BF  
3
Memory organization  
The memory is organized as shown in Figure 7.  
Figure 7. Block diagram  
WC  
E0  
E1  
E2  
High Voltage  
Generator  
Control Logic  
SCL  
SDA  
I/O Shift Register  
Address Register  
and Counter  
Data  
Register  
1 Page  
X Decoder  
AI06899  
12/38  
Doc ID 16892 Rev 20  
 
M24128-BW, M24128-BR, M24128-BF  
Device operation  
4
Device operation  
2
The device supports the I C protocol. This is summarized in Figure 6. Any device that sends  
data on to the bus is defined to be a transmitter, and any device that reads the data to be a  
receiver. The device that controls the data transfer is known as the bus master, and the  
other as the slave device. A data transfer can only be initiated by the bus master, which will  
also provide the serial clock for synchronization. The device is always a slave in all  
communications.  
4.1  
4.2  
Start condition  
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in  
the high state. A Start condition must precede any data transfer command. The device  
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock  
(SCL) for a Start condition, and will not respond unless one is given.  
Stop condition  
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable  
and driven high. A Stop condition terminates communication between the device and the  
bus master. A Read command that is followed by NoAck can be followed by a Stop condition  
to force the device into the Standby mode. A Stop condition at the end of a Write command  
triggers the internal Write cycle.  
4.3  
4.4  
Acknowledge bit (ACK)  
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,  
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits  
th  
of data. During the 9 clock pulse period, the receiver pulls Serial Data (SDA) low to  
acknowledge the receipt of the eight data bits.  
Data Input  
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock  
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge  
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock  
(SCL) is driven low.  
Doc ID 16892 Rev 20  
13/38  
Device operation  
M24128-BW, M24128-BR, M24128-BF  
4.5  
Memory addressing  
To start communication between the bus master and the slave device, the bus master must  
initiate a Start condition. Following this, the bus master sends the device select code, shown  
in Table 2 (on Serial Data (SDA), most significant bit first).  
The device select code consists of a 4-bit device type identifier, and a 3-bit Chip Enable  
“Address” (E2, E1, E0). To address the memory array, the 4-bit device type identifier is  
1010b.  
2
Up to eight memory devices can be connected on a single I C bus. Each one is given a  
unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the device select code is  
received, the device only responds if the Chip Enable Address is the same as the value on  
the Chip Enable (E0, E1, E2) inputs.  
th  
The 8 bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.  
If a match occurs on the device select code, the corresponding device gives an  
th  
acknowledgment on Serial Data (SDA) during the 9 bit time. If the device does not match  
the device select code, it deselects itself from the bus, and goes into Standby mode.  
Table 5.  
Mode  
Operating modes  
RW bit WC(1)  
Bytes  
Initial sequence  
Current Address  
Read  
1
X
1
Start, device select, RW = 1  
0
1
X
X
Start, device select, RW = 0, Address  
reStart, device select, RW = 1  
Random Address  
Read  
1
Similar to Current or Random Address  
Read  
Sequential Read  
1
X
≥ 1  
Byte Write  
Page Write  
0
0
VIL  
VIL  
1
Start, device select, RW = 0  
Start, device select, RW = 0  
≤ 64  
1. X = V or V .  
IH  
IL  
14/38  
Doc ID 16892 Rev 20  
M24128-BW, M24128-BR, M24128-BF  
Device operation  
Figure 8.  
Write mode sequences with WC = 1 (data write inhibited)  
WC  
ACK  
ACK  
ACK  
NO ACK  
Byte Write  
Dev select  
Byte address  
Byte address  
Data in  
R/W  
WC  
ACK  
ACK  
ACK  
NO ACK  
Data in 2  
Page Write  
Dev select  
Byte address  
Byte address  
Data in 1  
R/W  
WC (cont'd)  
NO ACK  
NO ACK  
Page Write  
(cont'd)  
Data in N  
AI01120d  
Doc ID 16892 Rev 20  
15/38  
 
Device operation  
M24128-BW, M24128-BR, M24128-BF  
4.6  
Write operations  
Following a Start condition the bus master sends a device select code with the Read/Write  
bit (RW) reset to 0. The device acknowledges this, as shown in Figure 9, and waits for two  
address bytes. The device responds to each address byte with an acknowledge bit, and  
then waits for the data Byte.  
Writing to the memory may be inhibited if Write Control (WC) is driven high. Any Write  
instruction with Write Control (WC) driven high (during a period of time from the Start  
condition until the end of the two address bytes) will not modify the memory contents, and  
the accompanying data bytes are not acknowledged, as shown in Figure 8.  
Each data byte in the memory has a 16-bit (two byte wide) address. The Most Significant  
Byte (Table 3) is sent first, followed by the Least Significant Byte (Table 4). Bits b15 to b0  
form the address of the byte in memory.  
th  
When the bus master generates a Stop condition immediately after the Ack bit (in the “10  
bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write cycle is  
triggered. A Stop condition at any other time slot does not trigger the internal Write cycle.  
After the Stop condition, the delay t , and the successful completion of a Write operation,  
W
the device’s internal address counter is incremented automatically, to point to the next byte  
address after the last one that was modified.  
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does  
not respond to any requests.  
4.7  
4.8  
Byte Write  
After the device select code and the address bytes, the bus master sends one data byte. If  
the addressed location is Write-protected, by Write Control (WC) being driven high, the  
device replies with NoAck, and the location is not modified. If, instead, the addressed  
location is not Write-protected, the device replies with Ack. The bus master terminates the  
transfer by generating a Stop condition, as shown in Figure 9.  
Page Write  
The Page Write mode allows up to 64 bytes to be written in a single Write cycle, provided  
that they are all located in the same ‘row’ in the memory: that is, the most significant  
memory address bits (b13-b6) are the same. If more bytes are sent than will fit up to the end  
of the row, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to  
become overwritten in an implementation dependent way.  
The bus master sends from 1 to 64 bytes of data, each of which is acknowledged by the  
device if Write Control (WC) is low. If Write Control (WC) is high, the contents of the  
addressed memory location are not modified, and each data byte is followed by a NoAck.  
After each byte is transferred, the internal byte address counter (inside the page) is  
incremented. The transfer is terminated by the bus master generating a Stop condition.  
16/38  
Doc ID 16892 Rev 20  
M24128-BW, M24128-BR, M24128-BF  
Device operation  
Figure 9.  
Write mode sequences with WC = 0 (data write enabled)  
WC  
ACK  
ACK  
ACK  
ACK  
Byte Write  
Dev Select  
Byte address  
Byte address  
Data in  
R/W  
WC  
ACK  
ACK  
ACK  
ACK  
Page Write  
Dev Select  
Byte address  
Byte address  
Data in 1  
Data in 2  
R/W  
WC (cont'd)  
ACK  
ACK  
Page Write  
(cont'd)  
Data in N  
AI01106d  
4.9  
ECC (error correction code) and write cycling  
The new M24128 devices offer an ECC (error correction code) logic which compares each  
4-byte word with its six associated EEPROM ECC bits. As a result, if a single bit out of 4  
bytes of data happens to be erroneous during a read operation, the ECC detects it and  
replaces it by the correct value. The read reliability is therefore much improved by the use of  
this feature.  
Note however that even if a single byte has to be written, 4 bytes are internally modified  
(plus the ECC word), that is, the addressed byte is cycled together with the three other bytes  
making up the word. It is therefore recommended to write by packets of 4 bytes in order to  
benefit from the larger amount of write cycles.  
All M24128 devices are qualified at 1 million (1 000 000) write cycles; the new M24128  
devices offering the ECC improvement are qualified using a cycling routine that writes to the  
device by multiples of 4-byte words.  
Doc ID 16892 Rev 20  
17/38  
 
Device operation  
M24128-BW, M24128-BR, M24128-BF  
Figure 10. Write cycle polling flowchart using ACK  
Write cycle  
in progress  
Start condition  
Device select  
with RW = 0  
ACK  
NO  
Returned  
First byte of instruction  
with RW = 0 already  
decoded by the device  
YES  
Next  
operation is  
addressing the  
memory  
NO  
YES  
Send address  
and receive ACK  
ReStart  
Start  
NO  
YES  
Stop  
condition  
Data for the  
Write operation  
Device select  
with RW = 1  
Continue the  
Continue the  
Random Read operation  
Write operation  
AI01847d  
4.10  
Minimizing system delays by polling on ACK  
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy  
of the data from its internal latches to the memory cells. The maximum Write time (tw) is  
shown in Table 16, but the typical time is shorter. To make use of this, a polling sequence can  
be used by the bus master.  
The sequence, as shown in Figure 10, is:  
1. Initial condition: a Write cycle is in progress.  
2. Step 1: the bus master issues a Start condition followed by a device select code (the  
first byte of the new instruction).  
3. Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and  
the bus master goes back to Step 1. If the device has terminated the internal Write  
cycle, it responds with an Ack, indicating that the device is ready to receive the second  
part of the instruction (the first byte of this instruction having been sent during Step 1).  
18/38  
Doc ID 16892 Rev 20  
 
M24128-BW, M24128-BR, M24128-BF  
Figure 11. Read mode sequences  
Device operation  
ACK  
NO ACK  
Current  
Address  
Read  
Dev select  
Data out  
R/W  
ACK  
ACK  
ACK  
ACK  
NO ACK  
Random  
Address  
Read  
Dev select *  
Byte address  
Byte address  
Dev select *  
Data out  
R/W  
R/W  
ACK  
ACK  
ACK  
NO ACK  
Data out N  
Sequential  
Current  
Read  
Dev select  
Data out 1  
R/W  
ACK  
ACK  
ACK  
ACK  
R/W  
ACK  
Sequential  
Random  
Read  
Dev select *  
Byte address  
Byte address  
Dev select *  
Data out 1  
R/W  
ACK  
NO ACK  
Data out N  
AI01105d  
1. The seven most significant bits of the device select code of a Random Read (in the 1st and 4th bytes) must  
be identical.  
Doc ID 16892 Rev 20  
19/38  
 
Device operation  
M24128-BW, M24128-BR, M24128-BF  
4.11  
Read operations  
Read operations are performed independently of the state of the Write Control (WC) signal.  
After the successful completion of a Read operation, the device’s internal address counter is  
incremented by one, to point to the next byte address.  
4.12  
Random Address Read  
A dummy Write is first performed to load the address into this address counter (as shown in  
Figure 11) but without sending a Stop condition. Then, the bus master sends another Start  
condition, and repeats the device select code, with the Read/Write bit (RW) set to 1. The  
device acknowledges this, and outputs the contents of the addressed byte. The bus master  
must not acknowledge the byte, and terminates the transfer with a Stop condition.  
4.13  
4.14  
Current Address Read  
For the Current Address Read operation, following a Start condition, the bus master only  
sends a device select code with the Read/Write bit (RW) set to 1. The device acknowledges  
this, and outputs the byte addressed by the internal address counter. The counter is then  
incremented. The bus master terminates the transfer with a Stop condition, as shown in  
Figure 11, without acknowledging the Byte.  
Sequential Read  
This operation can be used after a Current Address Read or a Random Address Read. The  
bus master does acknowledge the data byte output, and sends additional clock pulses so  
that the device continues to output the next byte in sequence. To terminate the stream of  
bytes, the bus master must not acknowledge the last byte, and must generate a Stop  
condition, as shown in Figure 11.  
The output data comes from consecutive addresses, with the internal address counter  
automatically incremented after each byte output. After the last memory address, the  
address counter ‘rolls-over’, and the device continues to output data from memory address  
00h.  
4.15  
Acknowledge in Read mode  
For all Read commands, the device waits, after each byte read, for an acknowledgment  
th  
during the 9 bit time. If the bus master does not drive Serial Data (SDA) low during this  
time, the device terminates the data transfer and switches to its Standby mode.  
20/38  
Doc ID 16892 Rev 20  
M24128-BW, M24128-BR, M24128-BF  
Initial delivery state  
5
Initial delivery state  
The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).  
6
Maximum rating  
Stressing the device outside the ratings listed in Table 6 may cause permanent damage to  
the device. These are stress ratings only, and operation of the device at these, or any other  
conditions outside those indicated in the Operating sections of this specification, is not  
implied. Exposure to absolute maximum rating conditions for extended periods may affect  
device reliability. Refer also to the STMicroelectronics SURE Program and other relevant  
quality documents.  
Table 6.  
Symbol  
Absolute maximum ratings  
Parameter  
Min.  
Max.  
Unit  
TA  
TSTG  
TLEAD  
VIO  
Ambient operating temperature  
Storage temperature  
–40  
–65  
130  
150  
°C  
°C  
°C  
V
Lead temperature during soldering  
Input or output range  
see note (1)  
–0.50  
-
6.5  
5
IOL  
DC output current (SDA = 0)  
mA  
V
VCC  
VESD  
Supply voltage  
–0.50  
–4000  
6.5  
4000  
Electrostatic discharge voltage (human body model)(2)  
V
1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®  
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)  
2002/95/EU.  
2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500 Ω, R2=500 Ω)  
Doc ID 16892 Rev 20  
21/38  
 
DC and AC parameters  
M24128-BW, M24128-BR, M24128-BF  
7
DC and AC parameters  
This section summarizes the operating and measurement conditions, and the DC and AC  
characteristics of the device. The parameters in the DC and AC characteristic tables that  
follow are derived from tests performed under the measurement conditions summarized in  
the relevant tables. Designers should check that the operating conditions in their circuit  
match the measurement conditions when relying on the quoted parameters.  
Table 7.  
Symbol  
Operating conditions (M24xxx-W)  
Parameter  
Min.  
Max.  
Unit  
VCC  
TA  
Supply voltage  
2.5  
–40  
–40  
5.5  
85  
V
Ambient operating temperature (device grade 6)  
Ambient operating temperature (device grade 3)  
°C  
°C  
125  
Table 8.  
Symbol  
Operating conditions (M24xxx-R)  
Parameter  
Min.  
Max.  
Unit  
VCC  
TA  
Supply voltage  
1.8  
5.5  
85  
V
Ambient operating temperature  
–40  
°C  
Table 9.  
Symbol  
Operating conditions (M24xxx-F)  
Parameter  
Min.  
Max.  
Unit  
VCC  
TA  
Supply voltage  
1.7  
–40  
–20  
5.5  
85  
85  
V
Ambient operating temperature (device grade 6)  
Ambient operating temperature (device grade 5)  
°C  
°C  
Table 10. AC test measurement conditions  
Symbol  
Parameter  
Min.  
Max.  
Unit  
CL  
Load capacitance  
100  
pF  
ns  
V
Input rise and fall times  
Input levels  
50  
0.2VCC to 0.8VCC  
0.3VCC to 0.7VCC  
Input and output timing reference levels  
V
22/38  
Doc ID 16892 Rev 20  
 
 
 
M24128-BW, M24128-BR, M24128-BF  
Figure 12. AC test measurement I/O waveform  
DC and AC parameters  
Input Levels  
Input and Output  
Timing Reference Levels  
0.8V  
CC  
0.7V  
CC  
0.3V  
CC  
0.2V  
CC  
AI00825B  
Table 11. Input parameters  
Symbol  
Parameter  
Test condition  
Min.  
Max.  
Unit  
CIN  
CIN  
Input capacitance (SDA)  
Input capacitance (other pins)  
WC input impedance  
8
6
pF  
pF  
kΩ  
kΩ  
(1)  
ZWCL  
VIN < 0.3VCC  
VIN > 0.7VCC  
50  
200  
(1)  
ZWCH  
WC input impedance  
500  
Pulse width ignored  
(Input filter on SCL and SDA)  
(1)  
tNS  
100  
ns  
1. Characterized only.  
Table 12. DC characteristics (M24xxx-W, device grade 6)  
Test condition  
Symbol  
Parameter  
Min.  
Max.  
Unit  
(in addition to those in Table 7)  
Input leakage current  
(SCL, SDA, E2, E1, E0)  
VIN = VSS or VCC  
device in Standby mode  
ILI  
2
2
µA  
µA  
SDA in Hi-Z, external voltage  
applied on SDA: VSS or VCC  
ILO  
Output leakage current  
ICC  
Supply current (Read)  
Supply current (Write)  
2.5 V < VCC < 5.5 V, fc = 400 kHz  
During tW, 2.5 V < VCC < 5.5 V  
2
mA  
mA  
ICC0  
5(1)  
Device not selected(2), VIN = VSS  
or VCC, VCC = 5.5 V  
Standby supply current  
Standby supply current  
5
µA  
µA  
V
ICC1  
Device not selected(2), VIN = VSS  
or VCC, VCC = 2.5 V  
2
Input low voltage (SDA,  
SCL, WC)  
VIL  
–0.45 0.3VCC  
0.7VCC 6.5  
Input high voltage  
(SCL, SDA)  
V
VIH  
Input high voltage  
(WC, E0, E1, E2)  
0.7VCC VCC+0.6  
0.4  
V
IOL = 2.1 mA, VCC = 2.5 V or  
IOL = 3 mA, VCC = 5.5 V  
VOL  
Output low voltage  
V
1. Characterized value, not tested in production.  
2. The device is not selected after power-up, after a Read command (after the Stop condition) or after the  
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write command).  
Doc ID 16892 Rev 20  
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DC and AC parameters  
M24128-BW, M24128-BR, M24128-BF  
Table 13. DC characteristics (M24xxx-W, device grade 3)  
Test condition  
(in addition to those in Table 7)  
Symbol  
Parameter  
Min.  
Max.  
Unit  
Input leakage current (SCL, SDA,  
E2, E1, E0)  
VIN = VSS or VCC  
device in Standby mode  
ILI  
2
2
µA  
µA  
SDA in Hi-Z, external voltage  
applied on SDA: VSS or VCC  
ILO  
Output leakage current  
ICC  
Supply current (Read)  
Supply current (Write)  
2.5 V < VCC < 5.5 V, fc = 400 kHz  
During tW, 2.5 V < VCC < 5.5 V  
2
mA  
mA  
ICC0  
5(1)  
Device not selected(2), VIN = VSS or  
VCC, 2.5 V < VCC < 5.5 V  
ICC1  
VIL  
Standby supply current  
10  
µA  
Input low voltage (SDA, SCL, WC)  
Input high voltage (SCL, SDA)  
–0.45  
0.3VCC  
6.5  
V
V
V
0.7VCC  
VIH  
Input high voltage (WC, E0, E1, E2)  
0.7VCC VCC+0.6  
0.4  
IOL = 2.1 mA, VCC = 2.5 V or  
IOL = 3 mA, VCC = 5.5 V  
VOL  
Output low voltage  
V
1. Characterized value, not tested in production.  
2. The device is not selected after power-up, after a Read command (after the Stop condition) or after the completion of the  
internal write cycle tW (tW is triggered by the correct decoding of a Write command).  
Table 14. DC characteristics (M24xxx-R - device grade 6)  
Test condition (in addition to  
Symbol  
Parameter  
Min.  
Max.  
Unit  
those in Table 8)(1)  
Input leakage current  
(SCL, SDA, E2, E1, E0)  
VIN = VSS or VCC  
device in Standby mode  
ILI  
2
2
µA  
µA  
SDA Hi-Z, external voltage  
applied on SDA: VSS or VCC  
ILO  
Output leakage current  
ICC  
Supply current (Read)  
Supply current (Write)  
VCC = 1.8 V, fc = 400 kHz  
0.8  
mA  
mA  
ICC0  
During tW, 1.8 V < VCC < 2.5 V  
3(2)  
Device not selected(3), VIN = VSS  
or VCC, VCC = 1.8 V  
ICC1  
Standby supply current  
1
µA  
1.8 V ≤ VCC < 2.5 V  
2.5 V ≤ VCC < 5.5 V  
–0.45  
–0.45  
0.25 VCC  
0.3 VCC  
6.5  
V
V
V
V
V
VIL  
Input low voltage (SDA, SCL, WC)  
Input high voltage (SCL, SDA)  
Input high voltage (WC, E0, E1, E2)  
Output low voltage  
0.7VCC  
0.7VCC  
VIH  
VCC+0.6  
0.2  
VOL  
IOL = 1 mA, VCC = 1.8 V  
1. If the application uses the M24128-BR at 2.5 V < VCC < 5.5 V and –40 °C < TA < +85 °C, please refer to Table 12: DC  
characteristics (M24xxx-W, device grade 6) instead of the above table.  
2. Characterized value, not tested in production.  
3. The device is not selected after power-up, after a Read command (after the Stop condition) or after the completion of the  
internal write cycle tW (tW is triggered by the correct decoding of a Write command).  
24/38  
Doc ID 16892 Rev 20  
 
 
M24128-BW, M24128-BR, M24128-BF  
DC and AC parameters  
Table 15. DC characteristics (M24xxx-F)  
Test condition  
(in addition to those in  
Table 9)  
Symbol  
Parameter  
Min.  
Max.  
Unit  
Input leakage current  
(SCL, SDA, E2, E1, E0)  
VIN = VSS or VCC  
device in Standby mode  
ILI  
2
µA  
SDA Hi-Z, external voltage  
applied on SDA: VSS or VCC  
ILO  
ICC  
Output leakage current  
Supply current (Read)  
Supply current (Write)  
2
0.8  
3(1)  
µA  
mA  
mA  
VCC =1.7 V, fc = 400 kHz  
During tW, 1.7 V < VCC < 2.5  
V
ICC0  
Device not selected(2), VIN  
VSS or VCC, VCC = 1.7 V  
=
ICC1  
Standby supply current  
1
µA  
1.8 V ≤ VCC < 2.5 V  
2.5 V ≤ VCC < 5.5 V  
–0.45 0.25 VCC  
V
V
V
Input low voltage (SDA, SCL,  
WC)  
VIL  
–0.45  
0.3 VCC  
6.5  
Input high voltage (SCL, SDA)  
0.7VCC  
VIH  
Input high voltage (WC, E0, E1,  
E2)  
0.7VCC VCC+0.6  
0.2  
V
V
VOL  
Output low voltage  
IOL = 0.7 mA, VCC = 1.7 V  
1. Characterized value, not tested in production.  
2. The device is not selected after power-up, after a Read command (after the Stop condition) or after the  
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write command).  
Doc ID 16892 Rev 20  
25/38  
 
DC and AC parameters  
M24128-BW, M24128-BR, M24128-BF  
Table 16. AC characteristics  
Test conditions specified in Table 7, Table 8 and Table 9  
Symbol  
Alt.  
Parameter  
Min.  
Max.  
Unit  
fC  
fSCL  
tHIGH  
tLOW  
tF  
Clock frequency  
400  
kHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCHCL  
tCLCH  
Clock pulse width high  
Clock pulse width low  
SDA (out) fall time  
600  
1300  
20(2)  
120  
(1)  
tQL1QL2  
tXH1XH2  
tXL1XL2  
tDXCX  
(3)  
(3)  
tR  
Input signal rise time  
Input signal fall time  
(3)  
(3)  
tF  
tSU:DAT Data in set up time  
tHD:DAT Data in hold time  
100  
0
tCLDX  
tCLQX  
tDH  
tAA  
Data out hold time  
200  
200  
600  
600  
600  
(4)(5)  
tCLQV  
tCHDL  
Clock low to next data valid (access time)  
900  
tSU:STA Start condition setup time  
tHD:STA Start condition hold time  
tSU:STO Stop condition set up time  
tDLCL  
tCHDH  
Time between Stop condition and next Start  
condition  
tDHDL  
tW  
tBUF  
tWR  
1300  
ns  
Write time  
5
ms  
1. Characterized only, not tested in production.  
2. With CL = 10 pF.  
3. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the  
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when  
f
C < 400 kHz.  
4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or  
rising edge of SDA.  
5.  
tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or  
0.7VCC, assuming that Rbus × Cbus time constant is within the values specified in Figure 5.  
26/38  
Doc ID 16892 Rev 20  
 
M24128-BW, M24128-BR, M24128-BF  
Figure 13. AC waveforms  
DC and AC parameters  
T8,ꢁ8,ꢆ  
T#(#,  
T8(ꢁ8(ꢆ  
3#,  
T#,#(  
T$,#,  
T8,ꢁ8,ꢆ  
3$! )N  
T#($,  
3TART  
CONDITION  
T#,$8  
T$8#(  
3$!  
#HANGE  
T8(ꢁ8(ꢆ  
T#($( T$($,  
3TART  
3$!  
)NPUT  
3TOP  
CONDITION  
CONDITION  
3#,  
3$! )N  
T7  
7RITE CYCLE  
T#($(  
T#($,  
3TOP  
CONDITION  
3TART  
CONDITION  
T#(#,  
3#,  
T#,16  
T#,18  
$ATA VALID  
T1,ꢁ1,ꢆ  
$ATA VALID  
3$! /UT  
!)ꢀꢀꢈꢊꢇF  
Doc ID 16892 Rev 20  
27/38  
 
Package mechanical data  
M24128-BW, M24128-BR, M24128-BF  
8
Package mechanical data  
In order to meet environmental requirements, ST offers these devices in different grades of  
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK  
specifications, grade definitions and product status are available at: www.st.com.  
®
ECOPACK is an ST trademark.  
Figure 14. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package  
outline  
h x 45˚  
A2  
A
c
ccc  
b
e
0.25 mm  
D
GAUGE PLANE  
k
8
1
E1  
E
L
A1  
L1  
SO-A  
1. Drawing is not to scale.  
Table 17. SO8 narrow – 8 lead plastic small outline, 150 mils body width,  
package mechanical data  
millimeters  
Min  
inches(1)  
Symbol  
Typ  
Max  
Typ  
Min  
Max  
A
A1  
A2  
b
1.75  
0.25  
0.0689  
0.0098  
0.10  
1.25  
0.28  
0.17  
0.0039  
0.0492  
0.0110  
0.0067  
0.48  
0.23  
0.10  
5.00  
6.20  
4.00  
–
0.0189  
0.0091  
0.0039  
0.1969  
0.2441  
0.1575  
–
c
ccc  
D
4.90  
6.00  
3.90  
1.27  
4.80  
5.80  
3.80  
–
0.1929  
0.2362  
0.1535  
0.0500  
0.1890  
0.2283  
0.1496  
–
E
E1  
e
h
0.25  
0°  
0.50  
8°  
k
0°  
8°  
28/38  
Doc ID 16892 Rev 20  
 
 
 
M24128-BW, M24128-BR, M24128-BF  
Package mechanical data  
Table 17. SO8 narrow – 8 lead plastic small outline, 150 mils body width,  
package mechanical data  
millimeters  
inches(1)  
Symbol  
Typ  
Min  
Max  
Typ  
Min  
Max  
L
0.40  
1.27  
0.0157  
0.0500  
L1  
1.04  
0.0410  
1. Values in inches are converted from mm and rounded to 4 decimal digits.  
Doc ID 16892 Rev 20  
29/38  
Package mechanical data  
M24128-BW, M24128-BR, M24128-BF  
Figure 15. TSSOP8 – 8 lead thin shrink small outline, package outline  
D
8
5
c
E1  
E
1
4
α
A1  
L
A
A2  
L1  
CP  
b
e
TSSOP8AM  
1. Drawing is not to scale.  
Table 18. TSSOP8 – 8 lead thin shrink small outline, package mechanical data  
millimeters  
Min.  
inches(1)  
Symbol  
Typ.  
Max.  
Typ.  
Min.  
Max.  
A
A1  
A2  
b
1.200  
0.150  
1.050  
0.300  
0.200  
0.100  
3.100  
–
0.0472  
0.0059  
0.0413  
0.0118  
0.0079  
0.0039  
0.1220  
–
0.050  
0.800  
0.190  
0.090  
0.0020  
0.0315  
0.0075  
0.0035  
1.000  
0.0394  
c
CP  
D
3.000  
0.650  
6.400  
4.400  
0.600  
1.000  
2.900  
–
0.1181  
0.0256  
0.2520  
0.1732  
0.0236  
0.0394  
0.1142  
–
e
E
6.200  
4.300  
0.450  
6.600  
4.500  
0.750  
0.2441  
0.1693  
0.0177  
0.2598  
0.1772  
0.0295  
E1  
L
L1  
α
0°  
8°  
0°  
8°  
1. Values in inches are converted from mm and rounded to 4 decimal digits.  
30/38  
Doc ID 16892 Rev 20  
M24128-BW, M24128-BR, M24128-BF  
Package mechanical data  
Figure 16. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead  
2 × 3mm, package outline  
-"  
-#  
E
B
E
B
$
,ꢁ  
,ꢁ  
,ꢄ  
,ꢄ  
0IN ꢁ  
%ꢆ  
+
%
%ꢆ  
+
,
,
!
$ꢆ  
$ꢆ  
EEE  
!ꢁ  
1. Drawing is not to scale.  
:7?-%E  
2. The central pad (E2 × D2 area in the above illustration) is internally pulled to VSS. It must not be allowed to  
be connected to any other voltage or signal line on the PCB, for example during the soldering process.  
3. The circle in the top view of the package indicates the position of pin 1.  
Table 19. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead  
2 x 3 mm, mechanical data  
millimeters  
Min  
inches(1)  
Symbol  
Typ  
Max  
Typ  
Min  
Max  
A
0.550  
0.020  
0.250  
2.000  
1.600  
0.450  
0.000  
0.200  
1.900  
1.500  
1.200  
2.900  
0.100  
1.200  
0.600  
0.050  
0.300  
2.100  
1.700  
1.600  
3.100  
0.300  
1.600  
0.0217  
0.0008  
0.0098  
0.0787  
0.0630  
0.0177  
0.0000  
0.0079  
0.0748  
0.0591  
0.0472  
0.1142  
0.0039  
0.0472  
0.0236  
0.0020  
0.0118  
0.0827  
0.0669  
0.0630  
0.1220  
0.0118  
0.0630  
A1  
b
D
D2 (rev MB)  
D2 (rev MC)  
E
3.000  
0.200  
0.1181  
0.0079  
E2 (rev MB)  
E2 (rev MC)  
e
K
0.500  
0.0197  
0.300  
0.300  
0.0118  
0.0118  
L
0.500  
0.150  
0.0197  
0.0059  
L1  
L3  
0.300  
0.080  
0.0118  
0.0031  
eee(2)  
1. Values in inches are converted from mm and rounded to four decimal digits.  
2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from  
measuring.  
Doc ID 16892 Rev 20  
31/38  
 
 
Package mechanical data  
M24128-BW, M24128-BR, M24128-BF  
Figure 17. WLCSP, 0.5 mm pitch, package outline  
Orientation references  
D
3
5
4
2
1
A
B
C
B
e1  
F
E
e3  
e2  
G
e
A
A1  
A2  
1. Drawing is not to scale.  
Table 20. WLCSP, 0.5 mm pitch, package mechanical data  
millimeters  
Symbol  
inches(1)  
Min.  
Typ.  
Min.  
Max.  
Typ.  
Max.  
A
A1  
A2  
B
0.585  
0.230  
0.355  
0.320  
1.805  
1.400  
0.5  
0.535  
0.205  
0.330  
0.290  
1.785  
1.380  
0.635  
0.255  
0.380  
0.350  
1.825  
1.420  
0.0230  
0.0091  
0.0140  
0.0126  
0.0711  
0.0551  
0.0197  
0.0349  
0.0098  
0.0174  
0.0101  
0.0158  
0.0211  
0.0081  
0.0130  
0.0114  
0.0703  
0.0543  
0.0250  
0.0100  
0.0150  
0.0138  
0.0719  
0.0559  
D
E
e
e1  
e2  
e3  
F
0.886  
0.250  
0.443  
0.257  
0.4025  
G
N(2)  
8
8
1. Values in inches are converted from mm and rounded to 4 decimal digits.  
2. N is the total number of terminals.  
32/38  
Doc ID 16892 Rev 20  
M24128-BW, M24128-BR, M24128-BF  
Part numbering  
9
Part numbering  
Table 21. Ordering information scheme  
Example:  
M24128–B  
W
MN 6  
T
P /P  
Device type  
M24 = I2C serial access EEPROM  
Device function  
128–B = 128 Kbit (16384 x 8)  
Operating voltage  
W = VCC = 2.5 V to 5.5 V  
R = VCC = 1.8 V to 5.5 V  
F = VCC = 1.7 V to 5.5 V  
Package  
MN = SO8 (150 mil width)(1)  
DW = TSSOP8 (169 mil width)(1)  
MB or MC = UFDFPN8 (MLP8)(1)  
CS = WLCSP(1)  
Device grade  
6 = Industrial: device tested with standard test flow  
over –40 to 85 °C  
3 = Automotive: device tested with high reliability  
certified flow(2) over –40 to 125°C.  
Option  
blank = standard packing  
T = Tape and reel packing  
Plating technology  
P or G = ECOPACK® (RoHS compliant)  
Process(3)  
P = F6DP26% Chartered  
A = F8L Rousset (only for the WLCSP package)  
1. ECOPACK2® (RoHS-compliant and Halogen-free).  
2. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment.  
The high reliability certified flow (HRCF) is described in the quality note QNEE9801. Please ask your  
nearest ST sales office for a copy.  
3. Used only for device grade 3 and WLCSP packages.  
For a list of available options (speed, package, etc.) or for further information on any aspect  
of this device, please contact your nearest ST sales office.  
Doc ID 16892 Rev 20  
33/38  
 
 
Revision history  
M24128-BW, M24128-BR, M24128-BF  
10  
Revision history  
Table 22. Document revision history  
Date  
Revision  
Changes  
TSSOP8 package in place of TSSOP14 (pp 1, 2, OrderingInfo,  
PackageMechData).  
22-Dec-1999  
28-Jun-2000  
2.3  
2.4  
TSSOP8 package data corrected  
References to Temperature Range 3 removed from Ordering Information  
31-Oct-2000  
2.5  
Voltage range -S added, and range -R removed from text and tables  
throughout.  
Lead Soldering Temperature in the Absolute Maximum Ratings table  
amended  
20-Apr-2001  
2.6  
Write Cycle Polling Flow Chart using ACK illustration updated  
References to PSDIP changed to PDIP and Package Mechanical data  
updated  
Test condition for ILI made more precise, and value of ILI for E2-E0 and  
WC added  
16-Jan-2002  
02-Aug-2002  
2.7  
2.8  
-R voltage range added  
Document reformatted using new template.  
TSSOP8 (3x3mm² body size) package (MSOP8) added.  
5ms write time offered for 5V and 2.5V devices  
04-Feb-2003  
27-May-2003  
2.9  
SO8W package removed. -S voltage range removed  
2.10  
TSSOP8 (3x3mm² body size) package (MSOP8) removed  
Table of contents, and Pb-free options added. Minor wording changes in  
Summary Description, Power-On Reset, Memory Addressing, Write  
Operations, Read Operations. VIL(min) improved to -0.45V.  
22-Oct-2003  
01-Jun-2004  
3.0  
4.0  
Absolute Maximum Ratings for VIO(min) and VCC(min) improved.  
Soldering temperature information clarified for RoHS compliant devices.  
Device Grade clarified  
Product List summary table added. Device Grade 3 added. 4.5-5.5V  
range is Not for New Design. Some minor wording changes. AEC-Q100-  
002 compliance. tNS(max) changed. VIL(min) is the same on all input  
pins of the device. ZWCL changed.  
04-Nov-2004  
05-Jan-2005  
5.0  
6.0  
UFDFPN8 package added. Small text changes.  
34/38  
Doc ID 16892 Rev 20  
M24128-BW, M24128-BR, M24128-BF  
Revision history  
Table 22. Document revision history (continued)  
Date Revision Changes  
Document converted to new ST template.  
M24C32 and M24C64 products (4.5 to 5.5V supply voltage) removed.  
M24C64 and M24C32 products (1.7 to 5.5V supply voltage) added.  
Section 2.3: Chip Enable (E0, E1, E2) and Section 2.4: Write Control  
(WC) modified, Section 2.6: Supply voltage (VCC) added and replaces  
Power On Reset: VCC Lock-Out Write Protect section.  
TA added, Note 1 updated and TLEAD specified for PDIP packages in  
Table 6: Absolute maximum ratings.  
ICC0 added, ICC voltage conditions changed and ICC1 specified over the  
whole voltage range in Table 12: DC characteristics (M24xxx-W, device  
grade 6).  
29-Jun-2006  
7
ICC0 added, ICC frequency conditions changed and ICC1 specified over  
the whole voltage range in Table 14: DC characteristics (M24xxx-R -  
device grade 6).  
tW modified in Table 16: AC characteristics.  
SO8N package specifications updated (see Figure 14 and Table 17).  
Device grade 5 added, B and P Process letters added to Table 21:  
Ordering information scheme. Small text changes.  
ICC1 modified in Table 12: DC characteristics (M24xxx-W, device grade  
6).  
03-Jul-2006  
17-Oct-2006  
8
9
Note 1 added to Table 15: DC characteristics (M24xxx-F) and table title  
modified.  
UFDFPN8 package specifications updated (see Table 19). M24128-BW-  
and M24128-BR part numbers added.  
Generic part number corrected in Features on page 1.  
ICC0 corrected in Table 13 and Table 12.  
Packages are ECOPACK® compliant.  
Available packages and temperature ranges by product specified in  
Table 22, Table 24 and Table 25.  
Notes modified below Table 11: Input parameters.  
VIH max modified in DC characteristics tables (see Table 12, Table 13,  
Table 14 and Table 15).  
27-Apr-2007  
10  
C process code added to Table 21: Ordering information scheme.  
For M24xxx-R (1.8 V to 5.5 V range) products assembled from July 2007  
on, tW will be 5 ms (see Table 16: AC characteristics.  
Small text changes. Section 2.5: VSS ground and Section 4.9: ECC  
(error correction code) and write cycling added.  
VIL and VIH modified in Table 14: DC characteristics (M24xxx-R - device  
grade 6).  
27-Nov-2007  
11  
JEDEC standard reference updated below Table 6: Absolute maximum  
ratings.  
Package mechanical data inch values calculated from mm and rounded  
to 4 decimal digits (see Section 8: Package mechanical data).  
Doc ID 16892 Rev 20  
35/38  
Revision history  
M24128-BW, M24128-BR, M24128-BF  
Table 22. Document revision history (continued)  
Date  
Revision  
Changes  
Added Section 2.6.2: Power-up conditions, updated Section 2.6.3:  
Device reset, and Section 2.6.4: Power-down conditions in Section 2.6:  
Supply voltage (VCC).  
Updated Figure 5: Maximum RP value versus bus parasitic capacitance  
(C) for an I2C bus.  
Replace M24128 and M24C64 by M24128-BFMB6 and M24C64-FMB6,  
respectively, in Section 4.9: ECC (error correction code) and write  
cycling.  
Added temperature grade 6 in Table 9: Operating conditions (M24xxx-  
F).  
Updated test conditions for ILO and VLO in Table 12: DC characteristics  
(M24xxx-W, device grade 6), Table 13: DC characteristics (M24xxx-W,  
device grade 3), and Table 14: DC characteristics (M24xxx-R - device  
grade 6).  
18-Dec-2007  
12  
Test condition updated for ILO, and VIH and VIL differentiate for 1.8 V ≤  
VCC < 2.5 V and 2.5 V ≤ VCC < 5.5 V in Table 15: DC characteristics  
(M24xxx-F).  
Updated Table 16: AC characteristics, and Table 17: AC characteristics  
(M24xxx-F).  
Updated Figure 13: AC waveforms.  
Added M24128-BF in Table 25: Available M24C32 products (package,  
voltage range, temperature grade).  
Process B removed fromTable 21: Ordering information scheme.  
Small text changes.  
30-May-2008  
15-Jul-2008  
13  
14  
C Process option and Blank Plating technology option removed from  
Table 21: Ordering information scheme.  
WLCSP package added (see Figure 3: WLCSP connections (top view,  
marking side, with balls on the underside) and Section 8: Package  
mechanical data). Section 4.9: ECC (error correction code) and write  
cycling updated.  
IOL added to Table 6: Absolute maximum ratings.  
Table 24: Available M24C32 products (package, voltage range,  
temperature grade) and Table 25: Available M24C32 products (package,  
voltage range, temperature grade) updated.  
16-Sep-2008  
05-Jan-2009  
15  
16  
I2C modes supported specified in Features on page 1.  
Note removed from Table 15: DC characteristics (M24xxx-F). Small text  
changes.  
36/38  
Doc ID 16892 Rev 20  
M24128-BW, M24128-BR, M24128-BF  
Revision history  
Table 22. Document revision history (continued)  
Date Revision Changes  
32 and 64 Kbit densities removed.  
ECOPACK status of packages specified on page 1 and in Table 21:  
Ordering information scheme.  
Section 2.6.2: Power-up conditions updated.  
Figure 5: Maximum RP value versus bus parasitic capacitance (C) for an  
I2C bus updated.  
tNS modified in Table 11: Input parameters.  
ICC1 and VIH updated in Table 12: DC characteristics (M24xxx-W, device  
grade 6), Table 13: DC characteristics (M24xxx-W, device grade 3),  
Table 14: DC characteristics (M24xxx-R - device grade 6) and Table 15:  
DC characteristics (M24xxx-F). Note added to Table 14: DC  
characteristics (M24xxx-R - device grade 6).  
10-Dec-2009  
17  
Table 16: AC characteristics modified.  
Figure 13: AC waveforms modified.  
Note added below Figure 16: UFDFPN8 (MLP8) – 8-lead ultra thin fine  
pitch dual flat package no lead 2 × 3mm, package outline.  
Small text changes.  
12-Jan-2010  
23-Mar-2010  
18  
19  
Section 4.9: ECC (error correction code) and write cycling modified.  
Removed PDIP package.  
Updated UFDFPN8 silhouette on cover page, Figure 16: UFDFPN8  
(MLP8) – 8-lead ultra thin fine pitch dual flat package no lead 2 × 3mm,  
package outline and Table 19: UFDFPN8 (MLP8) 8-lead ultra thin fine  
pitch dual flat package no lead 2 x 3 mm, mechanical data to add MC  
version.  
24-Nov-2011  
20  
Renamed Figure 2: 8-pin package connections.  
Removed “Available M24128 products“ table.  
Updated disclaimer on last page.  
Doc ID 16892 Rev 20  
37/38  
M24128-BW, M24128-BR, M24128-BF  
Please Read Carefully:  
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the  
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any  
time, without notice.  
All ST products are sold pursuant to ST’s terms and conditions of sale.  
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no  
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.  
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this  
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products  
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third party products or services or any intellectual property contained therein.  
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WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED  
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OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.  
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APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,  
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GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.  
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void  
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any  
liability of ST.  
ST and the ST logo are trademarks or registered trademarks of ST in various countries.  
Information in this document supersedes and replaces all information previously supplied.  
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.  
© 2011 STMicroelectronics - All rights reserved  
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38/38  
Doc ID 16892 Rev 20  

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SI9136_11

 Multi-Output Power-Supply Controller

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SI9130CG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

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SI9130LG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

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SI9130_11

 Pin-Programmable Dual Controller - Portable PCs

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SI9137

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9137DB

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9137LG

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9122E

 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

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