M24128-DL3 [STMICROELECTRONICS]
16KX8 I2C/2-WIRE SERIAL EEPROM, PDSO14, 0.169 INCH, TSSOP-14;型号: | M24128-DL3 |
厂家: | ST |
描述: | 16KX8 I2C/2-WIRE SERIAL EEPROM, PDSO14, 0.169 INCH, TSSOP-14 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 |
文件: | 总18页 (文件大小:139K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
M24256
M24128
2
256 Kbit/128 Kbit Serial I C Bus EEPROM
without Chip Enable Lines
PRELIMINARY DATA
COMPATIBLE with I2C EXTENDED
ADDRESSING
TWO WIRE I2C SERIAL INTERFACE,
SUPPORTS 400kHz PROTOCOL
100,000 ERASE/WRITE CYCLES
14
8
40 YEARS DATA RETENTION
1
1
SINGLE SUPPLY VOLTAGE
– 4.5V to 5.5V for M24256 and M24128
– 2.5V to 5.5V for M24256-W and M24128-W
– 1.8V to 3.6V for M24256-R and M24128-R
HARDWARE WRITE CONTROL
PSDIP8 (BN)
0.25mm Frame
TSSOP14 (DL)
169mil Width
8
8
BYTE and PAGE WRITE (up to 64 BYTES)
BYTE, RANDOM and SEQUENTIAL READ
MODES
SELF TIMED PROGRAMING CYCLE
1
1
SO8 (MN)
150mil Width
SO8 (MW)
200mil Width
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH-UP
PERFORMANCES
Figure 1. Logic Diagram
DESCRIPTION
The M24256 and the M24128 are a 256 Kbit and a
128 Kbit electrically erasable programmable
memories (EEPROM), organized as 32,768 x8 and
as 16,384 x8 bits respectively. The "-W" versions
operate with a power supply value as low as 2.5V
and the "-R" versions operate down to 1.8V. Plastic
Dual-in-Line, Plastic Small Outline and Thin Shrink
Small Outline packages are available.
V
CC
SCL
WC
SDA
M24256
M24128
Table 1. Signal Names
SDA
SCL
WC
VCC
VSS
Serial Data Address Input/Output
Serial Clock
V
SS
AI01882
Write Control
Supply Voltage
Ground
October 1998
1/18
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M24256, M24128
Table 2. Absolute Maximum Ratings (1)
Symbol
TA
Parameter
Value
Unit
°C
Ambient Operating Temperature (2)
Storage Temperature
–40 to 125
–65 to 150
TSTG
°C
TLEAD
Lead Temperature, Soldering
(SO8)
(PSDIP8)
40 sec
10 sec
215
260
°C
VIO
Input or Output Voltages
Supply Voltage
–0.6 to 6.5
–0.3 to 6.5
4000
V
V
V
V
VCC
Electrostatic Discharge Voltage (Human Body model) (3)
Electrostatic Discharge Voltage (Machine model) (4)
VESD
200
Notes:
1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and
other relevant quality documents.
2. Depends on range.
3. 100pF through 1500Ω; MIL-STD-883C, 3015.7
4. 200pF through 0Ω; EIAJ IC-121 (condition C)
Figure 2A. DIP Pin Connections
Figure 2B. SO Pin Connections
M24256
M24128
M24256
M24128
NC
NC
NC
1
2
3
4
8
V
NC
NC
NC
1
2
3
4
8
V
CC
WC
CC
7
6
WC
7
6
SCL
SDA
SCL
SDA
V
5
V
5
SS
SS
AI01883
AI01884
Warning:
Warning:
NC = Not Connected
NC = Not Connected
Figure 2C. TSSOP Pin Connections
DESCRIPTION
(cont’d)
Each memory is compatible with the I2C extended
memory standard, two wire serial interface which
uses a bi-directional data bus and serial clock. The
memory carries a built-in 4 bit, unique device iden-
tification code (1010) corresponding to the I2C bus
definition. The memory behaves as a slave device
in the I2C protocol with all memory operations
synchronized by the serial clock. Read and write
operations are initiated by a START condition gen-
erated by the bus master. The START condition is
followed by a stream of 4 bits (identification code
1010), then 3 bits (at 000) to form a 7 bit Device
Select, plus one read/write bit (RW) and terminated
by an acknowledge bit.
M24128
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
14
13
V
CC
WC
12
NC
11
NC
10
NC
9
SCL
SDA
V
8
SS
AI02249
Warning:
NC = Not Connected
2/18
M24256, M24128
Table 3. Device Select Code
Device Code
Chip Enable
RW
Bit
b7
1
b6
0
b5
1
b4
0
b3
0
b2
0
b1
0
b0
Device Select
RW
Note:
The MSB b7 is sent first.
Table 4. Operating Modes
Mode
RW bit
WC
Data Bytes
Initial Sequence
START, Device Select, RW = ’1’
Current Address Read
’1’
’0’
’1’
’1’
’0’
’0’
X
X
1
START, Device Select, RW = ’0’, Address,
reSTART, Device Select, RW = ’1’
As CURRENT or RANDOM Mode
START, Device Select, RW = ’0’
START, Device Select, RW = ’0’
Random Address Read
1
X
Sequential Read
Byte Write
X
≥ 1
1
VIL
VIL
Page Write
≤ 64
Note:
1. X = VIH or VIL.
Write Control (WC).
When writing data to the memory, it responds to the
8 bits received by asserting an acknowledge bit
during the 9th bit time. When data is read by the
bus master, it acknowledges the receipt of the data
bytes in the same way. Data transfers are termi-
nated with a STOP condition.
The Write Control feature WC
is useful to protect the contents of the memory from
any erroneous erase/write cycle. The Write Control
signal is used to enable (WC=VIH) or disable
(WC=VIL) the internal write protection. When the
WC pin is unconnected, the WC input is internally
read as VIL (see Table 5).
Power On Reset: VCC lock out write protect.
In
order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is implemented. Until the VCC
voltage has reached the POR threshold value, the
internal reset is active, all operations are disabled
and the device will not respond to any command.
In the same way, when VCC drops down from the
operating voltage to below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable VCC
must be applied before applying any logic signal.
When WC=1, Device Select and Address bytes are
acknowledged, Data bytes are not acknowledged.
Refer to Application Note AN404 for more detailed
information about Write Control feature.
DEVICE OPERATION
I2C Bus Background
The memory supports the extended addressing I2C
protocol. This protocol defines any device that
sends data onto the bus as a transmitter and any
device that reads the data as a receiver. The device
that controls the data transfer is known as the
master and the other as the slave. The master will
always initiate a data transfer and will provide the
serial clock for synchronisation. The memory is
always a slave device in all communications.
SIGNAL DESCRIPTIONS
Serial Clock (SCL).
The SCL input pin is used to
synchronize all data in and out of the memory. A
resistor can be connected from the SCL line to VCC
to act as a pull up (see Figure 3).
Serial Data (SDA).
The SDA pin is bi-directional
Start Condition.
START is identified by a high to
and is used to transfer data in or out of the memory.
It is an open drain output that may be wire-OR’ed
with other open drain or open collector signals on
the bus. Aresistor must be connected from the SDA
bus line to VCC to act as pull up (see Figure 3).
low transition of the SDA line while the clock SCL
is stable in the high state. A START condition must
precede any command for data transfer. Except
during a programming cycle, the memory continu-
ously monitors the SDA and SCL signals for a
START condition and will not respond unless one
is given.
3/18
M24256, M24128
Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus
V
CC
20
16
12
R
R
L
L
SDA
MASTER
C
BUS
8
SCL
fc = 100kHz
4
0
fc = 400kHz
C
BUS
10
100
(pF)
1000
C
BUS
AI01665
Stop Condition.
STOPis identified by a low to high
or WRITE (RW=0) operation. There are two modes
both for read and write. These are summarized in
Table 4 and described hereafter. A communication
between the master and the slave is ended with a
STOP condition.
transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition termi-
nates communication between the memoryand the
bus master. ASTOP condition at the end of a Read
command forces the standby state. ASTOP condi-
tion at the end of a Write command triggers the
internal EEPROM write cycle.
Memory Addressing.
A data byte in the memory
is addressed through 2 bytes of address informa-
tion. The Most Significant Byte is sent first and the
Least significant Byte is sent after. Bits b15 to b0
form the address of any byte of the memory. Bit b15
is don’t care on the M24256 series. Bits b15 and
b14 are don’t care on the M24128 series.
Acknowledge Bit (ACK).
An acknowledge signal
is used to indicate a successful data transfer. The
bus transmitter, either master or slave, will release
the SDAbus after sending 8 bits of data. During the
9th clock pulse the receiver pulls the SDA bus low
to acknowledge the receipt of the 8 bits of data.
Most Significant Byte
Data Input.
During data input the memory samples
the SDA bus signal on the rising edge of the clock
SCL. For correct device operation, the SDA signal
must be stable during the clock low to high transi-
tion and the data must change ONLYwhen the SCL
line is low.
b15 b14 b13 b12
b11
b10
b9
b1
b8
b0
b15 is don’t care on M24256 series.
b15 and b14 are don’t care on M24128 series.
Device Selection.
To start communication be-
Least Significant Byte
tween the bus master and the slave memory, the
master must initiate a START condition. The 8 bits
sent after a START condition are made up of a
device select of 4 bits thatidentifies the device type,
then 3 bits (at 000) and one bit for a READ (RW=1)
b7
b6
b5
b4
b3
b2
4/18
M24256, M24128
Table 5. Input Parameters (1)
Symbol
°
(TA = 25 C, f = 400 kHz )
Parameter
Test Condition
Min
Max
8
Unit
pF
CIN
CIN
Input Capacitance (SDA)
Input Capacitance (other pins)
6
pF
ZWCL
ZWCH
WC Input Impedance
WC Input Impedance
V
IN ≤ 0.3 VCC
IN ≥ 0.7 VCC
5
20
kΩ
kΩ
V
500
Low-pass filter input time constant
(SDA and SCL)
tLP
100
ns
Note:
1. Sampled only, not 100% tested.
Table 6. DC Characteristics
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.5V to 5.5V or 2.5V to 5.5V)
(TA = 0 to 70 °C or –20 to 85 °C; VCC = 1.8V to 3.6V)
Symbol
Parameter
Test Condition
Min
Max
Unit
Input Leakage Current
(SCL, SDA)
ILI
0V ≤ VIN ≤ VCC
±2
µA
0V ≤ VOUT ≤ VCC
ILO
Output Leakage Current
Supply Current
±2
2
µA
mA
mA
mA
µA
SDA in Hi-Z
V
CC = 5V, fC = 400kHz
(Rise/Fall time < 30ns)
ICC
V
CC = 2.5V, fC = 400kHz
(Rise/Fall time < 30ns)
Supply Current (-W series)
Supply Current (-R series)
Supply Current, Standby
1
VCC = 1.8V, fC = 100kHz
(Rise/Fall time < 30ns)
0.5
10
2
V
V
V
IN = VSS or VCC
,
,
,
VCC = 5V
Supply Current, Standby
(-W series)
IN = VSS or VCC
CC = 2.5V
ICC1
µA
V
Supply Current, Standby
(-R series)
IN = VSS or VCC
CC = 1.8V
1
µA
V
VIL
VIH
VIL
VIH
Input Low Voltage (SCL, SDA)
Input High Voltage (SCL, SDA)
Input Low Voltage (WC)
–0.3
0.7 VCC
–0.3
0.3 VCC
VCC + 1
0.5
V
V
V
V
V
V
V
Input High Voltage (WC)
VCC – 0.5
VCC + 1
0.4
Output Low Voltage
IOL = 3mA, VCC = 5V
VOL
Output Low Voltage (-W series)
Output Low Voltage (-R series)
I
OL = 2.1mA, VCC = 2.5V
0.4
I
OL = 0.15mA, VCC = 1.8V
0.2
5/18
M24256, M24128
Table 7. AC Characteristics
M24256 / M24128
VCC = 4.5V to 5.5V VCC = 2.5V to 5.5V VCC = 1.8V to 3.6V
Symbol
Alt
Parameter
Unit
T = 0 to 70 C
T = 0 to 70 C
T = 0 to 70 C
°
A
°
°
A
A
T = –40 to 85 C T = –40 to 85 C T = –20 to 85 C
°
Max
300
300
300
300
°
Max
300
300
300
300
°
Max
1000
300
A
A
A
Min
Min
Min
tCH1CH2
tCL1CL2
tR
tF
tR
tF
Clock Rise Time
ns
ns
ns
ns
Clock Fall Time
SDA Rise Time
SDA Fall Time
(1)
tDH1DH2
20
20
20
20
20
20
1000
300
(1)
tDL1DL2
Clock High to Input
Transition
(2)
tCHDX
tCHCL
tSU:STA
600
600
600
600
600
600
4700
4000
4000
ns
ns
ns
tHIGH Clock Pulse Width High
Input Low to Clock Low
(START)
tDLCL
tHD:STA
Clock Low to Input
tHD:DAT
tCLDX
tCLCH
tDXCX
0
0
0
µs
ns
ns
Transition
tLOW Clock Pulse Width Low
1300
100
1300
100
4700
250
Input Transition to Clock
Transition
tSU:DAT
Clock High to Input High
(STOP)
tCHDH
tDHDL
tSU:STO
600
600
4000
4700
ns
ns
ns
Input High to Input Low
(Bus Free)
tBUF
1300
1300
Clock Low to Next Data
Out Valid
(3)
tCLQV
tAA
200
200
900
200
200
900
200
200
3500
tCLQX
fC
tDH
fSCL Clock Frequency
tWR Write Time
Data Out Hold Time
ns
kHz
ms
400
10
400
10
100
10
tW
Notes:
1. Sampled only, not 100% tested.
2. For a reSTART condition, or following a write cycle.
3. The minimum value delays the falling/rising edge of SDA away form SCL = 1 in order to avoid unwanted START and/or STOP
condition.
Table 8. AC Measurement Conditions
Write Operations
Following a START condition the master sends a
Device Select code with the RW bit set to ’0’. The
memory acknowledges this and waits for 2 bytes
of address. These 2 address bytes (8 bits each)
provide access to any of the memory locations.
Writing in the memory may be inhibited if input pin
WC is taken high.
Input Rise and Fall Times
Input Pulse Voltages
≤ 50ns
0.2VCC to 0.8VCC
Input and Output Timing Ref.
Voltages
0.3VCC to 0.7VCC
Any write command with WC=1 (during a period of
time from the START condition until the end of the
2 bytes address) will not modify data and will NOT
be acknowledged on data bytes, as in Figure 9.
Figure 4. AC Testing Input Output Waveforms
0.8V
CC
0.7V
CC
Byte Write.
In the Byte Write mode the master
sends one data byte, which is acknowledged by the
memory. The master then terminates the transfer
by generating a STOP condition.
0.3V
CC
0.2V
CC
AI00825
6/18
M24256, M24128
Figure 5. AC Waveforms
tCHCL
tDLCL
tCLCH
SCL
tDXCX
tCHDH
SDA IN
tCHDX
tCLDX
SDA
tDHDL
START
CONDITION
SDA
STOP &
BUS FREE
INPUT CHANGE
SCL
tCLQV
tCLQX
DATA VALID
SDA OUT
DATA OUTPUT
SCL
tW
SDA IN
tCHDH
tCHDX
STOP
WRITE CYCLE
START
CONDITION
CONDITION
AI00795B
7/18
M24256, M24128
Figure 6. I2C Bus Protocol
SCL
SDA
START
SDA
SDA
STOP
CONDITION
INPUT CHANGE
CONDITION
1
2
3
7
8
9
SCL
SDA
ACK
MSB
START
CONDITION
1
2
3
7
8
9
SCL
SDA
MSB
ACK
STOP
CONDITION
AI00792
Page Write.
The Page Write mode allows up to 64
gram cycle. This STOP condition will trigger an
internal memory program cycle only if the STOP
condition is internally decoded right after the AC
Kbit; any STOP condition decoded out of this "10th
bit" time slot will not trigger the internal program-
ming cycle. All inputs are disabled until the comple-
tion of this cycle and the memory will not respond
to any request.
Minimizing System Delays by Polling On ACK.
During the internal Write cycle, the memory disable
itself from the bus in order to copy the data from
the internal latches to the memory cells. The maxi-
mum value of the Write time (tW) is given in the
Table 8, this timing value may be reduced by an
ACK polling sequence issued by the master.
bytes to be written in a single write cycle, provided
that they are all located in the same row of 64 bytes
in the memory, that is the same address bits (b14-
b6 for the M24256 and b13-b6 for the M24128).
The master sends from one up to 64 bytes of data,
which are each acknowledged by the memory.
After each byte is transferred, the internal byte
address counter (6 Least Significant Bits only) is
incremented. The transfer is terminated by the
master generating a STOPcondition. Care must be
taken to avoid address counter ’roll-over’ which
could result in data being overwritten. Note that, for
any write mode, the generation by the master of the
STOP condition starts the internal memory pro-
8/18
M24256, M24128
The sequence is:
Read Operations
– Initial condition: a Write isin progress (see Figure
7).
On delivery, the memory contents is set at all "1’s"
(or FFh).
– Step 1: the master issues a START condition
followed by a Device Select byte (1st byte of the
new instruction).
– Step 2: ifthe memory isinternallywriting, NoACK
will be returned. The master goes back to Step
1. If the memory has terminated the internal
writing, it will issue an ACK.
Current Address Read.
The memory has an inter-
nal byte address counter. Each time a byte is read,
this counter is incremented. For the Current Ad-
dress Read mode, following a START condition,
the master sends a Device Select with the RW bit
set to ’1’. The memory acknowledges this and
outputs the byte addressed by the internal address
counter. This counter is then incremented. The
master does NOT acknowledge the byte output,
but terminates the transfer with a STOP condition.
The memory is ready to receive the second part
of the instruction (the first byte of this instruction
was already sent during Step 1).
Figure 7. Write Cycle Polling using ACK
WRITE Cycle
in Progress
START Condition
DEVICE SELECT
with RW = 0
ACK
Returned
NO
First byte of instruction
with RW = 0 already
decoded by M24xxx
YES
Next
Operation is
Addressing the
Memory
NO
YES
Send
Byte Address
ReSTART
STOP
Proceed
WRITE Operation
Proceed
Random Address
READ Operation
AI01847
9/18
M24256, M24128
Figure 8. Write Modes Sequence with Write Control = 0
WC
ACK
ACK
ACK
ACK
BYTE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
DATA IN
R/W
WC
ACK
ACK
ACK
ACK
PAGE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
DATA IN 1
DATA IN 2
R/W
WC (cont'd)
ACK
ACK
PAGE WRITE
(cont'd)
DATA IN N
AI01106B
Random Address Read.
A dummy write is per-
master must NOT acknowledge the last byte out-
put, but MUST generate a STOP condition. The
output data is from consecutive byte addresses,
with the internal byte address counter automat-
ically incremented after each byte output. After a
count of the last memory address, the address
counter will ’roll-over’ and the memory will continue
to output data.
formed to load the address into the address
counter, see Figure 10. This is followed by another
START condition from the master and the byte
address repeated with the RW bit set to ’1’. The
memory acknowledges this and outputs the byte
addressed. The master have to NOT acknowledge
the byte output, but terminates the transfer with a
STOP condition.
Acknowledge in Read Mode.
In all read modes
Sequential Read.
This mode can be initiated with
the memory waits for an acknowledge during the
9th bit time. If the master does not pull the SDAline
low during this time, the memory terminates the
data transfer and switches to a standby state.
either a Current Address Read or a Random Ad-
dress Read. However, in this case the master
DOES acknowledge the data byte output and the
memory continues to output the next byte in se-
quence. To terminate the stream of bytes, the
10/18
M24256, M24128
Figure 9. Write Modes Sequence with Write Control = 1
WC
ACK
ACK
ACK
NO ACK
DATA IN
BYTE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
R/W
WC
ACK
ACK
ACK
NO ACK
DATA IN 1 DATA IN 2
PAGE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
R/W
WC (cont'd)
NO ACK
NO ACK
PAGE WRITE
(cont'd)
DATA IN N
AI01120B
11/18
M24256, M24128
Figure 10. Read Mode Sequences
ACK
NO ACK
DATA OUT
CURRENT
ADDRESS
READ
DEV SEL
R/W
ACK
ACK
ACK
ACK
NO ACK
DATA OUT
RANDOM
ADDRESS
READ
DEV SEL *
BYTE ADDR
BYTE ADDR
DEV SEL *
R/W
R/W
ACK
ACK
ACK
NO ACK
SEQUENTIAL
CURRENT
READ
DEV SEL
DATA OUT 1
DATA OUT N
R/W
ACK
ACK
ACK
ACK
ACK
SEQUENTIAL
RANDOM
READ
DEV SEL *
BYTE ADDR
BYTE ADDR
DEV SEL * DATA OUT 1
R/W
R/W
ACK
NO ACK
DATA OUT N
AI01105C
Note:
*
The 7 Most Significant bits of DEV SEL bytes of a Random Read (1st byte and 4th byte) must be identical.
12/18
M24256, M24128
ORDERING INFORMATION SCHEME
Example:
M24256
–
R
MW 1
T
Density
Operating Voltage
Package
Temperature Range
Option
256 256K (32 x8)
128 128K (16 x8)
blank 4.5V to 5.5V
BN PSDIP8
0.25mm Frame
MN (2) SO8
150mil Width
1
0 to 70 °C
T
Tape & Reel
Packing
W
2.5V to 5.5V
6
–40 to 85 °C
R (1) 1.8V to 3.6V
3 (5) –40 to 125 °C
MW (3)SO8
200mil Width
5
–20 to 85 °C
DL (4) TSSOP14
169mil Width
Notes:
1. -R version (1.8V to 3.6V) are only available in temperature ranges 5 or 1.
2. SO8, 150mil Width, package is available for M24128 series only.
3. SO8, 200mil Width, package is available for M24256 series only.
4. TSSOP14, 169mil Width, pakage is available for M24128 series only. Contact marketing for availability.
5. Produced with High Reliability Certified Flow (HRCF), in VCC range 4.5V to 5.5V at 100kHz only.
Devices are shipped from the factory with the memory content set at all "1’s" (FFh).
For a list of available options (Operating Voltage, Package, etc...) or for further information on any aspect
of this device, please contact the STMicroelectronics Sales Office nearest to you.
13/18
M24256, M24128
PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame
mm
Min
3.90
0.49
3.30
0.36
1.15
0.20
9.20
–
inches
Min
Symb
Typ
Max
5.90
–
Typ
Max
0.232
–
A
A1
A2
B
0.154
0.019
0.130
0.014
0.045
0.008
0.362
–
5.30
0.56
1.65
0.36
9.90
–
0.209
0.022
0.065
0.014
0.390
–
B1
C
D
E
7.62
2.54
0.300
0.100
E1
e1
eA
eB
L
6.00
–
6.70
–
0.236
–
0.264
–
7.80
–
0.307
–
10.00
3.80
0.394
0.150
3.00
8
0.118
8
N
A2
A
L
A1
e1
B
C
eA
eB
B1
D
N
1
E1
E
PSDIP-a
Drawing is not o scale.
14/18
M24256, M24128
SO8 - 8 lead Plastic Small Outline, 150 mils body width
mm
Min
1.35
0.10
0.33
0.19
4.80
3.80
–
inches
Symb
Typ
Max
1.75
0.25
0.51
0.25
5.00
4.00
–
Typ
Min
0.053
0.004
0.013
0.007
0.189
0.150
–
Max
0.069
0.010
0.020
0.010
0.197
0.157
–
A
A1
B
C
D
E
e
1.27
0.050
H
h
5.80
0.25
0.40
0
6.20
0.50
0.90
8
0.228
0.010
0.016
0
0.244
0.020
0.035
8
L
α
N
CP
8
8
0.10
0.004
A2
A
C
B
CP
e
D
N
1
E
H
A1
α
L
SO-b
Drawing is not to scale.
15/18
M24256, M24128
SO8 - 8 lead Plastic Small Outline, 200 mils body width
mm
Min
inches
Min
Symb
Typ
Max
2.03
0.25
1.78
0.45
–
Typ
Max
0.080
0.010
0.070
0.018
–
A
A1
A2
B
0.10
0.004
0.35
–
0.014
–
C
0.20
1.27
0.008
0.050
D
5.15
5.20
–
5.35
5.40
–
0.203
0.205
–
0.211
0.213
–
E
e
H
7.70
0.50
0°
8.10
0.80
10°
0.303
0.020
0°
0.319
0.031
10°
L
α
N
8
8
CP
0.10
0.004
A2
A
C
B
CP
e
D
N
1
E
H
A1
α
L
SO-b
Drawing is not to scale.
16/18
M24256, M24128
TSSOP14 - 14 lead Thin Shrink Small Outline
mm
Min
inches
Symb
Typ
Max
1.10
0.15
0.95
0.30
0.20
5.10
6.50
4.50
–
Typ
Min
Max
0.043
0.006
0.037
0.012
0.008
0.197
0.256
0.177
–
A
A1
A2
B
0.05
0.85
0.19
0.09
4.90
6.25
4.30
–
0.002
0.033
0.007
0.004
0.193
0.246
0.169
–
C
D
E
E1
e
0.65
0.026
L
0.50
0°
0.70
8°
0.020
0°
0.028
8°
α
N
14
14
CP
0.08
0.003
A2
A
C
B
CP
e
D
N
1
E
H
A1
α
L
SO-b
Drawing is not to scale.
17/18
M24256, M24128
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
© 1998 STMicroelectronics - All Rights Reserved
Purchase of I2C Components by STMicroelectronics, conveys a license under the Philips
I2C Patent. Rights to use these components in an I2C system, is granted provided that the system conforms to
the I2C Standard Specifications as defined by Philips.
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
http://www.st.com
18/18
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